[golan] Add Connect-IB, ConnectX-4 and ConnectX-4 Lx (Infiniband) support
[ipxe.git] / src / drivers / infiniband / golan.h
1 #ifndef _GOLAN_H_
2 #define _GOLAN_H_
3
4 /*
5 * Copyright (C) 2013-2015 Mellanox Technologies Ltd.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA.
21 */
22
23 FILE_LICENCE ( GPL2_OR_LATER );
24
25 #include <byteswap.h>
26 #include <errno.h>
27 #include <stdio.h>
28 #include <unistd.h>
29 #include <ipxe/io.h>
30 #include <ipxe/pci.h>
31 #include <ipxe/pcibackup.h>
32 #include "CIB_PRM.h"
33
34 #define GOLAN_PCI_CONFIG_BAR_SIZE 0x100000//HERMON_PCI_CONFIG_BAR_SIZE //TODO: What is the BAR size?
35
36 #define GOLAN_PAS_SIZE sizeof(uint64_t)
37
38 #define GOLAN_INVALID_LKEY 0x00000100UL
39
40 #define GOLAN_MAX_PORTS 2
41 #define GOLAN_PORT_BASE 1
42
43 #define MELLANOX_VID 0x15b3
44 #define GOLAN_HCA_BAR PCI_BASE_ADDRESS_0 //BAR 0
45
46 #define GOLAN_HCR_MAX_WAIT_MS 10000
47
48 #define min(a,b) ((a)<(b)?(a):(b))
49
50 #define GOLAN_PAGE_SHIFT 12
51 #define GOLAN_PAGE_SIZE (1 << GOLAN_PAGE_SHIFT)
52 #define GOLAN_PAGE_MASK (GOLAN_PAGE_SIZE - 1)
53
54 #define MAX_MBOX ( GOLAN_PAGE_SIZE / MAILBOX_STRIDE )
55 #define DEF_CMD_IDX 1
56 #define MEM_CMD_IDX 0
57 #define NO_MBOX 0xffff
58 #define MEM_MBOX MEM_CMD_IDX
59 #define GEN_MBOX DEF_CMD_IDX
60
61 #define CMD_IF_REV 4
62
63 #define MAX_PASE_MBOX ((GOLAN_CMD_PAS_CNT) - 2)
64
65 #define CMD_STATUS( golan , idx ) ((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->status
66 #define CMD_SYND( golan , idx ) ((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->syndrome
67 #define QRY_PAGES_OUT( golan, idx ) ((struct golan_query_pages_outbox *)(get_cmd( (golan) , (idx) )->out))
68
69 #define VIRT_2_BE64_BUS( addr ) cpu_to_be64(((unsigned long long )virt_to_bus(addr)))
70 #define BE64_BUS_2_VIRT( addr ) bus_to_virt(be64_to_cpu(addr))
71 #define USR_2_BE64_BUS( addr ) cpu_to_be64(((unsigned long long )user_to_phys(addr, 0)))
72 #define BE64_BUS_2_USR( addr ) be64_to_cpu(phys_to_user(addr))
73
74 #define GET_INBOX(golan, idx) (&(((struct mbox *)(golan->mboxes.inbox))[idx]))
75 #define GET_OUTBOX(golan, idx) (&(((struct mbox *)(golan->mboxes.outbox))[idx]))
76
77 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
78
79 /* Fw status fields */
80 typedef enum {
81 NO_ERRORS = 0x0,
82 SIGNATURE_ERROR = 0x1,
83 TOKEN_ERROR = 0x2,
84 BAD_BLOCK_NUMBER = 0x3,
85 BAD_OUTPUT_POINTER = 0x4, // pointer not align to mailbox size
86 BAD_INPUT_POINTER = 0x5, // pointer not align to mailbox size
87 INTERNAL_ERROR = 0x6,
88 INPUT_LEN_ERROR = 0x7, // input length less than 0x8.
89 OUTPUT_LEN_ERROR = 0x8, // output length less than 0x8.
90 RESERVE_NOT_ZERO = 0x9,
91 BAD_CMD_TYPE = 0x10,
92 } return_hdr_t;
93
94 struct golan_cmdq_md {
95 void *addr;
96 u16 log_stride;
97 u16 size;
98 };
99
100 struct golan_uar {
101 uint32_t index;
102 void *virt;
103 unsigned long phys;
104 };
105
106 /* Queue Pair */
107 #define GOLAN_SEND_WQE_BB_SIZE 64
108 #define GOLAN_SEND_UD_WQE_SIZE sizeof(struct golan_send_wqe_ud)
109 #define GOLAN_RECV_WQE_SIZE sizeof(struct golan_recv_wqe_ud)
110 #define GOLAN_WQEBBS_PER_SEND_UD_WQE DIV_ROUND_UP(GOLAN_SEND_UD_WQE_SIZE, GOLAN_SEND_WQE_BB_SIZE)
111 #define GOLAN_SEND_OPCODE 0x0a
112 #define GOLAN_WQE_CTRL_WQE_IDX_BIT 8
113
114 enum golan_ib_qp_state {
115 GOLAN_IB_QPS_RESET,
116 GOLAN_IB_QPS_INIT,
117 GOLAN_IB_QPS_RTR,
118 GOLAN_IB_QPS_RTS,
119 GOLAN_IB_QPS_SQD,
120 GOLAN_IB_QPS_SQE,
121 GOLAN_IB_QPS_ERR
122 };
123
124 struct golan_send_wqe_ud {
125 struct golan_wqe_ctrl_seg ctrl;
126 struct golan_av datagram;
127 struct golan_wqe_data_seg data;
128 };
129
130 union golan_send_wqe {
131 struct golan_send_wqe_ud ud;
132 uint8_t pad[GOLAN_WQEBBS_PER_SEND_UD_WQE * GOLAN_SEND_WQE_BB_SIZE];
133 };
134
135 struct golan_recv_wqe_ud {
136 struct golan_wqe_data_seg data[2];
137 };
138
139 struct golan_recv_wq {
140 struct golan_recv_wqe_ud *wqes;
141 /* WQ size in bytes */
142 int size;
143 /* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
144 u16 next_idx;
145 /** GRH buffers (if applicable) */
146 struct ib_global_route_header *grh;
147 /** Size of GRH buffers */
148 size_t grh_size;
149 };
150
151 struct golan_send_wq {
152 union golan_send_wqe *wqes;
153 /* WQ size in bytes */
154 int size;
155 /* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
156 u16 next_idx;
157 };
158
159 struct golan_queue_pair {
160 void *wqes;
161 int size;
162 struct golan_recv_wq rq;
163 struct golan_send_wq sq;
164 struct golan_qp_db *doorbell_record;
165 u32 doorbell_qpn;
166 enum golan_ib_qp_state state;
167 };
168
169 /* Completion Queue */
170 #define GOLAN_CQE_OPCODE_NOT_VALID 0x0f
171 #define GOLAN_CQE_OPCODE_BIT 4
172 #define GOLAN_CQ_DB_RECORD_SIZE sizeof(uint64_t)
173 #define GOLAN_CQE_OWNER_MASK 1
174
175 #define MANAGE_PAGES_PSA_OFFSET 0
176 #define PXE_CMDIF_REF 5
177
178 enum {
179 GOLAN_CQE_SW_OWNERSHIP = 0x0,
180 GOLAN_CQE_HW_OWNERSHIP = 0x1
181 };
182
183 enum {
184 GOLAN_CQE_SIZE_64 = 0,
185 GOLAN_CQE_SIZE_128 = 1
186 };
187
188 struct golan_completion_queue {
189 struct golan_cqe64 *cqes;
190 int size;
191 __be64 *doorbell_record;
192 };
193
194
195 /* Event Queue */
196 #define GOLAN_EQE_SIZE sizeof(struct golan_eqe)
197 #define GOLAN_NUM_EQES 8
198 #define GOLAN_EQ_DOORBELL_OFFSET 0x40
199
200 #define GOLAN_EQ_MAP_ALL_EVENTS \
201 ((1 << GOLAN_EVENT_TYPE_PATH_MIG )| \
202 (1 << GOLAN_EVENT_TYPE_COMM_EST )| \
203 (1 << GOLAN_EVENT_TYPE_SQ_DRAINED )| \
204 (1 << GOLAN_EVENT_TYPE_SRQ_LAST_WQE )| \
205 (1 << GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT )| \
206 (1 << GOLAN_EVENT_TYPE_CQ_ERROR )| \
207 (1 << GOLAN_EVENT_TYPE_WQ_CATAS_ERROR )| \
208 (1 << GOLAN_EVENT_TYPE_PATH_MIG_FAILED )| \
209 (1 << GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR )| \
210 (1 << GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR )| \
211 (1 << GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR )| \
212 (1 << GOLAN_EVENT_TYPE_INTERNAL_ERROR )| \
213 (1 << GOLAN_EVENT_TYPE_PORT_CHANGE )| \
214 (1 << GOLAN_EVENT_TYPE_GPIO_EVENT )| \
215 (1 << GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER )| \
216 (1 << GOLAN_EVENT_TYPE_REMOTE_CONFIG )| \
217 (1 << GOLAN_EVENT_TYPE_DB_BF_CONGESTION )| \
218 (1 << GOLAN_EVENT_TYPE_STALL_EVENT )| \
219 (1 << GOLAN_EVENT_TYPE_PACKET_DROPPED )| \
220 (1 << GOLAN_EVENT_TYPE_CMD )| \
221 (1 << GOLAN_EVENT_TYPE_PAGE_REQUEST ))
222
223 enum golan_event {
224 GOLAN_EVENT_TYPE_COMP = 0x0,
225
226 GOLAN_EVENT_TYPE_PATH_MIG = 0x01,
227 GOLAN_EVENT_TYPE_COMM_EST = 0x02,
228 GOLAN_EVENT_TYPE_SQ_DRAINED = 0x03,
229 GOLAN_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
230 GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
231
232 GOLAN_EVENT_TYPE_CQ_ERROR = 0x04,
233 GOLAN_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
234 GOLAN_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
235 GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
236 GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
237 GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
238
239 GOLAN_EVENT_TYPE_INTERNAL_ERROR = 0x08,
240 GOLAN_EVENT_TYPE_PORT_CHANGE = 0x09,
241 GOLAN_EVENT_TYPE_GPIO_EVENT = 0x15,
242 // GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER = 0x16,
243 GOLAN_EVENT_TYPE_REMOTE_CONFIG = 0x19,
244
245 GOLAN_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
246 GOLAN_EVENT_TYPE_STALL_EVENT = 0x1b,
247
248 GOLAN_EVENT_TYPE_PACKET_DROPPED = 0x1f,
249
250 GOLAN_EVENT_TYPE_CMD = 0x0a,
251 GOLAN_EVENT_TYPE_PAGE_REQUEST = 0x0b,
252 GOLAN_EVENT_TYPE_PAGE_FAULT = 0x0C,
253 };
254
255 enum golan_port_sub_event {
256 GOLAN_PORT_CHANGE_SUBTYPE_DOWN = 1,
257 GOLAN_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
258 GOLAN_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
259 GOLAN_PORT_CHANGE_SUBTYPE_LID = 6,
260 GOLAN_PORT_CHANGE_SUBTYPE_PKEY = 7,
261 GOLAN_PORT_CHANGE_SUBTYPE_GUID = 8,
262 GOLAN_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9
263 };
264
265
266 enum {
267 GOLAN_EQE_SW_OWNERSHIP = 0x0,
268 GOLAN_EQE_HW_OWNERSHIP = 0x1
269 };
270
271 enum {
272 GOLAN_EQ_UNARMED = 0,
273 GOLAN_EQ_ARMED = 1,
274 };
275
276 struct golan_event_queue {
277 uint8_t eqn;
278 uint64_t mask;
279 struct golan_eqe *eqes;
280 int size;
281 __be32 *doorbell;
282 uint32_t cons_index;
283 };
284
285 struct golan_port {
286 /** Infiniband device */
287 struct ib_device *ibdev;
288 /** Network device */
289 struct net_device *netdev;
290 /** VEP number */
291 u8 vep_number;
292 };
293
294 struct golan_mboxes {
295 void *inbox;
296 void *outbox;
297 };
298
299 #define GOLAN_OPEN 0x1
300
301 struct golan {
302 struct pci_device *pci;
303 struct golan_hca_init_seg *iseg;
304 struct golan_cmdq_md cmd;
305 struct golan_hca_cap caps; /* stored as big indian*/
306 struct golan_mboxes mboxes;
307 struct list_head pages;
308 uint32_t cmd_bm;
309 uint32_t total_dma_pages;
310 struct golan_uar uar;
311 struct golan_event_queue eq;
312 uint32_t pdn;
313 u32 mkey;
314 u32 flags;
315
316 struct golan_port ports[GOLAN_MAX_PORTS];
317 };
318
319 #endif /* _GOLAN_H_*/