[golan] Add Connect-IB, ConnectX-4 and ConnectX-4 Lx (Infiniband) support
[ipxe.git] / src / drivers / infiniband / mlx_utils / mlx_lib / mlx_link_speed / mlx_link_speed.h
1 #ifndef MLX_LINK_SPEED_H_
2 #define MLX_LINK_SPEED_H_
3
4 /*
5 * Copyright (C) 2015 Mellanox Technologies Ltd.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA.
21 */
22
23 FILE_LICENCE ( GPL2_OR_LATER );
24
25 #include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
26 #include "../../include/public/mlx_utils.h"
27
28 #define LINK_SPEED_100GB_MASK (ETH_SPEED_ENABLE_MASK_100GBASECR4 | ETH_SPEED_ENABLE_MASK_100GBASESR4 | ETH_SPEED_ENABLE_MASK_100GBASEKR4 | ETH_SPEED_ENABLE_MASK_100GBASELR4)
29 #define LINK_SPEED_56GB_MASK (ETH_SPEED_ENABLE_MASK_56GBASER4)
30 #define LINK_SPEED_50GB_MASK (ETH_SPEED_ENABLE_MASK_50GBASECR2 | ETH_SPEED_ENABLE_MASK_50GBASEKR2)
31 #define LINK_SPEED_40GB_MASK (ETH_SPEED_ENABLE_MASK_40GBASECR4 | ETH_SPEED_ENABLE_MASK_40GBASEKR4 | ETH_SPEED_ENABLE_MASK_40GBASESR4 | ETH_SPEED_ENABLE_MASK_40GBASELR4)
32 #define LINK_SPEED_25GB_MASK (ETH_SPEED_ENABLE_MASK_25GBASECR | ETH_SPEED_ENABLE_MASK_25GBASEKR | ETH_SPEED_ENABLE_MASK_25GBASESR)
33 #define LINK_SPEED_20GB_MASK (ETH_SPEED_ENABLE_MASK_20GBASER2)
34 #define LINK_SPEED_10GB_MASK (ETH_SPEED_ENABLE_MASK_10GBASECR | ETH_SPEED_ENABLE_MASK_10GBASESR | ETH_SPEED_ENABLE_MASK_10GBASELR | ETH_SPEED_ENABLE_MASK_10GBASEKR)
35 #define LINK_SPEED_1GB_MASK (ETH_SPEED_ENABLE_MASK_1000BASECX | ETH_SPEED_ENABLE_MASK_1000BASEKX | ETH_SPEED_ENABLE_MASK_100BaseTX | ETH_SPEED_ENABLE_MASK_1000BASET)
36
37 #define LINK_SPEED_SDR_MASK 0x1
38 #define LINK_SPEED_DDR_MASK 0x2
39 #define LINK_SPEED_QDR_MASK 0xC
40 #define LINK_SPEED_FDR_MASK 0x10
41 #define LINK_SPEED_EDR20_MASK 0x200
42 #define LINK_SPEED_EDR_MASK 0x20
43
44 #define LINK_SPEED_WITDH_1_MASK 0x1
45 #define LINK_SPEED_WITDH_2_MASK 0x2
46 #define LINK_SPEED_WITDH_4_MASK 0x4
47 #define LINK_SPEED_WITDH_8_MASK 0x8
48 #define LINK_SPEED_WITDH_12_MASK 0x10
49
50 #define GIGA_TO_BIT 0x40000000
51
52 enum {
53 ETH_SPEED_ENABLE_MASK_1000BASECX = 0x0001,
54 ETH_SPEED_ENABLE_MASK_1000BASEKX = 0x0002,
55 ETH_SPEED_ENABLE_MASK_10GBASECX4 = 0x0004,
56 ETH_SPEED_ENABLE_MASK_10GBASEKX4 = 0x0008,
57 ETH_SPEED_ENABLE_MASK_10GBASEKR = 0x0010,
58 ETH_SPEED_ENABLE_MASK_20GBASER2 = 0x0020,
59 ETH_SPEED_ENABLE_MASK_40GBASECR4 = 0x0040,
60 ETH_SPEED_ENABLE_MASK_40GBASEKR4 = 0x0080,
61 ETH_SPEED_ENABLE_MASK_56GBASER4 = 0x0100,
62 ETH_SPEED_ENABLE_MASK_10GBASECR = 0x1000,
63 ETH_SPEED_ENABLE_MASK_10GBASESR = 0x2000,
64 ETH_SPEED_ENABLE_MASK_10GBASELR = 0x4000,
65 ETH_SPEED_ENABLE_MASK_40GBASESR4 = 0x8000,
66 ETH_SPEED_ENABLE_MASK_40GBASELR4 = 0x10000,
67 ETH_SPEED_ENABLE_MASK_50GBASEKR4 = 0x80000,
68 ETH_SPEED_ENABLE_MASK_100GBASECR4 = 0x100000,
69 ETH_SPEED_ENABLE_MASK_100GBASESR4 = 0x200000,
70 ETH_SPEED_ENABLE_MASK_100GBASEKR4 = 0x400000,
71 ETH_SPEED_ENABLE_MASK_100GBASELR4 = 0x800000,
72 ETH_SPEED_ENABLE_MASK_100BaseTX = 0x1000000,
73 ETH_SPEED_ENABLE_MASK_1000BASET = 0x2000000,
74 ETH_SPEED_ENABLE_MASK_10GBASET = 0x4000000,
75 ETH_SPEED_ENABLE_MASK_25GBASECR = 0x8000000,
76 ETH_SPEED_ENABLE_MASK_25GBASEKR = 0x10000000,
77 ETH_SPEED_ENABLE_MASK_25GBASESR = 0x20000000,
78 ETH_SPEED_ENABLE_MASK_50GBASECR2 = 0x40000000,
79 ETH_SPEED_ENABLE_MASK_50GBASEKR2 = 0x80000000,
80 ETH_SPEED_ENABLE_MASK_BAD = 0xffff,
81 };
82
83
84 typedef enum {
85 LINK_SPEED_IB = 0,
86 LINK_SPEED_FC,
87 LINK_SPEED_ETH,
88 } LINK_SPEED_TYPE;
89
90 typedef enum {
91 LINK_SPEED_1GB = 0,
92 LINK_SPEED_10GB,
93 LINK_SPEED_40GB,
94 LINK_SPEED_100GB,
95 LINK_SPEED_SDR,
96 LINK_SPEED_DEFAULT,
97 } LINK_SPEED;
98
99 struct mlx_link_speed {
100 mlx_uint32 proto_mask :3;
101 mlx_uint32 reserved1 :13;
102 mlx_uint32 loacl_port :8;
103 mlx_uint32 reserved2 :8;
104 /* -------------- */
105 mlx_uint32 reserved3 :32;
106 /* -------------- */
107 mlx_uint32 reserved4 :32;
108 /* -------------- */
109 mlx_uint32 eth_proto_capability :32;
110 /* -------------- */
111 mlx_uint32 ib_proto_capability :16;
112 mlx_uint32 ib_link_width_capability :16;
113 /* -------------- */
114 mlx_uint32 reserved5 :32;
115 /* -------------- */
116 mlx_uint32 eth_proto_admin :32;
117 /* -------------- */
118 mlx_uint32 ib_proto_admin :16;
119 mlx_uint32 ib_link_width_admin :16;
120 /* -------------- */
121 mlx_uint32 reserved6 :32;
122 /* -------------- */
123 mlx_uint32 eth_proto_oper :32;
124 /* -------------- */
125 mlx_uint32 ib_proto_oper :16;
126 mlx_uint32 ib_link_width_oper :16;
127 };
128
129 mlx_status
130 mlx_set_link_speed(
131 IN mlx_utils *utils,
132 IN mlx_uint8 port_num,
133 IN LINK_SPEED_TYPE type,
134 IN LINK_SPEED speed
135 );
136
137 mlx_status
138 mlx_get_max_speed(
139 IN mlx_utils *utils,
140 IN mlx_uint8 port_num,
141 IN LINK_SPEED_TYPE type,
142 OUT mlx_uint64 *speed
143 );
144
145 #endif /* MLX_LINK_SPEED_H_ */