[golan] Add Connect-IB, ConnectX-4 and ConnectX-4 Lx (Infiniband) support
[ipxe.git] / src / drivers / infiniband / mlx_utils / mlx_lib / mlx_reg_access / mlx_reg_access.h
1 /*
2 * Copyright (C) 2015 Mellanox Technologies Ltd.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17 * 02110-1301, USA.
18 */
19
20 FILE_LICENCE ( GPL2_OR_LATER );
21
22 #ifndef MLX_REG_ACCESS_H_
23 #define MLX_REG_ACCESS_H_
24
25 #include "../../include/public/mlx_icmd.h"
26
27 #define REG_ACCESS_MAX_REG_SIZE 236
28
29 typedef enum {
30 REG_ACCESS_READ = 1,
31 REG_ACCESS_WRITE = 2,
32 } REG_ACCESS_OPT;
33
34 typedef enum {
35 TLV_ACCESS_DEFAULT_DIS = 0,
36 TLV_ACCESS_DEFAULT_EN = 1,
37 } NV_DEFAULT_OPT;
38
39 #define REG_ID_NVDA 0x9024
40 #define REG_ID_NVDI 0x9025
41 #define REG_ID_NVIA 0x9029
42 #define REG_ID_MLCR 0x902b
43 #define REG_ID_NVQC 0x9030
44 #define REG_ID_MFRL 0x9028
45 #define REG_ID_PTYS 0x5004
46 #define REG_ID_PMTU 0x5003
47
48 struct operation_tlv {
49 mlx_uint32 reserved0 :8; /* bit_offset:0 */ /* element_size: 8 */
50 mlx_uint32 status :7; /* bit_offset:8 */ /* element_size: 7 */
51 mlx_uint32 dr :1; /* bit_offset:15 */ /* element_size: 1 */
52 mlx_uint32 len :11; /* bit_offset:16 */ /* element_size: 11 */
53 mlx_uint32 Type :5; /* bit_offset:27 */ /* element_size: 5 */
54 mlx_uint32 cls :8; /* bit_offset:32 */ /* element_size: 8 */
55 mlx_uint32 method :7; /* bit_offset:40 */ /* element_size: 7 */
56 mlx_uint32 r :1; /* bit_offset:47 */ /* element_size: 1 */
57 mlx_uint32 register_id :16; /* bit_offset:48 */ /* element_size: 16 */
58 mlx_uint64 tid ; /* bit_offset:64 */ /* element_size: 64 */
59 };
60
61 struct reg_tlv {
62 mlx_uint32 reserved0 :16; /* bit_offset:0 */ /* element_size: 16 */
63 mlx_uint32 len :11; /* bit_offset:16 */ /* element_size: 11 */
64 mlx_uint32 Type :5; /* bit_offset:27 */ /* element_size: 5 */
65 mlx_uint8 data[REG_ACCESS_MAX_REG_SIZE];
66 };
67
68 struct mail_box_tlv {
69 struct operation_tlv operation_tlv;
70 struct reg_tlv reg_tlv;
71 };
72 mlx_status
73 mlx_reg_access(
74 IN mlx_utils *utils,
75 IN mlx_uint16 reg_id,
76 IN REG_ACCESS_OPT reg_opt,
77 IN OUT mlx_void *reg_data,
78 IN mlx_size reg_size,
79 OUT mlx_uint32 *reg_status
80 );
81
82 #endif /* MLX_REG_ACCESS_H_ */