[golan] Add Connect-IB, ConnectX-4 and ConnectX-4 Lx (Infiniband) support
[ipxe.git] / src / drivers / infiniband / mlx_utils_flexboot / src / mlx_pci_priv.c
1 /*
2 * MlxPciPriv.c
3 *
4 * Created on: Jan 21, 2015
5 * Author: maord
6 */
7
8 #include <ipxe/pci.h>
9 #include "../../mlx_utils/include/private/mlx_pci_priv.h"
10
11
12 static
13 mlx_status
14 mlx_pci_config_byte(
15 IN mlx_utils *utils,
16 IN mlx_boolean read,
17 IN mlx_uint32 offset,
18 IN OUT mlx_uint8 *buffer
19 )
20 {
21 mlx_status status = MLX_SUCCESS;
22 if (read) {
23 status = pci_read_config_byte(utils->pci, offset, buffer);
24 }else {
25 status = pci_write_config_byte(utils->pci, offset, *buffer);
26 }
27 return status;
28 }
29
30 static
31 mlx_status
32 mlx_pci_config_word(
33 IN mlx_utils *utils,
34 IN mlx_boolean read,
35 IN mlx_uint32 offset,
36 IN OUT mlx_uint16 *buffer
37 )
38 {
39 mlx_status status = MLX_SUCCESS;
40 if (read) {
41 status = pci_read_config_word(utils->pci, offset, buffer);
42 }else {
43 status = pci_write_config_word(utils->pci, offset, *buffer);
44 }
45 return status;
46 }
47
48 static
49 mlx_status
50 mlx_pci_config_dword(
51 IN mlx_utils *utils,
52 IN mlx_boolean read,
53 IN mlx_uint32 offset,
54 IN OUT mlx_uint32 *buffer
55 )
56 {
57 mlx_status status = MLX_SUCCESS;
58 if (read) {
59 status = pci_read_config_dword(utils->pci, offset, buffer);
60 }else {
61 status = pci_write_config_dword(utils->pci, offset, *buffer);
62 }
63 return status;
64 }
65 static
66 mlx_status
67 mlx_pci_config(
68 IN mlx_utils *utils,
69 IN mlx_boolean read,
70 IN mlx_pci_width width,
71 IN mlx_uint32 offset,
72 IN mlx_uintn count,
73 IN OUT mlx_void *buffer
74 )
75 {
76 mlx_status status = MLX_SUCCESS;
77 mlx_uint8 *tmp = (mlx_uint8*)buffer;
78 mlx_uintn iteration = 0;
79 if( width == MlxPciWidthUint64) {
80 width = MlxPciWidthUint32;
81 count = count * 2;
82 }
83
84 for(;iteration < count ; iteration++) {
85 switch (width){
86 case MlxPciWidthUint8:
87 status = mlx_pci_config_byte(utils, read , offset++, tmp++);
88 break;
89 case MlxPciWidthUint16:
90 status = mlx_pci_config_word(utils, read , offset, (mlx_uint16*)tmp);
91 tmp += 2;
92 offset += 2;
93 break;
94 case MlxPciWidthUint32:
95 status = mlx_pci_config_dword(utils, read , offset, (mlx_uint32*)tmp);
96 tmp += 4;
97 offset += 4;
98 break;
99 default:
100 status = MLX_INVALID_PARAMETER;
101 }
102 if(status != MLX_SUCCESS) {
103 goto config_error;
104 }
105 }
106 config_error:
107 return status;
108 }
109 mlx_status
110 mlx_pci_init_priv(
111 IN mlx_utils *utils
112 )
113 {
114 mlx_status status = MLX_SUCCESS;
115 adjust_pci_device ( utils->pci );
116 #ifdef DEVICE_CX3
117 utils->config = ioremap ( pci_bar_start ( utils->pci, PCI_BASE_ADDRESS_0),
118 0x100000 );
119 #endif
120 return status;
121 }
122
123 mlx_status
124 mlx_pci_read_priv(
125 IN mlx_utils *utils,
126 IN mlx_pci_width width,
127 IN mlx_uint32 offset,
128 IN mlx_uintn count,
129 OUT mlx_void *buffer
130 )
131 {
132 mlx_status status = MLX_SUCCESS;
133 status = mlx_pci_config(utils, TRUE, width, offset, count, buffer);
134 return status;
135 }
136
137 mlx_status
138 mlx_pci_write_priv(
139 IN mlx_utils *utils,
140 IN mlx_pci_width width,
141 IN mlx_uint32 offset,
142 IN mlx_uintn count,
143 IN mlx_void *buffer
144 )
145 {
146 mlx_status status = MLX_SUCCESS;
147 status = mlx_pci_config(utils, FALSE, width, offset, count, buffer);
148 return status;
149 }
150
151 mlx_status
152 mlx_pci_mem_read_priv(
153 IN mlx_utils *utils __attribute__ ((unused)),
154 IN mlx_pci_width width __attribute__ ((unused)),
155 IN mlx_uint8 bar_index __attribute__ ((unused)),
156 IN mlx_uint64 offset,
157 IN mlx_uintn count __attribute__ ((unused)),
158 OUT mlx_void *buffer
159 )
160 {
161 if (buffer == NULL || width != MlxPciWidthUint32)
162 return MLX_INVALID_PARAMETER;
163 *((mlx_uint32 *)buffer) = readl(offset);
164 return MLX_SUCCESS;
165 }
166
167 mlx_status
168 mlx_pci_mem_write_priv(
169 IN mlx_utils *utils __attribute__ ((unused)),
170 IN mlx_pci_width width __attribute__ ((unused)),
171 IN mlx_uint8 bar_index __attribute__ ((unused)),
172 IN mlx_uint64 offset,
173 IN mlx_uintn count __attribute__ ((unused)),
174 IN mlx_void *buffer
175 )
176 {
177 if (buffer == NULL || width != MlxPciWidthUint32)
178 return MLX_INVALID_PARAMETER;
179 barrier();
180 writel(*((mlx_uint32 *)buffer), offset);
181 return MLX_SUCCESS;
182 }