[tcpip] Allow supported address families to be detected at runtime
[ipxe.git] / src / drivers / infiniband / qib7322.h
1 #ifndef _QIB7322_H
2 #define _QIB7322_H
3
4 /*
5 * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA.
21 *
22 * You can also choose to distribute this program under the terms of
23 * the Unmodified Binary Distribution Licence (as given in the file
24 * COPYING.UBDL), provided that you have satisfied its requirements.
25 */
26
27 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
28
29 /**
30 * @file
31 *
32 * QLogic QIB7322 Infiniband HCA
33 *
34 */
35
36 #define BITOPS_LITTLE_ENDIAN
37 #include <ipxe/bitops.h>
38 #include "qib_7322_regs.h"
39
40 /** A QIB7322 GPIO register */
41 struct QIB_7322_GPIO_pb {
42 pseudo_bit_t GPIO[16];
43 pseudo_bit_t Reserved[48];
44 };
45 struct QIB_7322_GPIO {
46 PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIO_pb );
47 };
48
49 /** A QIB7322 general scalar register */
50 struct QIB_7322_scalar_pb {
51 pseudo_bit_t Value[64];
52 };
53 struct QIB_7322_scalar {
54 PSEUDO_BIT_STRUCT ( struct QIB_7322_scalar_pb );
55 };
56
57 /** QIB7322 feature mask */
58 struct QIB_7322_feature_mask_pb {
59 pseudo_bit_t Port0_Link_Speed_Supported[3];
60 pseudo_bit_t Port1_Link_Speed_Supported[3];
61 pseudo_bit_t _unused_0[58];
62 };
63 struct QIB_7322_feature_mask {
64 PSEUDO_BIT_STRUCT ( struct QIB_7322_feature_mask_pb );
65 };
66
67 /** QIB7322 send per-buffer control word */
68 struct QIB_7322_SendPbc_pb {
69 pseudo_bit_t LengthP1_toibc[11];
70 pseudo_bit_t Reserved1[4];
71 pseudo_bit_t LengthP1_trigger[11];
72 pseudo_bit_t Reserved2[3];
73 pseudo_bit_t TestEbp[1];
74 pseudo_bit_t Test[1];
75 pseudo_bit_t Intr[1];
76 pseudo_bit_t StaticRateControlCnt[14];
77 pseudo_bit_t Reserved3[12];
78 pseudo_bit_t Port[1];
79 pseudo_bit_t VLane[3];
80 pseudo_bit_t Reserved4[1];
81 pseudo_bit_t VL15[1];
82 };
83 struct QIB_7322_SendPbc {
84 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbc_pb );
85 };
86
87 /** QIB7322 send buffer availability */
88 struct QIB_7322_SendBufAvail_pb {
89 pseudo_bit_t InUseCheck[162][2];
90 pseudo_bit_t Reserved[60];
91 };
92 struct QIB_7322_SendBufAvail {
93 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail_pb );
94 };
95
96 /** DMA alignment for send buffer availability */
97 #define QIB7322_SENDBUFAVAIL_ALIGN 64
98
99 /** QIB7322 port-specific receive control */
100 struct QIB_7322_RcvCtrl_P_pb {
101 pseudo_bit_t ContextEnable[18];
102 pseudo_bit_t _unused_1[21];
103 pseudo_bit_t RcvIBPortEnable[1];
104 pseudo_bit_t RcvQPMapEnable[1];
105 pseudo_bit_t RcvPartitionKeyDisable[1];
106 pseudo_bit_t RcvResetCredit[1];
107 pseudo_bit_t _unused_2[21];
108 };
109 struct QIB_7322_RcvCtrl_P {
110 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_P_pb );
111 };
112
113 /** A QIB7322 eager receive descriptor */
114 struct QIB_7322_RcvEgr_pb {
115 pseudo_bit_t Addr[37];
116 pseudo_bit_t BufSize[3];
117 pseudo_bit_t Reserved[24];
118 };
119 struct QIB_7322_RcvEgr {
120 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgr_pb );
121 };
122
123 /** QIB7322 receive header flags */
124 struct QIB_7322_RcvHdrFlags_pb {
125 pseudo_bit_t PktLen[11];
126 pseudo_bit_t RcvType[3];
127 pseudo_bit_t SoftB[1];
128 pseudo_bit_t SoftA[1];
129 pseudo_bit_t EgrIndex[12];
130 pseudo_bit_t Reserved1[3];
131 pseudo_bit_t UseEgrBfr[1];
132 pseudo_bit_t RcvSeq[4];
133 pseudo_bit_t HdrqOffset[11];
134 pseudo_bit_t Reserved2[8];
135 pseudo_bit_t IBErr[1];
136 pseudo_bit_t MKErr[1];
137 pseudo_bit_t TIDErr[1];
138 pseudo_bit_t KHdrErr[1];
139 pseudo_bit_t MTUErr[1];
140 pseudo_bit_t LenErr[1];
141 pseudo_bit_t ParityErr[1];
142 pseudo_bit_t VCRCErr[1];
143 pseudo_bit_t ICRCErr[1];
144 };
145 struct QIB_7322_RcvHdrFlags {
146 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrFlags_pb );
147 };
148
149 /** QIB7322 DDS tuning parameters */
150 struct QIB_7322_IBSD_DDS_MAP_TABLE_pb {
151 pseudo_bit_t Pre[3];
152 pseudo_bit_t PreXtra[2];
153 pseudo_bit_t Post[4];
154 pseudo_bit_t Main[5];
155 pseudo_bit_t Amp[4];
156 pseudo_bit_t _unused_0[46];
157 };
158 struct QIB_7322_IBSD_DDS_MAP_TABLE {
159 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_DDS_MAP_TABLE_pb );
160 };
161
162 /** QIB7322 memory BAR size */
163 #define QIB7322_BAR0_SIZE 0x400000
164
165 /** QIB7322 base port number */
166 #define QIB7322_PORT_BASE 1
167
168 /** QIB7322 maximum number of ports */
169 #define QIB7322_MAX_PORTS 2
170
171 /** QIB7322 maximum width */
172 #define QIB7322_MAX_WIDTH 4
173
174 /** QIB7322 board identifiers */
175 enum qib7322_board_id {
176 QIB7322_BOARD_QLE7342_EMULATION = 0,
177 QIB7322_BOARD_QLE7340 = 1,
178 QIB7322_BOARD_QLE7342 = 2,
179 QIB7322_BOARD_QMI7342 = 3,
180 QIB7322_BOARD_QMH7342_UNSUPPORTED = 4,
181 QIB7322_BOARD_QME7342 = 5,
182 QIB7322_BOARD_QMH7342 = 6,
183 QIB7322_BOARD_QLE7342_TEST = 15,
184 };
185
186 /** QIB7322 I2C SCL line GPIO number */
187 #define QIB7322_GPIO_SCL 0
188
189 /** QIB7322 I2C SDA line GPIO number */
190 #define QIB7322_GPIO_SDA 1
191
192 /** GUID offset within EEPROM */
193 #define QIB7322_EEPROM_GUID_OFFSET 3
194
195 /** GUID size within EEPROM */
196 #define QIB7322_EEPROM_GUID_SIZE 8
197
198 /** Board serial number offset within EEPROM */
199 #define QIB7322_EEPROM_SERIAL_OFFSET 12
200
201 /** Board serial number size within EEPROM */
202 #define QIB7322_EEPROM_SERIAL_SIZE 12
203
204 /** QIB7322 small send buffer size */
205 #define QIB7322_SMALL_SEND_BUF_SIZE 4096
206
207 /** QIB7322 small send buffer starting index */
208 #define QIB7322_SMALL_SEND_BUF_START 0
209
210 /** QIB7322 small send buffer count */
211 #define QIB7322_SMALL_SEND_BUF_COUNT 128
212
213 /** QIB7322 large send buffer size */
214 #define QIB7322_LARGE_SEND_BUF_SIZE 8192
215
216 /** QIB7322 large send buffer starting index */
217 #define QIB7322_LARGE_SEND_BUF_START 128
218
219 /** QIB7322 large send buffer count */
220 #define QIB7322_LARGE_SEND_BUF_COUNT 32
221
222 /** QIB7322 VL15 port 0 send buffer starting index */
223 #define QIB7322_VL15_PORT0_SEND_BUF_START 160
224
225 /** QIB7322 VL15 port 0 send buffer count */
226 #define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1
227
228 /** QIB7322 VL15 port 0 send buffer size */
229 #define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192
230
231 /** QIB7322 VL15 port 0 send buffer starting index */
232 #define QIB7322_VL15_PORT1_SEND_BUF_START 161
233
234 /** QIB7322 VL15 port 0 send buffer count */
235 #define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1
236
237 /** QIB7322 VL15 port 0 send buffer size */
238 #define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192
239
240 /** Number of small send buffers used
241 *
242 * This is a policy decision. Must be less than or equal to the total
243 * number of small send buffers supported by the hardware
244 * (QIB7322_SMALL_SEND_BUF_COUNT).
245 */
246 #define QIB7322_SMALL_SEND_BUF_USED 32
247
248 /** Number of contexts (including kernel context)
249 *
250 * This is a policy decision. Must be 6, 10 or 18.
251 */
252 #define QIB7322_NUM_CONTEXTS 6
253
254 /** ContextCfg values for different numbers of contexts */
255 enum qib7322_contextcfg {
256 QIB7322_CONTEXTCFG_6CTX = 0,
257 QIB7322_CONTEXTCFG_10CTX = 1,
258 QIB7322_CONTEXTCFG_18CTX = 2,
259 };
260
261 /** ContextCfg values for different numbers of contexts */
262 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024
263 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096
264 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024
265 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048
266 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024
267 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024
268
269 /** Eager buffer required alignment */
270 #define QIB7322_EAGER_BUFFER_ALIGN 2048
271
272 /** Eager buffer size encodings */
273 enum qib7322_eager_buffer_size {
274 QIB7322_EAGER_BUFFER_NONE = 0,
275 QIB7322_EAGER_BUFFER_2K = 1,
276 QIB7322_EAGER_BUFFER_4K = 2,
277 QIB7322_EAGER_BUFFER_8K = 3,
278 QIB7322_EAGER_BUFFER_16K = 4,
279 QIB7322_EAGER_BUFFER_32K = 5,
280 QIB7322_EAGER_BUFFER_64K = 6,
281 };
282
283 /** Number of RX headers per context
284 *
285 * This is a policy decision.
286 */
287 #define QIB7322_RECV_HEADER_COUNT 8
288
289 /** Maximum size of each RX header
290 *
291 * This is a policy decision. Must be divisible by 4.
292 */
293 #define QIB7322_RECV_HEADER_SIZE 96
294
295 /** Total size of an RX header ring */
296 #define QIB7322_RECV_HEADERS_SIZE \
297 ( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT )
298
299 /** RX header alignment */
300 #define QIB7322_RECV_HEADERS_ALIGN 64
301
302 /** RX payload size
303 *
304 * This is a policy decision. Must be a valid eager buffer size.
305 */
306 #define QIB7322_RECV_PAYLOAD_SIZE 2048
307
308 /** Maximum number of credits per port
309 *
310 * 64kB of internal RX buffer space, in units of 64 bytes, split
311 * between two ports.
312 */
313 #define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS )
314
315 /** Number of credits to advertise for VL15
316 *
317 * This is a policy decision. Using 9 credits allows for 9*64=576
318 * bytes, which is enough for two MADs.
319 */
320 #define QIB7322_MAX_CREDITS_VL15 9
321
322 /** Number of credits to advertise for VL0
323 *
324 * This is a policy decision.
325 */
326 #define QIB7322_MAX_CREDITS_VL0 \
327 ( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 )
328
329 /** QPN used for Infinipath Packets
330 *
331 * This is a policy decision. Must have bit 0 clear. Must not be a
332 * QPN that we will use.
333 */
334 #define QIB7322_QP_IDETH 0xdead0
335
336 /** Maximum time for wait for AHB, in us */
337 #define QIB7322_AHB_MAX_WAIT_US 500
338
339 /** QIB7322 AHB locations */
340 #define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff )
341 #define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 )
342 #define QIB7322_AHB_CHAN_0 0
343 #define QIB7322_AHB_CHAN_1 1
344 #define QIB7322_AHB_PLL 2
345 #define QIB7322_AHB_CHAN_2 3
346 #define QIB7322_AHB_CHAN_3 4
347 #define QIB7322_AHB_SUBSYS 5
348 #define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) )
349 #define QIB7322_AHB_TARGET_0 2
350 #define QIB7322_AHB_TARGET_1 3
351 #define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 )
352 #define QIB7322_AHB_LOCATION( _port, _channel, _register ) \
353 ( ( QIB7322_AHB_TARGET(_port) << 16 ) | \
354 ( QIB7322_AHB_CHAN(_channel) << 7 ) | \
355 ( (_register) << 1 ) )
356
357 /** QIB7322 link states */
358 enum qib7322_link_state {
359 QIB7322_LINK_STATE_DOWN = 0,
360 QIB7322_LINK_STATE_INIT = 1,
361 QIB7322_LINK_STATE_ARM = 2,
362 QIB7322_LINK_STATE_ACTIVE = 3,
363 QIB7322_LINK_STATE_ACT_DEFER = 4,
364 };
365
366 /** Maximum time to wait for link state changes, in us */
367 #define QIB7322_LINK_STATE_MAX_WAIT_US 20
368
369 #endif /* _QIB7322_H */