[efi] Implement the EFI_PXE_BASE_CODE_PROTOCOL
[ipxe.git] / src / drivers / infiniband / qib_7322_regs.h
1 /*
2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */
33
34 /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */
35
36 FILE_LICENCE ( GPL2_ONLY );
37
38 #define QIB_7322_Revision_offset 0x00000000UL
39 struct QIB_7322_Revision_pb {
40 pseudo_bit_t R_ChipRevMinor[8];
41 pseudo_bit_t R_ChipRevMajor[8];
42 pseudo_bit_t R_Arch[8];
43 pseudo_bit_t R_SW[8];
44 pseudo_bit_t BoardID[8];
45 pseudo_bit_t R_Emulation_Revcode[22];
46 pseudo_bit_t R_Emulation[1];
47 pseudo_bit_t R_Simulator[1];
48 };
49 struct QIB_7322_Revision {
50 PSEUDO_BIT_STRUCT ( struct QIB_7322_Revision_pb );
51 };
52 /* Default value: 0x0000000002010601 */
53
54 #define QIB_7322_Control_offset 0x00000008UL
55 struct QIB_7322_Control_pb {
56 pseudo_bit_t SyncReset[1];
57 pseudo_bit_t FreezeMode[1];
58 pseudo_bit_t _unused_0[1];
59 pseudo_bit_t PCIERetryBufDiagEn[1];
60 pseudo_bit_t SDmaDescFetchPriorityEn[1];
61 pseudo_bit_t PCIEPostQDiagEn[1];
62 pseudo_bit_t PCIECplQDiagEn[1];
63 pseudo_bit_t _unused_1[57];
64 };
65 struct QIB_7322_Control {
66 PSEUDO_BIT_STRUCT ( struct QIB_7322_Control_pb );
67 };
68 /* Default value: 0x0000000000000000 */
69
70 #define QIB_7322_PageAlign_offset 0x00000010UL
71 /* Default value: 0x0000000000001000 */
72
73 #define QIB_7322_ContextCnt_offset 0x00000018UL
74 /* Default value: 0x0000000000000012 */
75
76 #define QIB_7322_Scratch_offset 0x00000020UL
77 /* Default value: 0x0000000000000000 */
78
79 #define QIB_7322_CntrRegBase_offset 0x00000028UL
80 /* Default value: 0x0000000000011000 */
81
82 #define QIB_7322_SendRegBase_offset 0x00000030UL
83 /* Default value: 0x0000000000003000 */
84
85 #define QIB_7322_UserRegBase_offset 0x00000038UL
86 /* Default value: 0x0000000000200000 */
87
88 #define QIB_7322_DebugPortSel_offset 0x00000040UL
89 struct QIB_7322_DebugPortSel_pb {
90 pseudo_bit_t DebugOutMuxSel[2];
91 pseudo_bit_t _unused_0[28];
92 pseudo_bit_t SrcMuxSel0[8];
93 pseudo_bit_t SrcMuxSel1[8];
94 pseudo_bit_t DbgClkPortSel[5];
95 pseudo_bit_t EnDbgPort[1];
96 pseudo_bit_t EnEnhancedDebugMode[1];
97 pseudo_bit_t EnhMode_SrcMuxSelIndex[10];
98 pseudo_bit_t EnhMode_SrcMuxSelWrEn[1];
99 };
100 struct QIB_7322_DebugPortSel {
101 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortSel_pb );
102 };
103 /* Default value: 0x0000000000000000 */
104
105 #define QIB_7322_DebugPortNibbleSel_offset 0x00000048UL
106 struct QIB_7322_DebugPortNibbleSel_pb {
107 pseudo_bit_t NibbleSel0[4];
108 pseudo_bit_t NibbleSel1[4];
109 pseudo_bit_t NibbleSel2[4];
110 pseudo_bit_t NibbleSel3[4];
111 pseudo_bit_t NibbleSel4[4];
112 pseudo_bit_t NibbleSel5[4];
113 pseudo_bit_t NibbleSel6[4];
114 pseudo_bit_t NibbleSel7[4];
115 pseudo_bit_t NibbleSel8[4];
116 pseudo_bit_t NibbleSel9[4];
117 pseudo_bit_t NibbleSel10[4];
118 pseudo_bit_t NibbleSel11[4];
119 pseudo_bit_t NibbleSel12[4];
120 pseudo_bit_t NibbleSel13[4];
121 pseudo_bit_t NibbleSel14[4];
122 pseudo_bit_t NibbleSel15[4];
123 };
124 struct QIB_7322_DebugPortNibbleSel {
125 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortNibbleSel_pb );
126 };
127 /* Default value: 0xFEDCBA9876543210 */
128
129 #define QIB_7322_DebugSigsIntSel_offset 0x00000050UL
130 struct QIB_7322_DebugSigsIntSel_pb {
131 pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3];
132 pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3];
133 pseudo_bit_t debug_port_sel_pcs_sdout[1];
134 pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4];
135 pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[3];
136 pseudo_bit_t EnableSDma_SelfDrain[1];
137 pseudo_bit_t debug_port_sel_pcie_rx_tx[1];
138 pseudo_bit_t _unused_0[1];
139 pseudo_bit_t debug_port_sel_tx_ibport[1];
140 pseudo_bit_t debug_port_sel_tx_sdma[1];
141 pseudo_bit_t debug_port_sel_rx_ibport[1];
142 pseudo_bit_t _unused_1[12];
143 pseudo_bit_t debug_port_sel_xgxs_0[4];
144 pseudo_bit_t debug_port_sel_credit_a_0[3];
145 pseudo_bit_t debug_port_sel_credit_b_0[3];
146 pseudo_bit_t debug_port_sel_xgxs_1[4];
147 pseudo_bit_t debug_port_sel_credit_a_1[3];
148 pseudo_bit_t debug_port_sel_credit_b_1[3];
149 pseudo_bit_t _unused_2[12];
150 };
151 struct QIB_7322_DebugSigsIntSel {
152 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugSigsIntSel_pb );
153 };
154 /* Default value: 0x0000000000000000 */
155
156 #define QIB_7322_DebugPortValueReg_offset 0x00000058UL
157
158 #define QIB_7322_IntBlocked_offset 0x00000060UL
159 struct QIB_7322_IntBlocked_pb {
160 pseudo_bit_t RcvAvail0IntBlocked[1];
161 pseudo_bit_t RcvAvail1IntBlocked[1];
162 pseudo_bit_t RcvAvail2IntBlocked[1];
163 pseudo_bit_t RcvAvail3IntBlocked[1];
164 pseudo_bit_t RcvAvail4IntBlocked[1];
165 pseudo_bit_t RcvAvail5IntBlocked[1];
166 pseudo_bit_t RcvAvail6IntBlocked[1];
167 pseudo_bit_t RcvAvail7IntBlocked[1];
168 pseudo_bit_t RcvAvail8IntBlocked[1];
169 pseudo_bit_t RcvAvail9IntBlocked[1];
170 pseudo_bit_t RcvAvail10IntBlocked[1];
171 pseudo_bit_t RcvAvail11IntBlocked[1];
172 pseudo_bit_t RcvAvail12IntBlocked[1];
173 pseudo_bit_t RcvAvail13IntBlocked[1];
174 pseudo_bit_t RcvAvail14IntBlocked[1];
175 pseudo_bit_t RcvAvail15IntBlocked[1];
176 pseudo_bit_t RcvAvail16IntBlocked[1];
177 pseudo_bit_t RcvAvail17IntBlocked[1];
178 pseudo_bit_t _unused_0[5];
179 pseudo_bit_t SendBufAvailIntBlocked[1];
180 pseudo_bit_t SendDoneIntBlocked_0[1];
181 pseudo_bit_t SendDoneIntBlocked_1[1];
182 pseudo_bit_t _unused_1[2];
183 pseudo_bit_t AssertGPIOIntBlocked[1];
184 pseudo_bit_t ErrIntBlocked[1];
185 pseudo_bit_t ErrIntBlocked_0[1];
186 pseudo_bit_t ErrIntBlocked_1[1];
187 pseudo_bit_t RcvUrg0IntBlocked[1];
188 pseudo_bit_t RcvUrg1IntBlocked[1];
189 pseudo_bit_t RcvUrg2IntBlocked[1];
190 pseudo_bit_t RcvUrg3IntBlocked[1];
191 pseudo_bit_t RcvUrg4IntBlocked[1];
192 pseudo_bit_t RcvUrg5IntBlocked[1];
193 pseudo_bit_t RcvUrg6IntBlocked[1];
194 pseudo_bit_t RcvUrg7IntBlocked[1];
195 pseudo_bit_t RcvUrg8IntBlocked[1];
196 pseudo_bit_t RcvUrg9IntBlocked[1];
197 pseudo_bit_t RcvUrg10IntBlocked[1];
198 pseudo_bit_t RcvUrg11IntBlocked[1];
199 pseudo_bit_t RcvUrg12IntBlocked[1];
200 pseudo_bit_t RcvUrg13IntBlocked[1];
201 pseudo_bit_t RcvUrg14IntBlocked[1];
202 pseudo_bit_t RcvUrg15IntBlocked[1];
203 pseudo_bit_t RcvUrg16IntBlocked[1];
204 pseudo_bit_t RcvUrg17IntBlocked[1];
205 pseudo_bit_t _unused_2[6];
206 pseudo_bit_t SDmaCleanupDoneBlocked_0[1];
207 pseudo_bit_t SDmaCleanupDoneBlocked_1[1];
208 pseudo_bit_t SDmaIdleIntBlocked_0[1];
209 pseudo_bit_t SDmaIdleIntBlocked_1[1];
210 pseudo_bit_t SDmaProgressIntBlocked_0[1];
211 pseudo_bit_t SDmaProgressIntBlocked_1[1];
212 pseudo_bit_t SDmaIntBlocked_0[1];
213 pseudo_bit_t SDmaIntBlocked_1[1];
214 };
215 struct QIB_7322_IntBlocked {
216 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntBlocked_pb );
217 };
218 /* Default value: 0x0000000000000000 */
219
220 #define QIB_7322_IntMask_offset 0x00000068UL
221 struct QIB_7322_IntMask_pb {
222 pseudo_bit_t RcvAvail0IntMask[1];
223 pseudo_bit_t RcvAvail1IntMask[1];
224 pseudo_bit_t RcvAvail2IntMask[1];
225 pseudo_bit_t RcvAvail3IntMask[1];
226 pseudo_bit_t RcvAvail4IntMask[1];
227 pseudo_bit_t RcvAvail5IntMask[1];
228 pseudo_bit_t RcvAvail6IntMask[1];
229 pseudo_bit_t RcvAvail7IntMask[1];
230 pseudo_bit_t RcvAvail8IntMask[1];
231 pseudo_bit_t RcvAvail9IntMask[1];
232 pseudo_bit_t RcvAvail10IntMask[1];
233 pseudo_bit_t RcvAvail11IntMask[1];
234 pseudo_bit_t RcvAvail12IntMask[1];
235 pseudo_bit_t RcvAvail13IntMask[1];
236 pseudo_bit_t RcvAvail14IntMask[1];
237 pseudo_bit_t RcvAvail15IntMask[1];
238 pseudo_bit_t RcvAvail16IntMask[1];
239 pseudo_bit_t RcvAvail17IntMask[1];
240 pseudo_bit_t _unused_0[5];
241 pseudo_bit_t SendBufAvailIntMask[1];
242 pseudo_bit_t SendDoneIntMask_0[1];
243 pseudo_bit_t SendDoneIntMask_1[1];
244 pseudo_bit_t _unused_1[2];
245 pseudo_bit_t AssertGPIOIntMask[1];
246 pseudo_bit_t ErrIntMask[1];
247 pseudo_bit_t ErrIntMask_0[1];
248 pseudo_bit_t ErrIntMask_1[1];
249 pseudo_bit_t RcvUrg0IntMask[1];
250 pseudo_bit_t RcvUrg1IntMask[1];
251 pseudo_bit_t RcvUrg2IntMask[1];
252 pseudo_bit_t RcvUrg3IntMask[1];
253 pseudo_bit_t RcvUrg4IntMask[1];
254 pseudo_bit_t RcvUrg5IntMask[1];
255 pseudo_bit_t RcvUrg6IntMask[1];
256 pseudo_bit_t RcvUrg7IntMask[1];
257 pseudo_bit_t RcvUrg8IntMask[1];
258 pseudo_bit_t RcvUrg9IntMask[1];
259 pseudo_bit_t RcvUrg10IntMask[1];
260 pseudo_bit_t RcvUrg11IntMask[1];
261 pseudo_bit_t RcvUrg12IntMask[1];
262 pseudo_bit_t RcvUrg13IntMask[1];
263 pseudo_bit_t RcvUrg14IntMask[1];
264 pseudo_bit_t RcvUrg15IntMask[1];
265 pseudo_bit_t RcvUrg16IntMask[1];
266 pseudo_bit_t RcvUrg17IntMask[1];
267 pseudo_bit_t _unused_2[6];
268 pseudo_bit_t SDmaCleanupDoneMask_0[1];
269 pseudo_bit_t SDmaCleanupDoneMask_1[1];
270 pseudo_bit_t SDmaIdleIntMask_0[1];
271 pseudo_bit_t SDmaIdleIntMask_1[1];
272 pseudo_bit_t SDmaProgressIntMask_0[1];
273 pseudo_bit_t SDmaProgressIntMask_1[1];
274 pseudo_bit_t SDmaIntMask_0[1];
275 pseudo_bit_t SDmaIntMask_1[1];
276 };
277 struct QIB_7322_IntMask {
278 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntMask_pb );
279 };
280 /* Default value: 0x0000000000000000 */
281
282 #define QIB_7322_IntStatus_offset 0x00000070UL
283 struct QIB_7322_IntStatus_pb {
284 pseudo_bit_t RcvAvail0[1];
285 pseudo_bit_t RcvAvail1[1];
286 pseudo_bit_t RcvAvail2[1];
287 pseudo_bit_t RcvAvail3[1];
288 pseudo_bit_t RcvAvail4[1];
289 pseudo_bit_t RcvAvail5[1];
290 pseudo_bit_t RcvAvail6[1];
291 pseudo_bit_t RcvAvail7[1];
292 pseudo_bit_t RcvAvail8[1];
293 pseudo_bit_t RcvAvail9[1];
294 pseudo_bit_t RcvAvail10[1];
295 pseudo_bit_t RcvAvail11[1];
296 pseudo_bit_t RcvAvail12[1];
297 pseudo_bit_t RcvAvail13[1];
298 pseudo_bit_t RcvAvail14[1];
299 pseudo_bit_t RcvAvail15[1];
300 pseudo_bit_t RcvAvail16[1];
301 pseudo_bit_t RcvAvail17[1];
302 pseudo_bit_t _unused_0[5];
303 pseudo_bit_t SendBufAvail[1];
304 pseudo_bit_t SendDone_0[1];
305 pseudo_bit_t SendDone_1[1];
306 pseudo_bit_t _unused_1[2];
307 pseudo_bit_t AssertGPIO[1];
308 pseudo_bit_t Err[1];
309 pseudo_bit_t Err_0[1];
310 pseudo_bit_t Err_1[1];
311 pseudo_bit_t RcvUrg0[1];
312 pseudo_bit_t RcvUrg1[1];
313 pseudo_bit_t RcvUrg2[1];
314 pseudo_bit_t RcvUrg3[1];
315 pseudo_bit_t RcvUrg4[1];
316 pseudo_bit_t RcvUrg5[1];
317 pseudo_bit_t RcvUrg6[1];
318 pseudo_bit_t RcvUrg7[1];
319 pseudo_bit_t RcvUrg8[1];
320 pseudo_bit_t RcvUrg9[1];
321 pseudo_bit_t RcvUrg10[1];
322 pseudo_bit_t RcvUrg11[1];
323 pseudo_bit_t RcvUrg12[1];
324 pseudo_bit_t RcvUrg13[1];
325 pseudo_bit_t RcvUrg14[1];
326 pseudo_bit_t RcvUrg15[1];
327 pseudo_bit_t RcvUrg16[1];
328 pseudo_bit_t RcvUrg17[1];
329 pseudo_bit_t _unused_2[6];
330 pseudo_bit_t SDmaCleanupDone_0[1];
331 pseudo_bit_t SDmaCleanupDone_1[1];
332 pseudo_bit_t SDmaIdleInt_0[1];
333 pseudo_bit_t SDmaIdleInt_1[1];
334 pseudo_bit_t SDmaProgressInt_0[1];
335 pseudo_bit_t SDmaProgressInt_1[1];
336 pseudo_bit_t SDmaInt_0[1];
337 pseudo_bit_t SDmaInt_1[1];
338 };
339 struct QIB_7322_IntStatus {
340 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntStatus_pb );
341 };
342 /* Default value: 0x0000000000000000 */
343
344 #define QIB_7322_IntClear_offset 0x00000078UL
345 struct QIB_7322_IntClear_pb {
346 pseudo_bit_t RcvAvail0IntClear[1];
347 pseudo_bit_t RcvAvail1IntClear[1];
348 pseudo_bit_t RcvAvail2IntClear[1];
349 pseudo_bit_t RcvAvail3IntClear[1];
350 pseudo_bit_t RcvAvail4IntClear[1];
351 pseudo_bit_t RcvAvail5IntClear[1];
352 pseudo_bit_t RcvAvail6IntClear[1];
353 pseudo_bit_t RcvAvail7IntClear[1];
354 pseudo_bit_t RcvAvail8IntClear[1];
355 pseudo_bit_t RcvAvail9IntClear[1];
356 pseudo_bit_t RcvAvail10IntClear[1];
357 pseudo_bit_t RcvAvail11IntClear[1];
358 pseudo_bit_t RcvAvail12IntClear[1];
359 pseudo_bit_t RcvAvail13IntClear[1];
360 pseudo_bit_t RcvAvail14IntClear[1];
361 pseudo_bit_t RcvAvail15IntClear[1];
362 pseudo_bit_t RcvAvail16IntClear[1];
363 pseudo_bit_t RcvAvail17IntClear[1];
364 pseudo_bit_t _unused_0[5];
365 pseudo_bit_t SendBufAvailIntClear[1];
366 pseudo_bit_t SendDoneIntClear_0[1];
367 pseudo_bit_t SendDoneIntClear_1[1];
368 pseudo_bit_t _unused_1[2];
369 pseudo_bit_t AssertGPIOIntClear[1];
370 pseudo_bit_t ErrIntClear[1];
371 pseudo_bit_t ErrIntClear_0[1];
372 pseudo_bit_t ErrIntClear_1[1];
373 pseudo_bit_t RcvUrg0IntClear[1];
374 pseudo_bit_t RcvUrg1IntClear[1];
375 pseudo_bit_t RcvUrg2IntClear[1];
376 pseudo_bit_t RcvUrg3IntClear[1];
377 pseudo_bit_t RcvUrg4IntClear[1];
378 pseudo_bit_t RcvUrg5IntClear[1];
379 pseudo_bit_t RcvUrg6IntClear[1];
380 pseudo_bit_t RcvUrg7IntClear[1];
381 pseudo_bit_t RcvUrg8IntClear[1];
382 pseudo_bit_t RcvUrg9IntClear[1];
383 pseudo_bit_t RcvUrg10IntClear[1];
384 pseudo_bit_t RcvUrg11IntClear[1];
385 pseudo_bit_t RcvUrg12IntClear[1];
386 pseudo_bit_t RcvUrg13IntClear[1];
387 pseudo_bit_t RcvUrg14IntClear[1];
388 pseudo_bit_t RcvUrg15IntClear[1];
389 pseudo_bit_t RcvUrg16IntClear[1];
390 pseudo_bit_t RcvUrg17IntClear[1];
391 pseudo_bit_t _unused_2[6];
392 pseudo_bit_t SDmaCleanupDoneClear_0[1];
393 pseudo_bit_t SDmaCleanupDoneClear_1[1];
394 pseudo_bit_t SDmaIdleIntClear_0[1];
395 pseudo_bit_t SDmaIdleIntClear_1[1];
396 pseudo_bit_t SDmaProgressIntClear_0[1];
397 pseudo_bit_t SDmaProgressIntClear_1[1];
398 pseudo_bit_t SDmaIntClear_0[1];
399 pseudo_bit_t SDmaIntClear_1[1];
400 };
401 struct QIB_7322_IntClear {
402 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntClear_pb );
403 };
404 /* Default value: 0x0000000000000000 */
405
406 #define QIB_7322_ErrMask_offset 0x00000080UL
407 struct QIB_7322_ErrMask_pb {
408 pseudo_bit_t _unused_0[12];
409 pseudo_bit_t RcvEgrFullErrMask[1];
410 pseudo_bit_t RcvHdrFullErrMask[1];
411 pseudo_bit_t _unused_1[11];
412 pseudo_bit_t SDmaBufMaskDuplicateErrMask[1];
413 pseudo_bit_t SDmaWrongPortErrMask[1];
414 pseudo_bit_t SendSpecialTriggerErrMask[1];
415 pseudo_bit_t _unused_2[7];
416 pseudo_bit_t SendArmLaunchErrMask[1];
417 pseudo_bit_t SendVLMismatchErrMask[1];
418 pseudo_bit_t _unused_3[15];
419 pseudo_bit_t RcvContextShareErrMask[1];
420 pseudo_bit_t InvalidEEPCmdMask[1];
421 pseudo_bit_t _unused_4[1];
422 pseudo_bit_t SBufVL15MisUseErrMask[1];
423 pseudo_bit_t SDmaVL15ErrMask[1];
424 pseudo_bit_t _unused_5[4];
425 pseudo_bit_t InvalidAddrErrMask[1];
426 pseudo_bit_t HardwareErrMask[1];
427 pseudo_bit_t ResetNegatedMask[1];
428 };
429 struct QIB_7322_ErrMask {
430 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_pb );
431 };
432 /* Default value: 0x0000000000000000 */
433
434 #define QIB_7322_ErrStatus_offset 0x00000088UL
435 struct QIB_7322_ErrStatus_pb {
436 pseudo_bit_t _unused_0[12];
437 pseudo_bit_t RcvEgrFullErr[1];
438 pseudo_bit_t RcvHdrFullErr[1];
439 pseudo_bit_t _unused_1[11];
440 pseudo_bit_t SDmaBufMaskDuplicateErr[1];
441 pseudo_bit_t SDmaWrongPortErr[1];
442 pseudo_bit_t SendSpecialTriggerErr[1];
443 pseudo_bit_t _unused_2[7];
444 pseudo_bit_t SendArmLaunchErr[1];
445 pseudo_bit_t SendVLMismatchErr[1];
446 pseudo_bit_t _unused_3[15];
447 pseudo_bit_t RcvContextShareErr[1];
448 pseudo_bit_t InvalidEEPCmdErr[1];
449 pseudo_bit_t _unused_4[1];
450 pseudo_bit_t SBufVL15MisUseErr[1];
451 pseudo_bit_t SDmaVL15Err[1];
452 pseudo_bit_t _unused_5[4];
453 pseudo_bit_t InvalidAddrErr[1];
454 pseudo_bit_t HardwareErr[1];
455 pseudo_bit_t ResetNegated[1];
456 };
457 struct QIB_7322_ErrStatus {
458 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_pb );
459 };
460 /* Default value: 0x0000000000000000 */
461
462 #define QIB_7322_ErrClear_offset 0x00000090UL
463 struct QIB_7322_ErrClear_pb {
464 pseudo_bit_t _unused_0[12];
465 pseudo_bit_t RcvEgrFullErrClear[1];
466 pseudo_bit_t RcvHdrFullErrClear[1];
467 pseudo_bit_t _unused_1[11];
468 pseudo_bit_t SDmaBufMaskDuplicateErrClear[1];
469 pseudo_bit_t SDmaWrongPortErrClear[1];
470 pseudo_bit_t SendSpecialTriggerErrClear[1];
471 pseudo_bit_t _unused_2[7];
472 pseudo_bit_t SendArmLaunchErrClear[1];
473 pseudo_bit_t SendVLMismatchErrMask[1];
474 pseudo_bit_t _unused_3[15];
475 pseudo_bit_t RcvContextShareErrClear[1];
476 pseudo_bit_t InvalidEEPCmdErrClear[1];
477 pseudo_bit_t _unused_4[1];
478 pseudo_bit_t SBufVL15MisUseErrClear[1];
479 pseudo_bit_t SDmaVL15ErrClear[1];
480 pseudo_bit_t _unused_5[4];
481 pseudo_bit_t InvalidAddrErrClear[1];
482 pseudo_bit_t HardwareErrClear[1];
483 pseudo_bit_t ResetNegatedClear[1];
484 };
485 struct QIB_7322_ErrClear {
486 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_pb );
487 };
488 /* Default value: 0x0000000000000000 */
489
490 #define QIB_7322_HwErrMask_offset 0x00000098UL
491 struct QIB_7322_HwErrMask_pb {
492 pseudo_bit_t _unused_0[11];
493 pseudo_bit_t LATriggeredMask[1];
494 pseudo_bit_t statusValidNoEopMask_0[1];
495 pseudo_bit_t IBCBusFromSPCParityErrMask_0[1];
496 pseudo_bit_t statusValidNoEopMask_1[1];
497 pseudo_bit_t IBCBusFromSPCParityErrMask_1[1];
498 pseudo_bit_t _unused_1[11];
499 pseudo_bit_t SDmaMemReadErrMask_0[1];
500 pseudo_bit_t SDmaMemReadErrMask_1[1];
501 pseudo_bit_t PciePoisonedTLPMask[1];
502 pseudo_bit_t PcieCplTimeoutMask[1];
503 pseudo_bit_t PCIeBusParityErrMask[3];
504 pseudo_bit_t pcie_phy_txParityErr[1];
505 pseudo_bit_t _unused_2[13];
506 pseudo_bit_t MemoryErrMask[1];
507 pseudo_bit_t _unused_3[4];
508 pseudo_bit_t TempsenseTholdReachedMask[1];
509 pseudo_bit_t PowerOnBISTFailedMask[1];
510 pseudo_bit_t PCIESerdesPClkNotDetectMask[1];
511 pseudo_bit_t _unused_4[6];
512 pseudo_bit_t IBSerdesPClkNotDetectMask_0[1];
513 pseudo_bit_t IBSerdesPClkNotDetectMask_1[1];
514 };
515 struct QIB_7322_HwErrMask {
516 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrMask_pb );
517 };
518 /* Default value: 0x0000000000000000 */
519
520 #define QIB_7322_HwErrStatus_offset 0x000000a0UL
521 struct QIB_7322_HwErrStatus_pb {
522 pseudo_bit_t _unused_0[11];
523 pseudo_bit_t LATriggered[1];
524 pseudo_bit_t statusValidNoEop_0[1];
525 pseudo_bit_t IBCBusFromSPCParityErr_0[1];
526 pseudo_bit_t statusValidNoEop_1[1];
527 pseudo_bit_t IBCBusFromSPCParityErr_1[1];
528 pseudo_bit_t _unused_1[11];
529 pseudo_bit_t SDmaMemReadErr_0[1];
530 pseudo_bit_t SDmaMemReadErr_1[1];
531 pseudo_bit_t PciePoisonedTLP[1];
532 pseudo_bit_t PcieCplTimeout[1];
533 pseudo_bit_t PCIeBusParity[3];
534 pseudo_bit_t pcie_phy_txParityErr[1];
535 pseudo_bit_t _unused_2[13];
536 pseudo_bit_t MemoryErr[1];
537 pseudo_bit_t _unused_3[4];
538 pseudo_bit_t TempsenseTholdReached[1];
539 pseudo_bit_t PowerOnBISTFailed[1];
540 pseudo_bit_t PCIESerdesPClkNotDetect[1];
541 pseudo_bit_t _unused_4[6];
542 pseudo_bit_t IBSerdesPClkNotDetect_0[1];
543 pseudo_bit_t IBSerdesPClkNotDetect_1[1];
544 };
545 struct QIB_7322_HwErrStatus {
546 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrStatus_pb );
547 };
548 /* Default value: 0x0000000000000000 */
549
550 #define QIB_7322_HwErrClear_offset 0x000000a8UL
551 struct QIB_7322_HwErrClear_pb {
552 pseudo_bit_t _unused_0[11];
553 pseudo_bit_t LATriggeredClear[1];
554 pseudo_bit_t IBCBusToSPCparityErrClear_0[1];
555 pseudo_bit_t IBCBusFromSPCParityErrClear_0[1];
556 pseudo_bit_t IBCBusToSPCparityErrClear_1[1];
557 pseudo_bit_t IBCBusFromSPCParityErrClear_1[1];
558 pseudo_bit_t _unused_1[11];
559 pseudo_bit_t SDmaMemReadErrClear_0[1];
560 pseudo_bit_t SDmaMemReadErrClear_1[1];
561 pseudo_bit_t PciePoisonedTLPClear[1];
562 pseudo_bit_t PcieCplTimeoutClear[1];
563 pseudo_bit_t PCIeBusParityClear[3];
564 pseudo_bit_t pcie_phy_txParityErr[1];
565 pseudo_bit_t _unused_2[13];
566 pseudo_bit_t MemoryErrClear[1];
567 pseudo_bit_t _unused_3[4];
568 pseudo_bit_t TempsenseTholdReachedClear[1];
569 pseudo_bit_t PowerOnBISTFailedClear[1];
570 pseudo_bit_t PCIESerdesPClkNotDetectClear[1];
571 pseudo_bit_t _unused_4[6];
572 pseudo_bit_t IBSerdesPClkNotDetectClear_0[1];
573 pseudo_bit_t IBSerdesPClkNotDetectClear_1[1];
574 };
575 struct QIB_7322_HwErrClear {
576 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrClear_pb );
577 };
578 /* Default value: 0x0000000000000000 */
579
580 #define QIB_7322_HwDiagCtrl_offset 0x000000b0UL
581 struct QIB_7322_HwDiagCtrl_pb {
582 pseudo_bit_t _unused_0[12];
583 pseudo_bit_t ForcestatusValidNoEop_0[1];
584 pseudo_bit_t ForceIBCBusFromSPCParityErr_0[1];
585 pseudo_bit_t ForcestatusValidNoEop_1[1];
586 pseudo_bit_t ForceIBCBusFromSPCParityErr_1[1];
587 pseudo_bit_t _unused_1[15];
588 pseudo_bit_t forcePCIeBusParity[4];
589 pseudo_bit_t _unused_2[25];
590 pseudo_bit_t CounterDisable[1];
591 pseudo_bit_t CounterWrEnable[1];
592 pseudo_bit_t _unused_3[1];
593 pseudo_bit_t Diagnostic[1];
594 };
595 struct QIB_7322_HwDiagCtrl {
596 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwDiagCtrl_pb );
597 };
598 /* Default value: 0x0000000000000000 */
599
600 #define QIB_7322_EXTStatus_offset 0x000000c0UL
601 struct QIB_7322_EXTStatus_pb {
602 pseudo_bit_t _unused_0[14];
603 pseudo_bit_t MemBISTEndTest[1];
604 pseudo_bit_t MemBISTDisabled[1];
605 pseudo_bit_t _unused_1[32];
606 pseudo_bit_t GPIOIn[16];
607 };
608 struct QIB_7322_EXTStatus {
609 PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTStatus_pb );
610 };
611 /* Default value: 0x000000000000X000 */
612
613 #define QIB_7322_EXTCtrl_offset 0x000000c8UL
614 struct QIB_7322_EXTCtrl_pb {
615 pseudo_bit_t LEDPort0YellowOn[1];
616 pseudo_bit_t LEDPort0GreenOn[1];
617 pseudo_bit_t LEDPort1YellowOn[1];
618 pseudo_bit_t LEDPort1GreenOn[1];
619 pseudo_bit_t _unused_0[28];
620 pseudo_bit_t GPIOInvert[16];
621 pseudo_bit_t GPIOOe[16];
622 };
623 struct QIB_7322_EXTCtrl {
624 PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTCtrl_pb );
625 };
626 /* Default value: 0x0000000000000000 */
627
628 #define QIB_7322_GPIODebugSelReg_offset 0x000000d8UL
629 struct QIB_7322_GPIODebugSelReg_pb {
630 pseudo_bit_t GPIOSourceSelDebug[16];
631 pseudo_bit_t SelPulse[16];
632 pseudo_bit_t _unused_0[32];
633 };
634 struct QIB_7322_GPIODebugSelReg {
635 PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIODebugSelReg_pb );
636 };
637 /* Default value: 0x0000000000000000 */
638
639 #define QIB_7322_GPIOOut_offset 0x000000e0UL
640 /* Default value: 0x0000000000000000 */
641
642 #define QIB_7322_GPIOMask_offset 0x000000e8UL
643 /* Default value: 0x0000000000000000 */
644
645 #define QIB_7322_GPIOStatus_offset 0x000000f0UL
646 /* Default value: 0x0000000000000000 */
647
648 #define QIB_7322_GPIOClear_offset 0x000000f8UL
649 /* Default value: 0x0000000000000000 */
650
651 #define QIB_7322_RcvCtrl_offset 0x00000100UL
652 struct QIB_7322_RcvCtrl_pb {
653 pseudo_bit_t dontDropRHQFull[18];
654 pseudo_bit_t _unused_0[2];
655 pseudo_bit_t IntrAvail[18];
656 pseudo_bit_t _unused_1[3];
657 pseudo_bit_t ContextCfg[2];
658 pseudo_bit_t TidFlowEnable[1];
659 pseudo_bit_t XrcTypeCode[3];
660 pseudo_bit_t TailUpd[1];
661 pseudo_bit_t TidReDirect[16];
662 };
663 struct QIB_7322_RcvCtrl {
664 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_pb );
665 };
666 /* Default value: 0x0000000000000000 */
667
668 #define QIB_7322_RcvHdrSize_offset 0x00000110UL
669 /* Default value: 0x0000000000000000 */
670
671 #define QIB_7322_RcvHdrCnt_offset 0x00000118UL
672 /* Default value: 0x0000000000000000 */
673
674 #define QIB_7322_RcvHdrEntSize_offset 0x00000120UL
675 /* Default value: 0x0000000000000000 */
676
677 #define QIB_7322_RcvTIDBase_offset 0x00000128UL
678 /* Default value: 0x0000000000050000 */
679
680 #define QIB_7322_RcvTIDCnt_offset 0x00000130UL
681 /* Default value: 0x0000000000000200 */
682
683 #define QIB_7322_RcvEgrBase_offset 0x00000138UL
684 /* Default value: 0x0000000000014000 */
685
686 #define QIB_7322_RcvEgrCnt_offset 0x00000140UL
687 /* Default value: 0x0000000000001000 */
688
689 #define QIB_7322_RcvBufBase_offset 0x00000148UL
690 /* Default value: 0x0000000000080000 */
691
692 #define QIB_7322_RcvBufSize_offset 0x00000150UL
693 /* Default value: 0x0000000000005000 */
694
695 #define QIB_7322_RxIntMemBase_offset 0x00000158UL
696 /* Default value: 0x0000000000077000 */
697
698 #define QIB_7322_RxIntMemSize_offset 0x00000160UL
699 /* Default value: 0x0000000000007000 */
700
701 #define QIB_7322_encryption_key_low_offset 0x00000180UL
702 /* Default value: 0x0000000000000000 */
703
704 #define QIB_7322_encryption_key_high_offset 0x00000188UL
705 /* Default value: 0x0000000000000000 */
706
707 #define QIB_7322_feature_mask_offset 0x00000190UL
708 /* Default value: 0x00000000000000XX */
709
710 #define QIB_7322_active_feature_mask_offset 0x00000198UL
711 struct QIB_7322_active_feature_mask_pb {
712 pseudo_bit_t Port0_SDR_Enabled[1];
713 pseudo_bit_t Port0_DDR_Enabled[1];
714 pseudo_bit_t Port0_QDR_Enabled[1];
715 pseudo_bit_t Port1_SDR_Enabled[1];
716 pseudo_bit_t Port1_DDR_Enabled[1];
717 pseudo_bit_t Port1_QDR_Enabled[1];
718 pseudo_bit_t _unused_0[58];
719 };
720 struct QIB_7322_active_feature_mask {
721 PSEUDO_BIT_STRUCT ( struct QIB_7322_active_feature_mask_pb );
722 };
723 /* Default value: 0x00000000000000XX */
724
725 #define QIB_7322_SendCtrl_offset 0x000001c0UL
726 struct QIB_7322_SendCtrl_pb {
727 pseudo_bit_t _unused_0[1];
728 pseudo_bit_t SendIntBufAvail[1];
729 pseudo_bit_t SendBufAvailUpd[1];
730 pseudo_bit_t _unused_1[1];
731 pseudo_bit_t SpecialTriggerEn[1];
732 pseudo_bit_t _unused_2[11];
733 pseudo_bit_t DisarmSendBuf[8];
734 pseudo_bit_t AvailUpdThld[5];
735 pseudo_bit_t SendBufAvailPad64Byte[1];
736 pseudo_bit_t _unused_3[1];
737 pseudo_bit_t Disarm[1];
738 pseudo_bit_t _unused_4[32];
739 };
740 struct QIB_7322_SendCtrl {
741 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_pb );
742 };
743 /* Default value: 0x0000000000000000 */
744
745 #define QIB_7322_SendBufBase_offset 0x000001c8UL
746 struct QIB_7322_SendBufBase_pb {
747 pseudo_bit_t BaseAddr_SmallPIO[21];
748 pseudo_bit_t _unused_0[11];
749 pseudo_bit_t BaseAddr_LargePIO[21];
750 pseudo_bit_t _unused_1[11];
751 };
752 struct QIB_7322_SendBufBase {
753 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufBase_pb );
754 };
755 /* Default value: 0x0018000000100000 */
756
757 #define QIB_7322_SendBufSize_offset 0x000001d0UL
758 struct QIB_7322_SendBufSize_pb {
759 pseudo_bit_t Size_SmallPIO[12];
760 pseudo_bit_t _unused_0[20];
761 pseudo_bit_t Size_LargePIO[13];
762 pseudo_bit_t _unused_1[19];
763 };
764 struct QIB_7322_SendBufSize {
765 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufSize_pb );
766 };
767 /* Default value: 0x0000108000000880 */
768
769 #define QIB_7322_SendBufCnt_offset 0x000001d8UL
770 struct QIB_7322_SendBufCnt_pb {
771 pseudo_bit_t Num_SmallBuffers[9];
772 pseudo_bit_t _unused_0[23];
773 pseudo_bit_t Num_LargeBuffers[6];
774 pseudo_bit_t _unused_1[26];
775 };
776 struct QIB_7322_SendBufCnt {
777 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufCnt_pb );
778 };
779 /* Default value: 0x0000002000000080 */
780
781 #define QIB_7322_SendBufAvailAddr_offset 0x000001e0UL
782 struct QIB_7322_SendBufAvailAddr_pb {
783 pseudo_bit_t _unused_0[6];
784 pseudo_bit_t SendBufAvailAddr[34];
785 pseudo_bit_t _unused_1[24];
786 };
787 struct QIB_7322_SendBufAvailAddr {
788 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvailAddr_pb );
789 };
790 /* Default value: 0x0000000000000000 */
791
792 #define QIB_7322_TxIntMemBase_offset 0x000001e8UL
793 /* Default value: 0x0000000000064000 */
794
795 #define QIB_7322_TxIntMemSize_offset 0x000001f0UL
796 /* Default value: 0x000000000000C000 */
797
798 #define QIB_7322_SendBufErr0_offset 0x00000240UL
799 struct QIB_7322_SendBufErr0_pb {
800 pseudo_bit_t SendBufErr_63_0[64];
801 };
802 struct QIB_7322_SendBufErr0 {
803 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufErr0_pb );
804 };
805 /* Default value: 0x0000000000000000 */
806
807 #define QIB_7322_AvailUpdCount_offset 0x00000268UL
808 struct QIB_7322_AvailUpdCount_pb {
809 pseudo_bit_t AvailUpdCount[5];
810 pseudo_bit_t _unused_0[59];
811 };
812 struct QIB_7322_AvailUpdCount {
813 PSEUDO_BIT_STRUCT ( struct QIB_7322_AvailUpdCount_pb );
814 };
815 /* Default value: 0x0000000000000000 */
816
817 #define QIB_7322_RcvHdrAddr0_offset 0x00000280UL
818 struct QIB_7322_RcvHdrAddr0_pb {
819 pseudo_bit_t _unused_0[2];
820 pseudo_bit_t RcvHdrAddr[38];
821 pseudo_bit_t _unused_1[24];
822 };
823 struct QIB_7322_RcvHdrAddr0 {
824 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrAddr0_pb );
825 };
826 /* Default value: 0x0000000000000000 */
827
828 #define QIB_7322_RcvHdrTailAddr0_offset 0x00000340UL
829 struct QIB_7322_RcvHdrTailAddr0_pb {
830 pseudo_bit_t _unused_0[2];
831 pseudo_bit_t RcvHdrTailAddr[38];
832 pseudo_bit_t _unused_1[24];
833 };
834 struct QIB_7322_RcvHdrTailAddr0 {
835 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrTailAddr0_pb );
836 };
837 /* Default value: 0x0000000000000000 */
838
839 #define QIB_7322_EEPCtlStat_offset 0x000003e8UL
840 struct QIB_7322_EEPCtlStat_pb {
841 pseudo_bit_t EPAccEn[2];
842 pseudo_bit_t EPReset[1];
843 pseudo_bit_t ByteProg[1];
844 pseudo_bit_t PageMode[1];
845 pseudo_bit_t LstDatWr[1];
846 pseudo_bit_t CmdWrErr[1];
847 pseudo_bit_t _unused_0[24];
848 pseudo_bit_t CtlrStat[1];
849 pseudo_bit_t _unused_1[32];
850 };
851 struct QIB_7322_EEPCtlStat {
852 PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPCtlStat_pb );
853 };
854 /* Default value: 0x0000000000000002 */
855
856 #define QIB_7322_EEPAddrCmd_offset 0x000003f0UL
857 struct QIB_7322_EEPAddrCmd_pb {
858 pseudo_bit_t EPAddr[24];
859 pseudo_bit_t EPCmd[8];
860 pseudo_bit_t _unused_0[32];
861 };
862 struct QIB_7322_EEPAddrCmd {
863 PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPAddrCmd_pb );
864 };
865 /* Default value: 0x0000000000000000 */
866
867 #define QIB_7322_EEPData_offset 0x000003f8UL
868 /* Default value: 0x0000000000000000 */
869
870 #define QIB_7322_efuse_control_reg_offset 0x00000410UL
871 struct QIB_7322_efuse_control_reg_pb {
872 pseudo_bit_t address[11];
873 pseudo_bit_t last_program_address[11];
874 pseudo_bit_t operation[2];
875 pseudo_bit_t start_operation[1];
876 pseudo_bit_t _unused_0[4];
877 pseudo_bit_t req_err[1];
878 pseudo_bit_t read_data_valid[1];
879 pseudo_bit_t rdy[1];
880 pseudo_bit_t _unused_1[32];
881 };
882 struct QIB_7322_efuse_control_reg {
883 PSEUDO_BIT_STRUCT ( struct QIB_7322_efuse_control_reg_pb );
884 };
885 /* Default value: 0x0000000080000000 */
886
887 #define QIB_7322_efuse_data_reg_offset 0x00000418UL
888 /* Default value: 0x0000000000000000 */
889
890 #define QIB_7322_voltage_margin_reg_offset 0x00000428UL
891 struct QIB_7322_voltage_margin_reg_pb {
892 pseudo_bit_t voltage_margin_settings_enable[1];
893 pseudo_bit_t voltage_margin_settings[2];
894 pseudo_bit_t _unused_0[61];
895 };
896 struct QIB_7322_voltage_margin_reg {
897 PSEUDO_BIT_STRUCT ( struct QIB_7322_voltage_margin_reg_pb );
898 };
899 /* Default value: 0x0000000000000000 */
900
901 #define QIB_7322_VTSense_reg_offset 0x00000430UL
902 struct QIB_7322_VTSense_reg_pb {
903 pseudo_bit_t temp_sense_select[3];
904 pseudo_bit_t adc_mode[1];
905 pseudo_bit_t start_busy[1];
906 pseudo_bit_t power_down[1];
907 pseudo_bit_t threshold[10];
908 pseudo_bit_t sensor_output_data[10];
909 pseudo_bit_t _unused_0[1];
910 pseudo_bit_t threshold_limbit[1];
911 pseudo_bit_t _unused_1[3];
912 pseudo_bit_t output_valid[1];
913 pseudo_bit_t _unused_2[32];
914 };
915 struct QIB_7322_VTSense_reg {
916 PSEUDO_BIT_STRUCT ( struct QIB_7322_VTSense_reg_pb );
917 };
918 /* Default value: 0x0000000000000020 */
919
920 #define QIB_7322_procmon_reg_offset 0x00000438UL
921 struct QIB_7322_procmon_reg_pb {
922 pseudo_bit_t ring_osc_select[3];
923 pseudo_bit_t _unused_0[12];
924 pseudo_bit_t start_counter[1];
925 pseudo_bit_t procmon_count[12];
926 pseudo_bit_t _unused_1[3];
927 pseudo_bit_t procmon_count_valid[1];
928 pseudo_bit_t _unused_2[32];
929 };
930 struct QIB_7322_procmon_reg {
931 PSEUDO_BIT_STRUCT ( struct QIB_7322_procmon_reg_pb );
932 };
933 /* Default value: 0x0000000000000000 */
934
935 #define QIB_7322_PcieRbufTestReg0_offset 0x00000440UL
936 /* Default value: 0x0000000000000000 */
937
938 #define QIB_7322_ahb_access_ctrl_offset 0x00000460UL
939 struct QIB_7322_ahb_access_ctrl_pb {
940 pseudo_bit_t sw_ahb_sel[1];
941 pseudo_bit_t sw_sel_ahb_trgt[2];
942 pseudo_bit_t _unused_0[61];
943 };
944 struct QIB_7322_ahb_access_ctrl {
945 PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_access_ctrl_pb );
946 };
947 /* Default value: 0x0000000000000000 */
948
949 #define QIB_7322_ahb_transaction_reg_offset 0x00000468UL
950 struct QIB_7322_ahb_transaction_reg_pb {
951 pseudo_bit_t _unused_0[16];
952 pseudo_bit_t ahb_address[11];
953 pseudo_bit_t write_not_read[1];
954 pseudo_bit_t _unused_1[2];
955 pseudo_bit_t ahb_req_err[1];
956 pseudo_bit_t ahb_rdy[1];
957 pseudo_bit_t ahb_data[32];
958 };
959 struct QIB_7322_ahb_transaction_reg {
960 PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_transaction_reg_pb );
961 };
962 /* Default value: 0x0000000080000000 */
963
964 #define QIB_7322_SPC_JTAG_ACCESS_REG_offset 0x00000470UL
965 struct QIB_7322_SPC_JTAG_ACCESS_REG_pb {
966 pseudo_bit_t rdy[1];
967 pseudo_bit_t tdo[1];
968 pseudo_bit_t tdi[1];
969 pseudo_bit_t opcode[2];
970 pseudo_bit_t bist_en[5];
971 pseudo_bit_t SPC_JTAG_ACCESS_EN[1];
972 pseudo_bit_t _unused_0[53];
973 };
974 struct QIB_7322_SPC_JTAG_ACCESS_REG {
975 PSEUDO_BIT_STRUCT ( struct QIB_7322_SPC_JTAG_ACCESS_REG_pb );
976 };
977 /* Default value: 0x0000000000000001 */
978
979 #define QIB_7322_LAControlReg_offset 0x00000478UL
980 struct QIB_7322_LAControlReg_pb {
981 pseudo_bit_t Finished[1];
982 pseudo_bit_t Address[9];
983 pseudo_bit_t Mode[2];
984 pseudo_bit_t Delay[20];
985 pseudo_bit_t Finished_sc[1];
986 pseudo_bit_t Address_sc[9];
987 pseudo_bit_t Mode_sc[2];
988 pseudo_bit_t Delay_sc[20];
989 };
990 struct QIB_7322_LAControlReg {
991 PSEUDO_BIT_STRUCT ( struct QIB_7322_LAControlReg_pb );
992 };
993 /* Default value: 0x0000000100000001 */
994
995 #define QIB_7322_PcieRhdrTestReg0_offset 0x00000480UL
996 /* Default value: 0x0000000000000000 */
997
998 #define QIB_7322_SendCheckMask0_offset 0x000004c0UL
999 struct QIB_7322_SendCheckMask0_pb {
1000 pseudo_bit_t SendCheckMask_63_32[64];
1001 };
1002 struct QIB_7322_SendCheckMask0 {
1003 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckMask0_pb );
1004 };
1005 /* Default value: 0x0000000000000000 */
1006
1007 #define QIB_7322_SendGRHCheckMask0_offset 0x000004e0UL
1008 struct QIB_7322_SendGRHCheckMask0_pb {
1009 pseudo_bit_t SendGRHCheckMask_63_32[64];
1010 };
1011 struct QIB_7322_SendGRHCheckMask0 {
1012 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendGRHCheckMask0_pb );
1013 };
1014 /* Default value: 0x0000000000000000 */
1015
1016 #define QIB_7322_SendIBPacketMask0_offset 0x00000500UL
1017 struct QIB_7322_SendIBPacketMask0_pb {
1018 pseudo_bit_t SendIBPacketMask_63_32[64];
1019 };
1020 struct QIB_7322_SendIBPacketMask0 {
1021 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBPacketMask0_pb );
1022 };
1023 /* Default value: 0x0000000000000000 */
1024
1025 #define QIB_7322_IntRedirect0_offset 0x00000540UL
1026 struct QIB_7322_IntRedirect0_pb {
1027 pseudo_bit_t vec0[5];
1028 pseudo_bit_t vec1[5];
1029 pseudo_bit_t vec2[5];
1030 pseudo_bit_t vec3[5];
1031 pseudo_bit_t vec4[5];
1032 pseudo_bit_t vec5[5];
1033 pseudo_bit_t vec6[5];
1034 pseudo_bit_t vec7[5];
1035 pseudo_bit_t vec8[5];
1036 pseudo_bit_t vec9[5];
1037 pseudo_bit_t vec10[5];
1038 pseudo_bit_t vec11[5];
1039 pseudo_bit_t _unused_0[4];
1040 };
1041 struct QIB_7322_IntRedirect0 {
1042 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntRedirect0_pb );
1043 };
1044 /* Default value: 0x0000000000000000 */
1045
1046 #define QIB_7322_Int_Granted_offset 0x00000570UL
1047 /* Default value: 0x0000000000000000 */
1048
1049 #define QIB_7322_vec_clr_without_int_offset 0x00000578UL
1050 /* Default value: 0x0000000000000000 */
1051
1052 #define QIB_7322_DCACtrlA_offset 0x00000580UL
1053 struct QIB_7322_DCACtrlA_pb {
1054 pseudo_bit_t RcvHdrqDCAEnable[1];
1055 pseudo_bit_t EagerDCAEnable[1];
1056 pseudo_bit_t RcvTailUpdDCAEnable[1];
1057 pseudo_bit_t SendDMAHead0DCAEnable[1];
1058 pseudo_bit_t SendDMAHead1DCAEnable[1];
1059 pseudo_bit_t _unused_0[59];
1060 };
1061 struct QIB_7322_DCACtrlA {
1062 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlA_pb );
1063 };
1064 /* Default value: 0x0000000000000000 */
1065
1066 #define QIB_7322_DCACtrlB_offset 0x00000588UL
1067 struct QIB_7322_DCACtrlB_pb {
1068 pseudo_bit_t RcvHdrq0DCAOPH[8];
1069 pseudo_bit_t RcvHdrq0DCAXfrCnt[6];
1070 pseudo_bit_t RcvHdrq1DCAOPH[8];
1071 pseudo_bit_t RcvHdrq1DCAXfrCnt[6];
1072 pseudo_bit_t _unused_0[4];
1073 pseudo_bit_t RcvHdrq2DCAOPH[8];
1074 pseudo_bit_t RcvHdrq2DCAXfrCnt[6];
1075 pseudo_bit_t RcvHdrq3DCAOPH[8];
1076 pseudo_bit_t RcvHdrq3DCAXfrCnt[6];
1077 pseudo_bit_t _unused_1[4];
1078 };
1079 struct QIB_7322_DCACtrlB {
1080 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlB_pb );
1081 };
1082 /* Default value: 0x0000000000000000 */
1083
1084 #define QIB_7322_DCACtrlC_offset 0x00000590UL
1085 struct QIB_7322_DCACtrlC_pb {
1086 pseudo_bit_t RcvHdrq4DCAOPH[8];
1087 pseudo_bit_t RcvHdrq4DCAXfrCnt[6];
1088 pseudo_bit_t RcvHdrq5DCAOPH[8];
1089 pseudo_bit_t RcvHdrq5DCAXfrCnt[6];
1090 pseudo_bit_t _unused_0[4];
1091 pseudo_bit_t RcvHdrq6DCAOPH[8];
1092 pseudo_bit_t RcvHdrq6DCAXfrCnt[6];
1093 pseudo_bit_t RcvHdrq7DCAOPH[8];
1094 pseudo_bit_t RcvHdrq7DCAXfrCnt[6];
1095 pseudo_bit_t _unused_1[4];
1096 };
1097 struct QIB_7322_DCACtrlC {
1098 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlC_pb );
1099 };
1100 /* Default value: 0x0000000000000000 */
1101
1102 #define QIB_7322_DCACtrlD_offset 0x00000598UL
1103 struct QIB_7322_DCACtrlD_pb {
1104 pseudo_bit_t RcvHdrq8DCAOPH[8];
1105 pseudo_bit_t RcvHdrq8DCAXfrCnt[6];
1106 pseudo_bit_t RcvHdrq9DCAOPH[8];
1107 pseudo_bit_t RcvHdrq9DCAXfrCnt[6];
1108 pseudo_bit_t _unused_0[4];
1109 pseudo_bit_t RcvHdrq10DCAOPH[8];
1110 pseudo_bit_t RcvHdrq10DCAXfrCnt[6];
1111 pseudo_bit_t RcvHdrq11DCAOPH[8];
1112 pseudo_bit_t RcvHdrq11DCAXfrCnt[6];
1113 pseudo_bit_t _unused_1[4];
1114 };
1115 struct QIB_7322_DCACtrlD {
1116 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlD_pb );
1117 };
1118 /* Default value: 0x0000000000000000 */
1119
1120 #define QIB_7322_DCACtrlE_offset 0x000005a0UL
1121 struct QIB_7322_DCACtrlE_pb {
1122 pseudo_bit_t RcvHdrq12DCAOPH[8];
1123 pseudo_bit_t RcvHdrq12DCAXfrCnt[6];
1124 pseudo_bit_t RcvHdrq13DCAOPH[8];
1125 pseudo_bit_t RcvHdrq13DCAXfrCnt[6];
1126 pseudo_bit_t _unused_0[4];
1127 pseudo_bit_t RcvHdrq14DCAOPH[8];
1128 pseudo_bit_t RcvHdrq14DCAXfrCnt[6];
1129 pseudo_bit_t RcvHdrq15DCAOPH[8];
1130 pseudo_bit_t RcvHdrq15DCAXfrCnt[6];
1131 pseudo_bit_t _unused_1[4];
1132 };
1133 struct QIB_7322_DCACtrlE {
1134 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlE_pb );
1135 };
1136 /* Default value: 0x0000000000000000 */
1137
1138 #define QIB_7322_DCACtrlF_offset 0x000005a8UL
1139 struct QIB_7322_DCACtrlF_pb {
1140 pseudo_bit_t RcvHdrq16DCAOPH[8];
1141 pseudo_bit_t RcvHdrq16DCAXfrCnt[6];
1142 pseudo_bit_t RcvHdrq17DCAOPH[8];
1143 pseudo_bit_t RcvHdrq17DCAXfrCnt[6];
1144 pseudo_bit_t _unused_0[4];
1145 pseudo_bit_t SendDma0DCAOPH[8];
1146 pseudo_bit_t SendDma1DCAOPH[8];
1147 pseudo_bit_t _unused_1[16];
1148 };
1149 struct QIB_7322_DCACtrlF {
1150 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlF_pb );
1151 };
1152 /* Default value: 0x0000000000000000 */
1153
1154 #define QIB_7322_MemErrCtrlA_offset 0x00000600UL
1155 struct QIB_7322_MemErrCtrlA_pb {
1156 pseudo_bit_t FSSUncErrRcvBuf_0[1];
1157 pseudo_bit_t FSSUncErrRcvFlags_0[1];
1158 pseudo_bit_t FSSUncErrLookupiqBuf_0[1];
1159 pseudo_bit_t FSSUncErrRcvDMAHdrBuf_0[1];
1160 pseudo_bit_t FSSUncErrRcvDMADataBuf_0[1];
1161 pseudo_bit_t FSSUncErrRcvBuf_1[1];
1162 pseudo_bit_t FSSUncErrRcvFlags_1[1];
1163 pseudo_bit_t FSSUncErrLookupiqBuf_1[1];
1164 pseudo_bit_t FSSUncErrRcvDMAHdrBuf_1[1];
1165 pseudo_bit_t FSSUncErrRcvDMADataBuf_1[1];
1166 pseudo_bit_t FSSUncErrRcvTIDArray[1];
1167 pseudo_bit_t FSSUncErrRcvEgrArray[1];
1168 pseudo_bit_t _unused_0[3];
1169 pseudo_bit_t FSSUncErrSendBufVL15[1];
1170 pseudo_bit_t FSSUncErrSendBufMain[1];
1171 pseudo_bit_t FSSUncErrSendBufExtra[1];
1172 pseudo_bit_t FSSUncErrSendPbcArray[1];
1173 pseudo_bit_t FSSUncErrSendLaFIFO0_0[1];
1174 pseudo_bit_t FSSUncErrSendLaFIFO1_0[1];
1175 pseudo_bit_t FSSUncErrSendLaFIFO2_0[1];
1176 pseudo_bit_t FSSUncErrSendLaFIFO3_0[1];
1177 pseudo_bit_t FSSUncErrSendLaFIFO4_0[1];
1178 pseudo_bit_t FSSUncErrSendLaFIFO5_0[1];
1179 pseudo_bit_t FSSUncErrSendLaFIFO6_0[1];
1180 pseudo_bit_t FSSUncErrSendLaFIFO7_0[1];
1181 pseudo_bit_t FSSUncErrSendLaFIFO0_1[1];
1182 pseudo_bit_t FSSUncErrSendLaFIFO1_1[1];
1183 pseudo_bit_t FSSUncErrSendLaFIFO2_1[1];
1184 pseudo_bit_t FSSUncErrSendLaFIFO3_1[1];
1185 pseudo_bit_t FSSUncErrSendLaFIFO4_1[1];
1186 pseudo_bit_t FSSUncErrSendLaFIFO5_1[1];
1187 pseudo_bit_t FSSUncErrSendLaFIFO6_1[1];
1188 pseudo_bit_t FSSUncErrSendLaFIFO7_1[1];
1189 pseudo_bit_t FSSUncErrSendRmFIFO_0[1];
1190 pseudo_bit_t FSSUncErrSendRmFIFO_1[1];
1191 pseudo_bit_t _unused_1[11];
1192 pseudo_bit_t FSSUncErrPCIeRetryBuf[1];
1193 pseudo_bit_t FSSUncErrPCIePostHdrBuf[1];
1194 pseudo_bit_t FSSUncErrPCIePostDataBuf[1];
1195 pseudo_bit_t FSSUncErrPCIeCompHdrBuf[1];
1196 pseudo_bit_t FSSUncErrPCIeCompDataBuf[1];
1197 pseudo_bit_t FSSUncErrMsixTable0[1];
1198 pseudo_bit_t FSSUncErrMsixTable1[1];
1199 pseudo_bit_t FSSUncErrMsixTable2[1];
1200 pseudo_bit_t _unused_2[4];
1201 pseudo_bit_t SwapEccDataMsixBits[1];
1202 pseudo_bit_t SwapEccDataExtraBits[1];
1203 pseudo_bit_t DisableEccCorrection[1];
1204 pseudo_bit_t SwapEccDataBits[1];
1205 };
1206 struct QIB_7322_MemErrCtrlA {
1207 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlA_pb );
1208 };
1209 /* Default value: 0x0000000000000000 */
1210
1211 #define QIB_7322_MemErrCtrlB_offset 0x00000608UL
1212 struct QIB_7322_MemErrCtrlB_pb {
1213 pseudo_bit_t FSSCorErrRcvBuf_0[1];
1214 pseudo_bit_t FSSCorErrRcvFlags_0[1];
1215 pseudo_bit_t FSSCorErrLookupiqBuf_0[1];
1216 pseudo_bit_t FSSCorErrRcvDMAHdrBuf_0[1];
1217 pseudo_bit_t FSSCorErrRcvDMADataBuf_0[1];
1218 pseudo_bit_t FSSCorErrRcvBuf_1[1];
1219 pseudo_bit_t FSSCorErrRcvFlags_1[1];
1220 pseudo_bit_t FSSCorErrLookupiqBuf_1[1];
1221 pseudo_bit_t FSSCorErrRcvDMAHdrBuf_1[1];
1222 pseudo_bit_t FSSCorErrRcvDMADataBuf_1[1];
1223 pseudo_bit_t FSSCorErrRcvTIDArray[1];
1224 pseudo_bit_t FSSCorErrRcvEgrArray[1];
1225 pseudo_bit_t _unused_0[3];
1226 pseudo_bit_t FSSCorErrSendBufVL15[1];
1227 pseudo_bit_t FSSCorErrSendBufMain[1];
1228 pseudo_bit_t FSSCorErrSendBufExtra[1];
1229 pseudo_bit_t FSSCorErrSendPbcArray[1];
1230 pseudo_bit_t FSSCorErrSendLaFIFO0_0[1];
1231 pseudo_bit_t FSSCorErrSendLaFIFO1_0[1];
1232 pseudo_bit_t FSSCorErrSendLaFIFO2_0[1];
1233 pseudo_bit_t FSSCorErrSendLaFIFO3_0[1];
1234 pseudo_bit_t FSSCorErrSendLaFIFO4_0[1];
1235 pseudo_bit_t FSSCorErrSendLaFIFO5_0[1];
1236 pseudo_bit_t FSSCorErrSendLaFIFO6_0[1];
1237 pseudo_bit_t FSSCorErrSendLaFIFO7_0[1];
1238 pseudo_bit_t FSSCorErrSendLaFIFO0_1[1];
1239 pseudo_bit_t FSSCorErrSendLaFIFO1_1[1];
1240 pseudo_bit_t FSSCorErrSendLaFIFO2_1[1];
1241 pseudo_bit_t FSSCorErrSendLaFIFO3_1[1];
1242 pseudo_bit_t FSSCorErrSendLaFIFO4_1[1];
1243 pseudo_bit_t FSSCorErrSendLaFIFO5_1[1];
1244 pseudo_bit_t FSSCorErrSendLaFIFO6_1[1];
1245 pseudo_bit_t FSSCorErrSendLaFIFO7_1[1];
1246 pseudo_bit_t FSSCorErrSendRmFIFO_0[1];
1247 pseudo_bit_t FSSCorErrSendRmFIFO_1[1];
1248 pseudo_bit_t _unused_1[11];
1249 pseudo_bit_t FSSCorErrPCIeRetryBuf[1];
1250 pseudo_bit_t FSSCorErrPCIePostHdrBuf[1];
1251 pseudo_bit_t FSSCorErrPCIePostDataBuf[1];
1252 pseudo_bit_t FSSCorErrPCIeCompHdrBuf[1];
1253 pseudo_bit_t FSSCorErrPCIeCompDataBuf[1];
1254 pseudo_bit_t FSSCorErrMsixTable0[1];
1255 pseudo_bit_t FSSCorErrMsixTable1[1];
1256 pseudo_bit_t FSSCorErrMsixTable2[1];
1257 pseudo_bit_t _unused_2[8];
1258 };
1259 struct QIB_7322_MemErrCtrlB {
1260 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlB_pb );
1261 };
1262 /* Default value: 0x0000000000000000 */
1263
1264 #define QIB_7322_MemMultiUnCorErrMask_offset 0x00000610UL
1265 struct QIB_7322_MemMultiUnCorErrMask_pb {
1266 pseudo_bit_t MulUncErrMskRcvBuf_0[1];
1267 pseudo_bit_t MulUncErrMskRcvFlags_0[1];
1268 pseudo_bit_t MulUncErrMskLookupiqBuf_0[1];
1269 pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_0[1];
1270 pseudo_bit_t MulUncErrMskRcvDMADataBuf_0[1];
1271 pseudo_bit_t MulUncErrMskRcvBuf_1[1];
1272 pseudo_bit_t MulUncErrMskRcvFlags_1[1];
1273 pseudo_bit_t MulUncErrMskLookupiqBuf_1[1];
1274 pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_1[1];
1275 pseudo_bit_t MulUncErrMskRcvDMADataBuf_1[1];
1276 pseudo_bit_t MulUncErrMskRcvTIDArray[1];
1277 pseudo_bit_t MulUncErrMskRcvEgrArray[1];
1278 pseudo_bit_t _unused_0[3];
1279 pseudo_bit_t MulUncErrMskSendBufVL15[1];
1280 pseudo_bit_t MulUncErrMskSendBufMain[1];
1281 pseudo_bit_t MulUncErrMskSendBufExtra[1];
1282 pseudo_bit_t MulUncErrMskSendPbcArray[1];
1283 pseudo_bit_t MulUncErrMskSendLaFIFO0_0[1];
1284 pseudo_bit_t MulUncErrMskSendLaFIFO1_0[1];
1285 pseudo_bit_t MulUncErrMskSendLaFIFO2_0[1];
1286 pseudo_bit_t MulUncErrMskSendLaFIFO3_0[1];
1287 pseudo_bit_t MulUncErrMskSendLaFIFO4_0[1];
1288 pseudo_bit_t MulUncErrMskSendLaFIFO5_0[1];
1289 pseudo_bit_t MulUncErrMskSendLaFIFO6_0[1];
1290 pseudo_bit_t MulUncErrMskSendLaFIFO7_0[1];
1291 pseudo_bit_t MulUncErrMskSendLaFIFO0_1[1];
1292 pseudo_bit_t MulUncErrMskSendLaFIFO1_1[1];
1293 pseudo_bit_t MulUncErrMskSendLaFIFO2_1[1];
1294 pseudo_bit_t MulUncErrMskSendLaFIFO3_1[1];
1295 pseudo_bit_t MulUncErrMskSendLaFIFO4_1[1];
1296 pseudo_bit_t MulUncErrMskSendLaFIFO5_1[1];
1297 pseudo_bit_t MulUncErrMskSendLaFIFO6_1[1];
1298 pseudo_bit_t MulUncErrMskSendLaFIFO7_1[1];
1299 pseudo_bit_t MulUncErrMskSendRmFIFO_0[1];
1300 pseudo_bit_t MulUncErrMskSendRmFIFO_1[1];
1301 pseudo_bit_t _unused_1[11];
1302 pseudo_bit_t MulUncErrMskPCIeRetryBuf[1];
1303 pseudo_bit_t MulUncErrMskPCIePostHdrBuf[1];
1304 pseudo_bit_t MulUncErrMskPCIePostDataBuf[1];
1305 pseudo_bit_t MulUncErrMskPCIeCompHdrBuf[1];
1306 pseudo_bit_t MulUncErrMskPCIeCompDataBuf[1];
1307 pseudo_bit_t MulUncErrMskMsixTable0[1];
1308 pseudo_bit_t MulUncErrMskMsixTable1[1];
1309 pseudo_bit_t MulUncErrMskMsixTable2[1];
1310 pseudo_bit_t _unused_2[8];
1311 };
1312 struct QIB_7322_MemMultiUnCorErrMask {
1313 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrMask_pb );
1314 };
1315 /* Default value: 0x0000000000000000 */
1316
1317 #define QIB_7322_MemMultiUnCorErrStatus_offset 0x00000618UL
1318 struct QIB_7322_MemMultiUnCorErrStatus_pb {
1319 pseudo_bit_t MulUncErrStatusRcvBuf_0[1];
1320 pseudo_bit_t MulUncErrStatusRcvFlags_0[1];
1321 pseudo_bit_t MulUncErrStatusLookupiqBuf_0[1];
1322 pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_0[1];
1323 pseudo_bit_t MulUncErrStatusRcvDMADataBuf_0[1];
1324 pseudo_bit_t MulUncErrStatusRcvBuf_1[1];
1325 pseudo_bit_t MulUncErrStatusRcvFlags_1[1];
1326 pseudo_bit_t MulUncErrStatusLookupiqBuf_1[1];
1327 pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_1[1];
1328 pseudo_bit_t MulUncErrStatusRcvDMADataBuf_1[1];
1329 pseudo_bit_t MulUncErrStatusRcvTIDArray[1];
1330 pseudo_bit_t MulUncErrStatusRcvEgrArray[1];
1331 pseudo_bit_t _unused_0[3];
1332 pseudo_bit_t MulUncErrStatusSendBufVL15[1];
1333 pseudo_bit_t MulUncErrStatusSendBufMain[1];
1334 pseudo_bit_t MulUncErrStatusSendBufExtra[1];
1335 pseudo_bit_t MulUncErrStatusSendPbcArray[1];
1336 pseudo_bit_t MulUncErrStatusSendLaFIFO0_0[1];
1337 pseudo_bit_t MulUncErrStatusSendLaFIFO1_0[1];
1338 pseudo_bit_t MulUncErrStatusSendLaFIFO2_0[1];
1339 pseudo_bit_t MulUncErrStatusSendLaFIFO3_0[1];
1340 pseudo_bit_t MulUncErrStatusSendLaFIFO4_0[1];
1341 pseudo_bit_t MulUncErrStatusSendLaFIFO5_0[1];
1342 pseudo_bit_t MulUncErrStatusSendLaFIFO6_0[1];
1343 pseudo_bit_t MulUncErrStatusSendLaFIFO7_0[1];
1344 pseudo_bit_t MulUncErrStatusSendLaFIFO0_1[1];
1345 pseudo_bit_t MulUncErrStatusSendLaFIFO1_1[1];
1346 pseudo_bit_t MulUncErrStatusSendLaFIFO2_1[1];
1347 pseudo_bit_t MulUncErrStatusSendLaFIFO3_1[1];
1348 pseudo_bit_t MulUncErrStatusSendLaFIFO4_1[1];
1349 pseudo_bit_t MulUncErrStatusSendLaFIFO5_1[1];
1350 pseudo_bit_t MulUncErrStatusSendLaFIFO6_1[1];
1351 pseudo_bit_t MulUncErrStatusSendLaFIFO7_1[1];
1352 pseudo_bit_t MulUncErrStatusSendRmFIFO_0[1];
1353 pseudo_bit_t MulUncErrStatusSendRmFIFO_1[1];
1354 pseudo_bit_t _unused_1[11];
1355 pseudo_bit_t MulUncErrStatusPCIeRetryBuf[1];
1356 pseudo_bit_t MulUncErrStatusPCIePostHdrBuf[1];
1357 pseudo_bit_t MulUncErrStatusPCIePostDataBuf[1];
1358 pseudo_bit_t MulUncErrStatusPCIeCompHdrBuf[1];
1359 pseudo_bit_t MulUncErrStatusPCIeCompDataBuf[1];
1360 pseudo_bit_t MulUncErrStatusMsixTable0[1];
1361 pseudo_bit_t MulUncErrStatusMsixTable1[1];
1362 pseudo_bit_t MulUncErrStatusMsixTable2[1];
1363 pseudo_bit_t _unused_2[8];
1364 };
1365 struct QIB_7322_MemMultiUnCorErrStatus {
1366 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrStatus_pb );
1367 };
1368 /* Default value: 0x0000000000000000 */
1369
1370 #define QIB_7322_MemMultiUnCorErrClear_offset 0x00000620UL
1371 struct QIB_7322_MemMultiUnCorErrClear_pb {
1372 pseudo_bit_t MulUncErrClearRcvBuf_0[1];
1373 pseudo_bit_t MulUncErrClearRcvFlags_0[1];
1374 pseudo_bit_t MulUncErrClearLookupiqBuf_0[1];
1375 pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_0[1];
1376 pseudo_bit_t MulUncErrClearRcvDMADataBuf_0[1];
1377 pseudo_bit_t MulUncErrClearRcvBuf_1[1];
1378 pseudo_bit_t MulUncErrClearRcvFlags_1[1];
1379 pseudo_bit_t MulUncErrClearLookupiqBuf_1[1];
1380 pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_1[1];
1381 pseudo_bit_t MulUncErrClearRcvDMADataBuf_1[1];
1382 pseudo_bit_t MulUncErrClearRcvTIDArray[1];
1383 pseudo_bit_t MulUncErrClearRcvEgrArray[1];
1384 pseudo_bit_t _unused_0[3];
1385 pseudo_bit_t MulUncErrClearSendBufVL15[1];
1386 pseudo_bit_t MulUncErrClearSendBufMain[1];
1387 pseudo_bit_t MulUncErrClearSendBufExtra[1];
1388 pseudo_bit_t MulUncErrClearSendPbcArray[1];
1389 pseudo_bit_t MulUncErrClearSendLaFIFO0_0[1];
1390 pseudo_bit_t MulUncErrClearSendLaFIFO1_0[1];
1391 pseudo_bit_t MulUncErrClearSendLaFIFO2_0[1];
1392 pseudo_bit_t MulUncErrClearSendLaFIFO3_0[1];
1393 pseudo_bit_t MulUncErrClearSendLaFIFO4_0[1];
1394 pseudo_bit_t MulUncErrClearSendLaFIFO5_0[1];
1395 pseudo_bit_t MulUncErrClearSendLaFIFO6_0[1];
1396 pseudo_bit_t MulUncErrClearSendLaFIFO7_0[1];
1397 pseudo_bit_t MulUncErrClearSendLaFIFO0_1[1];
1398 pseudo_bit_t MulUncErrClearSendLaFIFO1_1[1];
1399 pseudo_bit_t MulUncErrClearSendLaFIFO2_1[1];
1400 pseudo_bit_t MulUncErrClearSendLaFIFO3_1[1];
1401 pseudo_bit_t MulUncErrClearSendLaFIFO4_1[1];
1402 pseudo_bit_t MulUncErrClearSendLaFIFO5_1[1];
1403 pseudo_bit_t MulUncErrClearSendLaFIFO6_1[1];
1404 pseudo_bit_t MulUncErrClearSendLaFIFO7_1[1];
1405 pseudo_bit_t MulUncErrClearSendRmFIFO_0[1];
1406 pseudo_bit_t MulUncErrClearSendRmFIFO_1[1];
1407 pseudo_bit_t _unused_1[11];
1408 pseudo_bit_t MulUncErrClearPCIeRetryBuf[1];
1409 pseudo_bit_t MulUncErrClearPCIePostHdrBuf[1];
1410 pseudo_bit_t MulUncErrClearPCIePostDataBuf[1];
1411 pseudo_bit_t MulUncErrClearPCIeCompHdrBuf[1];
1412 pseudo_bit_t MulUncErrClearPCIeCompDataBuf[1];
1413 pseudo_bit_t MulUncErrClearMsixTable0[1];
1414 pseudo_bit_t MulUncErrClearMsixTable1[1];
1415 pseudo_bit_t MulUncErrClearMsixTable2[1];
1416 pseudo_bit_t _unused_2[8];
1417 };
1418 struct QIB_7322_MemMultiUnCorErrClear {
1419 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrClear_pb );
1420 };
1421 /* Default value: 0x0000000000000000 */
1422
1423 #define QIB_7322_MemUnCorErrMask_offset 0x00000628UL
1424 struct QIB_7322_MemUnCorErrMask_pb {
1425 pseudo_bit_t UncErrMskRcvBuf_0[1];
1426 pseudo_bit_t UncErrMskRcvFlags_0[1];
1427 pseudo_bit_t UncErrMskLookupiqBuf_0[1];
1428 pseudo_bit_t UncErrMskRcvDMAHdrBuf_0[1];
1429 pseudo_bit_t UncErrMskRcvDMADataBuf_0[1];
1430 pseudo_bit_t UncErrMskRcvBuf_1[1];
1431 pseudo_bit_t UncErrMskRcvFlags_1[1];
1432 pseudo_bit_t UncErrMskLookupiqBuf_1[1];
1433 pseudo_bit_t UncErrMskRcvDMAHdrBuf_1[1];
1434 pseudo_bit_t UncErrMskRcvDMADataBuf_1[1];
1435 pseudo_bit_t UncErrMskRcvTIDArray[1];
1436 pseudo_bit_t UncErrMskRcvEgrArray[1];
1437 pseudo_bit_t _unused_0[3];
1438 pseudo_bit_t UncErrMskSendBufVL15[1];
1439 pseudo_bit_t UncErrMskSendBufMain[1];
1440 pseudo_bit_t UncErrMskSendBufExtra[1];
1441 pseudo_bit_t UncErrMskSendPbcArray[1];
1442 pseudo_bit_t UncErrMskSendLaFIFO0_0[1];
1443 pseudo_bit_t UncErrMskSendLaFIFO1_0[1];
1444 pseudo_bit_t UncErrMskSendLaFIFO2_0[1];
1445 pseudo_bit_t UncErrMskSendLaFIFO3_0[1];
1446 pseudo_bit_t UncErrMskSendLaFIFO4_0[1];
1447 pseudo_bit_t UncErrMskSendLaFIFO5_0[1];
1448 pseudo_bit_t UncErrMskSendLaFIFO6_0[1];
1449 pseudo_bit_t UncErrMskSendLaFIFO7_0[1];
1450 pseudo_bit_t UncErrMskSendLaFIFO0_1[1];
1451 pseudo_bit_t UncErrMskSendLaFIFO1_1[1];
1452 pseudo_bit_t UncErrMskSendLaFIFO2_1[1];
1453 pseudo_bit_t UncErrMskSendLaFIFO3_1[1];
1454 pseudo_bit_t UncErrMskSendLaFIFO4_1[1];
1455 pseudo_bit_t UncErrMskSendLaFIFO5_1[1];
1456 pseudo_bit_t UncErrMskSendLaFIFO6_1[1];
1457 pseudo_bit_t UncErrMskSendLaFIFO7_1[1];
1458 pseudo_bit_t UncErrMskSendRmFIFO_0[1];
1459 pseudo_bit_t UncErrMskSendRmFIFO_1[1];
1460 pseudo_bit_t _unused_1[11];
1461 pseudo_bit_t UncErrMskPCIeRetryBuf[1];
1462 pseudo_bit_t UncErrMskPCIePostHdrBuf[1];
1463 pseudo_bit_t UncErrMskPCIePostDataBuf[1];
1464 pseudo_bit_t UncErrMskPCIeCompHdrBuf[1];
1465 pseudo_bit_t UncErrMskPCIeCompDataBuf[1];
1466 pseudo_bit_t UncErrMskMsixTable0[1];
1467 pseudo_bit_t UncErrMskMsixTable1[1];
1468 pseudo_bit_t UncErrMskMsixTable2[1];
1469 pseudo_bit_t _unused_2[8];
1470 };
1471 struct QIB_7322_MemUnCorErrMask {
1472 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrMask_pb );
1473 };
1474 /* Default value: 0x0000000000000000 */
1475
1476 #define QIB_7322_MemUnCorErrStatus_offset 0x00000630UL
1477 struct QIB_7322_MemUnCorErrStatus_pb {
1478 pseudo_bit_t UncErrStatusRcvBuf_0[1];
1479 pseudo_bit_t UncErrStatusRcvFlags_0[1];
1480 pseudo_bit_t UncErrStatusLookupiqBuf_0[1];
1481 pseudo_bit_t UncErrStatusRcvDMAHdrBuf_0[1];
1482 pseudo_bit_t UncErrStatusRcvDMADataBuf_0[1];
1483 pseudo_bit_t UncErrStatusRcvBuf_1[1];
1484 pseudo_bit_t UncErrStatusRcvFlags_1[1];
1485 pseudo_bit_t UncErrStatusLookupiqBuf_1[1];
1486 pseudo_bit_t UncErrStatusRcvDMAHdrBuf_1[1];
1487 pseudo_bit_t UncErrStatusRcvDMADataBuf_1[1];
1488 pseudo_bit_t UncErrStatusRcvTIDArray[1];
1489 pseudo_bit_t UncErrStatusRcvEgrArray[1];
1490 pseudo_bit_t _unused_0[3];
1491 pseudo_bit_t UncErrStatusSendBufVL15[1];
1492 pseudo_bit_t UncErrStatusSendBufMain[1];
1493 pseudo_bit_t UncErrStatusSendBufExtra[1];
1494 pseudo_bit_t UncErrStatusSendPbcArray[1];
1495 pseudo_bit_t UncErrStatusSendLaFIFO0_0[1];
1496 pseudo_bit_t UncErrStatusSendLaFIFO1_0[1];
1497 pseudo_bit_t UncErrStatusSendLaFIFO2_0[1];
1498 pseudo_bit_t UncErrStatusSendLaFIFO3_0[1];
1499 pseudo_bit_t UncErrStatusSendLaFIFO4_0[1];
1500 pseudo_bit_t UncErrStatusSendLaFIFO5_0[1];
1501 pseudo_bit_t UncErrStatusSendLaFIFO6_0[1];
1502 pseudo_bit_t UncErrStatusSendLaFIFO7_0[1];
1503 pseudo_bit_t UncErrStatusSendLaFIFO0_1[1];
1504 pseudo_bit_t UncErrStatusSendLaFIFO1_1[1];
1505 pseudo_bit_t UncErrStatusSendLaFIFO2_1[1];
1506 pseudo_bit_t UncErrStatusSendLaFIFO3_1[1];
1507 pseudo_bit_t UncErrStatusSendLaFIFO4_1[1];
1508 pseudo_bit_t UncErrStatusSendLaFIFO5_1[1];
1509 pseudo_bit_t UncErrStatusSendLaFIFO6_1[1];
1510 pseudo_bit_t UncErrStatusSendLaFIFO7_1[1];
1511 pseudo_bit_t UncErrStatusSendRmFIFO_0[1];
1512 pseudo_bit_t UncErrStatusSendRmFIFO_1[1];
1513 pseudo_bit_t _unused_1[11];
1514 pseudo_bit_t UncErrStatusPCIeRetryBuf[1];
1515 pseudo_bit_t UncErrStatusPCIePostHdrBuf[1];
1516 pseudo_bit_t UncErrStatusPCIePostDataBuf[1];
1517 pseudo_bit_t UncErrStatusPCIeCompHdrBuf[1];
1518 pseudo_bit_t UncErrStatusPCIeCompDataBuf[1];
1519 pseudo_bit_t UncErrStatusMsixTable0[1];
1520 pseudo_bit_t UncErrStatusMsixTable1[1];
1521 pseudo_bit_t UncErrStatusMsixTable2[1];
1522 pseudo_bit_t _unused_2[8];
1523 };
1524 struct QIB_7322_MemUnCorErrStatus {
1525 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrStatus_pb );
1526 };
1527 /* Default value: 0x0000000000000000 */
1528
1529 #define QIB_7322_MemUnCorErrClear_offset 0x00000638UL
1530 struct QIB_7322_MemUnCorErrClear_pb {
1531 pseudo_bit_t UncErrClearRcvBuf_0[1];
1532 pseudo_bit_t UncErrClearRcvFlags_0[1];
1533 pseudo_bit_t UncErrClearLookupiqBuf_0[1];
1534 pseudo_bit_t UncErrClearRcvDMAHdrBuf_0[1];
1535 pseudo_bit_t UncErrClearRcvDMADataBuf_0[1];
1536 pseudo_bit_t UncErrClearRcvBuf_1[1];
1537 pseudo_bit_t UncErrClearRcvFlags_1[1];
1538 pseudo_bit_t UncErrClearLookupiqBuf_1[1];
1539 pseudo_bit_t UncErrClearRcvDMAHdrBuf_1[1];
1540 pseudo_bit_t UncErrClearRcvDMADataBuf_1[1];
1541 pseudo_bit_t UncErrClearRcvTIDArray[1];
1542 pseudo_bit_t UncErrClearRcvEgrArray[1];
1543 pseudo_bit_t _unused_0[3];
1544 pseudo_bit_t UncErrClearSendBufVL15[1];
1545 pseudo_bit_t UncErrClearSendBufMain[1];
1546 pseudo_bit_t UncErrClearSendBufExtra[1];
1547 pseudo_bit_t UncErrClearSendPbcArray[1];
1548 pseudo_bit_t UncErrClearSendLaFIFO0_0[1];
1549 pseudo_bit_t UncErrClearSendLaFIFO1_0[1];
1550 pseudo_bit_t UncErrClearSendLaFIFO2_0[1];
1551 pseudo_bit_t UncErrClearSendLaFIFO3_0[1];
1552 pseudo_bit_t UncErrClearSendLaFIFO4_0[1];
1553 pseudo_bit_t UncErrClearSendLaFIFO5_0[1];
1554 pseudo_bit_t UncErrClearSendLaFIFO6_0[1];
1555 pseudo_bit_t UncErrClearSendLaFIFO7_0[1];
1556 pseudo_bit_t UncErrClearSendLaFIFO0_1[1];
1557 pseudo_bit_t UncErrClearSendLaFIFO1_1[1];
1558 pseudo_bit_t UncErrClearSendLaFIFO2_1[1];
1559 pseudo_bit_t UncErrClearSendLaFIFO3_1[1];
1560 pseudo_bit_t UncErrClearSendLaFIFO4_1[1];
1561 pseudo_bit_t UncErrClearSendLaFIFO5_1[1];
1562 pseudo_bit_t UncErrClearSendLaFIFO6_1[1];
1563 pseudo_bit_t UncErrClearSendLaFIFO7_1[1];
1564 pseudo_bit_t UncErrClearSendRmFIFO_0[1];
1565 pseudo_bit_t UncErrClearSendRmFIFO_1[1];
1566 pseudo_bit_t _unused_1[11];
1567 pseudo_bit_t UncErrClearPCIeRetryBuf[1];
1568 pseudo_bit_t UncErrClearPCIePostHdrBuf[1];
1569 pseudo_bit_t UncErrClearPCIePostDataBuf[1];
1570 pseudo_bit_t UncErrClearPCIeCompHdrBuf[1];
1571 pseudo_bit_t UncErrClearPCIeCompDataBuf[1];
1572 pseudo_bit_t UncErrClearMsixTable0[1];
1573 pseudo_bit_t UncErrClearMsixTable1[1];
1574 pseudo_bit_t UncErrClearMsixTable2[1];
1575 pseudo_bit_t _unused_2[8];
1576 };
1577 struct QIB_7322_MemUnCorErrClear {
1578 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrClear_pb );
1579 };
1580 /* Default value: 0x0000000000000000 */
1581
1582 #define QIB_7322_MemMultiCorErrMask_offset 0x00000640UL
1583 struct QIB_7322_MemMultiCorErrMask_pb {
1584 pseudo_bit_t MulCorErrMskRcvBuf_0[1];
1585 pseudo_bit_t MulCorErrMskRcvFlags_0[1];
1586 pseudo_bit_t MulCorErrMskLookupiqBuf_0[1];
1587 pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_0[1];
1588 pseudo_bit_t MulCorErrMskRcvDMADataBuf_0[1];
1589 pseudo_bit_t MulCorErrMskRcvBuf_1[1];
1590 pseudo_bit_t MulCorErrMskRcvFlags_1[1];
1591 pseudo_bit_t MulCorErrMskLookupiqBuf_1[1];
1592 pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_1[1];
1593 pseudo_bit_t MulCorErrMskRcvDMADataBuf_1[1];
1594 pseudo_bit_t MulCorErrMskRcvTIDArray[1];
1595 pseudo_bit_t MulCorErrMskRcvEgrArray[1];
1596 pseudo_bit_t _unused_0[3];
1597 pseudo_bit_t MulCorErrMskSendBufVL15[1];
1598 pseudo_bit_t MulCorErrMskSendBufMain[1];
1599 pseudo_bit_t MulCorErrMskSendBufExtra[1];
1600 pseudo_bit_t MulCorErrMskSendPbcArray[1];
1601 pseudo_bit_t MulCorErrMskSendLaFIFO0_0[1];
1602 pseudo_bit_t MulCorErrMskSendLaFIFO1_0[1];
1603 pseudo_bit_t MulCorErrMskSendLaFIFO2_0[1];
1604 pseudo_bit_t MulCorErrMskSendLaFIFO3_0[1];
1605 pseudo_bit_t MulCorErrMskSendLaFIFO4_0[1];
1606 pseudo_bit_t MulCorErrMskSendLaFIFO5_0[1];
1607 pseudo_bit_t MulCorErrMskSendLaFIFO6_0[1];
1608 pseudo_bit_t MulCorErrMskSendLaFIFO7_0[1];
1609 pseudo_bit_t MulCorErrMskSendLaFIFO0_1[1];
1610 pseudo_bit_t MulCorErrMskSendLaFIFO1_1[1];
1611 pseudo_bit_t MulCorErrMskSendLaFIFO2_1[1];
1612 pseudo_bit_t MulCorErrMskSendLaFIFO3_1[1];
1613 pseudo_bit_t MulCorErrMskSendLaFIFO4_1[1];
1614 pseudo_bit_t MulCorErrMskSendLaFIFO5_1[1];
1615 pseudo_bit_t MulCorErrMskSendLaFIFO6_1[1];
1616 pseudo_bit_t MulCorErrMskSendLaFIFO7_1[1];
1617 pseudo_bit_t MulCorErrMskSendRmFIFO_0[1];
1618 pseudo_bit_t MulCorErrMskSendRmFIFO_1[1];
1619 pseudo_bit_t _unused_1[11];
1620 pseudo_bit_t MulCorErrMskPCIeRetryBuf[1];
1621 pseudo_bit_t MulCorErrMskPCIePostHdrBuf[1];
1622 pseudo_bit_t MulCorErrMskPCIePostDataBuf[1];
1623 pseudo_bit_t MulCorErrMskPCIeCompHdrBuf[1];
1624 pseudo_bit_t MulCorErrMskPCIeCompDataBuf[1];
1625 pseudo_bit_t MulCorErrMskMsixTable0[1];
1626 pseudo_bit_t MulCorErrMskMsixTable1[1];
1627 pseudo_bit_t MulCorErrMskMsixTable2[1];
1628 pseudo_bit_t _unused_2[8];
1629 };
1630 struct QIB_7322_MemMultiCorErrMask {
1631 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrMask_pb );
1632 };
1633 /* Default value: 0x0000000000000000 */
1634
1635 #define QIB_7322_MemMultiCorErrStatus_offset 0x00000648UL
1636 struct QIB_7322_MemMultiCorErrStatus_pb {
1637 pseudo_bit_t MulCorErrStatusRcvBuf_0[1];
1638 pseudo_bit_t MulCorErrStatusRcvFlags_0[1];
1639 pseudo_bit_t MulCorErrStatusLookupiqBuf_0[1];
1640 pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_0[1];
1641 pseudo_bit_t MulCorErrStatusRcvDMADataBuf_0[1];
1642 pseudo_bit_t MulCorErrStatusRcvBuf_1[1];
1643 pseudo_bit_t MulCorErrStatusRcvFlags_1[1];
1644 pseudo_bit_t MulCorErrStatusLookupiqBuf_1[1];
1645 pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_1[1];
1646 pseudo_bit_t MulCorErrStatusRcvDMADataBuf_1[1];
1647 pseudo_bit_t MulCorErrStatusRcvTIDArray[1];
1648 pseudo_bit_t MulCorErrStatusRcvEgrArray[1];
1649 pseudo_bit_t _unused_0[3];
1650 pseudo_bit_t MulCorErrStatusSendBufVL15[1];
1651 pseudo_bit_t MulCorErrStatusSendBufMain[1];
1652 pseudo_bit_t MulCorErrStatusSendBufExtra[1];
1653 pseudo_bit_t MulCorErrStatusSendPbcArray[1];
1654 pseudo_bit_t MulCorErrStatusSendLaFIFO0_0[1];
1655 pseudo_bit_t MulCorErrStatusSendLaFIFO1_0[1];
1656 pseudo_bit_t MulCorErrStatusSendLaFIFO2_0[1];
1657 pseudo_bit_t MulCorErrStatusSendLaFIFO3_0[1];
1658 pseudo_bit_t MulCorErrStatusSendLaFIFO4_0[1];
1659 pseudo_bit_t MulCorErrStatusSendLaFIFO5_0[1];
1660 pseudo_bit_t MulCorErrStatusSendLaFIFO6_0[1];
1661 pseudo_bit_t MulCorErrStatusSendLaFIFO7_0[1];
1662 pseudo_bit_t MulCorErrStatusSendLaFIFO0_1[1];
1663 pseudo_bit_t MulCorErrStatusSendLaFIFO1_1[1];
1664 pseudo_bit_t MulCorErrStatusSendLaFIFO2_1[1];
1665 pseudo_bit_t MulCorErrStatusSendLaFIFO3_1[1];
1666 pseudo_bit_t MulCorErrStatusSendLaFIFO4_1[1];
1667 pseudo_bit_t MulCorErrStatusSendLaFIFO5_1[1];
1668 pseudo_bit_t MulCorErrStatusSendLaFIFO6_1[1];
1669 pseudo_bit_t MulCorErrStatusSendLaFIFO7_1[1];
1670 pseudo_bit_t MulCorErrStatusSendRmFIFO_0[1];
1671 pseudo_bit_t MulCorErrStatusSendRmFIFO_1[1];
1672 pseudo_bit_t _unused_1[11];
1673 pseudo_bit_t MulCorErrStatusPCIeRetryBuf[1];
1674 pseudo_bit_t MulCorErrStatusPCIePostHdrBuf[1];
1675 pseudo_bit_t MulCorErrStatusPCIePostDataBuf[1];
1676 pseudo_bit_t MulCorErrStatusPCIeCompHdrBuf[1];
1677 pseudo_bit_t MulCorErrStatusPCIeCompDataBuf[1];
1678 pseudo_bit_t MulCorErrStatusMsixTable0[1];
1679 pseudo_bit_t MulCorErrStatusMsixTable1[1];
1680 pseudo_bit_t MulCorErrStatusMsixTable2[1];
1681 pseudo_bit_t _unused_2[8];
1682 };
1683 struct QIB_7322_MemMultiCorErrStatus {
1684 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrStatus_pb );
1685 };
1686 /* Default value: 0x0000000000000000 */
1687
1688 #define QIB_7322_MemMultiCorErrClear_offset 0x00000650UL
1689 struct QIB_7322_MemMultiCorErrClear_pb {
1690 pseudo_bit_t MulCorErrClearRcvBuf_0[1];
1691 pseudo_bit_t MulCorErrClearRcvFlags_0[1];
1692 pseudo_bit_t MulCorErrClearLookupiqBuf_0[1];
1693 pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_0[1];
1694 pseudo_bit_t MulCorErrClearRcvDMADataBuf_0[1];
1695 pseudo_bit_t MulCorErrClearRcvBuf_1[1];
1696 pseudo_bit_t MulCorErrClearRcvFlags_1[1];
1697 pseudo_bit_t MulCorErrClearLookupiqBuf_1[1];
1698 pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_1[1];
1699 pseudo_bit_t MulCorErrClearRcvDMADataBuf_1[1];
1700 pseudo_bit_t MulCorErrClearRcvTIDArray[1];
1701 pseudo_bit_t MulCorErrClearRcvEgrArray[1];
1702 pseudo_bit_t _unused_0[3];
1703 pseudo_bit_t MulCorErrClearSendBufVL15[1];
1704 pseudo_bit_t MulCorErrClearSendBufMain[1];
1705 pseudo_bit_t MulCorErrClearSendBufExtra[1];
1706 pseudo_bit_t MulCorErrClearSendPbcArray[1];
1707 pseudo_bit_t MulCorErrClearSendLaFIFO0_0[1];
1708 pseudo_bit_t MulCorErrClearSendLaFIFO1_0[1];
1709 pseudo_bit_t MulCorErrClearSendLaFIFO2_0[1];
1710 pseudo_bit_t MulCorErrClearSendLaFIFO3_0[1];
1711 pseudo_bit_t MulCorErrClearSendLaFIFO4_0[1];
1712 pseudo_bit_t MulCorErrClearSendLaFIFO5_0[1];
1713 pseudo_bit_t MulCorErrClearSendLaFIFO6_0[1];
1714 pseudo_bit_t MulCorErrClearSendLaFIFO7_0[1];
1715 pseudo_bit_t MulCorErrClearSendLaFIFO0_1[1];
1716 pseudo_bit_t MulCorErrClearSendLaFIFO1_1[1];
1717 pseudo_bit_t MulCorErrClearSendLaFIFO2_1[1];
1718 pseudo_bit_t MulCorErrClearSendLaFIFO3_1[1];
1719 pseudo_bit_t MulCorErrClearSendLaFIFO4_1[1];
1720 pseudo_bit_t MulCorErrClearSendLaFIFO5_1[1];
1721 pseudo_bit_t MulCorErrClearSendLaFIFO6_1[1];
1722 pseudo_bit_t MulCorErrClearSendLaFIFO7_1[1];
1723 pseudo_bit_t MulCorErrClearSendRmFIFO_0[1];
1724 pseudo_bit_t MulCorErrClearSendRmFIFO_1[1];
1725 pseudo_bit_t _unused_1[11];
1726 pseudo_bit_t MulCorErrClearPCIeRetryBuf[1];
1727 pseudo_bit_t MulCorErrClearPCIePostHdrBuf[1];
1728 pseudo_bit_t MulCorErrClearPCIePostDataBuf[1];
1729 pseudo_bit_t MulCorErrClearPCIeCompHdrBuf[1];
1730 pseudo_bit_t MulCorErrClearPCIeCompDataBuf[1];
1731 pseudo_bit_t MulCorErrClearMsixTable0[1];
1732 pseudo_bit_t MulCorErrClearMsixTable1[1];
1733 pseudo_bit_t MulCorErrClearMsixTable2[1];
1734 pseudo_bit_t _unused_2[8];
1735 };
1736 struct QIB_7322_MemMultiCorErrClear {
1737 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrClear_pb );
1738 };
1739 /* Default value: 0x0000000000000000 */
1740
1741 #define QIB_7322_MemCorErrMask_offset 0x00000658UL
1742 struct QIB_7322_MemCorErrMask_pb {
1743 pseudo_bit_t CorErrMskRcvBuf_0[1];
1744 pseudo_bit_t CorErrMskRcvFlags_0[1];
1745 pseudo_bit_t CorErrMskLookupiqBuf_0[1];
1746 pseudo_bit_t CorErrMskRcvDMAHdrBuf_0[1];
1747 pseudo_bit_t CorErrMskRcvDMADataBuf_0[1];
1748 pseudo_bit_t CorErrMskRcvBuf_1[1];
1749 pseudo_bit_t CorErrMskRcvFlags_1[1];
1750 pseudo_bit_t CorErrMskLookupiqBuf_1[1];
1751 pseudo_bit_t CorErrMskRcvDMAHdrBuf_1[1];
1752 pseudo_bit_t CorErrMskRcvDMADataBuf_1[1];
1753 pseudo_bit_t CorErrMskRcvTIDArray[1];
1754 pseudo_bit_t CorErrMskRcvEgrArray[1];
1755 pseudo_bit_t _unused_0[3];
1756 pseudo_bit_t CorErrMskSendBufVL15[1];
1757 pseudo_bit_t CorErrMskSendBufMain[1];
1758 pseudo_bit_t CorErrMskSendBufExtra[1];
1759 pseudo_bit_t CorErrMskSendPbcArray[1];
1760 pseudo_bit_t CorErrMskSendLaFIFO0_0[1];
1761 pseudo_bit_t CorErrMskSendLaFIFO1_0[1];
1762 pseudo_bit_t CorErrMskSendLaFIFO2_0[1];
1763 pseudo_bit_t CorErrMskSendLaFIFO3_0[1];
1764 pseudo_bit_t CorErrMskSendLaFIFO4_0[1];
1765 pseudo_bit_t CorErrMskSendLaFIFO5_0[1];
1766 pseudo_bit_t CorErrMskSendLaFIFO6_0[1];
1767 pseudo_bit_t CorErrMskSendLaFIFO7_0[1];
1768 pseudo_bit_t CorErrMskSendLaFIFO0_1[1];
1769 pseudo_bit_t CorErrMskSendLaFIFO1_1[1];
1770 pseudo_bit_t CorErrMskSendLaFIFO2_1[1];
1771 pseudo_bit_t CorErrMskSendLaFIFO3_1[1];
1772 pseudo_bit_t CorErrMskSendLaFIFO4_1[1];
1773 pseudo_bit_t CorErrMskSendLaFIFO5_1[1];
1774 pseudo_bit_t CorErrMskSendLaFIFO6_1[1];
1775 pseudo_bit_t CorErrMskSendLaFIFO7_1[1];
1776 pseudo_bit_t CorErrMskSendRmFIFO_0[1];
1777 pseudo_bit_t CorErrMskSendRmFIFO_1[1];
1778 pseudo_bit_t _unused_1[11];
1779 pseudo_bit_t CorErrMskPCIeRetryBuf[1];
1780 pseudo_bit_t CorErrMskPCIePostHdrBuf[1];
1781 pseudo_bit_t CorErrMskPCIePostDataBuf[1];
1782 pseudo_bit_t CorErrMskPCIeCompHdrBuf[1];
1783 pseudo_bit_t CorErrMskPCIeCompDataBuf[1];
1784 pseudo_bit_t CorErrMskMsixTable0[1];
1785 pseudo_bit_t CorErrMskMsixTable1[1];
1786 pseudo_bit_t CorErrMskMsixTable2[1];
1787 pseudo_bit_t _unused_2[8];
1788 };
1789 struct QIB_7322_MemCorErrMask {
1790 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrMask_pb );
1791 };
1792 /* Default value: 0x0000000000000000 */
1793
1794 #define QIB_7322_MemCorErrStatus_offset 0x00000660UL
1795 struct QIB_7322_MemCorErrStatus_pb {
1796 pseudo_bit_t CorErrStatusRcvBuf_0[1];
1797 pseudo_bit_t CorErrStatusRcvFlags_0[1];
1798 pseudo_bit_t CorErrStatusLookupiqBuf_0[1];
1799 pseudo_bit_t CorErrStatusRcvDMAHdrBuf_0[1];
1800 pseudo_bit_t CorErrStatusRcvDMADataBuf_0[1];
1801 pseudo_bit_t CorErrStatusRcvBuf_1[1];
1802 pseudo_bit_t CorErrStatusRcvFlags_1[1];
1803 pseudo_bit_t CorErrStatusLookupiqBuf_1[1];
1804 pseudo_bit_t CorErrStatusRcvDMAHdrBuf_1[1];
1805 pseudo_bit_t CorErrStatusRcvDMADataBuf_1[1];
1806 pseudo_bit_t CorErrStatusRcvTIDArray[1];
1807 pseudo_bit_t CorErrStatusRcvEgrArray[1];
1808 pseudo_bit_t _unused_0[3];
1809 pseudo_bit_t CorErrStatusSendBufVL15[1];
1810 pseudo_bit_t CorErrStatusSendBufMain[1];
1811 pseudo_bit_t CorErrStatusSendBufExtra[1];
1812 pseudo_bit_t CorErrStatusSendPbcArray[1];
1813 pseudo_bit_t CorErrStatusSendLaFIFO0_0[1];
1814 pseudo_bit_t CorErrStatusSendLaFIFO1_0[1];
1815 pseudo_bit_t CorErrStatusSendLaFIFO2_0[1];
1816 pseudo_bit_t CorErrStatusSendLaFIFO3_0[1];
1817 pseudo_bit_t CorErrStatusSendLaFIFO4_0[1];
1818 pseudo_bit_t CorErrStatusSendLaFIFO5_0[1];
1819 pseudo_bit_t CorErrStatusSendLaFIFO6_0[1];
1820 pseudo_bit_t CorErrStatusSendLaFIFO7_0[1];
1821 pseudo_bit_t CorErrStatusSendLaFIFO0_1[1];
1822 pseudo_bit_t CorErrStatusSendLaFIFO1_1[1];
1823 pseudo_bit_t CorErrStatusSendLaFIFO2_1[1];
1824 pseudo_bit_t CorErrStatusSendLaFIFO3_1[1];
1825 pseudo_bit_t CorErrStatusSendLaFIFO4_1[1];
1826 pseudo_bit_t CorErrStatusSendLaFIFO5_1[1];
1827 pseudo_bit_t CorErrStatusSendLaFIFO6_1[1];
1828 pseudo_bit_t CorErrStatusSendLaFIFO7_1[1];
1829 pseudo_bit_t CorErrStatusSendRmFIFO_0[1];
1830 pseudo_bit_t CorErrStatusSendRmFIFO_1[1];
1831 pseudo_bit_t _unused_1[11];
1832 pseudo_bit_t CorErrStatusPCIeRetryBuf[1];
1833 pseudo_bit_t CorErrStatusPCIePostHdrBuf[1];
1834 pseudo_bit_t CorErrStatusPCIePostDataBuf[1];
1835 pseudo_bit_t CorErrStatusPCIeCompHdrBuf[1];
1836 pseudo_bit_t CorErrStatusPCIeCompDataBuf[1];
1837 pseudo_bit_t CorErrStatusMsixTable0[1];
1838 pseudo_bit_t CorErrStatusMsixTable1[1];
1839 pseudo_bit_t CorErrStatusMsixTable2[1];
1840 pseudo_bit_t _unused_2[8];
1841 };
1842 struct QIB_7322_MemCorErrStatus {
1843 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrStatus_pb );
1844 };
1845 /* Default value: 0x0000000000000000 */
1846
1847 #define QIB_7322_MemCorErrClear_offset 0x00000668UL
1848 struct QIB_7322_MemCorErrClear_pb {
1849 pseudo_bit_t CorErrClearRcvBuf_0[1];
1850 pseudo_bit_t CorErrClearRcvFlags_0[1];
1851 pseudo_bit_t CorErrClearLookupiqBuf_0[1];
1852 pseudo_bit_t CorErrClearRcvDMAHdrBuf_0[1];
1853 pseudo_bit_t CorErrClearRcvDMADataBuf_0[1];
1854 pseudo_bit_t CorErrClearRcvBuf_1[1];
1855 pseudo_bit_t CorErrClearRcvFlags_1[1];
1856 pseudo_bit_t CorErrClearLookupiqBuf_1[1];
1857 pseudo_bit_t CorErrClearRcvDMAHdrBuf_1[1];
1858 pseudo_bit_t CorErrClearRcvDMADataBuf_1[1];
1859 pseudo_bit_t CorErrClearRcvTIDArray[1];
1860 pseudo_bit_t CorErrClearRcvEgrArray[1];
1861 pseudo_bit_t _unused_0[3];
1862 pseudo_bit_t CorErrClearSendBufVL15[1];
1863 pseudo_bit_t CorErrClearSendBufMain[1];
1864 pseudo_bit_t CorErrClearSendBufExtra[1];
1865 pseudo_bit_t CorErrClearSendPbcArray[1];
1866 pseudo_bit_t CorErrClearSendLaFIFO0_0[1];
1867 pseudo_bit_t CorErrClearSendLaFIFO1_0[1];
1868 pseudo_bit_t CorErrClearSendLaFIFO2_0[1];
1869 pseudo_bit_t CorErrClearSendLaFIFO3_0[1];
1870 pseudo_bit_t CorErrClearSendLaFIFO4_0[1];
1871 pseudo_bit_t CorErrClearSendLaFIFO5_0[1];
1872 pseudo_bit_t CorErrClearSendLaFIFO6_0[1];
1873 pseudo_bit_t CorErrClearSendLaFIFO7_0[1];
1874 pseudo_bit_t CorErrClearSendLaFIFO0_1[1];
1875 pseudo_bit_t CorErrClearSendLaFIFO1_1[1];
1876 pseudo_bit_t CorErrClearSendLaFIFO2_1[1];
1877 pseudo_bit_t CorErrClearSendLaFIFO3_1[1];
1878 pseudo_bit_t CorErrClearSendLaFIFO4_1[1];
1879 pseudo_bit_t CorErrClearSendLaFIFO5_1[1];
1880 pseudo_bit_t CorErrClearSendLaFIFO6_1[1];
1881 pseudo_bit_t CorErrClearSendLaFIFO7_1[1];
1882 pseudo_bit_t CorErrClearSendRmFIFO_0[1];
1883 pseudo_bit_t CorErrClearSendRmFIFO_1[1];
1884 pseudo_bit_t _unused_1[11];
1885 pseudo_bit_t CorErrClearPCIeRetryBuf[1];
1886 pseudo_bit_t CorErrClearPCIePostHdrBuf[1];
1887 pseudo_bit_t CorErrClearPCIePostDataBuf[1];
1888 pseudo_bit_t CorErrClearPCIeCompHdrBuf[1];
1889 pseudo_bit_t CorErrClearPCIeCompDataBuf[1];
1890 pseudo_bit_t CorErrClearMsixTable0[1];
1891 pseudo_bit_t CorErrClearMsixTable1[1];
1892 pseudo_bit_t CorErrClearMsixTable2[1];
1893 pseudo_bit_t _unused_2[8];
1894 };
1895 struct QIB_7322_MemCorErrClear {
1896 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrClear_pb );
1897 };
1898 /* Default value: 0x0000000000000000 */
1899
1900 #define QIB_7322_MsixTableUnCorErrLogA_offset 0x00000680UL
1901 struct QIB_7322_MsixTableUnCorErrLogA_pb {
1902 pseudo_bit_t MsixTable_1_0_UnCorErrData[64];
1903 };
1904 struct QIB_7322_MsixTableUnCorErrLogA {
1905 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogA_pb );
1906 };
1907 /* Default value: 0x0000000000000000 */
1908
1909 #define QIB_7322_MsixTableUnCorErrLogB_offset 0x00000688UL
1910 struct QIB_7322_MsixTableUnCorErrLogB_pb {
1911 pseudo_bit_t MsixTable_2_UnCorErrData[32];
1912 pseudo_bit_t MsixTable_0_UnCorErrCheckBits[7];
1913 pseudo_bit_t MsixTable_1_UnCorErrCheckBits[7];
1914 pseudo_bit_t MsixTable_2_UnCorErrCheckBits[7];
1915 pseudo_bit_t _unused_0[11];
1916 };
1917 struct QIB_7322_MsixTableUnCorErrLogB {
1918 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogB_pb );
1919 };
1920 /* Default value: 0x0000000000000000 */
1921
1922 #define QIB_7322_MsixTableUnCorErrLogC_offset 0x00000690UL
1923 struct QIB_7322_MsixTableUnCorErrLogC_pb {
1924 pseudo_bit_t MsixTable_0_UnCorErrAddr[7];
1925 pseudo_bit_t MsixTable_1_UnCorErrAddr[7];
1926 pseudo_bit_t MsixTable_2_UnCorErrAddr[7];
1927 pseudo_bit_t _unused_0[43];
1928 };
1929 struct QIB_7322_MsixTableUnCorErrLogC {
1930 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogC_pb );
1931 };
1932 /* Default value: 0x0000000000000000 */
1933
1934 #define QIB_7322_MsixEntryWithUncorErr_offset 0x00000698UL
1935 /* Default value: 0x0000000000000000 */
1936
1937 #define QIB_7322_MsixTableCorErrLogA_offset 0x000006a0UL
1938 struct QIB_7322_MsixTableCorErrLogA_pb {
1939 pseudo_bit_t MsixTable_1_0_CorErrData[64];
1940 };
1941 struct QIB_7322_MsixTableCorErrLogA {
1942 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogA_pb );
1943 };
1944 /* Default value: 0x0000000000000000 */
1945
1946 #define QIB_7322_MsixTableCorErrLogB_offset 0x000006a8UL
1947 struct QIB_7322_MsixTableCorErrLogB_pb {
1948 pseudo_bit_t MsixTable_2_CorErrData[32];
1949 pseudo_bit_t MsixTable_0_CorErrCheckBits[7];
1950 pseudo_bit_t MsixTable_1_CorErrCheckBits[7];
1951 pseudo_bit_t MsixTable_2_CorErrCheckBits[7];
1952 pseudo_bit_t _unused_0[11];
1953 };
1954 struct QIB_7322_MsixTableCorErrLogB {
1955 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogB_pb );
1956 };
1957 /* Default value: 0x0000000000000000 */
1958
1959 #define QIB_7322_MsixTableCorErrLogC_offset 0x000006b0UL
1960 struct QIB_7322_MsixTableCorErrLogC_pb {
1961 pseudo_bit_t MsixTable_0_CorErrAddr[7];
1962 pseudo_bit_t MsixTable_1_CorErrAddr[7];
1963 pseudo_bit_t MsixTable_2_CorErrAddr[7];
1964 pseudo_bit_t _unused_0[43];
1965 };
1966 struct QIB_7322_MsixTableCorErrLogC {
1967 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogC_pb );
1968 };
1969 /* Default value: 0x0000000000000000 */
1970
1971 #define QIB_7322_PcieCplDataBufrUnCorErrLogA_offset 0x00000700UL
1972 struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb {
1973 pseudo_bit_t PcieCplDataBufrUnCorErrData_63_0[64];
1974 };
1975 struct QIB_7322_PcieCplDataBufrUnCorErrLogA {
1976 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb );
1977 };
1978 /* Default value: 0x0000000000000000 */
1979
1980 #define QIB_7322_PcieCplDataBufrUnCorErrLogB_offset 0x00000708UL
1981 struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb {
1982 pseudo_bit_t PcieCplDataBufrUnCorErrData_127_64[64];
1983 };
1984 struct QIB_7322_PcieCplDataBufrUnCorErrLogB {
1985 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb );
1986 };
1987 /* Default value: 0x0000000000000000 */
1988
1989 #define QIB_7322_PcieCplDataBufrUnCorErrLogC_offset 0x00000710UL
1990 struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb {
1991 pseudo_bit_t PcieCplDataBufrUnCorErrData_136_128[9];
1992 pseudo_bit_t PcieCplDataBufrUnCorErrCheckBit_21_0[22];
1993 pseudo_bit_t PcieCplDataBufrUnCorErrAddr_13_0[14];
1994 pseudo_bit_t _unused_0[19];
1995 };
1996 struct QIB_7322_PcieCplDataBufrUnCorErrLogC {
1997 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb );
1998 };
1999 /* Default value: 0x0000000000000000 */
2000
2001 #define QIB_7322_PcieCplHdrBufrUnCorErrLogA_offset 0x00000720UL
2002 struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb {
2003 pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_63_0[64];
2004 };
2005 struct QIB_7322_PcieCplHdrBufrUnCorErrLogA {
2006 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb );
2007 };
2008 /* Default value: 0x0000000000000000 */
2009
2010 #define QIB_7322_PcieCplHdrBufrUnCorErrLogB_offset 0x00000728UL
2011 struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb {
2012 pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_103_64[40];
2013 pseudo_bit_t _unused_0[24];
2014 };
2015 struct QIB_7322_PcieCplHdrBufrUnCorErrLogB {
2016 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb );
2017 };
2018 /* Default value: 0x0000000000000000 */
2019
2020 #define QIB_7322_PcieCplHdrBufrUnCorErrLogC_offset 0x00000730UL
2021 struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb {
2022 pseudo_bit_t PcieCplHdrBufrUnCorErrCheckBit_15_0[16];
2023 pseudo_bit_t PcieCplHdrBufrUnCorErrAddr_8_0[9];
2024 pseudo_bit_t _unused_0[39];
2025 };
2026 struct QIB_7322_PcieCplHdrBufrUnCorErrLogC {
2027 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb );
2028 };
2029 /* Default value: 0x0000000000000000 */
2030
2031 #define QIB_7322_PciePDataBufrUnCorErrLogA_offset 0x00000740UL
2032 struct QIB_7322_PciePDataBufrUnCorErrLogA_pb {
2033 pseudo_bit_t PciePDataBufrUnCorErrData_63_0[64];
2034 };
2035 struct QIB_7322_PciePDataBufrUnCorErrLogA {
2036 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogA_pb );
2037 };
2038 /* Default value: 0x0000000000000000 */
2039
2040 #define QIB_7322_PciePDataBufrUnCorErrLogB_offset 0x00000748UL
2041 struct QIB_7322_PciePDataBufrUnCorErrLogB_pb {
2042 pseudo_bit_t PciePDataBufrUnCorErrData_127_64[64];
2043 };
2044 struct QIB_7322_PciePDataBufrUnCorErrLogB {
2045 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogB_pb );
2046 };
2047 /* Default value: 0x0000000000000000 */
2048
2049 #define QIB_7322_PciePDataBufrUnCorErrLogC_offset 0x00000750UL
2050 struct QIB_7322_PciePDataBufrUnCorErrLogC_pb {
2051 pseudo_bit_t PciePDataBufrUnCorErrData_136_128[9];
2052 pseudo_bit_t PciePDataBufrUnCorErrCheckBit_21_0[22];
2053 pseudo_bit_t PciePDataBufrUnCorErrAddr_13_0[14];
2054 pseudo_bit_t _unused_0[19];
2055 };
2056 struct QIB_7322_PciePDataBufrUnCorErrLogC {
2057 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogC_pb );
2058 };
2059 /* Default value: 0x0000000000000000 */
2060
2061 #define QIB_7322_PciePHdrBufrUnCorErrLogA_offset 0x00000760UL
2062 struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb {
2063 pseudo_bit_t PciePHdrBufrUnCorErrData_63_0[64];
2064 };
2065 struct QIB_7322_PciePHdrBufrUnCorErrLogA {
2066 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb );
2067 };
2068 /* Default value: 0x0000000000000000 */
2069
2070 #define QIB_7322_PciePHdrBufrUnCorErrLogB_offset 0x00000768UL
2071 struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb {
2072 pseudo_bit_t PciePHdrBufrUnCorErrData_107_64[44];
2073 pseudo_bit_t _unused_0[20];
2074 };
2075 struct QIB_7322_PciePHdrBufrUnCorErrLogB {
2076 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb );
2077 };
2078 /* Default value: 0x0000000000000000 */
2079
2080 #define QIB_7322_PciePHdrBufrUnCorErrLogC_offset 0x00000770UL
2081 struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb {
2082 pseudo_bit_t PciePHdrBufrUnCorErrCheckBit_15_0[16];
2083 pseudo_bit_t PciePHdrBufrUnCorErrAddr_8_0[9];
2084 pseudo_bit_t _unused_0[39];
2085 };
2086 struct QIB_7322_PciePHdrBufrUnCorErrLogC {
2087 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb );
2088 };
2089 /* Default value: 0x0000000000000000 */
2090
2091 #define QIB_7322_PcieRetryBufrUnCorErrLogA_offset 0x00000780UL
2092 struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb {
2093 pseudo_bit_t PcieRetryBufrUnCorErrData_63_0[64];
2094 };
2095 struct QIB_7322_PcieRetryBufrUnCorErrLogA {
2096 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb );
2097 };
2098 /* Default value: 0x0000000000000000 */
2099
2100 #define QIB_7322_PcieRetryBufrUnCorErrLogB_offset 0x00000788UL
2101 struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb {
2102 pseudo_bit_t PcieRetryBufrUnCorErrData_127_64[64];
2103 };
2104 struct QIB_7322_PcieRetryBufrUnCorErrLogB {
2105 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb );
2106 };
2107 /* Default value: 0x0000000000000000 */
2108
2109 #define QIB_7322_PcieRetryBufrUnCorErrLogC_offset 0x00000790UL
2110 struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb {
2111 pseudo_bit_t PcieRetryBufrUnCorErrData_133_128[6];
2112 pseudo_bit_t PcieRetryBufrUnCorErrCheckBit_20_0[21];
2113 pseudo_bit_t PcieRetryBufrUnCorErrAddr_13_0[14];
2114 pseudo_bit_t _unused_0[23];
2115 };
2116 struct QIB_7322_PcieRetryBufrUnCorErrLogC {
2117 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb );
2118 };
2119 /* Default value: 0x0000000000000000 */
2120
2121 #define QIB_7322_RxTIDArrayUnCorErrLogA_offset 0x00000800UL
2122 struct QIB_7322_RxTIDArrayUnCorErrLogA_pb {
2123 pseudo_bit_t RxTIDArrayUnCorErrData_39_0[40];
2124 pseudo_bit_t RxTIDArrayUnCorErrCheckBit_11_0[12];
2125 pseudo_bit_t _unused_0[12];
2126 };
2127 struct QIB_7322_RxTIDArrayUnCorErrLogA {
2128 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogA_pb );
2129 };
2130 /* Default value: 0x0000000000000000 */
2131
2132 #define QIB_7322_RxTIDArrayUnCorErrLogB_offset 0x00000808UL
2133 struct QIB_7322_RxTIDArrayUnCorErrLogB_pb {
2134 pseudo_bit_t RxTIDArrayUnCorErrAddr_16_0[17];
2135 pseudo_bit_t _unused_0[47];
2136 };
2137 struct QIB_7322_RxTIDArrayUnCorErrLogB {
2138 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogB_pb );
2139 };
2140 /* Default value: 0x0000000000000000 */
2141
2142 #define QIB_7322_RxEagerArrayUnCorErrLogA_offset 0x00000810UL
2143 struct QIB_7322_RxEagerArrayUnCorErrLogA_pb {
2144 pseudo_bit_t RxEagerArrayUnCorErrData_39_0[40];
2145 pseudo_bit_t RxEagerArrayUnCorErrCheckBit_11_0[12];
2146 pseudo_bit_t _unused_0[12];
2147 };
2148 struct QIB_7322_RxEagerArrayUnCorErrLogA {
2149 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogA_pb );
2150 };
2151 /* Default value: 0x0000000000000000 */
2152
2153 #define QIB_7322_RxEagerArrayUnCorErrLogB_offset 0x00000818UL
2154 struct QIB_7322_RxEagerArrayUnCorErrLogB_pb {
2155 pseudo_bit_t RxEagerArrayUnCorErrAddr_17_0[18];
2156 pseudo_bit_t _unused_0[46];
2157 };
2158 struct QIB_7322_RxEagerArrayUnCorErrLogB {
2159 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogB_pb );
2160 };
2161 /* Default value: 0x0000000000000000 */
2162
2163 #define QIB_7322_SBufMainArrayUnCorErrLogA_offset 0x00000880UL
2164 struct QIB_7322_SBufMainArrayUnCorErrLogA_pb {
2165 pseudo_bit_t SBufMainArrayUnCorErrData_63_0[64];
2166 };
2167 struct QIB_7322_SBufMainArrayUnCorErrLogA {
2168 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogA_pb );
2169 };
2170 /* Default value: 0x0000000000000000 */
2171
2172 #define QIB_7322_SBufMainArrayUnCorErrLogB_offset 0x00000888UL
2173 struct QIB_7322_SBufMainArrayUnCorErrLogB_pb {
2174 pseudo_bit_t SBufMainArrayUnCorErrData_127_64[64];
2175 };
2176 struct QIB_7322_SBufMainArrayUnCorErrLogB {
2177 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogB_pb );
2178 };
2179 /* Default value: 0x0000000000000000 */
2180
2181 #define QIB_7322_SBufMainArrayUnCorErrLogC_offset 0x00000890UL
2182 struct QIB_7322_SBufMainArrayUnCorErrLogC_pb {
2183 pseudo_bit_t SBufMainArrayUnCorErrCheckBit_27_0[28];
2184 pseudo_bit_t SBufMainArrayUnCorErrAddr_18_0[19];
2185 pseudo_bit_t _unused_0[13];
2186 pseudo_bit_t SBufMainArrayUnCorErrDword_3_0[4];
2187 };
2188 struct QIB_7322_SBufMainArrayUnCorErrLogC {
2189 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogC_pb );
2190 };
2191 /* Default value: 0x0000000000000000 */
2192
2193 #define QIB_7322_SBufExtraArrayUnCorErrLogA_offset 0x00000898UL
2194 struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb {
2195 pseudo_bit_t SBufExtraArrayUnCorErrData_63_0[64];
2196 };
2197 struct QIB_7322_SBufExtraArrayUnCorErrLogA {
2198 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb );
2199 };
2200 /* Default value: 0x0000000000000000 */
2201
2202 #define QIB_7322_SBufExtraArrayUnCorErrLogB_offset 0x000008a0UL
2203 struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb {
2204 pseudo_bit_t SBufExtraArrayUnCorErrData_127_64[64];
2205 };
2206 struct QIB_7322_SBufExtraArrayUnCorErrLogB {
2207 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb );
2208 };
2209 /* Default value: 0x0000000000000000 */
2210
2211 #define QIB_7322_SBufExtraArrayUnCorErrLogC_offset 0x000008a8UL
2212 struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb {
2213 pseudo_bit_t SBufExtraArrayUnCorErrCheckBit_27_0[28];
2214 pseudo_bit_t SBufExtraArrayUnCorErrAddr_14_0[15];
2215 pseudo_bit_t _unused_0[17];
2216 pseudo_bit_t SBufExtraArrayUnCorErrAdd_3_0[4];
2217 };
2218 struct QIB_7322_SBufExtraArrayUnCorErrLogC {
2219 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb );
2220 };
2221 /* Default value: 0x0000000000000000 */
2222
2223 #define QIB_7322_SendPbcArrayUnCorErrLog_offset 0x000008b0UL
2224 struct QIB_7322_SendPbcArrayUnCorErrLog_pb {
2225 pseudo_bit_t SendPbcArrayUnCorErrData_21_0[22];
2226 pseudo_bit_t SendPbcArrayUnCorErrCheckBit_6_0[7];
2227 pseudo_bit_t SendPbcArrayUnCorErrAddr_9_0[10];
2228 pseudo_bit_t _unused_0[25];
2229 };
2230 struct QIB_7322_SendPbcArrayUnCorErrLog {
2231 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayUnCorErrLog_pb );
2232 };
2233 /* Default value: 0x0000000000000000 */
2234
2235 #define QIB_7322_SBufVL15ArrayUnCorErrLogA_offset 0x000008c0UL
2236 struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb {
2237 pseudo_bit_t SBufVL15ArrayUnCorErrData_63_0[64];
2238 };
2239 struct QIB_7322_SBufVL15ArrayUnCorErrLogA {
2240 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb );
2241 };
2242 /* Default value: 0x0000000000000000 */
2243
2244 #define QIB_7322_PcieCplDataBufrCorErrLogA_offset 0x00000900UL
2245 struct QIB_7322_PcieCplDataBufrCorErrLogA_pb {
2246 pseudo_bit_t PcieCplDataBufrCorErrData_63_0[64];
2247 };
2248 struct QIB_7322_PcieCplDataBufrCorErrLogA {
2249 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogA_pb );
2250 };
2251 /* Default value: 0x0000000000000000 */
2252
2253 #define QIB_7322_PcieCplDataBufrCorErrLogB_offset 0x00000908UL
2254 struct QIB_7322_PcieCplDataBufrCorErrLogB_pb {
2255 pseudo_bit_t PcieCplDataBufrCorErrData_127_64[64];
2256 };
2257 struct QIB_7322_PcieCplDataBufrCorErrLogB {
2258 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogB_pb );
2259 };
2260 /* Default value: 0x0000000000000000 */
2261
2262 #define QIB_7322_PcieCplDataBufrCorErrLogC_offset 0x00000910UL
2263 struct QIB_7322_PcieCplDataBufrCorErrLogC_pb {
2264 pseudo_bit_t PcieCplDataBufrCorErrData_136_128[9];
2265 pseudo_bit_t PcieCplDataBufrCorErrCheckBit_21_0[22];
2266 pseudo_bit_t PcieCplDataBufrCorErrAddr_13_0[14];
2267 pseudo_bit_t _unused_0[19];
2268 };
2269 struct QIB_7322_PcieCplDataBufrCorErrLogC {
2270 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogC_pb );
2271 };
2272 /* Default value: 0x0000000000000000 */
2273
2274 #define QIB_7322_PcieCplHdrBufrCorErrLogA_offset 0x00000920UL
2275 struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb {
2276 pseudo_bit_t PcieCplHdrBufrCorErrHdr_63_0[64];
2277 };
2278 struct QIB_7322_PcieCplHdrBufrCorErrLogA {
2279 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb );
2280 };
2281 /* Default value: 0x0000000000000000 */
2282
2283 #define QIB_7322_PcieCplHdrBufrCorErrLogB_offset 0x00000928UL
2284 struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb {
2285 pseudo_bit_t PcieCplHdrBufrCorErrHdr_103_64[40];
2286 pseudo_bit_t _unused_0[24];
2287 };
2288 struct QIB_7322_PcieCplHdrBufrCorErrLogB {
2289 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb );
2290 };
2291 /* Default value: 0x0000000000000000 */
2292
2293 #define QIB_7322_PcieCplHdrBufrCorErrLogC_offset 0x00000930UL
2294 struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb {
2295 pseudo_bit_t PcieCplHdrBufrCorErrCheckBit_15_0[16];
2296 pseudo_bit_t PcieCplHdrBufrCorErrAddr_8_0[9];
2297 pseudo_bit_t _unused_0[39];
2298 };
2299 struct QIB_7322_PcieCplHdrBufrCorErrLogC {
2300 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb );
2301 };
2302 /* Default value: 0x0000000000000000 */
2303
2304 #define QIB_7322_PciePDataBufrCorErrLogA_offset 0x00000940UL
2305 struct QIB_7322_PciePDataBufrCorErrLogA_pb {
2306 pseudo_bit_t PciePDataBufrCorErrData_63_0[64];
2307 };
2308 struct QIB_7322_PciePDataBufrCorErrLogA {
2309 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogA_pb );
2310 };
2311 /* Default value: 0x0000000000000000 */
2312
2313 #define QIB_7322_PciePDataBufrCorErrLogB_offset 0x00000948UL
2314 struct QIB_7322_PciePDataBufrCorErrLogB_pb {
2315 pseudo_bit_t PciePDataBufrCorErrData_127_64[64];
2316 };
2317 struct QIB_7322_PciePDataBufrCorErrLogB {
2318 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogB_pb );
2319 };
2320 /* Default value: 0x0000000000000000 */
2321
2322 #define QIB_7322_PciePDataBufrCorErrLogC_offset 0x00000950UL
2323 struct QIB_7322_PciePDataBufrCorErrLogC_pb {
2324 pseudo_bit_t PciePDataBufrCorErrData_136_128[9];
2325 pseudo_bit_t PciePDataBufrCorErrCheckBit_21_0[22];
2326 pseudo_bit_t PciePDataBufrCorErrAddr_13_0[14];
2327 pseudo_bit_t _unused_0[19];
2328 };
2329 struct QIB_7322_PciePDataBufrCorErrLogC {
2330 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogC_pb );
2331 };
2332 /* Default value: 0x0000000000000000 */
2333
2334 #define QIB_7322_PciePHdrBufrCorErrLogA_offset 0x00000960UL
2335 struct QIB_7322_PciePHdrBufrCorErrLogA_pb {
2336 pseudo_bit_t PciePHdrBufrCorErrData_63_0[64];
2337 };
2338 struct QIB_7322_PciePHdrBufrCorErrLogA {
2339 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogA_pb );
2340 };
2341 /* Default value: 0x0000000000000000 */
2342
2343 #define QIB_7322_PciePHdrBufrCorErrLogB_offset 0x00000968UL
2344 struct QIB_7322_PciePHdrBufrCorErrLogB_pb {
2345 pseudo_bit_t PciePHdrBufrCorErrData_107_64[44];
2346 pseudo_bit_t _unused_0[20];
2347 };
2348 struct QIB_7322_PciePHdrBufrCorErrLogB {
2349 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogB_pb );
2350 };
2351 /* Default value: 0x0000000000000000 */
2352
2353 #define QIB_7322_PciePHdrBufrCorErrLogC_offset 0x00000970UL
2354 struct QIB_7322_PciePHdrBufrCorErrLogC_pb {
2355 pseudo_bit_t PciePHdrBufrCorErrCheckBit_15_0[16];
2356 pseudo_bit_t PciePHdrBufrCorErrAddr_8_0[9];
2357 pseudo_bit_t _unused_0[39];
2358 };
2359 struct QIB_7322_PciePHdrBufrCorErrLogC {
2360 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogC_pb );
2361 };
2362 /* Default value: 0x0000000000000000 */
2363
2364 #define QIB_7322_PcieRetryBufrCorErrLogA_offset 0x00000980UL
2365 struct QIB_7322_PcieRetryBufrCorErrLogA_pb {
2366 pseudo_bit_t PcieRetryBufrCorErrData_63_0[64];
2367 };
2368 struct QIB_7322_PcieRetryBufrCorErrLogA {
2369 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogA_pb );
2370 };
2371 /* Default value: 0x0000000000000000 */
2372
2373 #define QIB_7322_PcieRetryBufrCorErrLogB_offset 0x00000988UL
2374 struct QIB_7322_PcieRetryBufrCorErrLogB_pb {
2375 pseudo_bit_t PcieRetryBufrCorErrData_127_64[64];
2376 };
2377 struct QIB_7322_PcieRetryBufrCorErrLogB {
2378 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogB_pb );
2379 };
2380 /* Default value: 0x0000000000000000 */
2381
2382 #define QIB_7322_PcieRetryBufrCorErrLogC_offset 0x00000990UL
2383 struct QIB_7322_PcieRetryBufrCorErrLogC_pb {
2384 pseudo_bit_t PcieRetryBufrCorErrData_133_128[6];
2385 pseudo_bit_t PcieRetryBufrCorErrCheckBit_20_0[21];
2386 pseudo_bit_t PcieRetryBufrCorErrAddr_13_0[14];
2387 pseudo_bit_t _unused_0[23];
2388 };
2389 struct QIB_7322_PcieRetryBufrCorErrLogC {
2390 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogC_pb );
2391 };
2392 /* Default value: 0x0000000000000000 */
2393
2394 #define QIB_7322_RxTIDArrayCorErrLogA_offset 0x00000a00UL
2395 struct QIB_7322_RxTIDArrayCorErrLogA_pb {
2396 pseudo_bit_t RxTIDArrayCorErrData_39_0[40];
2397 pseudo_bit_t RxTIDArrayCorErrCheckBit_11_0[12];
2398 pseudo_bit_t _unused_0[12];
2399 };
2400 struct QIB_7322_RxTIDArrayCorErrLogA {
2401 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogA_pb );
2402 };
2403 /* Default value: 0x0000000000000000 */
2404
2405 #define QIB_7322_RxTIDArrayCorErrLogB_offset 0x00000a08UL
2406 struct QIB_7322_RxTIDArrayCorErrLogB_pb {
2407 pseudo_bit_t RxTIDArrayCorErrAddr_16_0[17];
2408 pseudo_bit_t _unused_0[47];
2409 };
2410 struct QIB_7322_RxTIDArrayCorErrLogB {
2411 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogB_pb );
2412 };
2413 /* Default value: 0x0000000000000000 */
2414
2415 #define QIB_7322_RxEagerArrayCorErrLogA_offset 0x00000a10UL
2416 struct QIB_7322_RxEagerArrayCorErrLogA_pb {
2417 pseudo_bit_t RxEagerArrayCorErrData_39_0[40];
2418 pseudo_bit_t RxEagerArrayCorErrCheckBit_11_0[12];
2419 pseudo_bit_t _unused_0[12];
2420 };
2421 struct QIB_7322_RxEagerArrayCorErrLogA {
2422 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogA_pb );
2423 };
2424 /* Default value: 0x0000000000000000 */
2425
2426 #define QIB_7322_RxEagerArrayCorErrLogB_offset 0x00000a18UL
2427 struct QIB_7322_RxEagerArrayCorErrLogB_pb {
2428 pseudo_bit_t RxEagerArrayCorErrAddr_17_0[18];
2429 pseudo_bit_t _unused_0[46];
2430 };
2431 struct QIB_7322_RxEagerArrayCorErrLogB {
2432 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogB_pb );
2433 };
2434 /* Default value: 0x0000000000000000 */
2435
2436 #define QIB_7322_SBufMainArrayCorErrLogA_offset 0x00000a80UL
2437 struct QIB_7322_SBufMainArrayCorErrLogA_pb {
2438 pseudo_bit_t SBufMainArrayCorErrData_63_0[64];
2439 };
2440 struct QIB_7322_SBufMainArrayCorErrLogA {
2441 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogA_pb );
2442 };
2443 /* Default value: 0x0000000000000000 */
2444
2445 #define QIB_7322_SBufMainArrayCorErrLogB_offset 0x00000a88UL
2446 struct QIB_7322_SBufMainArrayCorErrLogB_pb {
2447 pseudo_bit_t SBufMainArrayCorErrData_127_64[64];
2448 };
2449 struct QIB_7322_SBufMainArrayCorErrLogB {
2450 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogB_pb );
2451 };
2452 /* Default value: 0x0000000000000000 */
2453
2454 #define QIB_7322_SBufMainArrayCorErrLogC_offset 0x00000a90UL
2455 struct QIB_7322_SBufMainArrayCorErrLogC_pb {
2456 pseudo_bit_t SBufMainArrayCorErrCheckBit_27_0[28];
2457 pseudo_bit_t SBufMainArrayCorErrAddr_18_0[19];
2458 pseudo_bit_t _unused_0[13];
2459 pseudo_bit_t SBufMainArrayCorErrDword_3_0[4];
2460 };
2461 struct QIB_7322_SBufMainArrayCorErrLogC {
2462 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogC_pb );
2463 };
2464 /* Default value: 0x0000000000000000 */
2465
2466 #define QIB_7322_SBufExtraArrayCorErrLogA_offset 0x00000a98UL
2467 struct QIB_7322_SBufExtraArrayCorErrLogA_pb {
2468 pseudo_bit_t SBufExtraArrayCorErrData_63_0[64];
2469 };
2470 struct QIB_7322_SBufExtraArrayCorErrLogA {
2471 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogA_pb );
2472 };
2473 /* Default value: 0x0000000000000000 */
2474
2475 #define QIB_7322_SBufExtraArrayCorErrLogB_offset 0x00000aa0UL
2476 struct QIB_7322_SBufExtraArrayCorErrLogB_pb {
2477 pseudo_bit_t SBufExtraArrayCorErrData_127_64[64];
2478 };
2479 struct QIB_7322_SBufExtraArrayCorErrLogB {
2480 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogB_pb );
2481 };
2482 /* Default value: 0x0000000000000000 */
2483
2484 #define QIB_7322_SBufExtraArrayCorErrLogC_offset 0x00000aa8UL
2485 struct QIB_7322_SBufExtraArrayCorErrLogC_pb {
2486 pseudo_bit_t SBufExtraArrayCorErrCheckBit_27_0[28];
2487 pseudo_bit_t SBufExtraArrayCorErrAddr_14_0[15];
2488 pseudo_bit_t _unused_0[17];
2489 pseudo_bit_t SBufExtraArrayCorErrAdd_3_0[4];
2490 };
2491 struct QIB_7322_SBufExtraArrayCorErrLogC {
2492 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogC_pb );
2493 };
2494 /* Default value: 0x0000000000000000 */
2495
2496 #define QIB_7322_SendPbcArrayCorErrLog_offset 0x00000ab0UL
2497 struct QIB_7322_SendPbcArrayCorErrLog_pb {
2498 pseudo_bit_t SendPbcArrayCorErrData_21_0[22];
2499 pseudo_bit_t SendPbcArrayCorErrCheckBit_6_0[7];
2500 pseudo_bit_t SendPbcArrayCorErrAddr_9_0[10];
2501 pseudo_bit_t _unused_0[25];
2502 };
2503 struct QIB_7322_SendPbcArrayCorErrLog {
2504 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayCorErrLog_pb );
2505 };
2506 /* Default value: 0x0000000000000000 */
2507
2508 #define QIB_7322_SBufVL15ArrayCorErrLogA_offset 0x00000ac0UL
2509 struct QIB_7322_SBufVL15ArrayCorErrLogA_pb {
2510 pseudo_bit_t SBufVL15ArrayCorErrData_63_0[64];
2511 };
2512 struct QIB_7322_SBufVL15ArrayCorErrLogA {
2513 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayCorErrLogA_pb );
2514 };
2515 /* Default value: 0x0000000000000000 */
2516
2517 #define QIB_7322_RcvAvailTimeOut0_offset 0x00000c00UL
2518 struct QIB_7322_RcvAvailTimeOut0_pb {
2519 pseudo_bit_t RcvAvailTOReload[16];
2520 pseudo_bit_t RcvAvailTOCount[16];
2521 pseudo_bit_t _unused_0[32];
2522 };
2523 struct QIB_7322_RcvAvailTimeOut0 {
2524 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvAvailTimeOut0_pb );
2525 };
2526 /* Default value: 0x0000000000000000 */
2527
2528 #define QIB_7322_CntrRegBase_0_offset 0x00001028UL
2529 /* Default value: 0x0000000000012000 */
2530
2531 #define QIB_7322_ErrMask_0_offset 0x00001080UL
2532 struct QIB_7322_ErrMask_0_pb {
2533 pseudo_bit_t RcvFormatErrMask[1];
2534 pseudo_bit_t RcvVCRCErrMask[1];
2535 pseudo_bit_t RcvICRCErrMask[1];
2536 pseudo_bit_t RcvMinPktLenErrMask[1];
2537 pseudo_bit_t RcvMaxPktLenErrMask[1];
2538 pseudo_bit_t RcvLongPktLenErrMask[1];
2539 pseudo_bit_t RcvShortPktLenErrMask[1];
2540 pseudo_bit_t RcvUnexpectedCharErrMask[1];
2541 pseudo_bit_t RcvUnsupportedVLErrMask[1];
2542 pseudo_bit_t RcvEBPErrMask[1];
2543 pseudo_bit_t RcvIBFlowErrMask[1];
2544 pseudo_bit_t RcvBadVersionErrMask[1];
2545 pseudo_bit_t _unused_0[2];
2546 pseudo_bit_t RcvBadTidErrMask[1];
2547 pseudo_bit_t RcvHdrLenErrMask[1];
2548 pseudo_bit_t RcvHdrErrMask[1];
2549 pseudo_bit_t RcvIBLostLinkErrMask[1];
2550 pseudo_bit_t _unused_1[11];
2551 pseudo_bit_t SendMinPktLenErrMask[1];
2552 pseudo_bit_t SendMaxPktLenErrMask[1];
2553 pseudo_bit_t SendUnderRunErrMask[1];
2554 pseudo_bit_t SendPktLenErrMask[1];
2555 pseudo_bit_t SendDroppedSmpPktErrMask[1];
2556 pseudo_bit_t SendDroppedDataPktErrMask[1];
2557 pseudo_bit_t _unused_2[1];
2558 pseudo_bit_t SendUnexpectedPktNumErrMask[1];
2559 pseudo_bit_t SendUnsupportedVLErrMask[1];
2560 pseudo_bit_t SendBufMisuseErrMask[1];
2561 pseudo_bit_t SDmaGenMismatchErrMask[1];
2562 pseudo_bit_t SDmaOutOfBoundErrMask[1];
2563 pseudo_bit_t SDmaTailOutOfBoundErrMask[1];
2564 pseudo_bit_t SDmaBaseErrMask[1];
2565 pseudo_bit_t SDma1stDescErrMask[1];
2566 pseudo_bit_t SDmaRpyTagErrMask[1];
2567 pseudo_bit_t SDmaDwEnErrMask[1];
2568 pseudo_bit_t SDmaMissingDwErrMask[1];
2569 pseudo_bit_t SDmaUnexpDataErrMask[1];
2570 pseudo_bit_t SDmaDescAddrMisalignErrMask[1];
2571 pseudo_bit_t SDmaHaltErrMask[1];
2572 pseudo_bit_t _unused_3[4];
2573 pseudo_bit_t VL15BufMisuseErrMask[1];
2574 pseudo_bit_t _unused_4[2];
2575 pseudo_bit_t SHeadersErrMask[1];
2576 pseudo_bit_t IBStatusChangedMask[1];
2577 pseudo_bit_t _unused_5[5];
2578 };
2579 struct QIB_7322_ErrMask_0 {
2580 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_0_pb );
2581 };
2582 /* Default value: 0x0000000000000000 */
2583
2584 #define QIB_7322_ErrStatus_0_offset 0x00001088UL
2585 struct QIB_7322_ErrStatus_0_pb {
2586 pseudo_bit_t RcvFormatErr[1];
2587 pseudo_bit_t RcvVCRCErr[1];
2588 pseudo_bit_t RcvICRCErr[1];
2589 pseudo_bit_t RcvMinPktLenErr[1];
2590 pseudo_bit_t RcvMaxPktLenErr[1];
2591 pseudo_bit_t RcvLongPktLenErr[1];
2592 pseudo_bit_t RcvShortPktLenErr[1];
2593 pseudo_bit_t RcvUnexpectedCharErr[1];
2594 pseudo_bit_t RcvUnsupportedVLErr[1];
2595 pseudo_bit_t RcvEBPErr[1];
2596 pseudo_bit_t RcvIBFlowErr[1];
2597 pseudo_bit_t RcvBadVersionErr[1];
2598 pseudo_bit_t _unused_0[2];
2599 pseudo_bit_t RcvBadTidErr[1];
2600 pseudo_bit_t RcvHdrLenErr[1];
2601 pseudo_bit_t RcvHdrErr[1];
2602 pseudo_bit_t RcvIBLostLinkErr[1];
2603 pseudo_bit_t _unused_1[11];
2604 pseudo_bit_t SendMinPktLenErr[1];
2605 pseudo_bit_t SendMaxPktLenErr[1];
2606 pseudo_bit_t SendUnderRunErr[1];
2607 pseudo_bit_t SendPktLenErr[1];
2608 pseudo_bit_t SendDroppedSmpPktErr[1];
2609 pseudo_bit_t SendDroppedDataPktErr[1];
2610 pseudo_bit_t _unused_2[1];
2611 pseudo_bit_t SendUnexpectedPktNumErr[1];
2612 pseudo_bit_t SendUnsupportedVLErr[1];
2613 pseudo_bit_t SendBufMisuseErr[1];
2614 pseudo_bit_t SDmaGenMismatchErr[1];
2615 pseudo_bit_t SDmaOutOfBoundErr[1];
2616 pseudo_bit_t SDmaTailOutOfBoundErr[1];
2617 pseudo_bit_t SDmaBaseErr[1];
2618 pseudo_bit_t SDma1stDescErr[1];
2619 pseudo_bit_t SDmaRpyTagErr[1];
2620 pseudo_bit_t SDmaDwEnErr[1];
2621 pseudo_bit_t SDmaMissingDwErr[1];
2622 pseudo_bit_t SDmaUnexpDataErr[1];
2623 pseudo_bit_t SDmaDescAddrMisalignErr[1];
2624 pseudo_bit_t SDmaHaltErr[1];
2625 pseudo_bit_t _unused_3[4];
2626 pseudo_bit_t VL15BufMisuseErr[1];
2627 pseudo_bit_t _unused_4[2];
2628 pseudo_bit_t SHeadersErr[1];
2629 pseudo_bit_t IBStatusChanged[1];
2630 pseudo_bit_t _unused_5[5];
2631 };
2632 struct QIB_7322_ErrStatus_0 {
2633 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_0_pb );
2634 };
2635 /* Default value: 0x0000000000000000 */
2636
2637 #define QIB_7322_ErrClear_0_offset 0x00001090UL
2638 struct QIB_7322_ErrClear_0_pb {
2639 pseudo_bit_t RcvFormatErrClear[1];
2640 pseudo_bit_t RcvVCRCErrClear[1];
2641 pseudo_bit_t RcvICRCErrClear[1];
2642 pseudo_bit_t RcvMinPktLenErrClear[1];
2643 pseudo_bit_t RcvMaxPktLenErrClear[1];
2644 pseudo_bit_t RcvLongPktLenErrClear[1];
2645 pseudo_bit_t RcvShortPktLenErrClear[1];
2646 pseudo_bit_t RcvUnexpectedCharErrClear[1];
2647 pseudo_bit_t RcvUnsupportedVLErrClear[1];
2648 pseudo_bit_t RcvEBPErrClear[1];
2649 pseudo_bit_t RcvIBFlowErrClear[1];
2650 pseudo_bit_t RcvBadVersionErrClear[1];
2651 pseudo_bit_t _unused_0[2];
2652 pseudo_bit_t RcvBadTidErrClear[1];
2653 pseudo_bit_t RcvHdrLenErrClear[1];
2654 pseudo_bit_t RcvHdrErrClear[1];
2655 pseudo_bit_t RcvIBLostLinkErrClear[1];
2656 pseudo_bit_t _unused_1[11];
2657 pseudo_bit_t SendMinPktLenErrClear[1];
2658 pseudo_bit_t SendMaxPktLenErrClear[1];
2659 pseudo_bit_t SendUnderRunErrClear[1];
2660 pseudo_bit_t SendPktLenErrClear[1];
2661 pseudo_bit_t SendDroppedSmpPktErrClear[1];
2662 pseudo_bit_t SendDroppedDataPktErrClear[1];
2663 pseudo_bit_t _unused_2[1];
2664 pseudo_bit_t SendUnexpectedPktNumErrClear[1];
2665 pseudo_bit_t SendUnsupportedVLErrClear[1];
2666 pseudo_bit_t SendBufMisuseErrClear[1];
2667 pseudo_bit_t SDmaGenMismatchErrClear[1];
2668 pseudo_bit_t SDmaOutOfBoundErrClear[1];
2669 pseudo_bit_t SDmaTailOutOfBoundErrClear[1];
2670 pseudo_bit_t SDmaBaseErrClear[1];
2671 pseudo_bit_t SDma1stDescErrClear[1];
2672 pseudo_bit_t SDmaRpyTagErrClear[1];
2673 pseudo_bit_t SDmaDwEnErrClear[1];
2674 pseudo_bit_t SDmaMissingDwErrClear[1];
2675 pseudo_bit_t SDmaUnexpDataErrClear[1];
2676 pseudo_bit_t SDmaDescAddrMisalignErrClear[1];
2677 pseudo_bit_t SDmaHaltErrClear[1];
2678 pseudo_bit_t _unused_3[4];
2679 pseudo_bit_t VL15BufMisuseErrClear[1];
2680 pseudo_bit_t _unused_4[2];
2681 pseudo_bit_t SHeadersErrClear[1];
2682 pseudo_bit_t IBStatusChangedClear[1];
2683 pseudo_bit_t _unused_5[5];
2684 };
2685 struct QIB_7322_ErrClear_0 {
2686 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_0_pb );
2687 };
2688 /* Default value: 0x0000000000000000 */
2689
2690 #define QIB_7322_TXEStatus_0_offset 0x000010b8UL
2691 struct QIB_7322_TXEStatus_0_pb {
2692 pseudo_bit_t LaFifoEmpty_VL0[1];
2693 pseudo_bit_t LaFifoEmpty_VL1[1];
2694 pseudo_bit_t LaFifoEmpty_VL2[1];
2695 pseudo_bit_t LaFifoEmpty_VL3[1];
2696 pseudo_bit_t LaFifoEmpty_VL4[1];
2697 pseudo_bit_t LaFifoEmpty_VL5[1];
2698 pseudo_bit_t LaFifoEmpty_VL6[1];
2699 pseudo_bit_t LaFifoEmpty_VL7[1];
2700 pseudo_bit_t _unused_0[7];
2701 pseudo_bit_t LaFifoEmpty_VL15[1];
2702 pseudo_bit_t _unused_1[14];
2703 pseudo_bit_t RmFifoEmpty[1];
2704 pseudo_bit_t TXE_IBC_Idle[1];
2705 pseudo_bit_t _unused_2[32];
2706 };
2707 struct QIB_7322_TXEStatus_0 {
2708 PSEUDO_BIT_STRUCT ( struct QIB_7322_TXEStatus_0_pb );
2709 };
2710 /* Default value: 0x0000000XC00080FF */
2711
2712 #define QIB_7322_RcvCtrl_0_offset 0x00001100UL
2713 struct QIB_7322_RcvCtrl_0_pb {
2714 pseudo_bit_t ContextEnableKernel[1];
2715 pseudo_bit_t _unused_0[1];
2716 pseudo_bit_t ContextEnableUser[16];
2717 pseudo_bit_t _unused_1[21];
2718 pseudo_bit_t RcvIBPortEnable[1];
2719 pseudo_bit_t RcvQPMapEnable[1];
2720 pseudo_bit_t RcvPartitionKeyDisable[1];
2721 pseudo_bit_t RcvResetCredit[1];
2722 pseudo_bit_t _unused_2[21];
2723 };
2724 struct QIB_7322_RcvCtrl_0 {
2725 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_0_pb );
2726 };
2727 /* Default value: 0x0000000000000000 */
2728
2729 #define QIB_7322_RcvBTHQP_0_offset 0x00001108UL
2730 struct QIB_7322_RcvBTHQP_0_pb {
2731 pseudo_bit_t RcvBTHQP[24];
2732 pseudo_bit_t _unused_0[40];
2733 };
2734 struct QIB_7322_RcvBTHQP_0 {
2735 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvBTHQP_0_pb );
2736 };
2737 /* Default value: 0x0000000000000000 */
2738
2739 #define QIB_7322_RcvQPMapTableA_0_offset 0x00001110UL
2740 struct QIB_7322_RcvQPMapTableA_0_pb {
2741 pseudo_bit_t RcvQPMapContext0[5];
2742 pseudo_bit_t RcvQPMapContext1[5];
2743 pseudo_bit_t RcvQPMapContext2[5];
2744 pseudo_bit_t RcvQPMapContext3[5];
2745 pseudo_bit_t RcvQPMapContext4[5];
2746 pseudo_bit_t RcvQPMapContext5[5];
2747 pseudo_bit_t _unused_0[34];
2748 };
2749 struct QIB_7322_RcvQPMapTableA_0 {
2750 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableA_0_pb );
2751 };
2752 /* Default value: 0x0000000000000000 */
2753
2754 #define QIB_7322_RcvQPMapTableB_0_offset 0x00001118UL
2755 struct QIB_7322_RcvQPMapTableB_0_pb {
2756 pseudo_bit_t RcvQPMapContext6[5];
2757 pseudo_bit_t RcvQPMapContext7[5];
2758 pseudo_bit_t RcvQPMapContext8[5];
2759 pseudo_bit_t RcvQPMapContext9[5];
2760 pseudo_bit_t RcvQPMapContext10[5];
2761 pseudo_bit_t RcvQPMapContext11[5];
2762 pseudo_bit_t _unused_0[34];
2763 };
2764 struct QIB_7322_RcvQPMapTableB_0 {
2765 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableB_0_pb );
2766 };
2767 /* Default value: 0x0000000000000000 */
2768
2769 #define QIB_7322_RcvQPMapTableC_0_offset 0x00001120UL
2770 struct QIB_7322_RcvQPMapTableC_0_pb {
2771 pseudo_bit_t RcvQPMapContext12[5];
2772 pseudo_bit_t RcvQPMapContext13[5];
2773 pseudo_bit_t RcvQPMapContext14[5];
2774 pseudo_bit_t RcvQPMapContext15[5];
2775 pseudo_bit_t RcvQPMapContext16[5];
2776 pseudo_bit_t RcvQPMapContext17[5];
2777 pseudo_bit_t _unused_0[34];
2778 };
2779 struct QIB_7322_RcvQPMapTableC_0 {
2780 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableC_0_pb );
2781 };
2782 /* Default value: 0x0000000000000000 */
2783
2784 #define QIB_7322_RcvQPMapTableD_0_offset 0x00001128UL
2785 struct QIB_7322_RcvQPMapTableD_0_pb {
2786 pseudo_bit_t RcvQPMapContext18[5];
2787 pseudo_bit_t RcvQPMapContext19[5];
2788 pseudo_bit_t RcvQPMapContext20[5];
2789 pseudo_bit_t RcvQPMapContext21[5];
2790 pseudo_bit_t RcvQPMapContext22[5];
2791 pseudo_bit_t RcvQPMapContext23[5];
2792 pseudo_bit_t _unused_0[34];
2793 };
2794 struct QIB_7322_RcvQPMapTableD_0 {
2795 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableD_0_pb );
2796 };
2797 /* Default value: 0x0000000000000000 */
2798
2799 #define QIB_7322_RcvQPMapTableE_0_offset 0x00001130UL
2800 struct QIB_7322_RcvQPMapTableE_0_pb {
2801 pseudo_bit_t RcvQPMapContext24[5];
2802 pseudo_bit_t RcvQPMapContext25[5];
2803 pseudo_bit_t RcvQPMapContext26[5];
2804 pseudo_bit_t RcvQPMapContext27[5];
2805 pseudo_bit_t RcvQPMapContext28[5];
2806 pseudo_bit_t RcvQPMapContext29[5];
2807 pseudo_bit_t _unused_0[34];
2808 };
2809 struct QIB_7322_RcvQPMapTableE_0 {
2810 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableE_0_pb );
2811 };
2812 /* Default value: 0x0000000000000000 */
2813
2814 #define QIB_7322_RcvQPMapTableF_0_offset 0x00001138UL
2815 struct QIB_7322_RcvQPMapTableF_0_pb {
2816 pseudo_bit_t RcvQPMapContext30[5];
2817 pseudo_bit_t RcvQPMapContext31[5];
2818 pseudo_bit_t _unused_0[54];
2819 };
2820 struct QIB_7322_RcvQPMapTableF_0 {
2821 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableF_0_pb );
2822 };
2823 /* Default value: 0x0000000000000000 */
2824
2825 #define QIB_7322_PSStat_0_offset 0x00001140UL
2826 /* Default value: 0x0000000000000000 */
2827
2828 #define QIB_7322_PSStart_0_offset 0x00001148UL
2829 /* Default value: 0x0000000000000000 */
2830
2831 #define QIB_7322_PSInterval_0_offset 0x00001150UL
2832 /* Default value: 0x0000000000000000 */
2833
2834 #define QIB_7322_RcvStatus_0_offset 0x00001160UL
2835 struct QIB_7322_RcvStatus_0_pb {
2836 pseudo_bit_t RxPktInProgress[1];
2837 pseudo_bit_t DmaeqBlockingContext[5];
2838 pseudo_bit_t _unused_0[58];
2839 };
2840 struct QIB_7322_RcvStatus_0 {
2841 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvStatus_0_pb );
2842 };
2843 /* Default value: 0x0000000000000000 */
2844
2845 #define QIB_7322_RcvPartitionKey_0_offset 0x00001168UL
2846 /* Default value: 0x0000000000000000 */
2847
2848 #define QIB_7322_RcvQPMulticastContext_0_offset 0x00001170UL
2849 struct QIB_7322_RcvQPMulticastContext_0_pb {
2850 pseudo_bit_t RcvQpMcContext[5];
2851 pseudo_bit_t _unused_0[59];
2852 };
2853 struct QIB_7322_RcvQPMulticastContext_0 {
2854 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMulticastContext_0_pb );
2855 };
2856 /* Default value: 0x0000000000000000 */
2857
2858 #define QIB_7322_RcvPktLEDCnt_0_offset 0x00001178UL
2859 struct QIB_7322_RcvPktLEDCnt_0_pb {
2860 pseudo_bit_t OFFperiod[32];
2861 pseudo_bit_t ONperiod[32];
2862 };
2863 struct QIB_7322_RcvPktLEDCnt_0 {
2864 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvPktLEDCnt_0_pb );
2865 };
2866 /* Default value: 0x0000000000000000 */
2867
2868 #define QIB_7322_SendDmaIdleCnt_0_offset 0x00001180UL
2869 struct QIB_7322_SendDmaIdleCnt_0_pb {
2870 pseudo_bit_t SendDmaIdleCnt[16];
2871 pseudo_bit_t _unused_0[48];
2872 };
2873 struct QIB_7322_SendDmaIdleCnt_0 {
2874 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaIdleCnt_0_pb );
2875 };
2876 /* Default value: 0x0000000000000000 */
2877
2878 #define QIB_7322_SendDmaReloadCnt_0_offset 0x00001188UL
2879 struct QIB_7322_SendDmaReloadCnt_0_pb {
2880 pseudo_bit_t SendDmaReloadCnt[16];
2881 pseudo_bit_t _unused_0[48];
2882 };
2883 struct QIB_7322_SendDmaReloadCnt_0 {
2884 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReloadCnt_0_pb );
2885 };
2886 /* Default value: 0x0000000000000000 */
2887
2888 #define QIB_7322_SendDmaDescCnt_0_offset 0x00001190UL
2889 struct QIB_7322_SendDmaDescCnt_0_pb {
2890 pseudo_bit_t SendDmaDescCnt[16];
2891 pseudo_bit_t _unused_0[48];
2892 };
2893 struct QIB_7322_SendDmaDescCnt_0 {
2894 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaDescCnt_0_pb );
2895 };
2896 /* Default value: 0x0000000000000000 */
2897
2898 #define QIB_7322_SendCtrl_0_offset 0x000011c0UL
2899 struct QIB_7322_SendCtrl_0_pb {
2900 pseudo_bit_t TxeAbortIbc[1];
2901 pseudo_bit_t TxeBypassIbc[1];
2902 pseudo_bit_t _unused_0[1];
2903 pseudo_bit_t SendEnable[1];
2904 pseudo_bit_t _unused_1[3];
2905 pseudo_bit_t ForceCreditUpToDate[1];
2906 pseudo_bit_t SDmaCleanup[1];
2907 pseudo_bit_t SDmaIntEnable[1];
2908 pseudo_bit_t SDmaSingleDescriptor[1];
2909 pseudo_bit_t SDmaEnable[1];
2910 pseudo_bit_t SDmaHalt[1];
2911 pseudo_bit_t TxeDrainLaFifo[1];
2912 pseudo_bit_t TxeDrainRmFifo[1];
2913 pseudo_bit_t IBVLArbiterEn[1];
2914 pseudo_bit_t _unused_2[48];
2915 };
2916 struct QIB_7322_SendCtrl_0 {
2917 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_0_pb );
2918 };
2919 /* Default value: 0x0000000000000000 */
2920
2921 #define QIB_7322_SendDmaBase_0_offset 0x000011f8UL
2922 struct QIB_7322_SendDmaBase_0_pb {
2923 pseudo_bit_t SendDmaBase[48];
2924 pseudo_bit_t _unused_0[16];
2925 };
2926 struct QIB_7322_SendDmaBase_0 {
2927 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBase_0_pb );
2928 };
2929 /* Default value: 0x0000000000000000 */
2930
2931 #define QIB_7322_SendDmaLenGen_0_offset 0x00001200UL
2932 struct QIB_7322_SendDmaLenGen_0_pb {
2933 pseudo_bit_t Length[16];
2934 pseudo_bit_t Generation[3];
2935 pseudo_bit_t _unused_0[45];
2936 };
2937 struct QIB_7322_SendDmaLenGen_0 {
2938 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaLenGen_0_pb );
2939 };
2940 /* Default value: 0x0000000000000000 */
2941
2942 #define QIB_7322_SendDmaTail_0_offset 0x00001208UL
2943 struct QIB_7322_SendDmaTail_0_pb {
2944 pseudo_bit_t SendDmaTail[16];
2945 pseudo_bit_t _unused_0[48];
2946 };
2947 struct QIB_7322_SendDmaTail_0 {
2948 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaTail_0_pb );
2949 };
2950 /* Default value: 0x0000000000000000 */
2951
2952 #define QIB_7322_SendDmaHead_0_offset 0x00001210UL
2953 struct QIB_7322_SendDmaHead_0_pb {
2954 pseudo_bit_t SendDmaHead[16];
2955 pseudo_bit_t _unused_0[16];
2956 pseudo_bit_t InternalSendDmaHead[16];
2957 pseudo_bit_t _unused_1[16];
2958 };
2959 struct QIB_7322_SendDmaHead_0 {
2960 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHead_0_pb );
2961 };
2962 /* Default value: 0x0000000000000000 */
2963
2964 #define QIB_7322_SendDmaHeadAddr_0_offset 0x00001218UL
2965 struct QIB_7322_SendDmaHeadAddr_0_pb {
2966 pseudo_bit_t SendDmaHeadAddr[48];
2967 pseudo_bit_t _unused_0[16];
2968 };
2969 struct QIB_7322_SendDmaHeadAddr_0 {
2970 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHeadAddr_0_pb );
2971 };
2972 /* Default value: 0x0000000000000000 */
2973
2974 #define QIB_7322_SendDmaBufMask0_0_offset 0x00001220UL
2975 struct QIB_7322_SendDmaBufMask0_0_pb {
2976 pseudo_bit_t BufMask_63_0[64];
2977 };
2978 struct QIB_7322_SendDmaBufMask0_0 {
2979 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufMask0_0_pb );
2980 };
2981 /* Default value: 0x0000000000000000 */
2982
2983 #define QIB_7322_SendDmaStatus_0_offset 0x00001238UL
2984 struct QIB_7322_SendDmaStatus_0_pb {
2985 pseudo_bit_t SplFifoDescIndex[16];
2986 pseudo_bit_t SplFifoBufNum[8];
2987 pseudo_bit_t SplFifoFull[1];
2988 pseudo_bit_t SplFifoEmpty[1];
2989 pseudo_bit_t SplFifoDisarmed[1];
2990 pseudo_bit_t SplFifoReadyToGo[1];
2991 pseudo_bit_t ScbFetchDescFlag[1];
2992 pseudo_bit_t ScbEntryValid[1];
2993 pseudo_bit_t ScbEmpty[1];
2994 pseudo_bit_t ScbFull[1];
2995 pseudo_bit_t RpyTag_7_0[8];
2996 pseudo_bit_t RpyLowAddr_6_0[7];
2997 pseudo_bit_t ScbDescIndex_13_0[14];
2998 pseudo_bit_t InternalSDmaHalt[1];
2999 pseudo_bit_t HaltInProg[1];
3000 pseudo_bit_t ScoreBoardDrainInProg[1];
3001 };
3002 struct QIB_7322_SendDmaStatus_0 {
3003 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaStatus_0_pb );
3004 };
3005 /* Default value: 0x0000000042000000 */
3006
3007 #define QIB_7322_SendDmaPriorityThld_0_offset 0x00001258UL
3008 struct QIB_7322_SendDmaPriorityThld_0_pb {
3009 pseudo_bit_t PriorityThreshold[4];
3010 pseudo_bit_t _unused_0[60];
3011 };
3012 struct QIB_7322_SendDmaPriorityThld_0 {
3013 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaPriorityThld_0_pb );
3014 };
3015 /* Default value: 0x0000000000000000 */
3016
3017 #define QIB_7322_SendHdrErrSymptom_0_offset 0x00001260UL
3018 struct QIB_7322_SendHdrErrSymptom_0_pb {
3019 pseudo_bit_t PacketTooSmall[1];
3020 pseudo_bit_t RawIPV6[1];
3021 pseudo_bit_t SLIDFail[1];
3022 pseudo_bit_t QPFail[1];
3023 pseudo_bit_t PkeyFail[1];
3024 pseudo_bit_t GRHFail[1];
3025 pseudo_bit_t NonKeyPacket[1];
3026 pseudo_bit_t _unused_0[57];
3027 };
3028 struct QIB_7322_SendHdrErrSymptom_0 {
3029 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendHdrErrSymptom_0_pb );
3030 };
3031 /* Default value: 0x0000000000000000 */
3032
3033 #define QIB_7322_RxCreditVL0_0_offset 0x00001280UL
3034 struct QIB_7322_RxCreditVL0_0_pb {
3035 pseudo_bit_t RxMaxCreditVL[12];
3036 pseudo_bit_t _unused_0[4];
3037 pseudo_bit_t RxBufrConsumedVL[12];
3038 pseudo_bit_t _unused_1[36];
3039 };
3040 struct QIB_7322_RxCreditVL0_0 {
3041 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxCreditVL0_0_pb );
3042 };
3043 /* Default value: 0x0000000000000000 */
3044
3045 #define QIB_7322_SendDmaBufUsed0_0_offset 0x00001480UL
3046 struct QIB_7322_SendDmaBufUsed0_0_pb {
3047 pseudo_bit_t BufUsed_63_0[64];
3048 };
3049 struct QIB_7322_SendDmaBufUsed0_0 {
3050 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufUsed0_0_pb );
3051 };
3052 /* Default value: 0x0000000000000000 */
3053
3054 #define QIB_7322_SendDmaReqTagUsed_0_offset 0x00001498UL
3055 struct QIB_7322_SendDmaReqTagUsed_0_pb {
3056 pseudo_bit_t ReqTagUsed_7_0[8];
3057 pseudo_bit_t _unused_0[56];
3058 };
3059 struct QIB_7322_SendDmaReqTagUsed_0 {
3060 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReqTagUsed_0_pb );
3061 };
3062 /* Default value: 0x0000000000000000 */
3063
3064 #define QIB_7322_SendCheckControl_0_offset 0x000014a8UL
3065 struct QIB_7322_SendCheckControl_0_pb {
3066 pseudo_bit_t PacketTooSmall_En[1];
3067 pseudo_bit_t RawIPV6_En[1];
3068 pseudo_bit_t SLID_En[1];
3069 pseudo_bit_t BTHQP_En[1];
3070 pseudo_bit_t PKey_En[1];
3071 pseudo_bit_t _unused_0[59];
3072 };
3073 struct QIB_7322_SendCheckControl_0 {
3074 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckControl_0_pb );
3075 };
3076 /* Default value: 0x0000000000000000 */
3077
3078 #define QIB_7322_SendIBSLIDMask_0_offset 0x000014b0UL
3079 struct QIB_7322_SendIBSLIDMask_0_pb {
3080 pseudo_bit_t SendIBSLIDMask_15_0[16];
3081 pseudo_bit_t _unused_0[48];
3082 };
3083 struct QIB_7322_SendIBSLIDMask_0 {
3084 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDMask_0_pb );
3085 };
3086 /* Default value: 0x0000000000000000 */
3087
3088 #define QIB_7322_SendIBSLIDAssign_0_offset 0x000014b8UL
3089 struct QIB_7322_SendIBSLIDAssign_0_pb {
3090 pseudo_bit_t SendIBSLIDAssign_15_0[16];
3091 pseudo_bit_t _unused_0[48];
3092 };
3093 struct QIB_7322_SendIBSLIDAssign_0 {
3094 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDAssign_0_pb );
3095 };
3096 /* Default value: 0x0000000000000000 */
3097
3098 #define QIB_7322_IBCStatusA_0_offset 0x00001540UL
3099 struct QIB_7322_IBCStatusA_0_pb {
3100 pseudo_bit_t LinkTrainingState[5];
3101 pseudo_bit_t LinkState[3];
3102 pseudo_bit_t LinkSpeedActive[1];
3103 pseudo_bit_t LinkWidthActive[1];
3104 pseudo_bit_t DDS_RXEQ_FAIL[1];
3105 pseudo_bit_t _unused_0[1];
3106 pseudo_bit_t IBRxLaneReversed[1];
3107 pseudo_bit_t IBTxLaneReversed[1];
3108 pseudo_bit_t ScrambleEn[1];
3109 pseudo_bit_t ScrambleCapRemote[1];
3110 pseudo_bit_t _unused_1[13];
3111 pseudo_bit_t LinkSpeedQDR[1];
3112 pseudo_bit_t TxReady[1];
3113 pseudo_bit_t _unused_2[1];
3114 pseudo_bit_t TxCreditOk_VL0[1];
3115 pseudo_bit_t TxCreditOk_VL1[1];
3116 pseudo_bit_t TxCreditOk_VL2[1];
3117 pseudo_bit_t TxCreditOk_VL3[1];
3118 pseudo_bit_t TxCreditOk_VL4[1];
3119 pseudo_bit_t TxCreditOk_VL5[1];
3120 pseudo_bit_t TxCreditOk_VL6[1];
3121 pseudo_bit_t TxCreditOk_VL7[1];
3122 pseudo_bit_t _unused_3[24];
3123 };
3124 struct QIB_7322_IBCStatusA_0 {
3125 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusA_0_pb );
3126 };
3127 /* Default value: 0x0000000000000X02 */
3128
3129 #define QIB_7322_IBCStatusB_0_offset 0x00001548UL
3130 struct QIB_7322_IBCStatusB_0_pb {
3131 pseudo_bit_t LinkRoundTripLatency[26];
3132 pseudo_bit_t ReqDDSLocalFromRmt[4];
3133 pseudo_bit_t RxEqLocalDevice[2];
3134 pseudo_bit_t heartbeat_crosstalk[4];
3135 pseudo_bit_t heartbeat_timed_out[1];
3136 pseudo_bit_t ibsd_adaptation_timer_started[1];
3137 pseudo_bit_t ibsd_adaptation_timer_reached_threshold[1];
3138 pseudo_bit_t ibsd_adaptation_timer_debug[1];
3139 pseudo_bit_t _unused_0[24];
3140 };
3141 struct QIB_7322_IBCStatusB_0 {
3142 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusB_0_pb );
3143 };
3144 /* Default value: 0x00000000XXXXXXXX */
3145
3146 #define QIB_7322_IBCCtrlA_0_offset 0x00001560UL
3147 struct QIB_7322_IBCCtrlA_0_pb {
3148 pseudo_bit_t FlowCtrlPeriod[8];
3149 pseudo_bit_t FlowCtrlWaterMark[8];
3150 pseudo_bit_t LinkInitCmd[3];
3151 pseudo_bit_t LinkCmd[2];
3152 pseudo_bit_t MaxPktLen[11];
3153 pseudo_bit_t PhyerrThreshold[4];
3154 pseudo_bit_t OverrunThreshold[4];
3155 pseudo_bit_t _unused_0[8];
3156 pseudo_bit_t NumVLane[3];
3157 pseudo_bit_t _unused_1[9];
3158 pseudo_bit_t IBStatIntReductionEn[1];
3159 pseudo_bit_t IBLinkEn[1];
3160 pseudo_bit_t LinkDownDefaultState[1];
3161 pseudo_bit_t Loopback[1];
3162 };
3163 struct QIB_7322_IBCCtrlA_0 {
3164 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlA_0_pb );
3165 };
3166 /* Default value: 0x0000000000000000 */
3167
3168 #define QIB_7322_IBCCtrlB_0_offset 0x00001568UL
3169 struct QIB_7322_IBCCtrlB_0_pb {
3170 pseudo_bit_t IB_ENHANCED_MODE[1];
3171 pseudo_bit_t SD_SPEED[1];
3172 pseudo_bit_t SD_SPEED_SDR[1];
3173 pseudo_bit_t SD_SPEED_DDR[1];
3174 pseudo_bit_t SD_SPEED_QDR[1];
3175 pseudo_bit_t IB_NUM_CHANNELS[2];
3176 pseudo_bit_t IB_POLARITY_REV_SUPP[1];
3177 pseudo_bit_t IB_LANE_REV_SUPPORTED[1];
3178 pseudo_bit_t SD_RX_EQUAL_ENABLE[1];
3179 pseudo_bit_t SD_ADD_ENB[1];
3180 pseudo_bit_t SD_DDSV[1];
3181 pseudo_bit_t SD_DDS[4];
3182 pseudo_bit_t HRTBT_ENB[1];
3183 pseudo_bit_t HRTBT_AUTO[1];
3184 pseudo_bit_t HRTBT_PORT[8];
3185 pseudo_bit_t HRTBT_REQ[1];
3186 pseudo_bit_t IB_ENABLE_FILT_DPKT[1];
3187 pseudo_bit_t _unused_0[4];
3188 pseudo_bit_t IB_DLID[16];
3189 pseudo_bit_t IB_DLID_MASK[16];
3190 };
3191 struct QIB_7322_IBCCtrlB_0 {
3192 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlB_0_pb );
3193 };
3194 /* Default value: 0x00000000000305FF */
3195
3196 #define QIB_7322_IBCCtrlC_0_offset 0x00001570UL
3197 struct QIB_7322_IBCCtrlC_0_pb {
3198 pseudo_bit_t IB_FRONT_PORCH[5];
3199 pseudo_bit_t IB_BACK_PORCH[5];
3200 pseudo_bit_t _unused_0[54];
3201 };
3202 struct QIB_7322_IBCCtrlC_0 {
3203 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlC_0_pb );
3204 };
3205 /* Default value: 0x0000000000000301 */
3206
3207 #define QIB_7322_HRTBT_GUID_0_offset 0x00001588UL
3208 /* Default value: 0x0000000000000000 */
3209
3210 #define QIB_7322_IB_SDTEST_IF_TX_0_offset 0x00001590UL
3211 struct QIB_7322_IB_SDTEST_IF_TX_0_pb {
3212 pseudo_bit_t TS_T_TX_VALID[1];
3213 pseudo_bit_t TS_3_TX_VALID[1];
3214 pseudo_bit_t VL_CAP[2];
3215 pseudo_bit_t CREDIT_CHANGE[1];
3216 pseudo_bit_t _unused_0[6];
3217 pseudo_bit_t TS_TX_OPCODE[2];
3218 pseudo_bit_t TS_TX_SPEED[3];
3219 pseudo_bit_t _unused_1[16];
3220 pseudo_bit_t TS_TX_TX_CFG[16];
3221 pseudo_bit_t TS_TX_RX_CFG[16];
3222 };
3223 struct QIB_7322_IB_SDTEST_IF_TX_0 {
3224 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_TX_0_pb );
3225 };
3226 /* Default value: 0x0000000000000000 */
3227
3228 #define QIB_7322_IB_SDTEST_IF_RX_0_offset 0x00001598UL