[build] Avoid implicit-fallthrough warnings on GCC 7
[ipxe.git] / src / drivers / net / ath / ath9k / ath9k_ar9003_phy.c
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <ipxe/io.h>
21
22 #include "hw.h"
23 #include "ar9003_phy.h"
24
25 static const int firstep_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
28
29 static const int cycpwrThr1_table[] =
30 /* level: 0 1 2 3 4 5 6 7 8 */
31 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
32
33 /*
34 * register values to turn OFDM weak signal detection OFF
35 */
36 static const int m1ThreshLow_off = 127;
37 static const int m2ThreshLow_off = 127;
38 static const int m1Thresh_off = 127;
39 static const int m2Thresh_off = 127;
40 static const int m2CountThr_off = 31;
41 static const int m2CountThrLow_off = 63;
42 static const int m1ThreshLowExt_off = 127;
43 static const int m2ThreshLowExt_off = 127;
44 static const int m1ThreshExt_off = 127;
45 static const int m2ThreshExt_off = 127;
46
47 /**
48 * ar9003_hw_set_channel - set channel on single-chip device
49 * @ah: atheros hardware structure
50 * @chan:
51 *
52 * This is the function to change channel on single-chip devices, that is
53 * all devices after ar9280.
54 *
55 * This function takes the channel value in MHz and sets
56 * hardware channel value. Assumes writes have been enabled to analog bus.
57 *
58 * Actual Expression,
59 *
60 * For 2GHz channel,
61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
62 * (freq_ref = 40MHz)
63 *
64 * For 5GHz channel,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
67 *
68 * For 5GHz channels which are 5MHz spaced,
69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
70 * (freq_ref = 40MHz)
71 */
72 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
73 {
74 u16 bMode, fracMode = 0, aModeRefSel = 0;
75 u32 freq, channelSel = 0, reg32 = 0;
76 struct chan_centers centers;
77 int loadSynthChannel;
78
79 ath9k_hw_get_channel_centers(ah, chan, &centers);
80 freq = centers.synth_center;
81
82 if (freq < 4800) { /* 2 GHz, fractional mode */
83 if (AR_SREV_9485(ah)) {
84 u32 chan_frac;
85
86 /*
87 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
88 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
89 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
90 */
91 channelSel = (freq * 4) / 120;
92 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
93 channelSel = (channelSel << 17) | chan_frac;
94 } else if (AR_SREV_9340(ah)) {
95 if (ah->is_clk_25mhz) {
96 u32 chan_frac;
97
98 channelSel = (freq * 2) / 75;
99 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
100 channelSel = (channelSel << 17) | chan_frac;
101 } else
102 channelSel = CHANSEL_2G(freq) >> 1;
103 } else
104 channelSel = CHANSEL_2G(freq);
105 /* Set to 2G mode */
106 bMode = 1;
107 } else {
108 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
109 u32 chan_frac;
110
111 channelSel = (freq * 2) / 75;
112 chan_frac = ((freq % 75) * 0x20000) / 75;
113 channelSel = (channelSel << 17) | chan_frac;
114 } else {
115 channelSel = CHANSEL_5G(freq);
116 /* Doubler is ON, so, divide channelSel by 2. */
117 channelSel >>= 1;
118 }
119 /* Set to 5G mode */
120 bMode = 0;
121 }
122
123 /* Enable fractional mode for all channels */
124 fracMode = 1;
125 aModeRefSel = 0;
126 loadSynthChannel = 0;
127
128 reg32 = (bMode << 29);
129 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
130
131 /* Enable Long shift Select for Synthesizer */
132 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
133 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
134
135 /* Program Synth. setting */
136 reg32 = (channelSel << 2) | (fracMode << 30) |
137 (aModeRefSel << 28) | (loadSynthChannel << 31);
138 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
139
140 /* Toggle Load Synth channel bit */
141 loadSynthChannel = 1;
142 reg32 = (channelSel << 2) | (fracMode << 30) |
143 (aModeRefSel << 28) | (loadSynthChannel << 31);
144 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
145
146 ah->curchan = chan;
147 ah->curchan_rad_index = -1;
148
149 return 0;
150 }
151
152 /**
153 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
154 * @ah: atheros hardware structure
155 * @chan:
156 *
157 * For single-chip solutions. Converts to baseband spur frequency given the
158 * input channel frequency and compute register settings below.
159 *
160 * Spur mitigation for MRC CCK
161 */
162 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
163 struct ath9k_channel *chan)
164 {
165 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
166 int cur_bb_spur, negative = 0, cck_spur_freq;
167 int i;
168 int range, max_spur_cnts, synth_freq;
169 u8 *spur_fbin_ptr = NULL;
170
171 /*
172 * Need to verify range +/- 10 MHz in control channel, otherwise spur
173 * is out-of-band and can be ignored.
174 */
175
176 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
177 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
178 IS_CHAN_2GHZ(chan));
179 if (spur_fbin_ptr[0] == 0) /* No spur */
180 return;
181 max_spur_cnts = 5;
182 if (IS_CHAN_HT40(chan)) {
183 range = 19;
184 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
185 AR_PHY_GC_DYN2040_PRI_CH) == 0)
186 synth_freq = chan->channel + 10;
187 else
188 synth_freq = chan->channel - 10;
189 } else {
190 range = 10;
191 synth_freq = chan->channel;
192 }
193 } else {
194 range = 10;
195 max_spur_cnts = 4;
196 synth_freq = chan->channel;
197 }
198
199 for (i = 0; i < max_spur_cnts; i++) {
200 negative = 0;
201 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
202 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
203 IS_CHAN_2GHZ(chan)) - synth_freq;
204 else
205 cur_bb_spur = spur_freq[i] - synth_freq;
206
207 if (cur_bb_spur < 0) {
208 negative = 1;
209 cur_bb_spur = -cur_bb_spur;
210 }
211 if (cur_bb_spur < range) {
212 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
213
214 if (negative == 1)
215 cck_spur_freq = -cck_spur_freq;
216
217 cck_spur_freq = cck_spur_freq & 0xfffff;
218
219 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
220 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
221 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
222 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
223 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
224 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
225 0x2);
226 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
227 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
228 0x1);
229 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
230 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
231 cck_spur_freq);
232
233 return;
234 }
235 }
236
237 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
238 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
239 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
240 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
243 }
244
245 /* Clean all spur register fields */
246 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
247 {
248 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
249 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
250 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
251 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
252 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
253 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
254 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
255 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
256 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
257 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
258 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
259 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
260 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
261 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
262 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
263 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
264 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
265 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
266
267 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
268 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
269 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
270 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
272 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
273 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
274 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
275 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
276 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
277 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
278 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
279 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
280 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
281 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
282 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
283 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
284 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
285 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
286 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
287 }
288
289 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
290 int freq_offset,
291 int spur_freq_sd,
292 int spur_delta_phase,
293 int spur_subchannel_sd)
294 {
295 int mask_index = 0;
296
297 /* OFDM Spur mitigation */
298 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
299 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
300 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
301 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
302 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
303 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
304 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
305 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
306 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
307 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
308 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
309 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
310 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
311 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
312 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
313 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
314 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
315 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
316
317 if (REG_READ_FIELD(ah, AR_PHY_MODE,
318 AR_PHY_MODE_DYNAMIC) == 0x1)
319 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
320 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
321
322 mask_index = (freq_offset << 4) / 5;
323 if (mask_index < 0)
324 mask_index = mask_index - 1;
325
326 mask_index = mask_index & 0x7f;
327
328 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
329 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
333 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
334 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
335 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
336 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
337 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
338 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
339 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
340 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
341 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
342 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
343 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
345 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
346 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
347 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
348 }
349
350 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
351 struct ath9k_channel *chan,
352 int freq_offset)
353 {
354 int spur_freq_sd = 0;
355 int spur_subchannel_sd = 0;
356 int spur_delta_phase = 0;
357
358 if (IS_CHAN_HT40(chan)) {
359 if (freq_offset < 0) {
360 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
361 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
362 spur_subchannel_sd = 1;
363 else
364 spur_subchannel_sd = 0;
365
366 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
367
368 } else {
369 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
370 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
371 spur_subchannel_sd = 0;
372 else
373 spur_subchannel_sd = 1;
374
375 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
376
377 }
378
379 spur_delta_phase = (freq_offset << 17) / 5;
380
381 } else {
382 spur_subchannel_sd = 0;
383 spur_freq_sd = (freq_offset << 9) /11;
384 spur_delta_phase = (freq_offset << 18) / 5;
385 }
386
387 spur_freq_sd = spur_freq_sd & 0x3ff;
388 spur_delta_phase = spur_delta_phase & 0xfffff;
389
390 ar9003_hw_spur_ofdm(ah,
391 freq_offset,
392 spur_freq_sd,
393 spur_delta_phase,
394 spur_subchannel_sd);
395 }
396
397 /* Spur mitigation for OFDM */
398 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
399 struct ath9k_channel *chan)
400 {
401 int synth_freq;
402 int range = 10;
403 int freq_offset = 0;
404 int mode;
405 u8* spurChansPtr;
406 unsigned int i;
407 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
408
409 if (IS_CHAN_5GHZ(chan)) {
410 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
411 mode = 0;
412 }
413 else {
414 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
415 mode = 1;
416 }
417
418 if (spurChansPtr[0] == 0)
419 return; /* No spur in the mode */
420
421 if (IS_CHAN_HT40(chan)) {
422 range = 19;
423 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
424 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
425 synth_freq = chan->channel - 10;
426 else
427 synth_freq = chan->channel + 10;
428 } else {
429 range = 10;
430 synth_freq = chan->channel;
431 }
432
433 ar9003_hw_spur_ofdm_clear(ah);
434
435 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
436 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
437 if (abs(freq_offset) < range) {
438 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
439 break;
440 }
441 }
442 }
443
444 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
445 struct ath9k_channel *chan)
446 {
447 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
448 ar9003_hw_spur_mitigate_ofdm(ah, chan);
449 }
450
451 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah __unused,
452 struct ath9k_channel *chan)
453 {
454 u32 pll;
455
456 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
457
458 if (chan && IS_CHAN_HALF_RATE(chan))
459 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
460 else if (chan && IS_CHAN_QUARTER_RATE(chan))
461 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
462
463 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
464
465 return pll;
466 }
467
468 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
469 struct ath9k_channel *chan)
470 {
471 u32 phymode;
472 u32 enableDacFifo = 0;
473
474 enableDacFifo =
475 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
476
477 /* Enable 11n HT, 20 MHz */
478 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
479 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
480
481 /* Configure baseband for dynamic 20/40 operation */
482 if (IS_CHAN_HT40(chan)) {
483 phymode |= AR_PHY_GC_DYN2040_EN;
484 /* Configure control (primary) channel at +-10MHz */
485 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
486 (chan->chanmode == CHANNEL_G_HT40PLUS))
487 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
488
489 }
490
491 /* make sure we preserve INI settings */
492 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
493 /* turn off Green Field detection for STA for now */
494 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
495
496 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
497
498 /* Configure MAC for 20/40 operation */
499 ath9k_hw_set11nmac2040(ah);
500
501 /* global transmit timeout (25 TUs default)*/
502 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
503 /* carrier sense timeout */
504 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
505 }
506
507 static void ar9003_hw_init_bb(struct ath_hw *ah,
508 struct ath9k_channel *chan)
509 {
510 u32 synthDelay;
511
512 /*
513 * Wait for the frequency synth to settle (synth goes on
514 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
515 * Value is in 100ns increments.
516 */
517 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
518 if (IS_CHAN_B(chan))
519 synthDelay = (4 * synthDelay) / 22;
520 else
521 synthDelay /= 10;
522
523 /* Activate the PHY (includes baseband activate + synthesizer on) */
524 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
525
526 /*
527 * There is an issue if the AP starts the calibration before
528 * the base band timeout completes. This could result in the
529 * rx_clear false triggering. As a workaround we add delay an
530 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
531 * does not happen.
532 */
533 udelay(synthDelay + BASE_ACTIVATE_DELAY);
534 }
535
536 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
537 {
538 switch (rx) {
539 case 0x5:
540 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
541 AR_PHY_SWAP_ALT_CHAIN);
542 /* Fall through */
543 case 0x3:
544 case 0x1:
545 case 0x2:
546 case 0x7:
547 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
548 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
549 break;
550 default:
551 break;
552 }
553
554 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
555 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
556 else
557 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
558
559 if (tx == 0x5) {
560 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
561 AR_PHY_SWAP_ALT_CHAIN);
562 }
563 }
564
565 /*
566 * Override INI values with chip specific configuration.
567 */
568 static void ar9003_hw_override_ini(struct ath_hw *ah)
569 {
570 u32 val;
571
572 /*
573 * Set the RX_ABORT and RX_DIS and clear it only after
574 * RXE is set for MAC. This prevents frames with
575 * corrupted descriptor status.
576 */
577 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
578
579 /*
580 * For AR9280 and above, there is a new feature that allows
581 * Multicast search based on both MAC Address and Key ID. By default,
582 * this feature is enabled. But since the driver is not using this
583 * feature, we switch it off; otherwise multicast search based on
584 * MAC addr only will fail.
585 */
586 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
587 REG_WRITE(ah, AR_PCU_MISC_MODE2,
588 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
589 }
590
591 static void ar9003_hw_prog_ini(struct ath_hw *ah,
592 struct ar5416IniArray *iniArr,
593 int column)
594 {
595 unsigned int i, regWrites = 0;
596
597 /* New INI format: Array may be undefined (pre, core, post arrays) */
598 if (!iniArr->ia_array)
599 return;
600
601 /*
602 * New INI format: Pre, core, and post arrays for a given subsystem
603 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
604 * the array is non-modal and force the column to 1.
605 */
606 if ((unsigned int)column >= iniArr->ia_columns)
607 column = 1;
608
609 for (i = 0; i < iniArr->ia_rows; i++) {
610 u32 reg = INI_RA(iniArr, i, 0);
611 u32 val = INI_RA(iniArr, i, column);
612
613 REG_WRITE(ah, reg, val);
614
615 DO_DELAY(regWrites);
616 }
617 }
618
619 static int ar9003_hw_process_ini(struct ath_hw *ah,
620 struct ath9k_channel *chan)
621 {
622 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
623 unsigned int regWrites = 0, i;
624 struct net80211_channel *channel = chan->chan;
625 u32 modesIndex;
626
627 switch (chan->chanmode) {
628 case CHANNEL_A:
629 case CHANNEL_A_HT20:
630 modesIndex = 1;
631 break;
632 case CHANNEL_A_HT40PLUS:
633 case CHANNEL_A_HT40MINUS:
634 modesIndex = 2;
635 break;
636 case CHANNEL_G:
637 case CHANNEL_G_HT20:
638 case CHANNEL_B:
639 modesIndex = 4;
640 break;
641 case CHANNEL_G_HT40PLUS:
642 case CHANNEL_G_HT40MINUS:
643 modesIndex = 3;
644 break;
645
646 default:
647 return -EINVAL;
648 }
649
650 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
651 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
652 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
653 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
654 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
655 }
656
657 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
658 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
659
660 /*
661 * For 5GHz channels requiring Fast Clock, apply
662 * different modal values.
663 */
664 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
665 REG_WRITE_ARRAY(&ah->iniModesAdditional,
666 modesIndex, regWrites);
667
668 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
669 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
670
671 ar9003_hw_override_ini(ah);
672 ar9003_hw_set_channel_regs(ah, chan);
673 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
674
675 /* Set TX power */
676 ah->eep_ops->set_txpower(ah, chan,
677 ath9k_regd_get_ctl(regulatory, chan),
678 0,
679 channel->maxpower * 2,
680 min((u32) MAX_RATE_POWER,
681 (u32) regulatory->power_limit), 0);
682
683 return 0;
684 }
685
686 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
687 struct ath9k_channel *chan)
688 {
689 u32 rfMode = 0;
690
691 if (chan == NULL)
692 return;
693
694 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
695 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
696
697 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
698 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
699
700 REG_WRITE(ah, AR_PHY_MODE, rfMode);
701 }
702
703 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
704 {
705 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
706 }
707
708 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
709 struct ath9k_channel *chan)
710 {
711 u32 coef_scaled, ds_coef_exp, ds_coef_man;
712 u32 clockMhzScaled = 0x64000000;
713 struct chan_centers centers;
714
715 /*
716 * half and quarter rate can divide the scaled clock by 2 or 4
717 * scale for selected channel bandwidth
718 */
719 if (IS_CHAN_HALF_RATE(chan))
720 clockMhzScaled = clockMhzScaled >> 1;
721 else if (IS_CHAN_QUARTER_RATE(chan))
722 clockMhzScaled = clockMhzScaled >> 2;
723
724 /*
725 * ALGO -> coef = 1e8/fcarrier*fclock/40;
726 * scaled coef to provide precision for this floating calculation
727 */
728 ath9k_hw_get_channel_centers(ah, chan, &centers);
729 coef_scaled = clockMhzScaled / centers.synth_center;
730
731 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
732 &ds_coef_exp);
733
734 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
735 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
736 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
737 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
738
739 /*
740 * For Short GI,
741 * scaled coeff is 9/10 that of normal coeff
742 */
743 coef_scaled = (9 * coef_scaled) / 10;
744
745 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
746 &ds_coef_exp);
747
748 /* for short gi */
749 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
750 AR_PHY_SGI_DSC_MAN, ds_coef_man);
751 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
752 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
753 }
754
755 static int ar9003_hw_rfbus_req(struct ath_hw *ah)
756 {
757 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
758 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
759 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
760 }
761
762 /*
763 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
764 * Read the phy active delay register. Value is in 100ns increments.
765 */
766 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
767 {
768 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
769 if (IS_CHAN_B(ah->curchan))
770 synthDelay = (4 * synthDelay) / 22;
771 else
772 synthDelay /= 10;
773
774 udelay(synthDelay + BASE_ACTIVATE_DELAY);
775
776 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
777 }
778
779 static void ar9003_hw_set_diversity(struct ath_hw *ah, int value)
780 {
781 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
782 if (value)
783 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
784 else
785 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
786 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
787 }
788
789 static int ar9003_hw_ani_control(struct ath_hw *ah,
790 enum ath9k_ani_cmd cmd, int param)
791 {
792 struct ath9k_channel *chan = ah->curchan;
793 struct ar5416AniState *aniState = &chan->ani;
794 s32 value, value2;
795
796 switch (cmd & ah->ani_function) {
797 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
798 /*
799 * on == 1 means ofdm weak signal detection is ON
800 * on == 1 is the default, for less noise immunity
801 *
802 * on == 0 means ofdm weak signal detection is OFF
803 * on == 0 means more noise imm
804 */
805 u32 on = param ? 1 : 0;
806 /*
807 * make register setting for default
808 * (weak sig detect ON) come from INI file
809 */
810 int m1ThreshLow = on ?
811 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
812 int m2ThreshLow = on ?
813 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
814 int m1Thresh = on ?
815 aniState->iniDef.m1Thresh : m1Thresh_off;
816 int m2Thresh = on ?
817 aniState->iniDef.m2Thresh : m2Thresh_off;
818 int m2CountThr = on ?
819 aniState->iniDef.m2CountThr : m2CountThr_off;
820 int m2CountThrLow = on ?
821 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
822 int m1ThreshLowExt = on ?
823 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
824 int m2ThreshLowExt = on ?
825 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
826 int m1ThreshExt = on ?
827 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
828 int m2ThreshExt = on ?
829 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
830
831 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
832 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
833 m1ThreshLow);
834 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
835 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
836 m2ThreshLow);
837 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
838 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
839 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
840 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
841 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
842 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
843 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
844 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
845 m2CountThrLow);
846
847 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
848 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
849 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
850 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
851 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
852 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
853 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
854 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
855
856 if (on)
857 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
858 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
859 else
860 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
861 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
862
863 if (on != aniState->ofdmWeakSigDetect) {
864 DBG2("ath9k: "
865 "** ch %d: ofdm weak signal: %s=>%s\n",
866 chan->channel,
867 aniState->ofdmWeakSigDetect ?
868 "on" : "off",
869 on ? "on" : "off");
870 if (on)
871 ah->stats.ast_ani_ofdmon++;
872 else
873 ah->stats.ast_ani_ofdmoff++;
874 aniState->ofdmWeakSigDetect = on;
875 }
876 break;
877 }
878 case ATH9K_ANI_FIRSTEP_LEVEL:{
879 u32 level = param;
880
881 if (level >= ARRAY_SIZE(firstep_table)) {
882 DBG("ath9k: "
883 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
884 level, ARRAY_SIZE(firstep_table));
885 return 0;
886 }
887
888 /*
889 * make register setting relative to default
890 * from INI file & cap value
891 */
892 value = firstep_table[level] -
893 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
894 aniState->iniDef.firstep;
895 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
896 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
897 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
898 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
899 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
900 AR_PHY_FIND_SIG_FIRSTEP,
901 value);
902 /*
903 * we need to set first step low register too
904 * make register setting relative to default
905 * from INI file & cap value
906 */
907 value2 = firstep_table[level] -
908 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
909 aniState->iniDef.firstepLow;
910 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
911 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
912 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
913 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
914
915 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
916 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
917
918 if (level != aniState->firstepLevel) {
919 DBG2("ath9k: "
920 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
921 chan->channel,
922 aniState->firstepLevel,
923 level,
924 ATH9K_ANI_FIRSTEP_LVL_NEW,
925 value,
926 aniState->iniDef.firstep);
927 DBG2("ath9k: "
928 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
929 chan->channel,
930 aniState->firstepLevel,
931 level,
932 ATH9K_ANI_FIRSTEP_LVL_NEW,
933 value2,
934 aniState->iniDef.firstepLow);
935 if (level > aniState->firstepLevel)
936 ah->stats.ast_ani_stepup++;
937 else if (level < aniState->firstepLevel)
938 ah->stats.ast_ani_stepdown++;
939 aniState->firstepLevel = level;
940 }
941 break;
942 }
943 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
944 u32 level = param;
945
946 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
947 DBG("ath9k: "
948 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
949 level, ARRAY_SIZE(cycpwrThr1_table));
950 return 0;
951 }
952 /*
953 * make register setting relative to default
954 * from INI file & cap value
955 */
956 value = cycpwrThr1_table[level] -
957 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
958 aniState->iniDef.cycpwrThr1;
959 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
960 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
961 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
962 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
963 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
964 AR_PHY_TIMING5_CYCPWR_THR1,
965 value);
966
967 /*
968 * set AR_PHY_EXT_CCA for extension channel
969 * make register setting relative to default
970 * from INI file & cap value
971 */
972 value2 = cycpwrThr1_table[level] -
973 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
974 aniState->iniDef.cycpwrThr1Ext;
975 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
976 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
977 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
978 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
979 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
980 AR_PHY_EXT_CYCPWR_THR1, value2);
981
982 if (level != aniState->spurImmunityLevel) {
983 DBG2("ath9k: "
984 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
985 chan->channel,
986 aniState->spurImmunityLevel,
987 level,
988 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
989 value,
990 aniState->iniDef.cycpwrThr1);
991 DBG2("ath9k: "
992 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
993 chan->channel,
994 aniState->spurImmunityLevel,
995 level,
996 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
997 value2,
998 aniState->iniDef.cycpwrThr1Ext);
999 if (level > aniState->spurImmunityLevel)
1000 ah->stats.ast_ani_spurup++;
1001 else if (level < aniState->spurImmunityLevel)
1002 ah->stats.ast_ani_spurdown++;
1003 aniState->spurImmunityLevel = level;
1004 }
1005 break;
1006 }
1007 case ATH9K_ANI_MRC_CCK:{
1008 /*
1009 * is_on == 1 means MRC CCK ON (default, less noise imm)
1010 * is_on == 0 means MRC CCK is OFF (more noise imm)
1011 */
1012 int is_on = param ? 1 : 0;
1013 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1014 AR_PHY_MRC_CCK_ENABLE, is_on);
1015 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1016 AR_PHY_MRC_CCK_MUX_REG, is_on);
1017 if (!(is_on != aniState->mrcCCKOff)) {
1018 DBG2("ath9k: "
1019 "** ch %d: MRC CCK: %s=>%s\n",
1020 chan->channel,
1021 !aniState->mrcCCKOff ? "on" : "off",
1022 is_on ? "on" : "off");
1023 if (is_on)
1024 ah->stats.ast_ani_ccklow++;
1025 else
1026 ah->stats.ast_ani_cckhigh++;
1027 aniState->mrcCCKOff = !is_on;
1028 }
1029 break;
1030 }
1031 case ATH9K_ANI_PRESENT:
1032 break;
1033 default:
1034 DBG2("ath9k: invalid cmd %d\n", cmd);
1035 return 0;
1036 }
1037
1038 DBG2("ath9k: "
1039 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1040 aniState->spurImmunityLevel,
1041 aniState->ofdmWeakSigDetect ? "on" : "off",
1042 aniState->firstepLevel,
1043 !aniState->mrcCCKOff ? "on" : "off",
1044 aniState->listenTime,
1045 aniState->ofdmPhyErrCount,
1046 aniState->cckPhyErrCount);
1047 return 1;
1048 }
1049
1050 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1051 int16_t nfarray[NUM_NF_READINGS])
1052 {
1053 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1054 #define AR_PHY_CH_MINCCA_PWR_S 20
1055 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1056 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1057
1058 int16_t nf;
1059 int i;
1060
1061 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1062 if (ah->rxchainmask & BIT(i)) {
1063 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1064 AR_PHY_CH_MINCCA_PWR);
1065 nfarray[i] = sign_extend32(nf, 8);
1066
1067 if (IS_CHAN_HT40(ah->curchan)) {
1068 u8 ext_idx = AR9300_MAX_CHAINS + i;
1069
1070 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1071 AR_PHY_CH_EXT_MINCCA_PWR);
1072 nfarray[ext_idx] = sign_extend32(nf, 8);
1073 }
1074 }
1075 }
1076 }
1077
1078 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1079 {
1080 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1081 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1082 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1083 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1084 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1085 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1086 }
1087
1088 /*
1089 * Initialize the ANI register values with default (ini) values.
1090 * This routine is called during a (full) hardware reset after
1091 * all the registers are initialised from the INI.
1092 */
1093 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1094 {
1095 struct ar5416AniState *aniState;
1096 struct ath9k_channel *chan = ah->curchan;
1097 struct ath9k_ani_default *iniDef;
1098 u32 val;
1099
1100 aniState = &ah->curchan->ani;
1101 iniDef = &aniState->iniDef;
1102
1103 DBG2("ath9k: "
1104 "ver %d.%d chan %d Mhz/0x%x\n",
1105 ah->hw_version.macVersion,
1106 ah->hw_version.macRev,
1107 chan->channel,
1108 chan->channelFlags);
1109
1110 val = REG_READ(ah, AR_PHY_SFCORR);
1111 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1112 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1113 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1114
1115 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1116 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1117 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1118 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1119
1120 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1121 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1122 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1123 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1124 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1125 iniDef->firstep = REG_READ_FIELD(ah,
1126 AR_PHY_FIND_SIG,
1127 AR_PHY_FIND_SIG_FIRSTEP);
1128 iniDef->firstepLow = REG_READ_FIELD(ah,
1129 AR_PHY_FIND_SIG_LOW,
1130 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1131 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1132 AR_PHY_TIMING5,
1133 AR_PHY_TIMING5_CYCPWR_THR1);
1134 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1135 AR_PHY_EXT_CCA,
1136 AR_PHY_EXT_CYCPWR_THR1);
1137
1138 /* these levels just got reset to defaults by the INI */
1139 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1140 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1141 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1142 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1143 }
1144
1145 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1146 struct ath_hw_radar_conf *conf)
1147 {
1148 u32 radar_0 = 0, radar_1 = 0;
1149
1150 if (!conf) {
1151 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1152 return;
1153 }
1154
1155 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1156 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1157 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1158 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1159 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1160 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1161
1162 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1163 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1164 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1165 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1166 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1167
1168 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1169 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1170 if (conf->ext_channel)
1171 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1172 else
1173 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1174 }
1175
1176 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1177 {
1178 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1179
1180 conf->fir_power = -28;
1181 conf->radar_rssi = 0;
1182 conf->pulse_height = 10;
1183 conf->pulse_rssi = 24;
1184 conf->pulse_inband = 8;
1185 conf->pulse_maxlen = 255;
1186 conf->pulse_inband_step = 12;
1187 conf->radar_inband = 8;
1188 }
1189
1190 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1191 struct ath_hw_antcomb_conf *antconf)
1192 {
1193 u32 regval;
1194
1195 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1196 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1197 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1198 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1199 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1200 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1201 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1202 antconf->lna1_lna2_delta = -9;
1203 antconf->div_group = 2;
1204 }
1205
1206 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1207 struct ath_hw_antcomb_conf *antconf)
1208 {
1209 u32 regval;
1210
1211 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1212 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1213 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1214 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1215 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1216 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1217 regval |= ((antconf->main_lna_conf <<
1218 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1219 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1220 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1221 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1222 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1223 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1224 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1225 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1226 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1227 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1228
1229 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1230 }
1231
1232 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1233 {
1234 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1235 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1236 static const u32 ar9300_cca_regs[6] = {
1237 AR_PHY_CCA_0,
1238 AR_PHY_CCA_1,
1239 AR_PHY_CCA_2,
1240 AR_PHY_EXT_CCA,
1241 AR_PHY_EXT_CCA_1,
1242 AR_PHY_EXT_CCA_2,
1243 };
1244
1245 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1246 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1247 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1248 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1249 priv_ops->init_bb = ar9003_hw_init_bb;
1250 priv_ops->process_ini = ar9003_hw_process_ini;
1251 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1252 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1253 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1254 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1255 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1256 priv_ops->set_diversity = ar9003_hw_set_diversity;
1257 priv_ops->ani_control = ar9003_hw_ani_control;
1258 priv_ops->do_getnf = ar9003_hw_do_getnf;
1259 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1260 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1261
1262 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1263 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1264
1265 ar9003_hw_set_nf_limits(ah);
1266 ar9003_hw_set_radar_conf(ah);
1267 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1268 }
1269
1270 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1271 {
1272 u32 val;
1273
1274 val = REG_READ(ah, AR_PHY_RESTART);
1275 val &= ~AR_PHY_RESTART_ENA;
1276
1277 REG_WRITE(ah, AR_PHY_RESTART, val);
1278 }