[exanic] Add driver for Exablaze ExaNIC cards
[ipxe.git] / src / drivers / net / exanic.h
1 #ifndef _EXANIC_H
2 #define _EXANIC_H
3
4 /** @file
5 *
6 * Exablaze ExaNIC driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/pci.h>
14 #include <ipxe/ethernet.h>
15 #include <ipxe/uaccess.h>
16 #include <ipxe/retry.h>
17 #include <ipxe/i2c.h>
18 #include <ipxe/bitbash.h>
19
20 /** Maximum number of ports */
21 #define EXANIC_MAX_PORTS 8
22
23 /** Register BAR */
24 #define EXANIC_REGS_BAR PCI_BASE_ADDRESS_0
25
26 /** Transmit region BAR */
27 #define EXANIC_TX_BAR PCI_BASE_ADDRESS_2
28
29 /** Alignment for DMA regions */
30 #define EXANIC_ALIGN 0x1000
31
32 /** Flag for 32-bit DMA addresses */
33 #define EXANIC_DMA_32_BIT 0x00000001UL
34
35 /** Register set length */
36 #define EXANIC_REGS_LEN 0x2000
37
38 /** Transmit feedback region length */
39 #define EXANIC_TXF_LEN 0x1000
40
41 /** Transmit feedback slot
42 *
43 * This is a policy decision.
44 */
45 #define EXANIC_TXF_SLOT( index ) ( 0x40 * (index) )
46
47 /** Receive region length */
48 #define EXANIC_RX_LEN 0x200000
49
50 /** Transmit feedback base address register */
51 #define EXANIC_TXF_BASE 0x0014
52
53 /** Capabilities register */
54 #define EXANIC_CAPS 0x0038
55 #define EXANIC_CAPS_100M 0x01000000UL /**< 100Mbps supported */
56 #define EXANIC_CAPS_1G 0x02000000UL /**< 1Gbps supported */
57 #define EXANIC_CAPS_10G 0x04000000UL /**< 10Gbps supported */
58 #define EXANIC_CAPS_40G 0x08000000UL /**< 40Gbps supported */
59 #define EXANIC_CAPS_100G 0x10000000UL /**< 100Gbps supported */
60 #define EXANIC_CAPS_SPEED_MASK 0x1f000000UL /**< Supported speeds mask */
61
62 /** I2C GPIO register */
63 #define EXANIC_I2C 0x012c
64
65 /** Port register offset */
66 #define EXANIC_PORT_REGS( index ) ( 0x0200 + ( 0x40 * (index) ) )
67
68 /** Port enable register */
69 #define EXANIC_PORT_ENABLE 0x0000
70 #define EXANIC_PORT_ENABLE_ENABLED 0x00000001UL /**< Port is enabled */
71
72 /** Port speed register */
73 #define EXANIC_PORT_SPEED 0x0004
74
75 /** Port status register */
76 #define EXANIC_PORT_STATUS 0x0008
77 #define EXANIC_PORT_STATUS_LINK 0x00000008UL /**< Link is up */
78 #define EXANIC_PORT_STATUS_ABSENT 0x80000000UL /**< Port is not present */
79
80 /** Port MAC address (second half) register */
81 #define EXANIC_PORT_MAC 0x000c
82
83 /** Port flags register */
84 #define EXANIC_PORT_FLAGS 0x0010
85 #define EXANIC_PORT_FLAGS_PROMISC 0x00000001UL /**< Promiscuous mode */
86
87 /** Port receive chunk base address register */
88 #define EXANIC_PORT_RX_BASE 0x0014
89
90 /** Port transmit command register */
91 #define EXANIC_PORT_TX_COMMAND 0x0020
92
93 /** Port transmit region offset register */
94 #define EXANIC_PORT_TX_OFFSET 0x0024
95
96 /** Port transmit region length register */
97 #define EXANIC_PORT_TX_LEN 0x0028
98
99 /** Port MAC address (first half) register */
100 #define EXANIC_PORT_OUI 0x0030
101
102 /** Port interrupt configuration register */
103 #define EXANIC_PORT_IRQ 0x0034
104
105 /** An ExaNIC transmit chunk descriptor */
106 struct exanic_tx_descriptor {
107 /** Feedback ID */
108 uint16_t txf_id;
109 /** Feedback slot */
110 uint16_t txf_slot;
111 /** Payload length (including padding */
112 uint16_t len;
113 /** Payload type */
114 uint8_t type;
115 /** Flags */
116 uint8_t flags;
117 } __attribute__ (( packed ));
118
119 /** An ExaNIC transmit chunk */
120 struct exanic_tx_chunk {
121 /** Descriptor */
122 struct exanic_tx_descriptor desc;
123 /** Padding */
124 uint8_t pad[2];
125 /** Payload data */
126 uint8_t data[2038];
127 } __attribute__ (( packed ));
128
129 /** Raw Ethernet frame type */
130 #define EXANIC_TYPE_RAW 0x01
131
132 /** An ExaNIC receive chunk descriptor */
133 struct exanic_rx_descriptor {
134 /** Timestamp */
135 uint32_t timestamp;
136 /** Status (valid only on final chunk) */
137 uint8_t status;
138 /** Length (zero except on the final chunk) */
139 uint8_t len;
140 /** Filter number */
141 uint8_t filter;
142 /** Generation */
143 uint8_t generation;
144 } __attribute__ (( packed ));
145
146 /** An ExaNIC receive chunk */
147 struct exanic_rx_chunk {
148 /** Payload data */
149 uint8_t data[120];
150 /** Descriptor */
151 struct exanic_rx_descriptor desc;
152 } __attribute__ (( packed ));
153
154 /** Receive status error mask */
155 #define EXANIC_STATUS_ERROR_MASK 0x0f
156
157 /** An ExaNIC I2C bus configuration */
158 struct exanic_i2c_config {
159 /** GPIO bit for pulling SCL low */
160 uint8_t setscl;
161 /** GPIO bit for pulling SDA low */
162 uint8_t setsda;
163 /** GPIO bit for reading SDA */
164 uint8_t getsda;
165 };
166
167 /** EEPROM address */
168 #define EXANIC_EEPROM_ADDRESS 0x50
169
170 /** An ExaNIC port */
171 struct exanic_port {
172 /** Network device */
173 struct net_device *netdev;
174 /** Port registers */
175 void *regs;
176
177 /** Transmit region offset */
178 size_t tx_offset;
179 /** Transmit region */
180 void *tx;
181 /** Number of transmit descriptors */
182 uint16_t tx_count;
183 /** Transmit producer counter */
184 uint16_t tx_prod;
185 /** Transmit consumer counter */
186 uint16_t tx_cons;
187 /** Transmit feedback slot */
188 uint16_t txf_slot;
189 /** Transmit feedback region */
190 uint16_t *txf;
191
192 /** Receive region */
193 userptr_t rx;
194 /** Receive consumer counter */
195 unsigned int rx_cons;
196 /** Receive I/O buffer (if any) */
197 struct io_buffer *rx_iobuf;
198 /** Receive status */
199 int rx_rc;
200
201 /** Port status */
202 uint32_t status;
203 /** Default link speed (as raw register value) */
204 uint32_t default_speed;
205 /** Speed capability bitmask */
206 uint32_t speeds;
207 /** Current attempted link speed (as a capability bit index) */
208 unsigned int speed;
209 /** Port status check timer */
210 struct retry_timer timer;
211 };
212
213 /** An ExaNIC */
214 struct exanic {
215 /** Registers */
216 void *regs;
217 /** Transmit region */
218 void *tx;
219 /** Transmit feedback region */
220 void *txf;
221
222 /** I2C bus configuration */
223 struct exanic_i2c_config i2cfg;
224 /** I2C bit-bashing interface */
225 struct i2c_bit_basher basher;
226 /** I2C serial EEPROM */
227 struct i2c_device eeprom;
228
229 /** Capabilities */
230 uint32_t caps;
231 /** Base MAC address */
232 uint8_t mac[ETH_ALEN];
233
234 /** Ports */
235 struct exanic_port *port[EXANIC_MAX_PORTS];
236 };
237
238 /** Maximum used length of transmit region
239 *
240 * This is a policy decision to avoid overflowing the 16-bit transmit
241 * producer and consumer counters.
242 */
243 #define EXANIC_MAX_TX_LEN ( 256 * sizeof ( struct exanic_tx_chunk ) )
244
245 /** Maximum length of received packet
246 *
247 * This is a policy decision.
248 */
249 #define EXANIC_MAX_RX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
250
251 /** Interval between link state checks
252 *
253 * This is a policy decision.
254 */
255 #define EXANIC_LINK_INTERVAL ( 1 * TICKS_PER_SEC )
256
257 #endif /* _EXANIC_H */