[intel] Add I217-LM PCI ID
[ipxe.git] / src / drivers / net / intel.c
1 /*
2 * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17 * 02110-1301, USA.
18 */
19
20 FILE_LICENCE ( GPL2_OR_LATER );
21
22 #include <stdint.h>
23 #include <string.h>
24 #include <unistd.h>
25 #include <errno.h>
26 #include <byteswap.h>
27 #include <ipxe/netdevice.h>
28 #include <ipxe/ethernet.h>
29 #include <ipxe/if_ether.h>
30 #include <ipxe/iobuf.h>
31 #include <ipxe/malloc.h>
32 #include <ipxe/pci.h>
33 #include <ipxe/profile.h>
34 #include "intel.h"
35
36 /** @file
37 *
38 * Intel 10/100/1000 network card driver
39 *
40 */
41
42 /** VM transmit profiler */
43 static struct profiler intel_vm_tx_profiler __profiler =
44 { .name = "intel.vm_tx" };
45
46 /** VM receive refill profiler */
47 static struct profiler intel_vm_refill_profiler __profiler =
48 { .name = "intel.vm_refill" };
49
50 /** VM poll profiler */
51 static struct profiler intel_vm_poll_profiler __profiler =
52 { .name = "intel.vm_poll" };
53
54 /******************************************************************************
55 *
56 * EEPROM interface
57 *
58 ******************************************************************************
59 */
60
61 /**
62 * Read data from EEPROM
63 *
64 * @v nvs NVS device
65 * @v address Address from which to read
66 * @v data Data buffer
67 * @v len Length of data buffer
68 * @ret rc Return status code
69 */
70 static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
71 void *data, size_t len ) {
72 struct intel_nic *intel =
73 container_of ( nvs, struct intel_nic, eeprom );
74 unsigned int i;
75 uint32_t value;
76 uint16_t *data_word = data;
77
78 /* Sanity check. We advertise a blocksize of one word, so
79 * should only ever receive single-word requests.
80 */
81 assert ( len == sizeof ( *data_word ) );
82
83 /* Initiate read */
84 writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
85 intel->regs + INTEL_EERD );
86
87 /* Wait for read to complete */
88 for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
89
90 /* If read is not complete, delay 1ms and retry */
91 value = readl ( intel->regs + INTEL_EERD );
92 if ( ! ( value & intel->eerd_done ) ) {
93 mdelay ( 1 );
94 continue;
95 }
96
97 /* Extract data */
98 *data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
99 return 0;
100 }
101
102 DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
103 return -ETIMEDOUT;
104 }
105
106 /**
107 * Write data to EEPROM
108 *
109 * @v nvs NVS device
110 * @v address Address to which to write
111 * @v data Data buffer
112 * @v len Length of data buffer
113 * @ret rc Return status code
114 */
115 static int intel_write_eeprom ( struct nvs_device *nvs,
116 unsigned int address __unused,
117 const void *data __unused,
118 size_t len __unused ) {
119 struct intel_nic *intel =
120 container_of ( nvs, struct intel_nic, eeprom );
121
122 DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
123 return -ENOTSUP;
124 }
125
126 /**
127 * Initialise EEPROM
128 *
129 * @v intel Intel device
130 * @ret rc Return status code
131 */
132 static int intel_init_eeprom ( struct intel_nic *intel ) {
133 unsigned int i;
134 uint32_t value;
135
136 /* The NIC automatically detects the type of attached EEPROM.
137 * The EERD register provides access to only a single word at
138 * a time, so we pretend to have a single-word block size.
139 *
140 * The EEPROM size may be larger than the minimum size, but
141 * this doesn't matter to us since we access only the first
142 * few words.
143 */
144 intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
145 intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
146 intel->eeprom.block_size = 1;
147 intel->eeprom.read = intel_read_eeprom;
148 intel->eeprom.write = intel_write_eeprom;
149
150 /* The layout of the EERD register was changed at some point
151 * to accommodate larger EEPROMs. Read from address zero (for
152 * which the request layouts are compatible) to determine
153 * which type of register we have.
154 */
155 writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
156 for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
157 value = readl ( intel->regs + INTEL_EERD );
158 if ( value & INTEL_EERD_DONE_LARGE ) {
159 DBGC ( intel, "INTEL %p has large-format EERD\n",
160 intel );
161 intel->eerd_done = INTEL_EERD_DONE_LARGE;
162 intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
163 return 0;
164 }
165 if ( value & INTEL_EERD_DONE_SMALL ) {
166 DBGC ( intel, "INTEL %p has small-format EERD\n",
167 intel );
168 intel->eerd_done = INTEL_EERD_DONE_SMALL;
169 intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
170 return 0;
171 }
172 mdelay ( 1 );
173 }
174
175 DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
176 "(value %08x)\n", intel, value );
177 return -ETIMEDOUT;
178 }
179
180 /******************************************************************************
181 *
182 * MAC address
183 *
184 ******************************************************************************
185 */
186
187 /**
188 * Fetch initial MAC address from EEPROM
189 *
190 * @v intel Intel device
191 * @v hw_addr Hardware address to fill in
192 * @ret rc Return status code
193 */
194 static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
195 uint8_t *hw_addr ) {
196 int rc;
197
198 /* Initialise EEPROM */
199 if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
200 return rc;
201
202 /* Read base MAC address from EEPROM */
203 if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
204 hw_addr, ETH_ALEN ) ) != 0 ) {
205 DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
206 "address: %s\n", intel, strerror ( rc ) );
207 return rc;
208 }
209
210 /* Adjust MAC address for multi-port devices */
211 hw_addr[ETH_ALEN-1] ^= intel->port;
212
213 DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
214 intel, eth_ntoa ( hw_addr ), intel->port );
215 return 0;
216 }
217
218 /**
219 * Fetch initial MAC address
220 *
221 * @v intel Intel device
222 * @v hw_addr Hardware address to fill in
223 * @ret rc Return status code
224 */
225 static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
226 union intel_receive_address mac;
227 int rc;
228
229 /* Read current address from RAL0/RAH0 */
230 mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
231 mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
232 DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
233 intel, eth_ntoa ( mac.raw ) );
234
235 /* Try to read address from EEPROM */
236 if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
237 return 0;
238
239 /* Use current address if valid */
240 if ( is_valid_ether_addr ( mac.raw ) ) {
241 memcpy ( hw_addr, mac.raw, ETH_ALEN );
242 return 0;
243 }
244
245 DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
246 return -ENOENT;
247 }
248
249 /******************************************************************************
250 *
251 * Diagnostics
252 *
253 ******************************************************************************
254 */
255
256 /**
257 * Dump diagnostic information
258 *
259 * @v intel Intel device
260 */
261 static void __attribute__ (( unused )) intel_diag ( struct intel_nic *intel ) {
262
263 DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
264 "RX %04x(%02x)/%04x(%02x)\n", intel,
265 ( intel->tx.cons & 0xffff ),
266 readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
267 ( intel->tx.prod & 0xffff ),
268 readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
269 ( intel->rx.cons & 0xffff ),
270 readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
271 ( intel->rx.prod & 0xffff ),
272 readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
273 }
274
275 /******************************************************************************
276 *
277 * Device reset
278 *
279 ******************************************************************************
280 */
281
282 /**
283 * Reset hardware
284 *
285 * @v intel Intel device
286 * @ret rc Return status code
287 */
288 static int intel_reset ( struct intel_nic *intel ) {
289 uint32_t pbs;
290 uint32_t pba;
291 uint32_t ctrl;
292 uint32_t status;
293
294 /* Force RX and TX packet buffer allocation, to work around an
295 * errata in ICH devices.
296 */
297 if ( intel->flags & INTEL_PBS_ERRATA ) {
298 DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
299 intel );
300 pbs = readl ( intel->regs + INTEL_PBS );
301 pba = readl ( intel->regs + INTEL_PBA );
302 writel ( 0x08, intel->regs + INTEL_PBA );
303 writel ( 0x10, intel->regs + INTEL_PBS );
304 DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
305 intel, pbs, readl ( intel->regs + INTEL_PBS ),
306 pba, readl ( intel->regs + INTEL_PBA ) );
307 }
308
309 /* Always reset MAC. Required to reset the TX and RX rings. */
310 ctrl = readl ( intel->regs + INTEL_CTRL );
311 writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
312 mdelay ( INTEL_RESET_DELAY_MS );
313
314 /* Set a sensible default configuration */
315 ctrl |= ( INTEL_CTRL_SLU | INTEL_CTRL_ASDE );
316 ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
317 writel ( ctrl, intel->regs + INTEL_CTRL );
318 mdelay ( INTEL_RESET_DELAY_MS );
319
320 /* If link is already up, do not attempt to reset the PHY. On
321 * some models (notably ICH), performing a PHY reset seems to
322 * drop the link speed to 10Mbps.
323 */
324 status = readl ( intel->regs + INTEL_STATUS );
325 if ( status & INTEL_STATUS_LU ) {
326 DBGC ( intel, "INTEL %p MAC reset (ctrl %08x)\n",
327 intel, ctrl );
328 return 0;
329 }
330
331 /* Reset PHY and MAC simultaneously */
332 writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
333 intel->regs + INTEL_CTRL );
334 mdelay ( INTEL_RESET_DELAY_MS );
335
336 /* PHY reset is not self-clearing on all models */
337 writel ( ctrl, intel->regs + INTEL_CTRL );
338 mdelay ( INTEL_RESET_DELAY_MS );
339
340 DBGC ( intel, "INTEL %p MAC+PHY reset (ctrl %08x)\n", intel, ctrl );
341 return 0;
342 }
343
344 /******************************************************************************
345 *
346 * Link state
347 *
348 ******************************************************************************
349 */
350
351 /**
352 * Check link state
353 *
354 * @v netdev Network device
355 */
356 static void intel_check_link ( struct net_device *netdev ) {
357 struct intel_nic *intel = netdev->priv;
358 uint32_t status;
359
360 /* Read link status */
361 status = readl ( intel->regs + INTEL_STATUS );
362 DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
363
364 /* Update network device */
365 if ( status & INTEL_STATUS_LU ) {
366 netdev_link_up ( netdev );
367 } else {
368 netdev_link_down ( netdev );
369 }
370 }
371
372 /******************************************************************************
373 *
374 * Network device interface
375 *
376 ******************************************************************************
377 */
378
379 /**
380 * Create descriptor ring
381 *
382 * @v intel Intel device
383 * @v ring Descriptor ring
384 * @ret rc Return status code
385 */
386 int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
387 physaddr_t address;
388 uint32_t dctl;
389
390 /* Allocate descriptor ring. Align ring on its own size to
391 * prevent any possible page-crossing errors due to hardware
392 * errata.
393 */
394 ring->desc = malloc_dma ( ring->len, ring->len );
395 if ( ! ring->desc )
396 return -ENOMEM;
397
398 /* Initialise descriptor ring */
399 memset ( ring->desc, 0, ring->len );
400
401 /* Program ring address */
402 address = virt_to_bus ( ring->desc );
403 writel ( ( address & 0xffffffffUL ),
404 ( intel->regs + ring->reg + INTEL_xDBAL ) );
405 if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
406 writel ( ( ( ( uint64_t ) address ) >> 32 ),
407 ( intel->regs + ring->reg + INTEL_xDBAH ) );
408 } else {
409 writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
410 }
411
412 /* Program ring length */
413 writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
414
415 /* Reset head and tail pointers */
416 writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
417 writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
418
419 /* Enable ring */
420 dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
421 dctl |= INTEL_xDCTL_ENABLE;
422 writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
423
424 DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
425 intel, ring->reg, ( ( unsigned long long ) address ),
426 ( ( unsigned long long ) address + ring->len ) );
427
428 return 0;
429 }
430
431 /**
432 * Destroy descriptor ring
433 *
434 * @v intel Intel device
435 * @v ring Descriptor ring
436 */
437 void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
438
439 /* Clear ring length */
440 writel ( 0, ( intel->regs + ring->reg + INTEL_xDLEN ) );
441
442 /* Clear ring address */
443 writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAL ) );
444 writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAH ) );
445
446 /* Free descriptor ring */
447 free_dma ( ring->desc, ring->len );
448 ring->desc = NULL;
449 ring->prod = 0;
450 ring->cons = 0;
451 }
452
453 /**
454 * Refill receive descriptor ring
455 *
456 * @v intel Intel device
457 */
458 void intel_refill_rx ( struct intel_nic *intel ) {
459 struct intel_descriptor *rx;
460 struct io_buffer *iobuf;
461 unsigned int rx_idx;
462 unsigned int rx_tail;
463 physaddr_t address;
464 unsigned int refilled = 0;
465
466 /* Refill ring */
467 while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
468
469 /* Allocate I/O buffer */
470 iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
471 if ( ! iobuf ) {
472 /* Wait for next refill */
473 break;
474 }
475
476 /* Get next receive descriptor */
477 rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
478 rx = &intel->rx.desc[rx_idx];
479
480 /* Populate receive descriptor */
481 address = virt_to_bus ( iobuf->data );
482 rx->address = cpu_to_le64 ( address );
483 rx->length = 0;
484 rx->status = 0;
485 rx->errors = 0;
486
487 /* Record I/O buffer */
488 assert ( intel->rx_iobuf[rx_idx] == NULL );
489 intel->rx_iobuf[rx_idx] = iobuf;
490
491 DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
492 ( ( unsigned long long ) address ),
493 ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
494 refilled++;
495 }
496
497 /* Push descriptors to card, if applicable */
498 if ( refilled ) {
499 wmb();
500 rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
501 profile_start ( &intel_vm_refill_profiler );
502 writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
503 profile_stop ( &intel_vm_refill_profiler );
504 profile_exclude ( &intel_vm_refill_profiler );
505 }
506 }
507
508 /**
509 * Discard unused receive I/O buffers
510 *
511 * @v intel Intel device
512 */
513 void intel_empty_rx ( struct intel_nic *intel ) {
514 unsigned int i;
515
516 for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
517 if ( intel->rx_iobuf[i] )
518 free_iob ( intel->rx_iobuf[i] );
519 intel->rx_iobuf[i] = NULL;
520 }
521 }
522
523 /**
524 * Open network device
525 *
526 * @v netdev Network device
527 * @ret rc Return status code
528 */
529 static int intel_open ( struct net_device *netdev ) {
530 struct intel_nic *intel = netdev->priv;
531 union intel_receive_address mac;
532 uint32_t tctl;
533 uint32_t rctl;
534 int rc;
535
536 /* Create transmit descriptor ring */
537 if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
538 goto err_create_tx;
539
540 /* Create receive descriptor ring */
541 if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
542 goto err_create_rx;
543
544 /* Program MAC address */
545 memset ( &mac, 0, sizeof ( mac ) );
546 memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
547 writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
548 writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
549 intel->regs + INTEL_RAH0 );
550
551 /* Enable transmitter */
552 tctl = readl ( intel->regs + INTEL_TCTL );
553 tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
554 tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
555 INTEL_TCTL_COLD_DEFAULT );
556 writel ( tctl, intel->regs + INTEL_TCTL );
557
558 /* Enable receiver */
559 rctl = readl ( intel->regs + INTEL_RCTL );
560 rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
561 rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
562 INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
563 writel ( rctl, intel->regs + INTEL_RCTL );
564
565 /* Fill receive ring */
566 intel_refill_rx ( intel );
567
568 /* Update link state */
569 intel_check_link ( netdev );
570
571 return 0;
572
573 intel_destroy_ring ( intel, &intel->rx );
574 err_create_rx:
575 intel_destroy_ring ( intel, &intel->tx );
576 err_create_tx:
577 return rc;
578 }
579
580 /**
581 * Close network device
582 *
583 * @v netdev Network device
584 */
585 static void intel_close ( struct net_device *netdev ) {
586 struct intel_nic *intel = netdev->priv;
587
588 /* Disable receiver */
589 writel ( 0, intel->regs + INTEL_RCTL );
590
591 /* Disable transmitter */
592 writel ( 0, intel->regs + INTEL_TCTL );
593
594 /* Destroy receive descriptor ring */
595 intel_destroy_ring ( intel, &intel->rx );
596
597 /* Discard any unused receive buffers */
598 intel_empty_rx ( intel );
599
600 /* Destroy transmit descriptor ring */
601 intel_destroy_ring ( intel, &intel->tx );
602
603 /* Reset the NIC, to flush the transmit and receive FIFOs */
604 intel_reset ( intel );
605 }
606
607 /**
608 * Transmit packet
609 *
610 * @v netdev Network device
611 * @v iobuf I/O buffer
612 * @ret rc Return status code
613 */
614 int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
615 struct intel_nic *intel = netdev->priv;
616 struct intel_descriptor *tx;
617 unsigned int tx_idx;
618 unsigned int tx_tail;
619 physaddr_t address;
620
621 /* Get next transmit descriptor */
622 if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
623 DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
624 return -ENOBUFS;
625 }
626 tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
627 tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
628 tx = &intel->tx.desc[tx_idx];
629
630 /* Populate transmit descriptor */
631 address = virt_to_bus ( iobuf->data );
632 tx->address = cpu_to_le64 ( address );
633 tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
634 tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
635 INTEL_DESC_CMD_EOP );
636 tx->status = 0;
637 wmb();
638
639 /* Notify card that there are packets ready to transmit */
640 profile_start ( &intel_vm_tx_profiler );
641 writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
642 profile_stop ( &intel_vm_tx_profiler );
643 profile_exclude ( &intel_vm_tx_profiler );
644
645 DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
646 ( ( unsigned long long ) address ),
647 ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
648
649 return 0;
650 }
651
652 /**
653 * Poll for completed packets
654 *
655 * @v netdev Network device
656 */
657 void intel_poll_tx ( struct net_device *netdev ) {
658 struct intel_nic *intel = netdev->priv;
659 struct intel_descriptor *tx;
660 unsigned int tx_idx;
661
662 /* Check for completed packets */
663 while ( intel->tx.cons != intel->tx.prod ) {
664
665 /* Get next transmit descriptor */
666 tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
667 tx = &intel->tx.desc[tx_idx];
668
669 /* Stop if descriptor is still in use */
670 if ( ! ( tx->status & INTEL_DESC_STATUS_DD ) )
671 return;
672
673 DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
674
675 /* Complete TX descriptor */
676 netdev_tx_complete_next ( netdev );
677 intel->tx.cons++;
678 }
679 }
680
681 /**
682 * Poll for received packets
683 *
684 * @v netdev Network device
685 */
686 void intel_poll_rx ( struct net_device *netdev ) {
687 struct intel_nic *intel = netdev->priv;
688 struct intel_descriptor *rx;
689 struct io_buffer *iobuf;
690 unsigned int rx_idx;
691 size_t len;
692
693 /* Check for received packets */
694 while ( intel->rx.cons != intel->rx.prod ) {
695
696 /* Get next receive descriptor */
697 rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
698 rx = &intel->rx.desc[rx_idx];
699
700 /* Stop if descriptor is still in use */
701 if ( ! ( rx->status & INTEL_DESC_STATUS_DD ) )
702 return;
703
704 /* Populate I/O buffer */
705 iobuf = intel->rx_iobuf[rx_idx];
706 intel->rx_iobuf[rx_idx] = NULL;
707 len = le16_to_cpu ( rx->length );
708 iob_put ( iobuf, len );
709
710 /* Hand off to network stack */
711 if ( rx->errors ) {
712 DBGC ( intel, "INTEL %p RX %d error (length %zd, "
713 "errors %02x)\n",
714 intel, rx_idx, len, rx->errors );
715 netdev_rx_err ( netdev, iobuf, -EIO );
716 } else {
717 DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
718 intel, rx_idx, len );
719 netdev_rx ( netdev, iobuf );
720 }
721 intel->rx.cons++;
722 }
723 }
724
725 /**
726 * Poll for completed and received packets
727 *
728 * @v netdev Network device
729 */
730 static void intel_poll ( struct net_device *netdev ) {
731 struct intel_nic *intel = netdev->priv;
732 uint32_t icr;
733
734 /* Check for and acknowledge interrupts */
735 profile_start ( &intel_vm_poll_profiler );
736 icr = readl ( intel->regs + INTEL_ICR );
737 profile_stop ( &intel_vm_poll_profiler );
738 profile_exclude ( &intel_vm_poll_profiler );
739 if ( ! icr )
740 return;
741
742 /* Poll for TX completions, if applicable */
743 if ( icr & INTEL_IRQ_TXDW )
744 intel_poll_tx ( netdev );
745
746 /* Poll for RX completions, if applicable */
747 if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
748 intel_poll_rx ( netdev );
749
750 /* Report receive overruns */
751 if ( icr & INTEL_IRQ_RXO )
752 netdev_rx_err ( netdev, NULL, -ENOBUFS );
753
754 /* Check link state, if applicable */
755 if ( icr & INTEL_IRQ_LSC )
756 intel_check_link ( netdev );
757
758 /* Refill RX ring */
759 intel_refill_rx ( intel );
760 }
761
762 /**
763 * Enable or disable interrupts
764 *
765 * @v netdev Network device
766 * @v enable Interrupts should be enabled
767 */
768 static void intel_irq ( struct net_device *netdev, int enable ) {
769 struct intel_nic *intel = netdev->priv;
770 uint32_t mask;
771
772 mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
773 if ( enable ) {
774 writel ( mask, intel->regs + INTEL_IMS );
775 } else {
776 writel ( mask, intel->regs + INTEL_IMC );
777 }
778 }
779
780 /** Intel network device operations */
781 static struct net_device_operations intel_operations = {
782 .open = intel_open,
783 .close = intel_close,
784 .transmit = intel_transmit,
785 .poll = intel_poll,
786 .irq = intel_irq,
787 };
788
789 /******************************************************************************
790 *
791 * PCI interface
792 *
793 ******************************************************************************
794 */
795
796 /**
797 * Probe PCI device
798 *
799 * @v pci PCI device
800 * @ret rc Return status code
801 */
802 static int intel_probe ( struct pci_device *pci ) {
803 struct net_device *netdev;
804 struct intel_nic *intel;
805 int rc;
806
807 /* Allocate and initialise net device */
808 netdev = alloc_etherdev ( sizeof ( *intel ) );
809 if ( ! netdev ) {
810 rc = -ENOMEM;
811 goto err_alloc;
812 }
813 netdev_init ( netdev, &intel_operations );
814 intel = netdev->priv;
815 pci_set_drvdata ( pci, netdev );
816 netdev->dev = &pci->dev;
817 memset ( intel, 0, sizeof ( *intel ) );
818 intel->port = PCI_FUNC ( pci->busdevfn );
819 intel->flags = pci->id->driver_data;
820 intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD );
821 intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD );
822
823 /* Fix up PCI device */
824 adjust_pci_device ( pci );
825
826 /* Map registers */
827 intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
828 if ( ! intel->regs ) {
829 rc = -ENODEV;
830 goto err_ioremap;
831 }
832
833 /* Reset the NIC */
834 if ( ( rc = intel_reset ( intel ) ) != 0 )
835 goto err_reset;
836
837 /* Fetch MAC address */
838 if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
839 goto err_fetch_mac;
840
841 /* Register network device */
842 if ( ( rc = register_netdev ( netdev ) ) != 0 )
843 goto err_register_netdev;
844
845 /* Set initial link state */
846 intel_check_link ( netdev );
847
848 return 0;
849
850 unregister_netdev ( netdev );
851 err_register_netdev:
852 err_fetch_mac:
853 intel_reset ( intel );
854 err_reset:
855 iounmap ( intel->regs );
856 err_ioremap:
857 netdev_nullify ( netdev );
858 netdev_put ( netdev );
859 err_alloc:
860 return rc;
861 }
862
863 /**
864 * Remove PCI device
865 *
866 * @v pci PCI device
867 */
868 static void intel_remove ( struct pci_device *pci ) {
869 struct net_device *netdev = pci_get_drvdata ( pci );
870 struct intel_nic *intel = netdev->priv;
871
872 /* Unregister network device */
873 unregister_netdev ( netdev );
874
875 /* Reset the NIC */
876 intel_reset ( intel );
877
878 /* Free network device */
879 iounmap ( intel->regs );
880 netdev_nullify ( netdev );
881 netdev_put ( netdev );
882 }
883
884 /** Intel PCI device IDs */
885 static struct pci_device_id intel_nics[] = {
886 PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
887 PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
888 PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
889 PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
890 PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
891 PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
892 PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
893 PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
894 PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
895 PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
896 PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
897 PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
898 PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", 0 ),
899 PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
900 PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
901 PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
902 PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
903 PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
904 PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
905 PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
906 PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
907 PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
908 PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
909 PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
910 PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
911 PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
912 PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
913 PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
914 PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
915 PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
916 PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
917 PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
918 PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
919 PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
920 PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
921 PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
922 PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
923 PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
924 PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
925 PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
926 PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
927 PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
928 PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
929 PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
930 PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
931 PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
932 PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
933 PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
934 PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
935 PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
936 PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
937 PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
938 PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
939 PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
940 PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
941 PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
942 PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
943 PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
944 PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
945 PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
946 PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
947 PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
948 PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
949 PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
950 PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
951 PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
952 PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
953 PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
954 PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
955 PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
956 PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
957 PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
958 PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
959 PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
960 PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
961 PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
962 PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
963 PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
964 PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
965 PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
966 PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
967 PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
968 PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
969 PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
970 PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
971 PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
972 PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
973 PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
974 PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
975 PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
976 PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
977 PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
978 PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
979 PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
980 PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", 0 ),
981 PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
982 PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
983 PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
984 PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
985 PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
986 PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
987 PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
988 PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
989 PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
990 PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
991 PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
992 PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
993 PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", 0 ),
994 PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
995 PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
996 PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
997 PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
998 PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
999 PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", 0 ),
1000 PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
1001 PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
1002 PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
1003 };
1004
1005 /** Intel PCI driver */
1006 struct pci_driver intel_driver __pci_driver = {
1007 .ids = intel_nics,
1008 .id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
1009 .probe = intel_probe,
1010 .remove = intel_remove,
1011 };