[intel] Add support for I219-V in 7th Gen Intel NUC
[ipxe.git] / src / drivers / net / intel.c
1 /*
2 * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17 * 02110-1301, USA.
18 *
19 * You can also choose to distribute this program under the terms of
20 * the Unmodified Binary Distribution Licence (as given in the file
21 * COPYING.UBDL), provided that you have satisfied its requirements.
22 */
23
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25
26 #include <stdint.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include <errno.h>
30 #include <byteswap.h>
31 #include <ipxe/netdevice.h>
32 #include <ipxe/ethernet.h>
33 #include <ipxe/if_ether.h>
34 #include <ipxe/iobuf.h>
35 #include <ipxe/malloc.h>
36 #include <ipxe/pci.h>
37 #include <ipxe/profile.h>
38 #include "intel.h"
39
40 /** @file
41 *
42 * Intel 10/100/1000 network card driver
43 *
44 */
45
46 /** VM transmit profiler */
47 static struct profiler intel_vm_tx_profiler __profiler =
48 { .name = "intel.vm_tx" };
49
50 /** VM receive refill profiler */
51 static struct profiler intel_vm_refill_profiler __profiler =
52 { .name = "intel.vm_refill" };
53
54 /** VM poll profiler */
55 static struct profiler intel_vm_poll_profiler __profiler =
56 { .name = "intel.vm_poll" };
57
58 /******************************************************************************
59 *
60 * EEPROM interface
61 *
62 ******************************************************************************
63 */
64
65 /**
66 * Read data from EEPROM
67 *
68 * @v nvs NVS device
69 * @v address Address from which to read
70 * @v data Data buffer
71 * @v len Length of data buffer
72 * @ret rc Return status code
73 */
74 static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
75 void *data, size_t len ) {
76 struct intel_nic *intel =
77 container_of ( nvs, struct intel_nic, eeprom );
78 unsigned int i;
79 uint32_t value;
80 uint16_t *data_word = data;
81
82 /* Sanity check. We advertise a blocksize of one word, so
83 * should only ever receive single-word requests.
84 */
85 assert ( len == sizeof ( *data_word ) );
86
87 /* Initiate read */
88 writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
89 intel->regs + INTEL_EERD );
90
91 /* Wait for read to complete */
92 for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
93
94 /* If read is not complete, delay 1ms and retry */
95 value = readl ( intel->regs + INTEL_EERD );
96 if ( ! ( value & intel->eerd_done ) ) {
97 mdelay ( 1 );
98 continue;
99 }
100
101 /* Extract data */
102 *data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
103 return 0;
104 }
105
106 DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
107 return -ETIMEDOUT;
108 }
109
110 /**
111 * Write data to EEPROM
112 *
113 * @v nvs NVS device
114 * @v address Address to which to write
115 * @v data Data buffer
116 * @v len Length of data buffer
117 * @ret rc Return status code
118 */
119 static int intel_write_eeprom ( struct nvs_device *nvs,
120 unsigned int address __unused,
121 const void *data __unused,
122 size_t len __unused ) {
123 struct intel_nic *intel =
124 container_of ( nvs, struct intel_nic, eeprom );
125
126 DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
127 return -ENOTSUP;
128 }
129
130 /**
131 * Initialise EEPROM
132 *
133 * @v intel Intel device
134 * @ret rc Return status code
135 */
136 static int intel_init_eeprom ( struct intel_nic *intel ) {
137 unsigned int i;
138 uint32_t value;
139
140 /* The NIC automatically detects the type of attached EEPROM.
141 * The EERD register provides access to only a single word at
142 * a time, so we pretend to have a single-word block size.
143 *
144 * The EEPROM size may be larger than the minimum size, but
145 * this doesn't matter to us since we access only the first
146 * few words.
147 */
148 intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
149 intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
150 intel->eeprom.block_size = 1;
151 intel->eeprom.read = intel_read_eeprom;
152 intel->eeprom.write = intel_write_eeprom;
153
154 /* The layout of the EERD register was changed at some point
155 * to accommodate larger EEPROMs. Read from address zero (for
156 * which the request layouts are compatible) to determine
157 * which type of register we have.
158 */
159 writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
160 for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
161 value = readl ( intel->regs + INTEL_EERD );
162 if ( value & INTEL_EERD_DONE_LARGE ) {
163 DBGC ( intel, "INTEL %p has large-format EERD\n",
164 intel );
165 intel->eerd_done = INTEL_EERD_DONE_LARGE;
166 intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
167 return 0;
168 }
169 if ( value & INTEL_EERD_DONE_SMALL ) {
170 DBGC ( intel, "INTEL %p has small-format EERD\n",
171 intel );
172 intel->eerd_done = INTEL_EERD_DONE_SMALL;
173 intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
174 return 0;
175 }
176 mdelay ( 1 );
177 }
178
179 DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
180 "(value %08x)\n", intel, value );
181 return -ETIMEDOUT;
182 }
183
184 /******************************************************************************
185 *
186 * MAC address
187 *
188 ******************************************************************************
189 */
190
191 /**
192 * Fetch initial MAC address from EEPROM
193 *
194 * @v intel Intel device
195 * @v hw_addr Hardware address to fill in
196 * @ret rc Return status code
197 */
198 static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
199 uint8_t *hw_addr ) {
200 int rc;
201
202 /* Initialise EEPROM */
203 if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
204 return rc;
205
206 /* Read base MAC address from EEPROM */
207 if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
208 hw_addr, ETH_ALEN ) ) != 0 ) {
209 DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
210 "address: %s\n", intel, strerror ( rc ) );
211 return rc;
212 }
213
214 /* Adjust MAC address for multi-port devices */
215 hw_addr[ETH_ALEN-1] ^= intel->port;
216
217 DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
218 intel, eth_ntoa ( hw_addr ), intel->port );
219 return 0;
220 }
221
222 /**
223 * Fetch initial MAC address
224 *
225 * @v intel Intel device
226 * @v hw_addr Hardware address to fill in
227 * @ret rc Return status code
228 */
229 static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
230 union intel_receive_address mac;
231 int rc;
232
233 /* Read current address from RAL0/RAH0 */
234 mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
235 mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
236 DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
237 intel, eth_ntoa ( mac.raw ) );
238
239 /* Use current address if valid */
240 if ( is_valid_ether_addr ( mac.raw ) ) {
241 memcpy ( hw_addr, mac.raw, ETH_ALEN );
242 return 0;
243 }
244
245 /* Otherwise, try to read address from EEPROM */
246 if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
247 return 0;
248
249 DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
250 return -ENOENT;
251 }
252
253 /******************************************************************************
254 *
255 * Device reset
256 *
257 ******************************************************************************
258 */
259
260 /**
261 * Reset hardware
262 *
263 * @v intel Intel device
264 * @ret rc Return status code
265 */
266 static int intel_reset ( struct intel_nic *intel ) {
267 uint32_t pbs;
268 uint32_t pba;
269 uint32_t ctrl;
270 uint32_t status;
271 uint32_t orig_ctrl;
272 uint32_t orig_status;
273
274 /* Record initial control and status register values */
275 orig_ctrl = ctrl = readl ( intel->regs + INTEL_CTRL );
276 orig_status = readl ( intel->regs + INTEL_STATUS );
277
278 /* Force RX and TX packet buffer allocation, to work around an
279 * errata in ICH devices.
280 */
281 if ( intel->flags & INTEL_PBS_ERRATA ) {
282 DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
283 intel );
284 pbs = readl ( intel->regs + INTEL_PBS );
285 pba = readl ( intel->regs + INTEL_PBA );
286 writel ( 0x08, intel->regs + INTEL_PBA );
287 writel ( 0x10, intel->regs + INTEL_PBS );
288 DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
289 intel, pbs, readl ( intel->regs + INTEL_PBS ),
290 pba, readl ( intel->regs + INTEL_PBA ) );
291 }
292
293 /* Always reset MAC. Required to reset the TX and RX rings. */
294 writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
295 mdelay ( INTEL_RESET_DELAY_MS );
296
297 /* Set a sensible default configuration */
298 if ( ! ( intel->flags & INTEL_NO_ASDE ) )
299 ctrl |= INTEL_CTRL_ASDE;
300 ctrl |= INTEL_CTRL_SLU;
301 ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
302 writel ( ctrl, intel->regs + INTEL_CTRL );
303 mdelay ( INTEL_RESET_DELAY_MS );
304
305 /* On some models (notably ICH), the PHY reset mechanism
306 * appears to be broken. In particular, the PHY_CTRL register
307 * will be correctly loaded from NVM but the values will not
308 * be propagated to the "OEM bits" PHY register. This
309 * typically has the effect of dropping the link speed to
310 * 10Mbps.
311 *
312 * Work around this problem by skipping the PHY reset if
313 * either (a) the link is already up, or (b) this particular
314 * NIC is known to be broken.
315 */
316 status = readl ( intel->regs + INTEL_STATUS );
317 if ( ( intel->flags & INTEL_NO_PHY_RST ) ||
318 ( status & INTEL_STATUS_LU ) ) {
319 DBGC ( intel, "INTEL %p %sMAC reset (%08x/%08x was "
320 "%08x/%08x)\n", intel,
321 ( ( intel->flags & INTEL_NO_PHY_RST ) ? "forced " : "" ),
322 ctrl, status, orig_ctrl, orig_status );
323 return 0;
324 }
325
326 /* Reset PHY and MAC simultaneously */
327 writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
328 intel->regs + INTEL_CTRL );
329 mdelay ( INTEL_RESET_DELAY_MS );
330
331 /* PHY reset is not self-clearing on all models */
332 writel ( ctrl, intel->regs + INTEL_CTRL );
333 mdelay ( INTEL_RESET_DELAY_MS );
334 status = readl ( intel->regs + INTEL_STATUS );
335
336 DBGC ( intel, "INTEL %p MAC+PHY reset (%08x/%08x was %08x/%08x)\n",
337 intel, ctrl, status, orig_ctrl, orig_status );
338 return 0;
339 }
340
341 /******************************************************************************
342 *
343 * Link state
344 *
345 ******************************************************************************
346 */
347
348 /**
349 * Check link state
350 *
351 * @v netdev Network device
352 */
353 static void intel_check_link ( struct net_device *netdev ) {
354 struct intel_nic *intel = netdev->priv;
355 uint32_t status;
356
357 /* Read link status */
358 status = readl ( intel->regs + INTEL_STATUS );
359 DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
360
361 /* Update network device */
362 if ( status & INTEL_STATUS_LU ) {
363 netdev_link_up ( netdev );
364 } else {
365 netdev_link_down ( netdev );
366 }
367 }
368
369 /******************************************************************************
370 *
371 * Descriptors
372 *
373 ******************************************************************************
374 */
375
376 /**
377 * Populate transmit descriptor
378 *
379 * @v tx Transmit descriptor
380 * @v addr Data buffer address
381 * @v len Length of data
382 */
383 void intel_describe_tx ( struct intel_descriptor *tx, physaddr_t addr,
384 size_t len ) {
385
386 /* Populate transmit descriptor */
387 tx->address = cpu_to_le64 ( addr );
388 tx->length = cpu_to_le16 ( len );
389 tx->flags = 0;
390 tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
391 INTEL_DESC_CMD_EOP );
392 tx->status = 0;
393 }
394
395 /**
396 * Populate advanced transmit descriptor
397 *
398 * @v tx Transmit descriptor
399 * @v addr Data buffer address
400 * @v len Length of data
401 */
402 void intel_describe_tx_adv ( struct intel_descriptor *tx, physaddr_t addr,
403 size_t len ) {
404
405 /* Populate advanced transmit descriptor */
406 tx->address = cpu_to_le64 ( addr );
407 tx->length = cpu_to_le16 ( len );
408 tx->flags = INTEL_DESC_FL_DTYP_DATA;
409 tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
410 INTEL_DESC_CMD_IFCS | INTEL_DESC_CMD_EOP );
411 tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
412 }
413
414 /**
415 * Populate receive descriptor
416 *
417 * @v rx Receive descriptor
418 * @v addr Data buffer address
419 * @v len Length of data
420 */
421 void intel_describe_rx ( struct intel_descriptor *rx, physaddr_t addr,
422 size_t len __unused ) {
423
424 /* Populate transmit descriptor */
425 rx->address = cpu_to_le64 ( addr );
426 rx->length = 0;
427 rx->status = 0;
428 }
429
430 /******************************************************************************
431 *
432 * Network device interface
433 *
434 ******************************************************************************
435 */
436
437 /**
438 * Disable descriptor ring
439 *
440 * @v intel Intel device
441 * @v reg Register block
442 * @ret rc Return status code
443 */
444 static int intel_disable_ring ( struct intel_nic *intel, unsigned int reg ) {
445 uint32_t dctl;
446 unsigned int i;
447
448 /* Disable ring */
449 writel ( 0, ( intel->regs + reg + INTEL_xDCTL ) );
450
451 /* Wait for disable to complete */
452 for ( i = 0 ; i < INTEL_DISABLE_MAX_WAIT_MS ; i++ ) {
453
454 /* Check if ring is disabled */
455 dctl = readl ( intel->regs + reg + INTEL_xDCTL );
456 if ( ! ( dctl & INTEL_xDCTL_ENABLE ) )
457 return 0;
458
459 /* Delay */
460 mdelay ( 1 );
461 }
462
463 DBGC ( intel, "INTEL %p ring %05x timed out waiting for disable "
464 "(dctl %08x)\n", intel, reg, dctl );
465 return -ETIMEDOUT;
466 }
467
468 /**
469 * Reset descriptor ring
470 *
471 * @v intel Intel device
472 * @v reg Register block
473 * @ret rc Return status code
474 */
475 void intel_reset_ring ( struct intel_nic *intel, unsigned int reg ) {
476
477 /* Disable ring. Ignore errors and continue to reset the ring anyway */
478 intel_disable_ring ( intel, reg );
479
480 /* Clear ring length */
481 writel ( 0, ( intel->regs + reg + INTEL_xDLEN ) );
482
483 /* Clear ring address */
484 writel ( 0, ( intel->regs + reg + INTEL_xDBAH ) );
485 writel ( 0, ( intel->regs + reg + INTEL_xDBAL ) );
486
487 /* Reset head and tail pointers */
488 writel ( 0, ( intel->regs + reg + INTEL_xDH ) );
489 writel ( 0, ( intel->regs + reg + INTEL_xDT ) );
490 }
491
492 /**
493 * Create descriptor ring
494 *
495 * @v intel Intel device
496 * @v ring Descriptor ring
497 * @ret rc Return status code
498 */
499 int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
500 physaddr_t address;
501 uint32_t dctl;
502
503 /* Allocate descriptor ring. Align ring on its own size to
504 * prevent any possible page-crossing errors due to hardware
505 * errata.
506 */
507 ring->desc = malloc_dma ( ring->len, ring->len );
508 if ( ! ring->desc )
509 return -ENOMEM;
510
511 /* Initialise descriptor ring */
512 memset ( ring->desc, 0, ring->len );
513
514 /* Program ring address */
515 address = virt_to_bus ( ring->desc );
516 writel ( ( address & 0xffffffffUL ),
517 ( intel->regs + ring->reg + INTEL_xDBAL ) );
518 if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
519 writel ( ( ( ( uint64_t ) address ) >> 32 ),
520 ( intel->regs + ring->reg + INTEL_xDBAH ) );
521 } else {
522 writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
523 }
524
525 /* Program ring length */
526 writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
527
528 /* Reset head and tail pointers */
529 writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
530 writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
531
532 /* Enable ring */
533 dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
534 dctl |= INTEL_xDCTL_ENABLE;
535 writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
536
537 DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
538 intel, ring->reg, ( ( unsigned long long ) address ),
539 ( ( unsigned long long ) address + ring->len ) );
540
541 return 0;
542 }
543
544 /**
545 * Destroy descriptor ring
546 *
547 * @v intel Intel device
548 * @v ring Descriptor ring
549 */
550 void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
551
552 /* Reset ring */
553 intel_reset_ring ( intel, ring->reg );
554
555 /* Free descriptor ring */
556 free_dma ( ring->desc, ring->len );
557 ring->desc = NULL;
558 ring->prod = 0;
559 ring->cons = 0;
560 }
561
562 /**
563 * Refill receive descriptor ring
564 *
565 * @v intel Intel device
566 */
567 void intel_refill_rx ( struct intel_nic *intel ) {
568 struct intel_descriptor *rx;
569 struct io_buffer *iobuf;
570 unsigned int rx_idx;
571 unsigned int rx_tail;
572 physaddr_t address;
573 unsigned int refilled = 0;
574
575 /* Refill ring */
576 while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
577
578 /* Allocate I/O buffer */
579 iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
580 if ( ! iobuf ) {
581 /* Wait for next refill */
582 break;
583 }
584
585 /* Get next receive descriptor */
586 rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
587 rx = &intel->rx.desc[rx_idx];
588
589 /* Populate receive descriptor */
590 address = virt_to_bus ( iobuf->data );
591 intel->rx.describe ( rx, address, 0 );
592
593 /* Record I/O buffer */
594 assert ( intel->rx_iobuf[rx_idx] == NULL );
595 intel->rx_iobuf[rx_idx] = iobuf;
596
597 DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
598 ( ( unsigned long long ) address ),
599 ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
600 refilled++;
601 }
602
603 /* Push descriptors to card, if applicable */
604 if ( refilled ) {
605 wmb();
606 rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
607 profile_start ( &intel_vm_refill_profiler );
608 writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
609 profile_stop ( &intel_vm_refill_profiler );
610 profile_exclude ( &intel_vm_refill_profiler );
611 }
612 }
613
614 /**
615 * Discard unused receive I/O buffers
616 *
617 * @v intel Intel device
618 */
619 void intel_empty_rx ( struct intel_nic *intel ) {
620 unsigned int i;
621
622 for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
623 if ( intel->rx_iobuf[i] )
624 free_iob ( intel->rx_iobuf[i] );
625 intel->rx_iobuf[i] = NULL;
626 }
627 }
628
629 /**
630 * Open network device
631 *
632 * @v netdev Network device
633 * @ret rc Return status code
634 */
635 static int intel_open ( struct net_device *netdev ) {
636 struct intel_nic *intel = netdev->priv;
637 union intel_receive_address mac;
638 uint32_t tctl;
639 uint32_t rctl;
640 int rc;
641
642 /* Create transmit descriptor ring */
643 if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
644 goto err_create_tx;
645
646 /* Create receive descriptor ring */
647 if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
648 goto err_create_rx;
649
650 /* Program MAC address */
651 memset ( &mac, 0, sizeof ( mac ) );
652 memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
653 writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
654 writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
655 intel->regs + INTEL_RAH0 );
656
657 /* Enable transmitter */
658 tctl = readl ( intel->regs + INTEL_TCTL );
659 tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
660 tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
661 INTEL_TCTL_COLD_DEFAULT );
662 writel ( tctl, intel->regs + INTEL_TCTL );
663
664 /* Enable receiver */
665 rctl = readl ( intel->regs + INTEL_RCTL );
666 rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
667 rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
668 INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
669 writel ( rctl, intel->regs + INTEL_RCTL );
670
671 /* Fill receive ring */
672 intel_refill_rx ( intel );
673
674 /* Update link state */
675 intel_check_link ( netdev );
676
677 /* Apply required errata */
678 if ( intel->flags & INTEL_VMWARE ) {
679 DBGC ( intel, "INTEL %p applying VMware errata workaround\n",
680 intel );
681 intel->force_icr = INTEL_IRQ_RXT0;
682 }
683
684 return 0;
685
686 intel_destroy_ring ( intel, &intel->rx );
687 err_create_rx:
688 intel_destroy_ring ( intel, &intel->tx );
689 err_create_tx:
690 return rc;
691 }
692
693 /**
694 * Close network device
695 *
696 * @v netdev Network device
697 */
698 static void intel_close ( struct net_device *netdev ) {
699 struct intel_nic *intel = netdev->priv;
700
701 /* Disable receiver */
702 writel ( 0, intel->regs + INTEL_RCTL );
703
704 /* Disable transmitter */
705 writel ( 0, intel->regs + INTEL_TCTL );
706
707 /* Destroy receive descriptor ring */
708 intel_destroy_ring ( intel, &intel->rx );
709
710 /* Discard any unused receive buffers */
711 intel_empty_rx ( intel );
712
713 /* Destroy transmit descriptor ring */
714 intel_destroy_ring ( intel, &intel->tx );
715
716 /* Reset the NIC, to flush the transmit and receive FIFOs */
717 intel_reset ( intel );
718 }
719
720 /**
721 * Transmit packet
722 *
723 * @v netdev Network device
724 * @v iobuf I/O buffer
725 * @ret rc Return status code
726 */
727 int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
728 struct intel_nic *intel = netdev->priv;
729 struct intel_descriptor *tx;
730 unsigned int tx_idx;
731 unsigned int tx_tail;
732 physaddr_t address;
733 size_t len;
734
735 /* Get next transmit descriptor */
736 if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
737 DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
738 return -ENOBUFS;
739 }
740 tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
741 tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
742 tx = &intel->tx.desc[tx_idx];
743
744 /* Populate transmit descriptor */
745 address = virt_to_bus ( iobuf->data );
746 len = iob_len ( iobuf );
747 intel->tx.describe ( tx, address, len );
748 wmb();
749
750 /* Notify card that there are packets ready to transmit */
751 profile_start ( &intel_vm_tx_profiler );
752 writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
753 profile_stop ( &intel_vm_tx_profiler );
754 profile_exclude ( &intel_vm_tx_profiler );
755
756 DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
757 ( ( unsigned long long ) address ),
758 ( ( unsigned long long ) address + len ) );
759
760 return 0;
761 }
762
763 /**
764 * Poll for completed packets
765 *
766 * @v netdev Network device
767 */
768 void intel_poll_tx ( struct net_device *netdev ) {
769 struct intel_nic *intel = netdev->priv;
770 struct intel_descriptor *tx;
771 unsigned int tx_idx;
772
773 /* Check for completed packets */
774 while ( intel->tx.cons != intel->tx.prod ) {
775
776 /* Get next transmit descriptor */
777 tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
778 tx = &intel->tx.desc[tx_idx];
779
780 /* Stop if descriptor is still in use */
781 if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
782 return;
783
784 DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
785
786 /* Complete TX descriptor */
787 netdev_tx_complete_next ( netdev );
788 intel->tx.cons++;
789 }
790 }
791
792 /**
793 * Poll for received packets
794 *
795 * @v netdev Network device
796 */
797 void intel_poll_rx ( struct net_device *netdev ) {
798 struct intel_nic *intel = netdev->priv;
799 struct intel_descriptor *rx;
800 struct io_buffer *iobuf;
801 unsigned int rx_idx;
802 size_t len;
803
804 /* Check for received packets */
805 while ( intel->rx.cons != intel->rx.prod ) {
806
807 /* Get next receive descriptor */
808 rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
809 rx = &intel->rx.desc[rx_idx];
810
811 /* Stop if descriptor is still in use */
812 if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
813 return;
814
815 /* Populate I/O buffer */
816 iobuf = intel->rx_iobuf[rx_idx];
817 intel->rx_iobuf[rx_idx] = NULL;
818 len = le16_to_cpu ( rx->length );
819 iob_put ( iobuf, len );
820
821 /* Hand off to network stack */
822 if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
823 DBGC ( intel, "INTEL %p RX %d error (length %zd, "
824 "status %08x)\n", intel, rx_idx, len,
825 le32_to_cpu ( rx->status ) );
826 netdev_rx_err ( netdev, iobuf, -EIO );
827 } else {
828 DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
829 intel, rx_idx, len );
830 netdev_rx ( netdev, iobuf );
831 }
832 intel->rx.cons++;
833 }
834 }
835
836 /**
837 * Poll for completed and received packets
838 *
839 * @v netdev Network device
840 */
841 static void intel_poll ( struct net_device *netdev ) {
842 struct intel_nic *intel = netdev->priv;
843 uint32_t icr;
844
845 /* Check for and acknowledge interrupts */
846 profile_start ( &intel_vm_poll_profiler );
847 icr = readl ( intel->regs + INTEL_ICR );
848 profile_stop ( &intel_vm_poll_profiler );
849 profile_exclude ( &intel_vm_poll_profiler );
850 icr |= intel->force_icr;
851 if ( ! icr )
852 return;
853
854 /* Poll for TX completions, if applicable */
855 if ( icr & INTEL_IRQ_TXDW )
856 intel_poll_tx ( netdev );
857
858 /* Poll for RX completions, if applicable */
859 if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
860 intel_poll_rx ( netdev );
861
862 /* Report receive overruns */
863 if ( icr & INTEL_IRQ_RXO )
864 netdev_rx_err ( netdev, NULL, -ENOBUFS );
865
866 /* Check link state, if applicable */
867 if ( icr & INTEL_IRQ_LSC )
868 intel_check_link ( netdev );
869
870 /* Check for unexpected interrupts */
871 if ( icr & ~( INTEL_IRQ_TXDW | INTEL_IRQ_TXQE | INTEL_IRQ_LSC |
872 INTEL_IRQ_RXDMT0 | INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) ) {
873 DBGC ( intel, "INTEL %p unexpected ICR %08x\n", intel, icr );
874 /* Report as a TX error */
875 netdev_tx_err ( netdev, NULL, -ENOTSUP );
876 }
877
878 /* Refill RX ring */
879 intel_refill_rx ( intel );
880 }
881
882 /**
883 * Enable or disable interrupts
884 *
885 * @v netdev Network device
886 * @v enable Interrupts should be enabled
887 */
888 static void intel_irq ( struct net_device *netdev, int enable ) {
889 struct intel_nic *intel = netdev->priv;
890 uint32_t mask;
891
892 mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
893 if ( enable ) {
894 writel ( mask, intel->regs + INTEL_IMS );
895 } else {
896 writel ( mask, intel->regs + INTEL_IMC );
897 }
898 }
899
900 /** Intel network device operations */
901 static struct net_device_operations intel_operations = {
902 .open = intel_open,
903 .close = intel_close,
904 .transmit = intel_transmit,
905 .poll = intel_poll,
906 .irq = intel_irq,
907 };
908
909 /******************************************************************************
910 *
911 * PCI interface
912 *
913 ******************************************************************************
914 */
915
916 /**
917 * Probe PCI device
918 *
919 * @v pci PCI device
920 * @ret rc Return status code
921 */
922 static int intel_probe ( struct pci_device *pci ) {
923 struct net_device *netdev;
924 struct intel_nic *intel;
925 int rc;
926
927 /* Allocate and initialise net device */
928 netdev = alloc_etherdev ( sizeof ( *intel ) );
929 if ( ! netdev ) {
930 rc = -ENOMEM;
931 goto err_alloc;
932 }
933 netdev_init ( netdev, &intel_operations );
934 intel = netdev->priv;
935 pci_set_drvdata ( pci, netdev );
936 netdev->dev = &pci->dev;
937 memset ( intel, 0, sizeof ( *intel ) );
938 intel->port = PCI_FUNC ( pci->busdevfn );
939 intel->flags = pci->id->driver_data;
940 intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD,
941 intel_describe_tx );
942 intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD,
943 intel_describe_rx );
944
945 /* Fix up PCI device */
946 adjust_pci_device ( pci );
947
948 /* Map registers */
949 intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
950 if ( ! intel->regs ) {
951 rc = -ENODEV;
952 goto err_ioremap;
953 }
954
955 /* Reset the NIC */
956 if ( ( rc = intel_reset ( intel ) ) != 0 )
957 goto err_reset;
958
959 /* Fetch MAC address */
960 if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
961 goto err_fetch_mac;
962
963 /* Register network device */
964 if ( ( rc = register_netdev ( netdev ) ) != 0 )
965 goto err_register_netdev;
966
967 /* Set initial link state */
968 intel_check_link ( netdev );
969
970 return 0;
971
972 unregister_netdev ( netdev );
973 err_register_netdev:
974 err_fetch_mac:
975 intel_reset ( intel );
976 err_reset:
977 iounmap ( intel->regs );
978 err_ioremap:
979 netdev_nullify ( netdev );
980 netdev_put ( netdev );
981 err_alloc:
982 return rc;
983 }
984
985 /**
986 * Remove PCI device
987 *
988 * @v pci PCI device
989 */
990 static void intel_remove ( struct pci_device *pci ) {
991 struct net_device *netdev = pci_get_drvdata ( pci );
992 struct intel_nic *intel = netdev->priv;
993
994 /* Unregister network device */
995 unregister_netdev ( netdev );
996
997 /* Reset the NIC */
998 intel_reset ( intel );
999
1000 /* Free network device */
1001 iounmap ( intel->regs );
1002 netdev_nullify ( netdev );
1003 netdev_put ( netdev );
1004 }
1005
1006 /** Intel PCI device IDs */
1007 static struct pci_device_id intel_nics[] = {
1008 PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
1009 PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
1010 PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
1011 PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
1012 PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
1013 PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
1014 PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
1015 PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
1016 PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
1017 PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
1018 PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
1019 PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
1020 PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", INTEL_VMWARE ),
1021 PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
1022 PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
1023 PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
1024 PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
1025 PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
1026 PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
1027 PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
1028 PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
1029 PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
1030 PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
1031 PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
1032 PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
1033 PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
1034 PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
1035 PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
1036 PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
1037 PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
1038 PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
1039 PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
1040 PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
1041 PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
1042 PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
1043 PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
1044 PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
1045 PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
1046 PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
1047 PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
1048 PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
1049 PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
1050 PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
1051 PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
1052 PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
1053 PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
1054 PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
1055 PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
1056 PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
1057 PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
1058 PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
1059 PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
1060 PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
1061 PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
1062 PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
1063 PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
1064 PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
1065 PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
1066 PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
1067 PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
1068 PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
1069 PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
1070 PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
1071 PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
1072 PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
1073 PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
1074 PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
1075 PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
1076 PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
1077 PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
1078 PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
1079 PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
1080 PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
1081 PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
1082 PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
1083 PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
1084 PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
1085 PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
1086 PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
1087 PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
1088 PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
1089 PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
1090 PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
1091 PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
1092 PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
1093 PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
1094 PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
1095 PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
1096 PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
1097 PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
1098 PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
1099 PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
1100 PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
1101 PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
1102 PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", INTEL_NO_PHY_RST ),
1103 PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
1104 PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
1105 PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
1106 PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
1107 PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
1108 PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
1109 PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
1110 PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
1111 PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
1112 PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
1113 PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
1114 PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
1115 PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", INTEL_NO_ASDE ),
1116 PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
1117 PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
1118 PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
1119 PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
1120 PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
1121 PCI_ROM ( 0x8086, 0x1539, "i211", "I211", 0 ),
1122 PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", INTEL_NO_PHY_RST ),
1123 PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
1124 PCI_ROM ( 0x8086, 0x1559, "i218v", "I218-V", 0),
1125 PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218-LM", 0),
1126 PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", 0 ),
1127 PCI_ROM ( 0x8086, 0x1570, "i219v", "I219-V", INTEL_NO_PHY_RST ),
1128 PCI_ROM ( 0x8086, 0x157b, "i210-2", "I210", 0 ),
1129 PCI_ROM ( 0x8086, 0x15a0, "i218lm-2", "I218-LM", INTEL_NO_PHY_RST ),
1130 PCI_ROM ( 0x8086, 0x15a1, "i218v-2", "I218-V", 0 ),
1131 PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", INTEL_NO_PHY_RST ),
1132 PCI_ROM ( 0x8086, 0x15a3, "i218v-3", "I218-V", INTEL_NO_PHY_RST ),
1133 PCI_ROM ( 0x8086, 0x15b7, "i219lm-2", "I219-LM (2)", INTEL_NO_PHY_RST ),
1134 PCI_ROM ( 0x8086, 0x15b8, "i219v-2", "I219-V (2)", 0 ),
1135 PCI_ROM ( 0x8086, 0x15d8, "i219v-4", "I219-V (4)", INTEL_NO_PHY_RST ),
1136 PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
1137 PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
1138 };
1139
1140 /** Intel PCI driver */
1141 struct pci_driver intel_driver __pci_driver = {
1142 .ids = intel_nics,
1143 .id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
1144 .probe = intel_probe,
1145 .remove = intel_remove,
1146 };