[intel] Forcibly skip PHY reset on some models
[ipxe.git] / src / drivers / net / intel.h
1 #ifndef _INTEL_H
2 #define _INTEL_H
3
4 /** @file
5 *
6 * Intel 10/100/1000 network card driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 #include <ipxe/nvs.h>
15
16 /** Intel BAR size */
17 #define INTEL_BAR_SIZE ( 128 * 1024 )
18
19 /** A packet descriptor */
20 struct intel_descriptor {
21 /** Buffer address */
22 uint64_t address;
23 /** Length */
24 uint16_t length;
25 /** Flags */
26 uint8_t flags;
27 /** Command */
28 uint8_t command;
29 /** Status */
30 uint32_t status;
31 } __attribute__ (( packed ));
32
33 /** Descriptor type */
34 #define INTEL_DESC_FL_DTYP( dtyp ) ( (dtyp) << 4 )
35 #define INTEL_DESC_FL_DTYP_DATA INTEL_DESC_FL_DTYP ( 0x03 )
36
37 /** Descriptor extension */
38 #define INTEL_DESC_CMD_DEXT 0x20
39
40 /** Report status */
41 #define INTEL_DESC_CMD_RS 0x08
42
43 /** Insert frame checksum (CRC) */
44 #define INTEL_DESC_CMD_IFCS 0x02
45
46 /** End of packet */
47 #define INTEL_DESC_CMD_EOP 0x01
48
49 /** Descriptor done */
50 #define INTEL_DESC_STATUS_DD 0x00000001UL
51
52 /** Receive error */
53 #define INTEL_DESC_STATUS_RXE 0x00000100UL
54
55 /** Payload length */
56 #define INTEL_DESC_STATUS_PAYLEN( len ) ( (len) << 14 )
57
58 /** Device Control Register */
59 #define INTEL_CTRL 0x00000UL
60 #define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
61 #define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
62 #define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
63 #define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
64 #define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
65 #define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
66 #define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
67
68 /** Time to delay for device reset, in milliseconds */
69 #define INTEL_RESET_DELAY_MS 20
70
71 /** Device Status Register */
72 #define INTEL_STATUS 0x00008UL
73 #define INTEL_STATUS_LU 0x00000002UL /**< Link up */
74
75 /** EEPROM Read Register */
76 #define INTEL_EERD 0x00014UL
77 #define INTEL_EERD_START 0x00000001UL /**< Start read */
78 #define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
79 #define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
80 #define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
81 #define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
82 #define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
83
84 /** Maximum time to wait for EEPROM read, in milliseconds */
85 #define INTEL_EEPROM_MAX_WAIT_MS 100
86
87 /** EEPROM word length */
88 #define INTEL_EEPROM_WORD_LEN_LOG2 1
89
90 /** Minimum EEPROM size, in words */
91 #define INTEL_EEPROM_MIN_SIZE_WORDS 64
92
93 /** Offset of MAC address within EEPROM */
94 #define INTEL_EEPROM_MAC 0x00
95
96 /** Interrupt Cause Read Register */
97 #define INTEL_ICR 0x000c0UL
98 #define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
99 #define INTEL_IRQ_TXQE 0x00000002UL /**< Transmit queue empty */
100 #define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
101 #define INTEL_IRQ_RXDMT0 0x00000010UL /**< Receive queue low */
102 #define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
103 #define INTEL_IRQ_RXO 0x00000400UL /**< Receive overrun */
104
105 /** Interrupt Mask Set/Read Register */
106 #define INTEL_IMS 0x000d0UL
107
108 /** Interrupt Mask Clear Register */
109 #define INTEL_IMC 0x000d8UL
110
111 /** Receive Control Register */
112 #define INTEL_RCTL 0x00100UL
113 #define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
114 #define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
115 #define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
116 #define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
117 #define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
118 ( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
119 #define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
120 #define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
121 #define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
122
123 /** Transmit Control Register */
124 #define INTEL_TCTL 0x00400UL
125 #define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
126 #define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
127 #define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
128 #define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
129 #define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
130 #define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
131 #define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
132 #define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
133
134 /** Packet Buffer Allocation */
135 #define INTEL_PBA 0x01000UL
136
137 /** Packet Buffer Size */
138 #define INTEL_PBS 0x01008UL
139
140 /** Receive Descriptor register block */
141 #define INTEL_RD 0x02800UL
142
143 /** Number of receive descriptors
144 *
145 * Minimum value is 8, since the descriptor ring length must be a
146 * multiple of 128.
147 */
148 #define INTEL_NUM_RX_DESC 16
149
150 /** Receive descriptor ring fill level */
151 #define INTEL_RX_FILL 8
152
153 /** Receive buffer length */
154 #define INTEL_RX_MAX_LEN 2048
155
156 /** Transmit Descriptor register block */
157 #define INTEL_TD 0x03800UL
158
159 /** Number of transmit descriptors
160 *
161 * Descriptor ring length must be a multiple of 16. ICH8/9/10
162 * requires a minimum of 16 TX descriptors.
163 */
164 #define INTEL_NUM_TX_DESC 16
165
166 /** Transmit descriptor ring maximum fill level */
167 #define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
168
169 /** Receive/Transmit Descriptor Base Address Low (offset) */
170 #define INTEL_xDBAL 0x00
171
172 /** Receive/Transmit Descriptor Base Address High (offset) */
173 #define INTEL_xDBAH 0x04
174
175 /** Receive/Transmit Descriptor Length (offset) */
176 #define INTEL_xDLEN 0x08
177
178 /** Receive/Transmit Descriptor Head (offset) */
179 #define INTEL_xDH 0x10
180
181 /** Receive/Transmit Descriptor Tail (offset) */
182 #define INTEL_xDT 0x18
183
184 /** Receive/Transmit Descriptor Control (offset) */
185 #define INTEL_xDCTL 0x28
186 #define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
187
188 /** Receive Address Low */
189 #define INTEL_RAL0 0x05400UL
190
191 /** Receive Address High */
192 #define INTEL_RAH0 0x05404UL
193 #define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
194
195 /** Receive address */
196 union intel_receive_address {
197 struct {
198 uint32_t low;
199 uint32_t high;
200 } __attribute__ (( packed )) reg;
201 uint8_t raw[ETH_ALEN];
202 };
203
204 /** An Intel descriptor ring */
205 struct intel_ring {
206 /** Descriptors */
207 struct intel_descriptor *desc;
208 /** Producer index */
209 unsigned int prod;
210 /** Consumer index */
211 unsigned int cons;
212
213 /** Register block */
214 unsigned int reg;
215 /** Length (in bytes) */
216 size_t len;
217
218 /** Populate descriptor
219 *
220 * @v desc Descriptor
221 * @v addr Data buffer address
222 * @v len Length of data
223 */
224 void ( * describe ) ( struct intel_descriptor *desc, physaddr_t addr,
225 size_t len );
226 };
227
228 /**
229 * Initialise descriptor ring
230 *
231 * @v ring Descriptor ring
232 * @v count Number of descriptors
233 * @v reg Descriptor register block
234 * @v describe Method to populate descriptor
235 */
236 static inline __attribute__ (( always_inline)) void
237 intel_init_ring ( struct intel_ring *ring, unsigned int count, unsigned int reg,
238 void ( * describe ) ( struct intel_descriptor *desc,
239 physaddr_t addr, size_t len ) ) {
240
241 ring->len = ( count * sizeof ( ring->desc[0] ) );
242 ring->reg = reg;
243 ring->describe = describe;
244 }
245
246 /** An Intel virtual function mailbox */
247 struct intel_mailbox {
248 /** Mailbox control register */
249 unsigned int ctrl;
250 /** Mailbox memory base */
251 unsigned int mem;
252 };
253
254 /**
255 * Initialise mailbox
256 *
257 * @v mbox Mailbox
258 * @v ctrl Mailbox control register
259 * @v mem Mailbox memory register base
260 */
261 static inline __attribute__ (( always_inline )) void
262 intel_init_mbox ( struct intel_mailbox *mbox, unsigned int ctrl,
263 unsigned int mem ) {
264
265 mbox->ctrl = ctrl;
266 mbox->mem = mem;
267 }
268
269 /** An Intel network card */
270 struct intel_nic {
271 /** Registers */
272 void *regs;
273 /** Port number (for multi-port devices) */
274 unsigned int port;
275 /** Flags */
276 unsigned int flags;
277 /** Forced interrupts */
278 unsigned int force_icr;
279
280 /** EEPROM */
281 struct nvs_device eeprom;
282 /** EEPROM done flag */
283 uint32_t eerd_done;
284 /** EEPROM address shift */
285 unsigned int eerd_addr_shift;
286
287 /** Mailbox */
288 struct intel_mailbox mbox;
289
290 /** Transmit descriptor ring */
291 struct intel_ring tx;
292 /** Receive descriptor ring */
293 struct intel_ring rx;
294 /** Receive I/O buffers */
295 struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
296 };
297
298 /** Driver flags */
299 enum intel_flags {
300 /** PBS/PBA errata workaround required */
301 INTEL_PBS_ERRATA = 0x0001,
302 /** VMware missing interrupt workaround required */
303 INTEL_VMWARE = 0x0002,
304 /** PHY reset is broken */
305 INTEL_NO_PHY_RST = 0x0004,
306 };
307
308 /**
309 * Dump diagnostic information
310 *
311 * @v intel Intel device
312 */
313 static inline void intel_diag ( struct intel_nic *intel ) {
314
315 DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
316 "RX %04x(%02x)/%04x(%02x)\n", intel,
317 ( intel->tx.cons & 0xffff ),
318 readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
319 ( intel->tx.prod & 0xffff ),
320 readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
321 ( intel->rx.cons & 0xffff ),
322 readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
323 ( intel->rx.prod & 0xffff ),
324 readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
325 }
326
327 extern void intel_describe_tx ( struct intel_descriptor *tx,
328 physaddr_t addr, size_t len );
329 extern void intel_describe_tx_adv ( struct intel_descriptor *tx,
330 physaddr_t addr, size_t len );
331 extern void intel_describe_rx ( struct intel_descriptor *rx,
332 physaddr_t addr, size_t len );
333 extern int intel_create_ring ( struct intel_nic *intel,
334 struct intel_ring *ring );
335 extern void intel_destroy_ring ( struct intel_nic *intel,
336 struct intel_ring *ring );
337 extern void intel_refill_rx ( struct intel_nic *intel );
338 extern void intel_empty_rx ( struct intel_nic *intel );
339 extern int intel_transmit ( struct net_device *netdev,
340 struct io_buffer *iobuf );
341 extern void intel_poll_tx ( struct net_device *netdev );
342 extern void intel_poll_rx ( struct net_device *netdev );
343
344 #endif /* _INTEL_H */