[intelxl] Use one admin queue buffer per admin queue descriptor
[ipxe.git] / src / drivers / net / intelxl.h
1 #ifndef _INTELX_H
2 #define _INTELX_H
3
4 /** @file
5 *
6 * Intel 40 Gigabit Ethernet network card driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14
15 struct intelxl_nic;
16
17 /** BAR size */
18 #define INTELXL_BAR_SIZE 0x200000
19
20 /** Alignment
21 *
22 * No data structure requires greater than 128 byte alignment.
23 */
24 #define INTELXL_ALIGN 128
25
26 /******************************************************************************
27 *
28 * Admin queue
29 *
30 ******************************************************************************
31 */
32
33 /** PF Admin Command Queue register block */
34 #define INTELXL_ADMIN_CMD 0x080000
35
36 /** PF Admin Event Queue register block */
37 #define INTELXL_ADMIN_EVT 0x080080
38
39 /** Admin Queue Base Address Low Register (offset) */
40 #define INTELXL_ADMIN_BAL 0x000
41
42 /** Admin Queue Base Address High Register (offset) */
43 #define INTELXL_ADMIN_BAH 0x100
44
45 /** Admin Queue Length Register (offset) */
46 #define INTELXL_ADMIN_LEN 0x200
47 #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
48 #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
49
50 /** Admin Queue Head Register (offset) */
51 #define INTELXL_ADMIN_HEAD 0x300
52
53 /** Admin Queue Tail Register (offset) */
54 #define INTELXL_ADMIN_TAIL 0x400
55
56 /** Admin queue register offsets
57 *
58 * The physical and virtual function register maps have no discernible
59 * relationship.
60 */
61 struct intelxl_admin_offsets {
62 /** Base Address Low Register offset */
63 unsigned int bal;
64 /** Base Address High Register offset */
65 unsigned int bah;
66 /** Length Register offset */
67 unsigned int len;
68 /** Head Register offset */
69 unsigned int head;
70 /** Tail Register offset */
71 unsigned int tail;
72 };
73
74 /** Admin queue data buffer command parameters */
75 struct intelxl_admin_buffer_params {
76 /** Reserved */
77 uint8_t reserved[8];
78 /** Buffer address high */
79 uint32_t high;
80 /** Buffer address low */
81 uint32_t low;
82 } __attribute__ (( packed ));
83
84 /** Admin queue Get Version command */
85 #define INTELXL_ADMIN_VERSION 0x0001
86
87 /** Admin queue version number */
88 struct intelxl_admin_version {
89 /** Major version number */
90 uint16_t major;
91 /** Minor version number */
92 uint16_t minor;
93 } __attribute__ (( packed ));
94
95 /** Admin queue Get Version command parameters */
96 struct intelxl_admin_version_params {
97 /** ROM version */
98 uint32_t rom;
99 /** Firmware build ID */
100 uint32_t build;
101 /** Firmware version */
102 struct intelxl_admin_version firmware;
103 /** API version */
104 struct intelxl_admin_version api;
105 } __attribute__ (( packed ));
106
107 /** Admin queue Driver Version command */
108 #define INTELXL_ADMIN_DRIVER 0x0002
109
110 /** Admin queue Driver Version command parameters */
111 struct intelxl_admin_driver_params {
112 /** Driver version */
113 uint8_t major;
114 /** Minor version */
115 uint8_t minor;
116 /** Build version */
117 uint8_t build;
118 /** Sub-build version */
119 uint8_t sub;
120 /** Reserved */
121 uint8_t reserved[4];
122 /** Data buffer address */
123 uint64_t address;
124 } __attribute__ (( packed ));
125
126 /** Admin queue Driver Version data buffer */
127 struct intelxl_admin_driver_buffer {
128 /** Driver name */
129 char name[32];
130 } __attribute__ (( packed ));
131
132 /** Admin queue Shutdown command */
133 #define INTELXL_ADMIN_SHUTDOWN 0x0003
134
135 /** Admin queue Shutdown command parameters */
136 struct intelxl_admin_shutdown_params {
137 /** Driver unloading */
138 uint8_t unloading;
139 /** Reserved */
140 uint8_t reserved[15];
141 } __attribute__ (( packed ));
142
143 /** Driver is unloading */
144 #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
145
146 /** Admin queue Get Switch Configuration command */
147 #define INTELXL_ADMIN_SWITCH 0x0200
148
149 /** Switching element configuration */
150 struct intelxl_admin_switch_config {
151 /** Switching element type */
152 uint8_t type;
153 /** Revision */
154 uint8_t revision;
155 /** Switching element ID */
156 uint16_t seid;
157 /** Uplink switching element ID */
158 uint16_t uplink;
159 /** Downlink switching element ID */
160 uint16_t downlink;
161 /** Reserved */
162 uint8_t reserved_b[3];
163 /** Connection type */
164 uint8_t connection;
165 /** Reserved */
166 uint8_t reserved_c[2];
167 /** Element specific information */
168 uint16_t info;
169 } __attribute__ (( packed ));
170
171 /** Virtual Station Inferface element type */
172 #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
173
174 /** Admin queue Get Switch Configuration command parameters */
175 struct intelxl_admin_switch_params {
176 /** Starting switching element identifier */
177 uint16_t next;
178 /** Reserved */
179 uint8_t reserved[6];
180 /** Data buffer address */
181 uint64_t address;
182 } __attribute__ (( packed ));
183
184 /** Admin queue Get Switch Configuration data buffer */
185 struct intelxl_admin_switch_buffer {
186 /** Number of switching elements reported */
187 uint16_t count;
188 /** Total number of switching elements */
189 uint16_t total;
190 /** Reserved */
191 uint8_t reserved_a[12];
192 /** Switch configuration */
193 struct intelxl_admin_switch_config cfg;
194 } __attribute__ (( packed ));
195
196 /** Admin queue Get VSI Parameters command */
197 #define INTELXL_ADMIN_VSI 0x0212
198
199 /** Admin queue Get VSI Parameters command parameters */
200 struct intelxl_admin_vsi_params {
201 /** VSI switching element ID */
202 uint16_t vsi;
203 /** Reserved */
204 uint8_t reserved[6];
205 /** Data buffer address */
206 uint64_t address;
207 } __attribute__ (( packed ));
208
209 /** Admin queue Get VSI Parameters data buffer */
210 struct intelxl_admin_vsi_buffer {
211 /** Reserved */
212 uint8_t reserved_a[30];
213 /** Queue numbers */
214 uint16_t queue[16];
215 /** Reserved */
216 uint8_t reserved_b[34];
217 /** Queue set handles for each traffic class */
218 uint16_t qset[8];
219 /** Reserved */
220 uint8_t reserved_c[16];
221 } __attribute__ (( packed ));
222
223 /** Admin queue Set VSI Promiscuous Modes command */
224 #define INTELXL_ADMIN_PROMISC 0x0254
225
226 /** Admin queue Set VSI Promiscuous Modes command parameters */
227 struct intelxl_admin_promisc_params {
228 /** Flags */
229 uint16_t flags;
230 /** Valid flags */
231 uint16_t valid;
232 /** VSI switching element ID */
233 uint16_t vsi;
234 /** Reserved */
235 uint8_t reserved[10];
236 } __attribute__ (( packed ));
237
238 /** Promiscuous unicast mode */
239 #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
240
241 /** Promiscuous multicast mode */
242 #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
243
244 /** Promiscuous broadcast mode */
245 #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
246
247 /** Promiscuous VLAN mode */
248 #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
249
250 /** Admin queue Restart Autonegotiation command */
251 #define INTELXL_ADMIN_AUTONEG 0x0605
252
253 /** Admin queue Restart Autonegotiation command parameters */
254 struct intelxl_admin_autoneg_params {
255 /** Flags */
256 uint8_t flags;
257 /** Reserved */
258 uint8_t reserved[15];
259 } __attribute__ (( packed ));
260
261 /** Restart autonegotiation */
262 #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
263
264 /** Enable link */
265 #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
266
267 /** Admin queue Get Link Status command */
268 #define INTELXL_ADMIN_LINK 0x0607
269
270 /** Admin queue Get Link Status command parameters */
271 struct intelxl_admin_link_params {
272 /** Link status notification */
273 uint8_t notify;
274 /** Reserved */
275 uint8_t reserved_a;
276 /** PHY type */
277 uint8_t phy;
278 /** Link speed */
279 uint8_t speed;
280 /** Link status */
281 uint8_t status;
282 /** Reserved */
283 uint8_t reserved_b[11];
284 } __attribute__ (( packed ));
285
286 /** Notify driver of link status changes */
287 #define INTELXL_ADMIN_LINK_NOTIFY 0x03
288
289 /** Link is up */
290 #define INTELXL_ADMIN_LINK_UP 0x01
291
292 /** Admin queue command parameters */
293 union intelxl_admin_params {
294 /** Additional data buffer command parameters */
295 struct intelxl_admin_buffer_params buffer;
296 /** Get Version command parameters */
297 struct intelxl_admin_version_params version;
298 /** Driver Version command parameters */
299 struct intelxl_admin_driver_params driver;
300 /** Shutdown command parameters */
301 struct intelxl_admin_shutdown_params shutdown;
302 /** Get Switch Configuration command parameters */
303 struct intelxl_admin_switch_params sw;
304 /** Get VSI Parameters command parameters */
305 struct intelxl_admin_vsi_params vsi;
306 /** Set VSI Promiscuous Modes command parameters */
307 struct intelxl_admin_promisc_params promisc;
308 /** Restart Autonegotiation command parameters */
309 struct intelxl_admin_autoneg_params autoneg;
310 /** Get Link Status command parameters */
311 struct intelxl_admin_link_params link;
312 } __attribute__ (( packed ));
313
314 /** Admin queue data buffer */
315 union intelxl_admin_buffer {
316 /** Driver Version data buffer */
317 struct intelxl_admin_driver_buffer driver;
318 /** Get Switch Configuration data buffer */
319 struct intelxl_admin_switch_buffer sw;
320 /** Get VSI Parameters data buffer */
321 struct intelxl_admin_vsi_buffer vsi;
322 /** Alignment padding */
323 uint8_t pad[INTELXL_ALIGN];
324 } __attribute__ (( packed ));
325
326 /** Admin queue descriptor */
327 struct intelxl_admin_descriptor {
328 /** Flags */
329 uint16_t flags;
330 /** Opcode */
331 uint16_t opcode;
332 /** Data length */
333 uint16_t len;
334 /** Return value */
335 uint16_t ret;
336 /** Cookie */
337 uint32_t cookie;
338 /** Reserved */
339 uint32_t reserved;
340 /** Parameters */
341 union intelxl_admin_params params;
342 } __attribute__ (( packed ));
343
344 /** Admin descriptor done */
345 #define INTELXL_ADMIN_FL_DD 0x0001
346
347 /** Admin descriptor contains a completion */
348 #define INTELXL_ADMIN_FL_CMP 0x0002
349
350 /** Admin descriptor completed in error */
351 #define INTELXL_ADMIN_FL_ERR 0x0004
352
353 /** Admin descriptor uses data buffer for command parameters */
354 #define INTELXL_ADMIN_FL_RD 0x0400
355
356 /** Admin descriptor uses data buffer */
357 #define INTELXL_ADMIN_FL_BUF 0x1000
358
359 /** Admin queue */
360 struct intelxl_admin {
361 /** Descriptors */
362 struct intelxl_admin_descriptor *desc;
363 /** Data buffers */
364 union intelxl_admin_buffer *buf;
365 /** Queue index */
366 unsigned int index;
367
368 /** Register block base */
369 unsigned int base;
370 /** Register offsets */
371 const struct intelxl_admin_offsets *regs;
372 };
373
374 /**
375 * Initialise admin queue
376 *
377 * @v admin Admin queue
378 * @v base Register block base
379 * @v regs Register offsets
380 */
381 static inline __attribute__ (( always_inline )) void
382 intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
383 const struct intelxl_admin_offsets *regs ) {
384
385 admin->base = base;
386 admin->regs = regs;
387 }
388
389 /** Number of admin queue descriptors */
390 #define INTELXL_ADMIN_NUM_DESC 4
391
392 /** Maximum time to wait for an admin request to complete */
393 #define INTELXL_ADMIN_MAX_WAIT_MS 100
394
395 /** Admin queue API major version */
396 #define INTELXL_ADMIN_API_MAJOR 1
397
398 /******************************************************************************
399 *
400 * Transmit and receive queue context
401 *
402 ******************************************************************************
403 */
404
405 /** CMLAN Context Data Register */
406 #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
407
408 /** CMLAN Context Control Register */
409 #define INTELXL_PFCM_LANCTXCTL 0x10c300
410 #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
411 ( (x) << 0 ) /**< Queue number */
412 #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
413 ( (x) << 12 ) /**< Sub-line */
414 #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
415 ( (x) << 15 ) /**< Queue type */
416 #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
417 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
418 #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
419 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
420 #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
421 ( (x) << 17 ) /**< Op code */
422 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
423 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
424 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
425 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
426
427 /** CMLAN Context Status Register */
428 #define INTELXL_PFCM_LANCTXSTAT 0x10c380
429 #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
430
431 /** Queue context line */
432 struct intelxl_context_line {
433 /** Raw data */
434 uint32_t raw[4];
435 } __attribute__ (( packed ));
436
437 /** Transmit queue context */
438 struct intelxl_context_tx {
439 /** Head pointer */
440 uint16_t head;
441 /** Flags */
442 uint16_t flags;
443 /** Base address */
444 uint64_t base;
445 /** Reserved */
446 uint8_t reserved_a[8];
447 /** Queue count */
448 uint16_t count;
449 /** Reserved */
450 uint8_t reserved_b[100];
451 /** Queue set */
452 uint16_t qset;
453 /** Reserved */
454 uint8_t reserved_c[4];
455 } __attribute__ (( packed ));
456
457 /** New transmit queue context */
458 #define INTELXL_CTX_TX_FL_NEW 0x4000
459
460 /** Transmit queue base address */
461 #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
462
463 /** Transmit queue count */
464 #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
465
466 /** Transmit queue set */
467 #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
468
469 /** Receive queue context */
470 struct intelxl_context_rx {
471 /** Head pointer */
472 uint16_t head;
473 /** Reserved */
474 uint8_t reserved_a[2];
475 /** Base address and queue count */
476 uint64_t base_count;
477 /** Data buffer length */
478 uint16_t len;
479 /** Flags */
480 uint8_t flags;
481 /** Reserved */
482 uint8_t reserved_b[7];
483 /** Maximum frame size */
484 uint16_t mfs;
485 } __attribute__ (( packed ));
486
487 /** Receive queue base address and queue count */
488 #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
489 ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
490
491 /** Receive queue data buffer length */
492 #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
493
494 /** Strip CRC from received packets */
495 #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
496
497 /** Receive queue maximum frame size */
498 #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
499
500 /** Maximum time to wait for a context operation to complete */
501 #define INTELXL_CTX_MAX_WAIT_MS 100
502
503 /** Time to wait for a queue to become enabled */
504 #define INTELXL_QUEUE_ENABLE_DELAY_US 20
505
506 /** Time to wait for a transmit queue to become pre-disabled */
507 #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
508
509 /** Maximum time to wait for a queue to become disabled */
510 #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
511
512 /******************************************************************************
513 *
514 * Transmit and receive descriptors
515 *
516 ******************************************************************************
517 */
518
519 /** Global Transmit Queue Head register */
520 #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
521
522 /** Global Transmit Pre Queue Disable register */
523 #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
524 #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
525 ( (x) << 0 ) /**< Queue index */
526 #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
527 0x40000000UL /**< Set disable */
528 #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
529 0x80000000UL /**< Clear disable */
530
531 /** Global Transmit Queue register block */
532 #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
533
534 /** Global Receive Queue register block */
535 #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
536
537 /** Queue Enable Register (offset) */
538 #define INTELXL_QXX_ENA 0x0000
539 #define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
540 #define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
541
542 /** Queue Control Register (offset) */
543 #define INTELXL_QXX_CTL 0x4000
544 #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
545 #define INTELXL_QXX_CTL_PFVF_Q_PF \
546 INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
547 #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
548
549 /** Queue Tail Pointer Register (offset) */
550 #define INTELXL_QXX_TAIL 0x8000
551
552 /** Transmit data descriptor */
553 struct intelxl_tx_data_descriptor {
554 /** Buffer address */
555 uint64_t address;
556 /** Flags */
557 uint32_t flags;
558 /** Length */
559 uint32_t len;
560 } __attribute__ (( packed ));
561
562 /** Transmit data descriptor type */
563 #define INTELXL_TX_DATA_DTYP 0x0
564
565 /** Transmit data descriptor end of packet */
566 #define INTELXL_TX_DATA_EOP 0x10
567
568 /** Transmit data descriptor report status */
569 #define INTELXL_TX_DATA_RS 0x20
570
571 /** Transmit data descriptor pretty please
572 *
573 * This bit is completely missing from older versions of the XL710
574 * datasheet. Later versions describe it innocuously as "reserved,
575 * must be 1". Without this bit, everything will appear to work (up
576 * to and including the port "transmit good octets" counter), but no
577 * packet will actually be sent.
578 */
579 #define INTELXL_TX_DATA_JFDI 0x40
580
581 /** Transmit data descriptor length */
582 #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
583
584 /** Transmit writeback descriptor */
585 struct intelxl_tx_writeback_descriptor {
586 /** Reserved */
587 uint8_t reserved_a[8];
588 /** Flags */
589 uint8_t flags;
590 /** Reserved */
591 uint8_t reserved_b[7];
592 } __attribute__ (( packed ));
593
594 /** Transmit writeback descriptor complete */
595 #define INTELXL_TX_WB_FL_DD 0x01
596
597 /** Receive data descriptor */
598 struct intelxl_rx_data_descriptor {
599 /** Buffer address */
600 uint64_t address;
601 /** Flags */
602 uint32_t flags;
603 /** Reserved */
604 uint8_t reserved[4];
605 } __attribute__ (( packed ));
606
607 /** Receive writeback descriptor */
608 struct intelxl_rx_writeback_descriptor {
609 /** Reserved */
610 uint8_t reserved_a[2];
611 /** VLAN tag */
612 uint16_t vlan;
613 /** Reserved */
614 uint8_t reserved_b[4];
615 /** Flags */
616 uint32_t flags;
617 /** Length */
618 uint32_t len;
619 } __attribute__ (( packed ));
620
621 /** Receive writeback descriptor complete */
622 #define INTELXL_RX_WB_FL_DD 0x00000001UL
623
624 /** Receive writeback descriptor VLAN tag present */
625 #define INTELXL_RX_WB_FL_VLAN 0x00000004UL
626
627 /** Receive writeback descriptor error */
628 #define INTELXL_RX_WB_FL_RXE 0x00080000UL
629
630 /** Receive writeback descriptor length */
631 #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
632
633 /** Packet descriptor */
634 union intelxl_descriptor {
635 /** Transmit data descriptor */
636 struct intelxl_tx_data_descriptor tx;
637 /** Transmit writeback descriptor */
638 struct intelxl_tx_writeback_descriptor tx_wb;
639 /** Receive data descriptor */
640 struct intelxl_rx_data_descriptor rx;
641 /** Receive writeback descriptor */
642 struct intelxl_rx_writeback_descriptor rx_wb;
643 };
644
645 /** Descriptor ring */
646 struct intelxl_ring {
647 /** Descriptors */
648 union intelxl_descriptor *desc;
649 /** Producer index */
650 unsigned int prod;
651 /** Consumer index */
652 unsigned int cons;
653
654 /** Register block */
655 unsigned int reg;
656 /** Length (in bytes) */
657 size_t len;
658 /** Program queue context
659 *
660 * @v intelxl Intel device
661 * @v address Descriptor ring base address
662 */
663 int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
664 };
665
666 /**
667 * Initialise descriptor ring
668 *
669 * @v ring Descriptor ring
670 * @v count Number of descriptors
671 * @v context Method to program queue context
672 */
673 static inline __attribute__ (( always_inline)) void
674 intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count,
675 int ( * context ) ( struct intelxl_nic *intelxl,
676 physaddr_t address ) ) {
677
678 ring->len = ( count * sizeof ( ring->desc[0] ) );
679 ring->context = context;
680 }
681
682 /** Number of transmit descriptors */
683 #define INTELXL_TX_NUM_DESC 16
684
685 /** Transmit descriptor ring maximum fill level */
686 #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
687
688 /** Number of receive descriptors
689 *
690 * In PXE mode (i.e. able to post single receive descriptors), 8
691 * descriptors is the only permitted value covering all possible
692 * numbers of PFs.
693 */
694 #define INTELXL_RX_NUM_DESC 8
695
696 /** Receive descriptor ring fill level */
697 #define INTELXL_RX_FILL ( INTELXL_RX_NUM_DESC - 1 )
698
699 /******************************************************************************
700 *
701 * Top level
702 *
703 ******************************************************************************
704 */
705
706 /** PF Interrupt Zero Dynamic Control Register */
707 #define INTELXL_PFINT_DYN_CTL0 0x038480
708 #define INTELXL_PFINT_DYN_CTL0_INTENA 0x00000001UL /**< Enable */
709 #define INTELXL_PFINT_DYN_CTL0_CLEARPBA 0x00000002UL /**< Acknowledge */
710 #define INTELXL_PFINT_DYN_CTL0_INTENA_MASK 0x80000000UL /**< Ignore enable */
711
712 /** PF Interrupt Zero Linked List Register */
713 #define INTELXL_PFINT_LNKLST0 0x038500
714 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
715 ( (x) << 0 ) /**< Queue index */
716 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
717 INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
718 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
719 ( (x) << 11 ) /**< Queue type */
720 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
721 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
722 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
723 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
724
725 /** PF Interrupt Zero Cause Enablement Register */
726 #define INTELXL_PFINT_ICR0_ENA 0x038800
727 #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
728
729 /** Receive Queue Interrupt Cause Control Register */
730 #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
731 #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
732 #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
733 INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
734 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
735 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
736 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
737 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
738 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
739 #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
740
741 /** Transmit Queue Interrupt Cause Control Register */
742 #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
743 #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
744 #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
745 INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
746 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
747 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
748 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
749 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
750 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
751 #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
752
753 /** PF Control Register */
754 #define INTELXL_PFGEN_CTRL 0x092400
755 #define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
756
757 /** Time to delay for device reset, in milliseconds */
758 #define INTELXL_RESET_DELAY_MS 100
759
760 /** PF Queue Allocation Register */
761 #define INTELXL_PFLAN_QALLOC 0x1c0400
762 #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
763 ( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
764 #define INTELXL_PFLAN_QALLOC_LASTQ(x) \
765 ( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
766
767 /** PF LAN Port Number Register */
768 #define INTELXL_PFGEN_PORTNUM 0x1c0480
769 #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
770 ( ( (x) >> 0 ) & 0x3 ) /**< Port number */
771
772 /** Port MAC Address Low Register */
773 #define INTELXL_PRTGL_SAL 0x1e2120
774
775 /** Port MAC Address High Register */
776 #define INTELXL_PRTGL_SAH 0x1e2140
777 #define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
778 #define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
779
780 /** Receive address */
781 union intelxl_receive_address {
782 struct {
783 uint32_t low;
784 uint32_t high;
785 } __attribute__ (( packed )) reg;
786 uint8_t raw[ETH_ALEN];
787 };
788
789 /** An Intel 40Gigabit network card */
790 struct intelxl_nic {
791 /** Registers */
792 void *regs;
793 /** Maximum frame size */
794 size_t mfs;
795
796 /** Physical function number */
797 unsigned int pf;
798 /** Absolute queue number base */
799 unsigned int base;
800 /** Port number */
801 unsigned int port;
802 /** Queue number */
803 unsigned int queue;
804 /** Virtual Station Interface switching element ID */
805 unsigned int vsi;
806 /** Queue set handle */
807 unsigned int qset;
808
809 /** Admin command queue */
810 struct intelxl_admin command;
811 /** Admin event queue */
812 struct intelxl_admin event;
813
814 /** Transmit descriptor ring */
815 struct intelxl_ring tx;
816 /** Receive descriptor ring */
817 struct intelxl_ring rx;
818 /** Receive I/O buffers */
819 struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
820 };
821
822 #endif /* _INTELXL_H */