[intelxl] Choose to operate in non-PXE mode
[ipxe.git] / src / drivers / net / intelxl.h
1 #ifndef _INTELX_H
2 #define _INTELX_H
3
4 /** @file
5 *
6 * Intel 40 Gigabit Ethernet network card driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 #include <ipxe/pcimsix.h>
15
16 struct intelxl_nic;
17
18 /** BAR size */
19 #define INTELXL_BAR_SIZE 0x200000
20
21 /** Alignment
22 *
23 * No data structure requires greater than 128 byte alignment.
24 */
25 #define INTELXL_ALIGN 128
26
27 /******************************************************************************
28 *
29 * Admin queue
30 *
31 ******************************************************************************
32 */
33
34 /** PF Admin Command Queue register block */
35 #define INTELXL_ADMIN_CMD 0x080000
36
37 /** PF Admin Event Queue register block */
38 #define INTELXL_ADMIN_EVT 0x080080
39
40 /** Admin Queue Base Address Low Register (offset) */
41 #define INTELXL_ADMIN_BAL 0x000
42
43 /** Admin Queue Base Address High Register (offset) */
44 #define INTELXL_ADMIN_BAH 0x100
45
46 /** Admin Queue Length Register (offset) */
47 #define INTELXL_ADMIN_LEN 0x200
48 #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
49 #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
50
51 /** Admin Queue Head Register (offset) */
52 #define INTELXL_ADMIN_HEAD 0x300
53
54 /** Admin Queue Tail Register (offset) */
55 #define INTELXL_ADMIN_TAIL 0x400
56
57 /** Admin queue register offsets
58 *
59 * The physical and virtual function register maps have no discernible
60 * relationship.
61 */
62 struct intelxl_admin_offsets {
63 /** Base Address Low Register offset */
64 unsigned int bal;
65 /** Base Address High Register offset */
66 unsigned int bah;
67 /** Length Register offset */
68 unsigned int len;
69 /** Head Register offset */
70 unsigned int head;
71 /** Tail Register offset */
72 unsigned int tail;
73 };
74
75 /** Admin queue data buffer command parameters */
76 struct intelxl_admin_buffer_params {
77 /** Reserved */
78 uint8_t reserved[8];
79 /** Buffer address high */
80 uint32_t high;
81 /** Buffer address low */
82 uint32_t low;
83 } __attribute__ (( packed ));
84
85 /** Admin queue Get Version command */
86 #define INTELXL_ADMIN_VERSION 0x0001
87
88 /** Admin queue version number */
89 struct intelxl_admin_version {
90 /** Major version number */
91 uint16_t major;
92 /** Minor version number */
93 uint16_t minor;
94 } __attribute__ (( packed ));
95
96 /** Admin queue Get Version command parameters */
97 struct intelxl_admin_version_params {
98 /** ROM version */
99 uint32_t rom;
100 /** Firmware build ID */
101 uint32_t build;
102 /** Firmware version */
103 struct intelxl_admin_version firmware;
104 /** API version */
105 struct intelxl_admin_version api;
106 } __attribute__ (( packed ));
107
108 /** Admin queue Driver Version command */
109 #define INTELXL_ADMIN_DRIVER 0x0002
110
111 /** Admin queue Driver Version command parameters */
112 struct intelxl_admin_driver_params {
113 /** Driver version */
114 uint8_t major;
115 /** Minor version */
116 uint8_t minor;
117 /** Build version */
118 uint8_t build;
119 /** Sub-build version */
120 uint8_t sub;
121 /** Reserved */
122 uint8_t reserved[4];
123 /** Data buffer address */
124 uint64_t address;
125 } __attribute__ (( packed ));
126
127 /** Admin queue Driver Version data buffer */
128 struct intelxl_admin_driver_buffer {
129 /** Driver name */
130 char name[32];
131 } __attribute__ (( packed ));
132
133 /** Admin queue Shutdown command */
134 #define INTELXL_ADMIN_SHUTDOWN 0x0003
135
136 /** Admin queue Shutdown command parameters */
137 struct intelxl_admin_shutdown_params {
138 /** Driver unloading */
139 uint8_t unloading;
140 /** Reserved */
141 uint8_t reserved[15];
142 } __attribute__ (( packed ));
143
144 /** Driver is unloading */
145 #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
146
147 /** Admin queue Clear PXE Mode command */
148 #define INTELXL_ADMIN_CLEAR_PXE 0x0110
149
150 /** Admin queue Clear PXE Mode command parameters */
151 struct intelxl_admin_clear_pxe_params {
152 /** Magic value */
153 uint8_t magic;
154 /** Reserved */
155 uint8_t reserved[15];
156 } __attribute__ (( packed ));
157
158 /** Clear PXE Mode magic value */
159 #define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02
160
161 /** Admin queue Get Switch Configuration command */
162 #define INTELXL_ADMIN_SWITCH 0x0200
163
164 /** Switching element configuration */
165 struct intelxl_admin_switch_config {
166 /** Switching element type */
167 uint8_t type;
168 /** Revision */
169 uint8_t revision;
170 /** Switching element ID */
171 uint16_t seid;
172 /** Uplink switching element ID */
173 uint16_t uplink;
174 /** Downlink switching element ID */
175 uint16_t downlink;
176 /** Reserved */
177 uint8_t reserved_b[3];
178 /** Connection type */
179 uint8_t connection;
180 /** Reserved */
181 uint8_t reserved_c[2];
182 /** Element specific information */
183 uint16_t info;
184 } __attribute__ (( packed ));
185
186 /** Virtual Station Inferface element type */
187 #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
188
189 /** Admin queue Get Switch Configuration command parameters */
190 struct intelxl_admin_switch_params {
191 /** Starting switching element identifier */
192 uint16_t next;
193 /** Reserved */
194 uint8_t reserved[6];
195 /** Data buffer address */
196 uint64_t address;
197 } __attribute__ (( packed ));
198
199 /** Admin queue Get Switch Configuration data buffer */
200 struct intelxl_admin_switch_buffer {
201 /** Number of switching elements reported */
202 uint16_t count;
203 /** Total number of switching elements */
204 uint16_t total;
205 /** Reserved */
206 uint8_t reserved_a[12];
207 /** Switch configuration */
208 struct intelxl_admin_switch_config cfg;
209 } __attribute__ (( packed ));
210
211 /** Admin queue Get VSI Parameters command */
212 #define INTELXL_ADMIN_VSI 0x0212
213
214 /** Admin queue Get VSI Parameters command parameters */
215 struct intelxl_admin_vsi_params {
216 /** VSI switching element ID */
217 uint16_t vsi;
218 /** Reserved */
219 uint8_t reserved[6];
220 /** Data buffer address */
221 uint64_t address;
222 } __attribute__ (( packed ));
223
224 /** Admin queue Get VSI Parameters data buffer */
225 struct intelxl_admin_vsi_buffer {
226 /** Reserved */
227 uint8_t reserved_a[30];
228 /** Queue numbers */
229 uint16_t queue[16];
230 /** Reserved */
231 uint8_t reserved_b[34];
232 /** Queue set handles for each traffic class */
233 uint16_t qset[8];
234 /** Reserved */
235 uint8_t reserved_c[16];
236 } __attribute__ (( packed ));
237
238 /** Admin queue Set VSI Promiscuous Modes command */
239 #define INTELXL_ADMIN_PROMISC 0x0254
240
241 /** Admin queue Set VSI Promiscuous Modes command parameters */
242 struct intelxl_admin_promisc_params {
243 /** Flags */
244 uint16_t flags;
245 /** Valid flags */
246 uint16_t valid;
247 /** VSI switching element ID */
248 uint16_t vsi;
249 /** Reserved */
250 uint8_t reserved[10];
251 } __attribute__ (( packed ));
252
253 /** Promiscuous unicast mode */
254 #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
255
256 /** Promiscuous multicast mode */
257 #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
258
259 /** Promiscuous broadcast mode */
260 #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
261
262 /** Promiscuous VLAN mode */
263 #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
264
265 /** Admin queue Restart Autonegotiation command */
266 #define INTELXL_ADMIN_AUTONEG 0x0605
267
268 /** Admin queue Restart Autonegotiation command parameters */
269 struct intelxl_admin_autoneg_params {
270 /** Flags */
271 uint8_t flags;
272 /** Reserved */
273 uint8_t reserved[15];
274 } __attribute__ (( packed ));
275
276 /** Restart autonegotiation */
277 #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
278
279 /** Enable link */
280 #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
281
282 /** Admin queue Get Link Status command */
283 #define INTELXL_ADMIN_LINK 0x0607
284
285 /** Admin queue Get Link Status command parameters */
286 struct intelxl_admin_link_params {
287 /** Link status notification */
288 uint8_t notify;
289 /** Reserved */
290 uint8_t reserved_a;
291 /** PHY type */
292 uint8_t phy;
293 /** Link speed */
294 uint8_t speed;
295 /** Link status */
296 uint8_t status;
297 /** Reserved */
298 uint8_t reserved_b[11];
299 } __attribute__ (( packed ));
300
301 /** Notify driver of link status changes */
302 #define INTELXL_ADMIN_LINK_NOTIFY 0x03
303
304 /** Link is up */
305 #define INTELXL_ADMIN_LINK_UP 0x01
306
307 /** Admin queue Send Message to PF command */
308 #define INTELXL_ADMIN_SEND_TO_PF 0x0801
309
310 /** Admin queue Send Message to VF command */
311 #define INTELXL_ADMIN_SEND_TO_VF 0x0802
312
313 /** Admin queue command parameters */
314 union intelxl_admin_params {
315 /** Additional data buffer command parameters */
316 struct intelxl_admin_buffer_params buffer;
317 /** Get Version command parameters */
318 struct intelxl_admin_version_params version;
319 /** Driver Version command parameters */
320 struct intelxl_admin_driver_params driver;
321 /** Shutdown command parameters */
322 struct intelxl_admin_shutdown_params shutdown;
323 /** Clear PXE Mode command parameters */
324 struct intelxl_admin_clear_pxe_params pxe;
325 /** Get Switch Configuration command parameters */
326 struct intelxl_admin_switch_params sw;
327 /** Get VSI Parameters command parameters */
328 struct intelxl_admin_vsi_params vsi;
329 /** Set VSI Promiscuous Modes command parameters */
330 struct intelxl_admin_promisc_params promisc;
331 /** Restart Autonegotiation command parameters */
332 struct intelxl_admin_autoneg_params autoneg;
333 /** Get Link Status command parameters */
334 struct intelxl_admin_link_params link;
335 } __attribute__ (( packed ));
336
337 /** Admin queue data buffer */
338 union intelxl_admin_buffer {
339 /** Driver Version data buffer */
340 struct intelxl_admin_driver_buffer driver;
341 /** Get Switch Configuration data buffer */
342 struct intelxl_admin_switch_buffer sw;
343 /** Get VSI Parameters data buffer */
344 struct intelxl_admin_vsi_buffer vsi;
345 /** Alignment padding */
346 uint8_t pad[INTELXL_ALIGN];
347 } __attribute__ (( packed ));
348
349 /** Admin queue descriptor */
350 struct intelxl_admin_descriptor {
351 /** Flags */
352 uint16_t flags;
353 /** Opcode */
354 uint16_t opcode;
355 /** Data length */
356 uint16_t len;
357 /** Return value */
358 uint16_t ret;
359 /** Opaque cookie / VF opcode */
360 union {
361 /** Cookie */
362 uint32_t cookie;
363 /** VF opcode */
364 uint32_t vopcode;
365 };
366 /** VF return value */
367 int32_t vret;
368 /** Parameters */
369 union intelxl_admin_params params;
370 } __attribute__ (( packed ));
371
372 /** Admin descriptor done */
373 #define INTELXL_ADMIN_FL_DD 0x0001
374
375 /** Admin descriptor contains a completion */
376 #define INTELXL_ADMIN_FL_CMP 0x0002
377
378 /** Admin descriptor completed in error */
379 #define INTELXL_ADMIN_FL_ERR 0x0004
380
381 /** Admin descriptor uses data buffer for command parameters */
382 #define INTELXL_ADMIN_FL_RD 0x0400
383
384 /** Admin descriptor uses data buffer */
385 #define INTELXL_ADMIN_FL_BUF 0x1000
386
387 /** Admin queue */
388 struct intelxl_admin {
389 /** Descriptors */
390 struct intelxl_admin_descriptor *desc;
391 /** Data buffers */
392 union intelxl_admin_buffer *buf;
393 /** Queue index */
394 unsigned int index;
395
396 /** Register block base */
397 unsigned int base;
398 /** Register offsets */
399 const struct intelxl_admin_offsets *regs;
400 };
401
402 /**
403 * Initialise admin queue
404 *
405 * @v admin Admin queue
406 * @v base Register block base
407 * @v regs Register offsets
408 */
409 static inline __attribute__ (( always_inline )) void
410 intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
411 const struct intelxl_admin_offsets *regs ) {
412
413 admin->base = base;
414 admin->regs = regs;
415 }
416
417 /** Number of admin queue descriptors */
418 #define INTELXL_ADMIN_NUM_DESC 4
419
420 /** Maximum time to wait for an admin request to complete */
421 #define INTELXL_ADMIN_MAX_WAIT_MS 100
422
423 /** Admin queue API major version */
424 #define INTELXL_ADMIN_API_MAJOR 1
425
426 /******************************************************************************
427 *
428 * Transmit and receive queue context
429 *
430 ******************************************************************************
431 */
432
433 /** CMLAN Context Data Register */
434 #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
435
436 /** CMLAN Context Control Register */
437 #define INTELXL_PFCM_LANCTXCTL 0x10c300
438 #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
439 ( (x) << 0 ) /**< Queue number */
440 #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
441 ( (x) << 12 ) /**< Sub-line */
442 #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
443 ( (x) << 15 ) /**< Queue type */
444 #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
445 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
446 #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
447 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
448 #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
449 ( (x) << 17 ) /**< Op code */
450 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
451 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
452 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
453 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
454
455 /** CMLAN Context Status Register */
456 #define INTELXL_PFCM_LANCTXSTAT 0x10c380
457 #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
458
459 /** Queue context line */
460 struct intelxl_context_line {
461 /** Raw data */
462 uint32_t raw[4];
463 } __attribute__ (( packed ));
464
465 /** Transmit queue context */
466 struct intelxl_context_tx {
467 /** Head pointer */
468 uint16_t head;
469 /** Flags */
470 uint16_t flags;
471 /** Base address */
472 uint64_t base;
473 /** Reserved */
474 uint8_t reserved_a[8];
475 /** Queue count */
476 uint16_t count;
477 /** Reserved */
478 uint8_t reserved_b[100];
479 /** Queue set */
480 uint16_t qset;
481 /** Reserved */
482 uint8_t reserved_c[4];
483 } __attribute__ (( packed ));
484
485 /** New transmit queue context */
486 #define INTELXL_CTX_TX_FL_NEW 0x4000
487
488 /** Transmit queue base address */
489 #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
490
491 /** Transmit queue count */
492 #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
493
494 /** Transmit queue set */
495 #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
496
497 /** Receive queue context */
498 struct intelxl_context_rx {
499 /** Head pointer */
500 uint16_t head;
501 /** Reserved */
502 uint8_t reserved_a[2];
503 /** Base address and queue count */
504 uint64_t base_count;
505 /** Data buffer length */
506 uint16_t len;
507 /** Flags */
508 uint8_t flags;
509 /** Reserved */
510 uint8_t reserved_b[7];
511 /** Maximum frame size */
512 uint16_t mfs;
513 } __attribute__ (( packed ));
514
515 /** Receive queue base address and queue count */
516 #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
517 ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
518
519 /** Receive queue data buffer length */
520 #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
521
522 /** Use 32-byte receive descriptors */
523 #define INTELXL_CTX_RX_FL_DSIZE 0x10
524
525 /** Strip CRC from received packets */
526 #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
527
528 /** Receive queue maximum frame size */
529 #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
530
531 /** Maximum time to wait for a context operation to complete */
532 #define INTELXL_CTX_MAX_WAIT_MS 100
533
534 /** Time to wait for a queue to become enabled */
535 #define INTELXL_QUEUE_ENABLE_DELAY_US 20
536
537 /** Time to wait for a transmit queue to become pre-disabled */
538 #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
539
540 /** Maximum time to wait for a queue to become disabled */
541 #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
542
543 /******************************************************************************
544 *
545 * Transmit and receive descriptors
546 *
547 ******************************************************************************
548 */
549
550 /** Global Transmit Queue Head register */
551 #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
552
553 /** Global Transmit Pre Queue Disable register */
554 #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
555 #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
556 ( (x) << 0 ) /**< Queue index */
557 #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
558 0x40000000UL /**< Set disable */
559 #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
560 0x80000000UL /**< Clear disable */
561
562 /** Global Transmit Queue register block */
563 #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
564
565 /** Global Receive Queue register block */
566 #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
567
568 /** Queue Enable Register (offset) */
569 #define INTELXL_QXX_ENA 0x0000
570 #define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
571 #define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
572
573 /** Queue Control Register (offset) */
574 #define INTELXL_QXX_CTL 0x4000
575 #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
576 #define INTELXL_QXX_CTL_PFVF_Q_PF \
577 INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
578 #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
579
580 /** Queue Tail Pointer Register (offset) */
581 #define INTELXL_QXX_TAIL 0x8000
582
583 /** Global RLAN Control 0 register */
584 #define INTELXL_GLLAN_RCTL_0 0x12a500
585 #define INTELXL_GLLAN_RCTL_0_PXE_MODE 0x00000001UL /**< PXE mode */
586
587 /** Transmit data descriptor */
588 struct intelxl_tx_data_descriptor {
589 /** Buffer address */
590 uint64_t address;
591 /** Flags */
592 uint32_t flags;
593 /** Length */
594 uint32_t len;
595 } __attribute__ (( packed ));
596
597 /** Transmit data descriptor type */
598 #define INTELXL_TX_DATA_DTYP 0x0
599
600 /** Transmit data descriptor end of packet */
601 #define INTELXL_TX_DATA_EOP 0x10
602
603 /** Transmit data descriptor report status */
604 #define INTELXL_TX_DATA_RS 0x20
605
606 /** Transmit data descriptor pretty please
607 *
608 * This bit is completely missing from older versions of the XL710
609 * datasheet. Later versions describe it innocuously as "reserved,
610 * must be 1". Without this bit, everything will appear to work (up
611 * to and including the port "transmit good octets" counter), but no
612 * packet will actually be sent.
613 */
614 #define INTELXL_TX_DATA_JFDI 0x40
615
616 /** Transmit data descriptor length */
617 #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
618
619 /** Transmit writeback descriptor */
620 struct intelxl_tx_writeback_descriptor {
621 /** Reserved */
622 uint8_t reserved_a[8];
623 /** Flags */
624 uint8_t flags;
625 /** Reserved */
626 uint8_t reserved_b[7];
627 } __attribute__ (( packed ));
628
629 /** Transmit writeback descriptor complete */
630 #define INTELXL_TX_WB_FL_DD 0x01
631
632 /** Transmit descriptor */
633 union intelxl_tx_descriptor {
634 /** Transmit data descriptor */
635 struct intelxl_tx_data_descriptor data;
636 /** Transmit writeback descriptor */
637 struct intelxl_tx_writeback_descriptor wb;
638 };
639
640 /** Receive data descriptor */
641 struct intelxl_rx_data_descriptor {
642 /** Buffer address */
643 uint64_t address;
644 /** Flags */
645 uint32_t flags;
646 /** Reserved */
647 uint8_t reserved[20];
648 } __attribute__ (( packed ));
649
650 /** Receive writeback descriptor */
651 struct intelxl_rx_writeback_descriptor {
652 /** Reserved */
653 uint8_t reserved_a[2];
654 /** VLAN tag */
655 uint16_t vlan;
656 /** Reserved */
657 uint8_t reserved_b[4];
658 /** Flags */
659 uint32_t flags;
660 /** Length */
661 uint32_t len;
662 /** Reserved */
663 uint8_t reserved_c[16];
664 } __attribute__ (( packed ));
665
666 /** Receive writeback descriptor complete */
667 #define INTELXL_RX_WB_FL_DD 0x00000001UL
668
669 /** Receive writeback descriptor VLAN tag present */
670 #define INTELXL_RX_WB_FL_VLAN 0x00000004UL
671
672 /** Receive writeback descriptor error */
673 #define INTELXL_RX_WB_FL_RXE 0x00080000UL
674
675 /** Receive writeback descriptor length */
676 #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
677
678 /** Packet descriptor */
679 union intelxl_rx_descriptor {
680 /** Receive data descriptor */
681 struct intelxl_rx_data_descriptor data;
682 /** Receive writeback descriptor */
683 struct intelxl_rx_writeback_descriptor wb;
684 };
685
686 /** Descriptor ring */
687 struct intelxl_ring {
688 /** Descriptors */
689 union {
690 /** Transmit descriptors */
691 union intelxl_tx_descriptor *tx;
692 /** Receive descriptors */
693 union intelxl_rx_descriptor *rx;
694 /** Raw data */
695 void *raw;
696 } desc;
697 /** Producer index */
698 unsigned int prod;
699 /** Consumer index */
700 unsigned int cons;
701
702 /** Register block */
703 unsigned int reg;
704 /** Tail register */
705 unsigned int tail;
706 /** Length (in bytes) */
707 size_t len;
708 /** Program queue context
709 *
710 * @v intelxl Intel device
711 * @v address Descriptor ring base address
712 */
713 int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
714 };
715
716 /**
717 * Initialise descriptor ring
718 *
719 * @v ring Descriptor ring
720 * @v count Number of descriptors
721 * @v len Length of a single descriptor
722 * @v context Method to program queue context
723 */
724 static inline __attribute__ (( always_inline)) void
725 intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count, size_t len,
726 int ( * context ) ( struct intelxl_nic *intelxl,
727 physaddr_t address ) ) {
728
729 ring->len = ( count * len );
730 ring->context = context;
731 }
732
733 /** Number of transmit descriptors
734 *
735 * Chosen to exceed the receive ring fill level, in order to avoid
736 * running out of transmit descriptors when sending TCP ACKs.
737 */
738 #define INTELXL_TX_NUM_DESC 64
739
740 /** Transmit descriptor ring maximum fill level */
741 #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
742
743 /** Number of receive descriptors
744 *
745 * Must be a multiple of 32.
746 */
747 #define INTELXL_RX_NUM_DESC 32
748
749 /** Receive descriptor ring fill level
750 *
751 * Must be a multiple of 8 and greater than 8.
752 */
753 #define INTELXL_RX_FILL 16
754
755 /******************************************************************************
756 *
757 * Top level
758 *
759 ******************************************************************************
760 */
761
762 /** PF Interrupt Zero Dynamic Control Register */
763 #define INTELXL_PFINT_DYN_CTL0 0x038480
764 #define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL /**< Enable */
765 #define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL /**< Acknowledge */
766 #define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL /**< Ignore enable */
767
768 /** PF Interrupt Zero Linked List Register */
769 #define INTELXL_PFINT_LNKLST0 0x038500
770 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
771 ( (x) << 0 ) /**< Queue index */
772 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
773 INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
774 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
775 ( (x) << 11 ) /**< Queue type */
776 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
777 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
778 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
779 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
780
781 /** PF Interrupt Zero Cause Enablement Register */
782 #define INTELXL_PFINT_ICR0_ENA 0x038800
783 #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
784
785 /** Receive Queue Interrupt Cause Control Register */
786 #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
787 #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
788 #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
789 INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
790 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
791 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
792 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
793 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
794 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
795 #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
796
797 /** Transmit Queue Interrupt Cause Control Register */
798 #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
799 #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
800 #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
801 INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
802 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
803 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
804 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
805 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
806 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
807 #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
808
809 /** PF Control Register */
810 #define INTELXL_PFGEN_CTRL 0x092400
811 #define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
812
813 /** Time to delay for device reset, in milliseconds */
814 #define INTELXL_RESET_DELAY_MS 100
815
816 /** PF Queue Allocation Register */
817 #define INTELXL_PFLAN_QALLOC 0x1c0400
818 #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
819 ( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
820 #define INTELXL_PFLAN_QALLOC_LASTQ(x) \
821 ( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
822
823 /** PF LAN Port Number Register */
824 #define INTELXL_PFGEN_PORTNUM 0x1c0480
825 #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
826 ( ( (x) >> 0 ) & 0x3 ) /**< Port number */
827
828 /** Port MAC Address Low Register */
829 #define INTELXL_PRTGL_SAL 0x1e2120
830
831 /** Port MAC Address High Register */
832 #define INTELXL_PRTGL_SAH 0x1e2140
833 #define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
834 #define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
835
836 /** Receive address */
837 union intelxl_receive_address {
838 struct {
839 uint32_t low;
840 uint32_t high;
841 } __attribute__ (( packed )) reg;
842 uint8_t raw[ETH_ALEN];
843 };
844
845 /** An Intel 40Gigabit network card */
846 struct intelxl_nic {
847 /** Registers */
848 void *regs;
849 /** Maximum frame size */
850 size_t mfs;
851
852 /** Physical function number */
853 unsigned int pf;
854 /** Absolute queue number base */
855 unsigned int base;
856 /** Port number */
857 unsigned int port;
858 /** Queue number */
859 unsigned int queue;
860 /** Virtual Station Interface switching element ID */
861 unsigned int vsi;
862 /** Queue set handle */
863 unsigned int qset;
864 /** Interrupt control register */
865 unsigned int intr;
866 /** MSI-X capability */
867 struct pci_msix msix;
868 /** MSI-X dummy interrupt target */
869 uint32_t msg;
870
871 /** Admin command queue */
872 struct intelxl_admin command;
873 /** Admin event queue */
874 struct intelxl_admin event;
875
876 /** Transmit descriptor ring */
877 struct intelxl_ring tx;
878 /** Receive descriptor ring */
879 struct intelxl_ring rx;
880 /** Receive I/O buffers */
881 struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
882 };
883
884 extern int intelxl_msix_enable ( struct intelxl_nic *intelxl,
885 struct pci_device *pci );
886 extern void intelxl_msix_disable ( struct intelxl_nic *intelxl,
887 struct pci_device *pci );
888 extern struct intelxl_admin_descriptor *
889 intelxl_admin_command_descriptor ( struct intelxl_nic *intelxl );
890 extern union intelxl_admin_buffer *
891 intelxl_admin_command_buffer ( struct intelxl_nic *intelxl );
892 extern int intelxl_admin_command ( struct intelxl_nic *intelxl );
893 extern void intelxl_poll_admin ( struct net_device *netdev );
894 extern int intelxl_open_admin ( struct intelxl_nic *intelxl );
895 extern void intelxl_reopen_admin ( struct intelxl_nic *intelxl );
896 extern void intelxl_close_admin ( struct intelxl_nic *intelxl );
897 extern int intelxl_alloc_ring ( struct intelxl_nic *intelxl,
898 struct intelxl_ring *ring );
899 extern void intelxl_free_ring ( struct intelxl_nic *intelxl,
900 struct intelxl_ring *ring );
901 extern void intelxl_empty_rx ( struct intelxl_nic *intelxl );
902 extern int intelxl_transmit ( struct net_device *netdev,
903 struct io_buffer *iobuf );
904 extern void intelxl_poll ( struct net_device *netdev );
905
906 extern void intelxlvf_admin_event ( struct net_device *netdev,
907 struct intelxl_admin_descriptor *evt,
908 union intelxl_admin_buffer *buf );
909
910 #endif /* _INTELXL_H */