[intelxl] Allow admin cookie to hold extended opcode and return code
[ipxe.git] / src / drivers / net / intelxl.h
1 #ifndef _INTELX_H
2 #define _INTELX_H
3
4 /** @file
5 *
6 * Intel 40 Gigabit Ethernet network card driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14
15 struct intelxl_nic;
16
17 /** BAR size */
18 #define INTELXL_BAR_SIZE 0x200000
19
20 /** Alignment
21 *
22 * No data structure requires greater than 128 byte alignment.
23 */
24 #define INTELXL_ALIGN 128
25
26 /******************************************************************************
27 *
28 * Admin queue
29 *
30 ******************************************************************************
31 */
32
33 /** PF Admin Command Queue register block */
34 #define INTELXL_ADMIN_CMD 0x080000
35
36 /** PF Admin Event Queue register block */
37 #define INTELXL_ADMIN_EVT 0x080080
38
39 /** Admin Queue Base Address Low Register (offset) */
40 #define INTELXL_ADMIN_BAL 0x000
41
42 /** Admin Queue Base Address High Register (offset) */
43 #define INTELXL_ADMIN_BAH 0x100
44
45 /** Admin Queue Length Register (offset) */
46 #define INTELXL_ADMIN_LEN 0x200
47 #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
48 #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
49
50 /** Admin Queue Head Register (offset) */
51 #define INTELXL_ADMIN_HEAD 0x300
52
53 /** Admin Queue Tail Register (offset) */
54 #define INTELXL_ADMIN_TAIL 0x400
55
56 /** Admin queue register offsets
57 *
58 * The physical and virtual function register maps have no discernible
59 * relationship.
60 */
61 struct intelxl_admin_offsets {
62 /** Base Address Low Register offset */
63 unsigned int bal;
64 /** Base Address High Register offset */
65 unsigned int bah;
66 /** Length Register offset */
67 unsigned int len;
68 /** Head Register offset */
69 unsigned int head;
70 /** Tail Register offset */
71 unsigned int tail;
72 };
73
74 /** Admin queue data buffer command parameters */
75 struct intelxl_admin_buffer_params {
76 /** Reserved */
77 uint8_t reserved[8];
78 /** Buffer address high */
79 uint32_t high;
80 /** Buffer address low */
81 uint32_t low;
82 } __attribute__ (( packed ));
83
84 /** Admin queue Get Version command */
85 #define INTELXL_ADMIN_VERSION 0x0001
86
87 /** Admin queue version number */
88 struct intelxl_admin_version {
89 /** Major version number */
90 uint16_t major;
91 /** Minor version number */
92 uint16_t minor;
93 } __attribute__ (( packed ));
94
95 /** Admin queue Get Version command parameters */
96 struct intelxl_admin_version_params {
97 /** ROM version */
98 uint32_t rom;
99 /** Firmware build ID */
100 uint32_t build;
101 /** Firmware version */
102 struct intelxl_admin_version firmware;
103 /** API version */
104 struct intelxl_admin_version api;
105 } __attribute__ (( packed ));
106
107 /** Admin queue Driver Version command */
108 #define INTELXL_ADMIN_DRIVER 0x0002
109
110 /** Admin queue Driver Version command parameters */
111 struct intelxl_admin_driver_params {
112 /** Driver version */
113 uint8_t major;
114 /** Minor version */
115 uint8_t minor;
116 /** Build version */
117 uint8_t build;
118 /** Sub-build version */
119 uint8_t sub;
120 /** Reserved */
121 uint8_t reserved[4];
122 /** Data buffer address */
123 uint64_t address;
124 } __attribute__ (( packed ));
125
126 /** Admin queue Driver Version data buffer */
127 struct intelxl_admin_driver_buffer {
128 /** Driver name */
129 char name[32];
130 } __attribute__ (( packed ));
131
132 /** Admin queue Shutdown command */
133 #define INTELXL_ADMIN_SHUTDOWN 0x0003
134
135 /** Admin queue Shutdown command parameters */
136 struct intelxl_admin_shutdown_params {
137 /** Driver unloading */
138 uint8_t unloading;
139 /** Reserved */
140 uint8_t reserved[15];
141 } __attribute__ (( packed ));
142
143 /** Driver is unloading */
144 #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
145
146 /** Admin queue Get Switch Configuration command */
147 #define INTELXL_ADMIN_SWITCH 0x0200
148
149 /** Switching element configuration */
150 struct intelxl_admin_switch_config {
151 /** Switching element type */
152 uint8_t type;
153 /** Revision */
154 uint8_t revision;
155 /** Switching element ID */
156 uint16_t seid;
157 /** Uplink switching element ID */
158 uint16_t uplink;
159 /** Downlink switching element ID */
160 uint16_t downlink;
161 /** Reserved */
162 uint8_t reserved_b[3];
163 /** Connection type */
164 uint8_t connection;
165 /** Reserved */
166 uint8_t reserved_c[2];
167 /** Element specific information */
168 uint16_t info;
169 } __attribute__ (( packed ));
170
171 /** Virtual Station Inferface element type */
172 #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
173
174 /** Admin queue Get Switch Configuration command parameters */
175 struct intelxl_admin_switch_params {
176 /** Starting switching element identifier */
177 uint16_t next;
178 /** Reserved */
179 uint8_t reserved[6];
180 /** Data buffer address */
181 uint64_t address;
182 } __attribute__ (( packed ));
183
184 /** Admin queue Get Switch Configuration data buffer */
185 struct intelxl_admin_switch_buffer {
186 /** Number of switching elements reported */
187 uint16_t count;
188 /** Total number of switching elements */
189 uint16_t total;
190 /** Reserved */
191 uint8_t reserved_a[12];
192 /** Switch configuration */
193 struct intelxl_admin_switch_config cfg;
194 } __attribute__ (( packed ));
195
196 /** Admin queue Get VSI Parameters command */
197 #define INTELXL_ADMIN_VSI 0x0212
198
199 /** Admin queue Get VSI Parameters command parameters */
200 struct intelxl_admin_vsi_params {
201 /** VSI switching element ID */
202 uint16_t vsi;
203 /** Reserved */
204 uint8_t reserved[6];
205 /** Data buffer address */
206 uint64_t address;
207 } __attribute__ (( packed ));
208
209 /** Admin queue Get VSI Parameters data buffer */
210 struct intelxl_admin_vsi_buffer {
211 /** Reserved */
212 uint8_t reserved_a[30];
213 /** Queue numbers */
214 uint16_t queue[16];
215 /** Reserved */
216 uint8_t reserved_b[34];
217 /** Queue set handles for each traffic class */
218 uint16_t qset[8];
219 /** Reserved */
220 uint8_t reserved_c[16];
221 } __attribute__ (( packed ));
222
223 /** Admin queue Set VSI Promiscuous Modes command */
224 #define INTELXL_ADMIN_PROMISC 0x0254
225
226 /** Admin queue Set VSI Promiscuous Modes command parameters */
227 struct intelxl_admin_promisc_params {
228 /** Flags */
229 uint16_t flags;
230 /** Valid flags */
231 uint16_t valid;
232 /** VSI switching element ID */
233 uint16_t vsi;
234 /** Reserved */
235 uint8_t reserved[10];
236 } __attribute__ (( packed ));
237
238 /** Promiscuous unicast mode */
239 #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
240
241 /** Promiscuous multicast mode */
242 #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
243
244 /** Promiscuous broadcast mode */
245 #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
246
247 /** Promiscuous VLAN mode */
248 #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
249
250 /** Admin queue Restart Autonegotiation command */
251 #define INTELXL_ADMIN_AUTONEG 0x0605
252
253 /** Admin queue Restart Autonegotiation command parameters */
254 struct intelxl_admin_autoneg_params {
255 /** Flags */
256 uint8_t flags;
257 /** Reserved */
258 uint8_t reserved[15];
259 } __attribute__ (( packed ));
260
261 /** Restart autonegotiation */
262 #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
263
264 /** Enable link */
265 #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
266
267 /** Admin queue Get Link Status command */
268 #define INTELXL_ADMIN_LINK 0x0607
269
270 /** Admin queue Get Link Status command parameters */
271 struct intelxl_admin_link_params {
272 /** Link status notification */
273 uint8_t notify;
274 /** Reserved */
275 uint8_t reserved_a;
276 /** PHY type */
277 uint8_t phy;
278 /** Link speed */
279 uint8_t speed;
280 /** Link status */
281 uint8_t status;
282 /** Reserved */
283 uint8_t reserved_b[11];
284 } __attribute__ (( packed ));
285
286 /** Notify driver of link status changes */
287 #define INTELXL_ADMIN_LINK_NOTIFY 0x03
288
289 /** Link is up */
290 #define INTELXL_ADMIN_LINK_UP 0x01
291
292 /** Admin queue command parameters */
293 union intelxl_admin_params {
294 /** Additional data buffer command parameters */
295 struct intelxl_admin_buffer_params buffer;
296 /** Get Version command parameters */
297 struct intelxl_admin_version_params version;
298 /** Driver Version command parameters */
299 struct intelxl_admin_driver_params driver;
300 /** Shutdown command parameters */
301 struct intelxl_admin_shutdown_params shutdown;
302 /** Get Switch Configuration command parameters */
303 struct intelxl_admin_switch_params sw;
304 /** Get VSI Parameters command parameters */
305 struct intelxl_admin_vsi_params vsi;
306 /** Set VSI Promiscuous Modes command parameters */
307 struct intelxl_admin_promisc_params promisc;
308 /** Restart Autonegotiation command parameters */
309 struct intelxl_admin_autoneg_params autoneg;
310 /** Get Link Status command parameters */
311 struct intelxl_admin_link_params link;
312 } __attribute__ (( packed ));
313
314 /** Admin queue data buffer */
315 union intelxl_admin_buffer {
316 /** Driver Version data buffer */
317 struct intelxl_admin_driver_buffer driver;
318 /** Get Switch Configuration data buffer */
319 struct intelxl_admin_switch_buffer sw;
320 /** Get VSI Parameters data buffer */
321 struct intelxl_admin_vsi_buffer vsi;
322 /** Alignment padding */
323 uint8_t pad[INTELXL_ALIGN];
324 } __attribute__ (( packed ));
325
326 /** Admin queue descriptor */
327 struct intelxl_admin_descriptor {
328 /** Flags */
329 uint16_t flags;
330 /** Opcode */
331 uint16_t opcode;
332 /** Data length */
333 uint16_t len;
334 /** Return value */
335 uint16_t ret;
336 /** Opaque cookie / VF opcode */
337 union {
338 /** Cookie */
339 uint32_t cookie;
340 /** VF opcode */
341 uint32_t vopcode;
342 };
343 /** VF return value */
344 int32_t vret;
345 /** Parameters */
346 union intelxl_admin_params params;
347 } __attribute__ (( packed ));
348
349 /** Admin descriptor done */
350 #define INTELXL_ADMIN_FL_DD 0x0001
351
352 /** Admin descriptor contains a completion */
353 #define INTELXL_ADMIN_FL_CMP 0x0002
354
355 /** Admin descriptor completed in error */
356 #define INTELXL_ADMIN_FL_ERR 0x0004
357
358 /** Admin descriptor uses data buffer for command parameters */
359 #define INTELXL_ADMIN_FL_RD 0x0400
360
361 /** Admin descriptor uses data buffer */
362 #define INTELXL_ADMIN_FL_BUF 0x1000
363
364 /** Admin queue */
365 struct intelxl_admin {
366 /** Descriptors */
367 struct intelxl_admin_descriptor *desc;
368 /** Data buffers */
369 union intelxl_admin_buffer *buf;
370 /** Queue index */
371 unsigned int index;
372
373 /** Register block base */
374 unsigned int base;
375 /** Register offsets */
376 const struct intelxl_admin_offsets *regs;
377 };
378
379 /**
380 * Initialise admin queue
381 *
382 * @v admin Admin queue
383 * @v base Register block base
384 * @v regs Register offsets
385 */
386 static inline __attribute__ (( always_inline )) void
387 intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
388 const struct intelxl_admin_offsets *regs ) {
389
390 admin->base = base;
391 admin->regs = regs;
392 }
393
394 /** Number of admin queue descriptors */
395 #define INTELXL_ADMIN_NUM_DESC 4
396
397 /** Maximum time to wait for an admin request to complete */
398 #define INTELXL_ADMIN_MAX_WAIT_MS 100
399
400 /** Admin queue API major version */
401 #define INTELXL_ADMIN_API_MAJOR 1
402
403 /******************************************************************************
404 *
405 * Transmit and receive queue context
406 *
407 ******************************************************************************
408 */
409
410 /** CMLAN Context Data Register */
411 #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
412
413 /** CMLAN Context Control Register */
414 #define INTELXL_PFCM_LANCTXCTL 0x10c300
415 #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
416 ( (x) << 0 ) /**< Queue number */
417 #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
418 ( (x) << 12 ) /**< Sub-line */
419 #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
420 ( (x) << 15 ) /**< Queue type */
421 #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
422 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
423 #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
424 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
425 #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
426 ( (x) << 17 ) /**< Op code */
427 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
428 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
429 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
430 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
431
432 /** CMLAN Context Status Register */
433 #define INTELXL_PFCM_LANCTXSTAT 0x10c380
434 #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
435
436 /** Queue context line */
437 struct intelxl_context_line {
438 /** Raw data */
439 uint32_t raw[4];
440 } __attribute__ (( packed ));
441
442 /** Transmit queue context */
443 struct intelxl_context_tx {
444 /** Head pointer */
445 uint16_t head;
446 /** Flags */
447 uint16_t flags;
448 /** Base address */
449 uint64_t base;
450 /** Reserved */
451 uint8_t reserved_a[8];
452 /** Queue count */
453 uint16_t count;
454 /** Reserved */
455 uint8_t reserved_b[100];
456 /** Queue set */
457 uint16_t qset;
458 /** Reserved */
459 uint8_t reserved_c[4];
460 } __attribute__ (( packed ));
461
462 /** New transmit queue context */
463 #define INTELXL_CTX_TX_FL_NEW 0x4000
464
465 /** Transmit queue base address */
466 #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
467
468 /** Transmit queue count */
469 #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
470
471 /** Transmit queue set */
472 #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
473
474 /** Receive queue context */
475 struct intelxl_context_rx {
476 /** Head pointer */
477 uint16_t head;
478 /** Reserved */
479 uint8_t reserved_a[2];
480 /** Base address and queue count */
481 uint64_t base_count;
482 /** Data buffer length */
483 uint16_t len;
484 /** Flags */
485 uint8_t flags;
486 /** Reserved */
487 uint8_t reserved_b[7];
488 /** Maximum frame size */
489 uint16_t mfs;
490 } __attribute__ (( packed ));
491
492 /** Receive queue base address and queue count */
493 #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
494 ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
495
496 /** Receive queue data buffer length */
497 #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
498
499 /** Strip CRC from received packets */
500 #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
501
502 /** Receive queue maximum frame size */
503 #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
504
505 /** Maximum time to wait for a context operation to complete */
506 #define INTELXL_CTX_MAX_WAIT_MS 100
507
508 /** Time to wait for a queue to become enabled */
509 #define INTELXL_QUEUE_ENABLE_DELAY_US 20
510
511 /** Time to wait for a transmit queue to become pre-disabled */
512 #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
513
514 /** Maximum time to wait for a queue to become disabled */
515 #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
516
517 /******************************************************************************
518 *
519 * Transmit and receive descriptors
520 *
521 ******************************************************************************
522 */
523
524 /** Global Transmit Queue Head register */
525 #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
526
527 /** Global Transmit Pre Queue Disable register */
528 #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
529 #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
530 ( (x) << 0 ) /**< Queue index */
531 #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
532 0x40000000UL /**< Set disable */
533 #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
534 0x80000000UL /**< Clear disable */
535
536 /** Global Transmit Queue register block */
537 #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
538
539 /** Global Receive Queue register block */
540 #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
541
542 /** Queue Enable Register (offset) */
543 #define INTELXL_QXX_ENA 0x0000
544 #define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
545 #define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
546
547 /** Queue Control Register (offset) */
548 #define INTELXL_QXX_CTL 0x4000
549 #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
550 #define INTELXL_QXX_CTL_PFVF_Q_PF \
551 INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
552 #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
553
554 /** Queue Tail Pointer Register (offset) */
555 #define INTELXL_QXX_TAIL 0x8000
556
557 /** Transmit data descriptor */
558 struct intelxl_tx_data_descriptor {
559 /** Buffer address */
560 uint64_t address;
561 /** Flags */
562 uint32_t flags;
563 /** Length */
564 uint32_t len;
565 } __attribute__ (( packed ));
566
567 /** Transmit data descriptor type */
568 #define INTELXL_TX_DATA_DTYP 0x0
569
570 /** Transmit data descriptor end of packet */
571 #define INTELXL_TX_DATA_EOP 0x10
572
573 /** Transmit data descriptor report status */
574 #define INTELXL_TX_DATA_RS 0x20
575
576 /** Transmit data descriptor pretty please
577 *
578 * This bit is completely missing from older versions of the XL710
579 * datasheet. Later versions describe it innocuously as "reserved,
580 * must be 1". Without this bit, everything will appear to work (up
581 * to and including the port "transmit good octets" counter), but no
582 * packet will actually be sent.
583 */
584 #define INTELXL_TX_DATA_JFDI 0x40
585
586 /** Transmit data descriptor length */
587 #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
588
589 /** Transmit writeback descriptor */
590 struct intelxl_tx_writeback_descriptor {
591 /** Reserved */
592 uint8_t reserved_a[8];
593 /** Flags */
594 uint8_t flags;
595 /** Reserved */
596 uint8_t reserved_b[7];
597 } __attribute__ (( packed ));
598
599 /** Transmit writeback descriptor complete */
600 #define INTELXL_TX_WB_FL_DD 0x01
601
602 /** Receive data descriptor */
603 struct intelxl_rx_data_descriptor {
604 /** Buffer address */
605 uint64_t address;
606 /** Flags */
607 uint32_t flags;
608 /** Reserved */
609 uint8_t reserved[4];
610 } __attribute__ (( packed ));
611
612 /** Receive writeback descriptor */
613 struct intelxl_rx_writeback_descriptor {
614 /** Reserved */
615 uint8_t reserved_a[2];
616 /** VLAN tag */
617 uint16_t vlan;
618 /** Reserved */
619 uint8_t reserved_b[4];
620 /** Flags */
621 uint32_t flags;
622 /** Length */
623 uint32_t len;
624 } __attribute__ (( packed ));
625
626 /** Receive writeback descriptor complete */
627 #define INTELXL_RX_WB_FL_DD 0x00000001UL
628
629 /** Receive writeback descriptor VLAN tag present */
630 #define INTELXL_RX_WB_FL_VLAN 0x00000004UL
631
632 /** Receive writeback descriptor error */
633 #define INTELXL_RX_WB_FL_RXE 0x00080000UL
634
635 /** Receive writeback descriptor length */
636 #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
637
638 /** Packet descriptor */
639 union intelxl_descriptor {
640 /** Transmit data descriptor */
641 struct intelxl_tx_data_descriptor tx;
642 /** Transmit writeback descriptor */
643 struct intelxl_tx_writeback_descriptor tx_wb;
644 /** Receive data descriptor */
645 struct intelxl_rx_data_descriptor rx;
646 /** Receive writeback descriptor */
647 struct intelxl_rx_writeback_descriptor rx_wb;
648 };
649
650 /** Descriptor ring */
651 struct intelxl_ring {
652 /** Descriptors */
653 union intelxl_descriptor *desc;
654 /** Producer index */
655 unsigned int prod;
656 /** Consumer index */
657 unsigned int cons;
658
659 /** Register block */
660 unsigned int reg;
661 /** Length (in bytes) */
662 size_t len;
663 /** Program queue context
664 *
665 * @v intelxl Intel device
666 * @v address Descriptor ring base address
667 */
668 int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
669 };
670
671 /**
672 * Initialise descriptor ring
673 *
674 * @v ring Descriptor ring
675 * @v count Number of descriptors
676 * @v context Method to program queue context
677 */
678 static inline __attribute__ (( always_inline)) void
679 intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count,
680 int ( * context ) ( struct intelxl_nic *intelxl,
681 physaddr_t address ) ) {
682
683 ring->len = ( count * sizeof ( ring->desc[0] ) );
684 ring->context = context;
685 }
686
687 /** Number of transmit descriptors */
688 #define INTELXL_TX_NUM_DESC 16
689
690 /** Transmit descriptor ring maximum fill level */
691 #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
692
693 /** Number of receive descriptors
694 *
695 * In PXE mode (i.e. able to post single receive descriptors), 8
696 * descriptors is the only permitted value covering all possible
697 * numbers of PFs.
698 */
699 #define INTELXL_RX_NUM_DESC 8
700
701 /** Receive descriptor ring fill level */
702 #define INTELXL_RX_FILL ( INTELXL_RX_NUM_DESC - 1 )
703
704 /******************************************************************************
705 *
706 * Top level
707 *
708 ******************************************************************************
709 */
710
711 /** PF Interrupt Zero Dynamic Control Register */
712 #define INTELXL_PFINT_DYN_CTL0 0x038480
713 #define INTELXL_PFINT_DYN_CTL0_INTENA 0x00000001UL /**< Enable */
714 #define INTELXL_PFINT_DYN_CTL0_CLEARPBA 0x00000002UL /**< Acknowledge */
715 #define INTELXL_PFINT_DYN_CTL0_INTENA_MASK 0x80000000UL /**< Ignore enable */
716
717 /** PF Interrupt Zero Linked List Register */
718 #define INTELXL_PFINT_LNKLST0 0x038500
719 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
720 ( (x) << 0 ) /**< Queue index */
721 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
722 INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
723 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
724 ( (x) << 11 ) /**< Queue type */
725 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
726 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
727 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
728 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
729
730 /** PF Interrupt Zero Cause Enablement Register */
731 #define INTELXL_PFINT_ICR0_ENA 0x038800
732 #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
733
734 /** Receive Queue Interrupt Cause Control Register */
735 #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
736 #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
737 #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
738 INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
739 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
740 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
741 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
742 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
743 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
744 #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
745
746 /** Transmit Queue Interrupt Cause Control Register */
747 #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
748 #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
749 #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
750 INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
751 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
752 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
753 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
754 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
755 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
756 #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
757
758 /** PF Control Register */
759 #define INTELXL_PFGEN_CTRL 0x092400
760 #define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
761
762 /** Time to delay for device reset, in milliseconds */
763 #define INTELXL_RESET_DELAY_MS 100
764
765 /** PF Queue Allocation Register */
766 #define INTELXL_PFLAN_QALLOC 0x1c0400
767 #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
768 ( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
769 #define INTELXL_PFLAN_QALLOC_LASTQ(x) \
770 ( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
771
772 /** PF LAN Port Number Register */
773 #define INTELXL_PFGEN_PORTNUM 0x1c0480
774 #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
775 ( ( (x) >> 0 ) & 0x3 ) /**< Port number */
776
777 /** Port MAC Address Low Register */
778 #define INTELXL_PRTGL_SAL 0x1e2120
779
780 /** Port MAC Address High Register */
781 #define INTELXL_PRTGL_SAH 0x1e2140
782 #define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
783 #define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
784
785 /** Receive address */
786 union intelxl_receive_address {
787 struct {
788 uint32_t low;
789 uint32_t high;
790 } __attribute__ (( packed )) reg;
791 uint8_t raw[ETH_ALEN];
792 };
793
794 /** An Intel 40Gigabit network card */
795 struct intelxl_nic {
796 /** Registers */
797 void *regs;
798 /** Maximum frame size */
799 size_t mfs;
800
801 /** Physical function number */
802 unsigned int pf;
803 /** Absolute queue number base */
804 unsigned int base;
805 /** Port number */
806 unsigned int port;
807 /** Queue number */
808 unsigned int queue;
809 /** Virtual Station Interface switching element ID */
810 unsigned int vsi;
811 /** Queue set handle */
812 unsigned int qset;
813
814 /** Admin command queue */
815 struct intelxl_admin command;
816 /** Admin event queue */
817 struct intelxl_admin event;
818
819 /** Transmit descriptor ring */
820 struct intelxl_ring tx;
821 /** Receive descriptor ring */
822 struct intelxl_ring rx;
823 /** Receive I/O buffers */
824 struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
825 };
826
827 #endif /* _INTELXL_H */