[lan78xx] Always enable automatic speed and duplex detection
[ipxe.git] / src / drivers / net / lan78xx.h
1 #ifndef _LAN78XX_H
2 #define _LAN78XX_H
3
4 /** @file
5 *
6 * Microchip LAN78xx USB Ethernet driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include "smscusb.h"
13 #include "smsc75xx.h"
14
15 /** Hardware configuration register */
16 #define LAN78XX_HW_CFG 0x0010
17 #define LAN78XX_HW_CFG_LED1_EN 0x00200000UL /**< LED1 enable */
18 #define LAN78XX_HW_CFG_LED0_EN 0x00100000UL /**< LED1 enable */
19 #define LAN78XX_HW_CFG_LRST 0x00000002UL /**< Soft lite reset */
20
21 /** Interrupt endpoint control register */
22 #define LAN78XX_INT_EP_CTL 0x0098
23 #define LAN78XX_INT_EP_CTL_RDFO_EN 0x00400000UL /**< RX FIFO overflow */
24 #define LAN78XX_INT_EP_CTL_PHY_EN 0x00020000UL /**< PHY interrupt */
25
26 /** Bulk IN delay register */
27 #define LAN78XX_BULK_IN_DLY 0x0094
28 #define LAN78XX_BULK_IN_DLY_SET(ticks) ( (ticks) << 0 ) /**< Delay / 16.7ns */
29
30 /** EEPROM register base */
31 #define LAN78XX_E2P_BASE 0x0040
32
33 /** USB configuration register 0 */
34 #define LAN78XX_USB_CFG0 0x0080
35 #define LAN78XX_USB_CFG0_BIR 0x00000040UL /**< Bulk IN use NAK */
36
37 /** Receive filtering engine control register */
38 #define LAN78XX_RFE_CTL 0x00b0
39 #define LAN78XX_RFE_CTL_AB 0x00000400UL /**< Accept broadcast */
40 #define LAN78XX_RFE_CTL_AM 0x00000200UL /**< Accept multicast */
41 #define LAN78XX_RFE_CTL_AU 0x00000100UL /**< Accept unicast */
42
43 /** FIFO controller RX FIFO control register */
44 #define LAN78XX_FCT_RX_CTL 0x00c0
45 #define LAN78XX_FCT_RX_CTL_EN 0x80000000UL /**< FCT RX enable */
46 #define LAN78XX_FCT_RX_CTL_BAD 0x02000000UL /**< Store bad frames */
47
48 /** FIFO controller TX FIFO control register */
49 #define LAN78XX_FCT_TX_CTL 0x00c4
50 #define LAN78XX_FCT_TX_CTL_EN 0x80000000UL /**< FCT TX enable */
51
52 /** MAC control register */
53 #define LAN78XX_MAC_CR 0x0100
54 #define LAN78XX_MAC_CR_ADP 0x00002000UL /**< Duplex polarity */
55 #define LAN78XX_MAC_CR_ADD 0x00001000UL /**< Auto duplex */
56 #define LAN78XX_MAC_CR_ASD 0x00000800UL /**< Auto speed */
57
58 /** MAC receive register */
59 #define LAN78XX_MAC_RX 0x0104
60 #define LAN78XX_MAC_RX_MAX_SIZE(mtu) ( (mtu) << 16 ) /**< Max frame size */
61 #define LAN78XX_MAC_RX_MAX_SIZE_DEFAULT \
62 LAN78XX_MAC_RX_MAX_SIZE ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
63 #define LAN78XX_MAC_RX_FCS 0x00000010UL /**< FCS stripping */
64 #define LAN78XX_MAC_RX_EN 0x00000001UL /**< RX enable */
65
66 /** MAC transmit register */
67 #define LAN78XX_MAC_TX 0x0108
68 #define LAN78XX_MAC_TX_EN 0x00000001UL /**< TX enable */
69
70 /** MAC receive address register base */
71 #define LAN78XX_RX_ADDR_BASE 0x0118
72
73 /** MII register base */
74 #define LAN78XX_MII_BASE 0x0120
75
76 /** PHY interrupt mask MII register */
77 #define LAN78XX_MII_PHY_INTR_MASK 25
78
79 /** PHY interrupt source MII register */
80 #define LAN78XX_MII_PHY_INTR_SOURCE 26
81
82 /** PHY interrupt: global enable */
83 #define LAN78XX_PHY_INTR_ENABLE 0x8000
84
85 /** PHY interrupt: link state change */
86 #define LAN78XX_PHY_INTR_LINK 0x2000
87
88 /** PHY interrupt: auto-negotiation failure */
89 #define LAN78XX_PHY_INTR_ANEG_ERR 0x0800
90
91 /** PHY interrupt: auto-negotiation complete */
92 #define LAN78XX_PHY_INTR_ANEG_DONE 0x0400
93
94 /** MAC address perfect filter register base */
95 #define LAN78XX_ADDR_FILT_BASE 0x0400
96
97 /** OTP register base */
98 #define LAN78XX_OTP_BASE 0x1000
99
100 /** Maximum time to wait for reset (in milliseconds) */
101 #define LAN78XX_RESET_MAX_WAIT_MS 100
102
103 #endif /* _LAN78XX_H */