[phantom] Add CLP settings interface
[ipxe.git] / src / drivers / net / phantom / phantom.c
1 /*
2 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
3 * Copyright (C) 2008 NetXen, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of the
8 * License, or any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 #include <stdint.h>
21 #include <stdlib.h>
22 #include <string.h>
23 #include <unistd.h>
24 #include <errno.h>
25 #include <assert.h>
26 #include <byteswap.h>
27 #include <gpxe/pci.h>
28 #include <gpxe/io.h>
29 #include <gpxe/malloc.h>
30 #include <gpxe/iobuf.h>
31 #include <gpxe/netdevice.h>
32 #include <gpxe/if_ether.h>
33 #include <gpxe/ethernet.h>
34 #include <gpxe/spi.h>
35 #include <gpxe/settings.h>
36 #include "phantom.h"
37
38 /**
39 * @file
40 *
41 * NetXen Phantom NICs
42 *
43 */
44
45 /** Maximum time to wait for SPI lock */
46 #define PHN_SPI_LOCK_TIMEOUT_MS 100
47
48 /** Maximum time to wait for SPI command to be issued */
49 #define PHN_SPI_CMD_TIMEOUT_MS 100
50
51 /** Maximum time to wait for command PEG to initialise
52 *
53 * BUGxxxx
54 *
55 * The command PEG will currently report initialisation complete only
56 * when at least one PHY has detected a link (so that the global PHY
57 * clock can be set to 10G/1G as appropriate). This can take a very,
58 * very long time.
59 *
60 * A future firmware revision should decouple PHY initialisation from
61 * firmware initialisation, at which point the command PEG will report
62 * initialisation complete much earlier, and this timeout can be
63 * reduced.
64 */
65 #define PHN_CMDPEG_INIT_TIMEOUT_SEC 50
66
67 /** Maximum time to wait for receive PEG to initialise */
68 #define PHN_RCVPEG_INIT_TIMEOUT_SEC 2
69
70 /** Maximum time to wait for firmware to accept a command */
71 #define PHN_ISSUE_CMD_TIMEOUT_MS 2000
72
73 /** Maximum time to wait for test memory */
74 #define PHN_TEST_MEM_TIMEOUT_MS 100
75
76 /** Maximum time to wait for CLP command to be issued */
77 #define PHN_CLP_CMD_TIMEOUT_MS 500
78
79 /** Link state poll frequency
80 *
81 * The link state will be checked once in every N calls to poll().
82 */
83 #define PHN_LINK_POLL_FREQUENCY 4096
84
85 /** Number of RX descriptors */
86 #define PHN_NUM_RDS 32
87
88 /** RX maximum fill level. Must be strictly less than PHN_NUM_RDS. */
89 #define PHN_RDS_MAX_FILL 16
90
91 /** RX buffer size */
92 #define PHN_RX_BUFSIZE ( 32 /* max LL padding added by card */ + \
93 ETH_FRAME_LEN )
94
95 /** Number of RX status descriptors */
96 #define PHN_NUM_SDS 32
97
98 /** Number of TX descriptors */
99 #define PHN_NUM_CDS 8
100
101 /** A Phantom descriptor ring set */
102 struct phantom_descriptor_rings {
103 /** RX descriptors */
104 struct phantom_rds rds[PHN_NUM_RDS];
105 /** RX status descriptors */
106 struct phantom_sds sds[PHN_NUM_SDS];
107 /** TX descriptors */
108 union phantom_cds cds[PHN_NUM_CDS];
109 /** TX consumer index */
110 volatile uint32_t cmd_cons;
111 };
112
113 /** A Phantom NIC port */
114 struct phantom_nic_port {
115 /** Phantom NIC containing this port */
116 struct phantom_nic *phantom;
117 /** Port number */
118 unsigned int port;
119
120
121 /** RX context ID */
122 uint16_t rx_context_id;
123 /** RX descriptor producer CRB offset */
124 unsigned long rds_producer_crb;
125 /** RX status descriptor consumer CRB offset */
126 unsigned long sds_consumer_crb;
127
128 /** RX producer index */
129 unsigned int rds_producer_idx;
130 /** RX consumer index */
131 unsigned int rds_consumer_idx;
132 /** RX status consumer index */
133 unsigned int sds_consumer_idx;
134 /** RX I/O buffers */
135 struct io_buffer *rds_iobuf[PHN_RDS_MAX_FILL];
136
137
138 /** TX context ID */
139 uint16_t tx_context_id;
140 /** TX descriptor producer CRB offset */
141 unsigned long cds_producer_crb;
142
143 /** TX producer index */
144 unsigned int cds_producer_idx;
145 /** TX consumer index */
146 unsigned int cds_consumer_idx;
147 /** TX I/O buffers */
148 struct io_buffer *cds_iobuf[PHN_NUM_CDS];
149
150
151 /** Link state poll timer */
152 unsigned long link_poll_timer;
153
154
155 /** Descriptor rings */
156 struct phantom_descriptor_rings *desc;
157
158 /** Non-volatile settings */
159 struct settings settings;
160 };
161
162 /** RX context creation request and response buffers */
163 struct phantom_create_rx_ctx_rqrsp {
164 struct {
165 struct nx_hostrq_rx_ctx_s rx_ctx;
166 struct nx_hostrq_rds_ring_s rds;
167 struct nx_hostrq_sds_ring_s sds;
168 } __unm_dma_aligned hostrq;
169 struct {
170 struct nx_cardrsp_rx_ctx_s rx_ctx;
171 struct nx_cardrsp_rds_ring_s rds;
172 struct nx_cardrsp_sds_ring_s sds;
173 } __unm_dma_aligned cardrsp;
174 };
175
176 /** TX context creation request and response buffers */
177 struct phantom_create_tx_ctx_rqrsp {
178 struct {
179 struct nx_hostrq_tx_ctx_s tx_ctx;
180 } __unm_dma_aligned hostrq;
181 struct {
182 struct nx_cardrsp_tx_ctx_s tx_ctx;
183 } __unm_dma_aligned cardrsp;
184 };
185
186 /** A Phantom DMA buffer area */
187 union phantom_dma_buffer {
188 /** Dummy area required for (read-only) self-tests */
189 uint8_t dummy_dma[UNM_DUMMY_DMA_SIZE];
190 /** RX context creation request and response buffers */
191 struct phantom_create_rx_ctx_rqrsp create_rx_ctx;
192 /** TX context creation request and response buffers */
193 struct phantom_create_tx_ctx_rqrsp create_tx_ctx;
194 };
195
196 /** A Phantom NIC */
197 struct phantom_nic {
198 /** BAR 0 */
199 void *bar0;
200 /** Current CRB window */
201 unsigned long crb_window;
202 /** CRB window access method */
203 unsigned long ( *crb_access ) ( struct phantom_nic *phantom,
204 unsigned long reg );
205
206 /** Number of ports */
207 int num_ports;
208 /** Per-port network devices */
209 struct net_device *netdev[UNM_FLASH_NUM_PORTS];
210
211 /** DMA buffers */
212 union phantom_dma_buffer *dma_buf;
213
214 /** Flash memory SPI bus */
215 struct spi_bus spi_bus;
216 /** Flash memory SPI device */
217 struct spi_device flash;
218
219 /** Last known link state */
220 uint32_t link_state;
221 };
222
223 /***************************************************************************
224 *
225 * CRB register access
226 *
227 */
228
229 /**
230 * Prepare for access to CRB register via 128MB BAR
231 *
232 * @v phantom Phantom NIC
233 * @v reg Register offset within abstract address space
234 * @ret offset Register offset within PCI BAR0
235 */
236 static unsigned long phantom_crb_access_128m ( struct phantom_nic *phantom,
237 unsigned long reg ) {
238 unsigned long offset = ( 0x6000000 + ( reg & 0x1ffffff ) );
239 uint32_t window = ( reg & 0x2000000 );
240 uint32_t verify_window;
241
242 if ( phantom->crb_window != window ) {
243
244 /* Write to the CRB window register */
245 writel ( window, phantom->bar0 + UNM_128M_CRB_WINDOW );
246
247 /* Ensure that the write has reached the card */
248 verify_window = readl ( phantom->bar0 + UNM_128M_CRB_WINDOW );
249 assert ( verify_window == window );
250
251 /* Record new window */
252 phantom->crb_window = window;
253 }
254
255 return offset;
256 }
257
258 /**
259 * Prepare for access to CRB register via 32MB BAR
260 *
261 * @v phantom Phantom NIC
262 * @v reg Register offset within abstract address space
263 * @ret offset Register offset within PCI BAR0
264 */
265 static unsigned long phantom_crb_access_32m ( struct phantom_nic *phantom,
266 unsigned long reg ) {
267 unsigned long offset = ( reg & 0x1ffffff );
268 uint32_t window = ( reg & 0x2000000 );
269 uint32_t verify_window;
270
271 if ( phantom->crb_window != window ) {
272
273 /* Write to the CRB window register */
274 writel ( window, phantom->bar0 + UNM_32M_CRB_WINDOW );
275
276 /* Ensure that the write has reached the card */
277 verify_window = readl ( phantom->bar0 + UNM_32M_CRB_WINDOW );
278 assert ( verify_window == window );
279
280 /* Record new window */
281 phantom->crb_window = window;
282 }
283
284 return offset;
285 }
286
287 /**
288 * Prepare for access to CRB register via 2MB BAR
289 *
290 * @v phantom Phantom NIC
291 * @v reg Register offset within abstract address space
292 * @ret offset Register offset within PCI BAR0
293 */
294 static unsigned long phantom_crb_access_2m ( struct phantom_nic *phantom,
295 unsigned long reg ) {
296 static const struct {
297 uint8_t block;
298 uint16_t window_hi;
299 } reg_window_hi[] = {
300 { UNM_CRB_BLK_PCIE, 0x773 },
301 { UNM_CRB_BLK_CAM, 0x416 },
302 { UNM_CRB_BLK_ROMUSB, 0x421 },
303 { UNM_CRB_BLK_TEST, 0x295 },
304 { UNM_CRB_BLK_PEG_0, 0x340 },
305 { UNM_CRB_BLK_PEG_1, 0x341 },
306 { UNM_CRB_BLK_PEG_2, 0x342 },
307 { UNM_CRB_BLK_PEG_3, 0x343 },
308 { UNM_CRB_BLK_PEG_4, 0x34b },
309 };
310 unsigned int block = UNM_CRB_BLK ( reg );
311 unsigned long offset = UNM_CRB_OFFSET ( reg );
312 uint32_t window;
313 uint32_t verify_window;
314 unsigned int i;
315
316 for ( i = 0 ; i < ( sizeof ( reg_window_hi ) /
317 sizeof ( reg_window_hi[0] ) ) ; i++ ) {
318
319 if ( reg_window_hi[i].block != block )
320 continue;
321
322 window = ( ( reg_window_hi[i].window_hi << 20 ) |
323 ( offset & 0x000f0000 ) );
324
325 if ( phantom->crb_window != window ) {
326
327 /* Write to the CRB window register */
328 writel ( window, phantom->bar0 + UNM_2M_CRB_WINDOW );
329
330 /* Ensure that the write has reached the card */
331 verify_window = readl ( phantom->bar0 +
332 UNM_2M_CRB_WINDOW );
333 assert ( verify_window == window );
334
335 /* Record new window */
336 phantom->crb_window = window;
337 }
338
339 return ( 0x1e0000 + ( offset & 0xffff ) );
340 }
341
342 assert ( 0 );
343 return 0;
344 }
345
346 /**
347 * Read from Phantom CRB register
348 *
349 * @v phantom Phantom NIC
350 * @v reg Register offset within abstract address space
351 * @ret value Register value
352 */
353 static uint32_t phantom_readl ( struct phantom_nic *phantom,
354 unsigned long reg ) {
355 unsigned long offset;
356
357 offset = phantom->crb_access ( phantom, reg );
358 return readl ( phantom->bar0 + offset );
359 }
360
361 /**
362 * Write to Phantom CRB register
363 *
364 * @v phantom Phantom NIC
365 * @v value Register value
366 * @v reg Register offset within abstract address space
367 */
368 static void phantom_writel ( struct phantom_nic *phantom, uint32_t value,
369 unsigned long reg ) {
370 unsigned long offset;
371
372 offset = phantom->crb_access ( phantom, reg );
373 writel ( value, phantom->bar0 + offset );
374 }
375
376 /**
377 * Write to Phantom CRB HI/LO register pair
378 *
379 * @v phantom Phantom NIC
380 * @v value Register value
381 * @v lo_offset LO register offset within CRB
382 * @v hi_offset HI register offset within CRB
383 */
384 static inline void phantom_write_hilo ( struct phantom_nic *phantom,
385 uint64_t value,
386 unsigned long lo_offset,
387 unsigned long hi_offset ) {
388 uint32_t lo = ( value & 0xffffffffUL );
389 uint32_t hi = ( value >> 32 );
390
391 phantom_writel ( phantom, lo, lo_offset );
392 phantom_writel ( phantom, hi, hi_offset );
393 }
394
395 /***************************************************************************
396 *
397 * Firmware message buffer access (for debug)
398 *
399 */
400
401 /**
402 * Read from Phantom test memory
403 *
404 * @v phantom Phantom NIC
405 * @v offset Offset within test memory
406 * @v buf 8-byte buffer to fill
407 * @ret rc Return status code
408 */
409 static int phantom_read_test_mem_block ( struct phantom_nic *phantom,
410 unsigned long offset,
411 uint32_t buf[2] ) {
412 unsigned int retries;
413 uint32_t test_control;
414
415 phantom_write_hilo ( phantom, offset, UNM_TEST_ADDR_LO,
416 UNM_TEST_ADDR_HI );
417 phantom_writel ( phantom, UNM_TEST_CONTROL_ENABLE, UNM_TEST_CONTROL );
418 phantom_writel ( phantom,
419 ( UNM_TEST_CONTROL_ENABLE | UNM_TEST_CONTROL_START ),
420 UNM_TEST_CONTROL );
421
422 for ( retries = 0 ; retries < PHN_TEST_MEM_TIMEOUT_MS ; retries++ ) {
423 test_control = phantom_readl ( phantom, UNM_TEST_CONTROL );
424 if ( ( test_control & UNM_TEST_CONTROL_BUSY ) == 0 ) {
425 buf[0] = phantom_readl ( phantom, UNM_TEST_RDDATA_LO );
426 buf[1] = phantom_readl ( phantom, UNM_TEST_RDDATA_HI );
427 return 0;
428 }
429 mdelay ( 1 );
430 }
431
432 DBGC ( phantom, "Phantom %p timed out waiting for test memory\n",
433 phantom );
434 return -ETIMEDOUT;
435 }
436
437 /**
438 * Read single byte from Phantom test memory
439 *
440 * @v phantom Phantom NIC
441 * @v offset Offset within test memory
442 * @ret byte Byte read, or negative error
443 */
444 static int phantom_read_test_mem ( struct phantom_nic *phantom,
445 unsigned long offset ) {
446 static union {
447 uint8_t bytes[8];
448 uint32_t dwords[2];
449 } cache;
450 static unsigned long cache_offset = -1UL;
451 unsigned long sub_offset;
452 int rc;
453
454 sub_offset = ( offset & ( sizeof ( cache ) - 1 ) );
455 offset = ( offset & ~( sizeof ( cache ) - 1 ) );
456
457 if ( cache_offset != offset ) {
458 if ( ( rc = phantom_read_test_mem_block ( phantom, offset,
459 cache.dwords )) !=0 )
460 return rc;
461 cache_offset = offset;
462 }
463
464 return cache.bytes[sub_offset];
465 }
466
467 /**
468 * Dump Phantom firmware dmesg log
469 *
470 * @v phantom Phantom NIC
471 * @v log Log number
472 * @v max_lines Maximum number of lines to show, or -1 to show all
473 * @ret rc Return status code
474 */
475 static int phantom_dmesg ( struct phantom_nic *phantom, unsigned int log,
476 unsigned int max_lines ) {
477 uint32_t head;
478 uint32_t tail;
479 uint32_t len;
480 uint32_t sig;
481 uint32_t offset;
482 int byte;
483
484 /* Optimise out for non-debug builds */
485 if ( ! DBG_LOG )
486 return 0;
487
488 /* Locate log */
489 head = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_HEAD ( log ) );
490 len = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_LEN ( log ) );
491 tail = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_TAIL ( log ) );
492 sig = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_SIG ( log ) );
493 DBGC ( phantom, "Phantom %p firmware dmesg buffer %d (%08lx-%08lx)\n",
494 phantom, log, head, tail );
495 assert ( ( head & 0x07 ) == 0 );
496 if ( sig != UNM_CAM_RAM_DMESG_SIG_MAGIC ) {
497 DBGC ( phantom, "Warning: bad signature %08lx (want %08lx)\n",
498 sig, UNM_CAM_RAM_DMESG_SIG_MAGIC );
499 }
500
501 /* Locate start of last (max_lines) lines */
502 for ( offset = tail ; offset > head ; offset-- ) {
503 if ( ( byte = phantom_read_test_mem ( phantom,
504 ( offset - 1 ) ) ) < 0 )
505 return byte;
506 if ( ( byte == '\n' ) && ( max_lines-- == 0 ) )
507 break;
508 }
509
510 /* Print lines */
511 for ( ; offset < tail ; offset++ ) {
512 if ( ( byte = phantom_read_test_mem ( phantom, offset ) ) < 0 )
513 return byte;
514 DBG ( "%c", byte );
515 }
516 DBG ( "\n" );
517 return 0;
518 }
519
520 /**
521 * Dump Phantom firmware dmesg logs
522 *
523 * @v phantom Phantom NIC
524 * @v max_lines Maximum number of lines to show, or -1 to show all
525 */
526 static void __attribute__ (( unused ))
527 phantom_dmesg_all ( struct phantom_nic *phantom, unsigned int max_lines ) {
528 unsigned int i;
529
530 for ( i = 0 ; i < UNM_CAM_RAM_NUM_DMESG_BUFFERS ; i++ )
531 phantom_dmesg ( phantom, i, max_lines );
532 }
533
534 /***************************************************************************
535 *
536 * SPI bus access (for flash memory)
537 *
538 */
539
540 /**
541 * Acquire Phantom SPI lock
542 *
543 * @v phantom Phantom NIC
544 * @ret rc Return status code
545 */
546 static int phantom_spi_lock ( struct phantom_nic *phantom ) {
547 unsigned int retries;
548 uint32_t pcie_sem2_lock;
549
550 for ( retries = 0 ; retries < PHN_SPI_LOCK_TIMEOUT_MS ; retries++ ) {
551 pcie_sem2_lock = phantom_readl ( phantom, UNM_PCIE_SEM2_LOCK );
552 if ( pcie_sem2_lock != 0 )
553 return 0;
554 mdelay ( 1 );
555 }
556
557 DBGC ( phantom, "Phantom %p timed out waiting for SPI lock\n",
558 phantom );
559 return -ETIMEDOUT;
560 }
561
562 /**
563 * Wait for Phantom SPI command to complete
564 *
565 * @v phantom Phantom NIC
566 * @ret rc Return status code
567 */
568 static int phantom_spi_wait ( struct phantom_nic *phantom ) {
569 unsigned int retries;
570 uint32_t glb_status;
571
572 for ( retries = 0 ; retries < PHN_SPI_CMD_TIMEOUT_MS ; retries++ ) {
573 glb_status = phantom_readl ( phantom, UNM_ROMUSB_GLB_STATUS );
574 if ( glb_status & UNM_ROMUSB_GLB_STATUS_ROM_DONE )
575 return 0;
576 mdelay ( 1 );
577 }
578
579 DBGC ( phantom, "Phantom %p timed out waiting for SPI command\n",
580 phantom );
581 return -ETIMEDOUT;
582 }
583
584 /**
585 * Release Phantom SPI lock
586 *
587 * @v phantom Phantom NIC
588 */
589 static void phantom_spi_unlock ( struct phantom_nic *phantom ) {
590 phantom_readl ( phantom, UNM_PCIE_SEM2_UNLOCK );
591 }
592
593 /**
594 * Read/write data via Phantom SPI bus
595 *
596 * @v bus SPI bus
597 * @v device SPI device
598 * @v command Command
599 * @v address Address to read/write (<0 for no address)
600 * @v data_out TX data buffer (or NULL)
601 * @v data_in RX data buffer (or NULL)
602 * @v len Length of data buffer(s)
603 * @ret rc Return status code
604 */
605 static int phantom_spi_rw ( struct spi_bus *bus,
606 struct spi_device *device,
607 unsigned int command, int address,
608 const void *data_out, void *data_in,
609 size_t len ) {
610 struct phantom_nic *phantom =
611 container_of ( bus, struct phantom_nic, spi_bus );
612 uint32_t data;
613 int rc;
614
615 DBGCP ( phantom, "Phantom %p SPI command %x at %x+%zx\n",
616 phantom, command, address, len );
617 if ( data_out )
618 DBGCP_HDA ( phantom, address, data_out, len );
619
620 /* We support only exactly 4-byte reads */
621 if ( len != UNM_SPI_BLKSIZE ) {
622 DBGC ( phantom, "Phantom %p invalid SPI length %zx\n",
623 phantom, len );
624 return -EINVAL;
625 }
626
627 /* Acquire SPI lock */
628 if ( ( rc = phantom_spi_lock ( phantom ) ) != 0 )
629 goto err_lock;
630
631 /* Issue SPI command as per the PRM */
632 if ( data_out ) {
633 memcpy ( &data, data_out, sizeof ( data ) );
634 phantom_writel ( phantom, data, UNM_ROMUSB_ROM_WDATA );
635 }
636 phantom_writel ( phantom, address, UNM_ROMUSB_ROM_ADDRESS );
637 phantom_writel ( phantom, ( device->address_len / 8 ),
638 UNM_ROMUSB_ROM_ABYTE_CNT );
639 udelay ( 100 ); /* according to PRM */
640 phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
641 phantom_writel ( phantom, command, UNM_ROMUSB_ROM_INSTR_OPCODE );
642
643 /* Wait for SPI command to complete */
644 if ( ( rc = phantom_spi_wait ( phantom ) ) != 0 )
645 goto err_wait;
646
647 /* Reset address byte count and dummy byte count, because the
648 * PRM asks us to.
649 */
650 phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_ABYTE_CNT );
651 udelay ( 100 ); /* according to PRM */
652 phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
653
654 /* Read data, if applicable */
655 if ( data_in ) {
656 data = phantom_readl ( phantom, UNM_ROMUSB_ROM_RDATA );
657 memcpy ( data_in, &data, sizeof ( data ) );
658 DBGCP_HDA ( phantom, address, data_in, len );
659 }
660
661 err_wait:
662 phantom_spi_unlock ( phantom );
663 err_lock:
664 return rc;
665 }
666
667 /***************************************************************************
668 *
669 * Firmware interface
670 *
671 */
672
673 /**
674 * Wait for firmware to accept command
675 *
676 * @v phantom Phantom NIC
677 * @ret rc Return status code
678 */
679 static int phantom_wait_for_cmd ( struct phantom_nic *phantom ) {
680 unsigned int retries;
681 uint32_t cdrp;
682
683 for ( retries = 0 ; retries < PHN_ISSUE_CMD_TIMEOUT_MS ; retries++ ) {
684 mdelay ( 1 );
685 cdrp = phantom_readl ( phantom, UNM_NIC_REG_NX_CDRP );
686 if ( NX_CDRP_IS_RSP ( cdrp ) ) {
687 switch ( NX_CDRP_FORM_RSP ( cdrp ) ) {
688 case NX_CDRP_RSP_OK:
689 return 0;
690 case NX_CDRP_RSP_FAIL:
691 return -EIO;
692 case NX_CDRP_RSP_TIMEOUT:
693 return -ETIMEDOUT;
694 default:
695 return -EPROTO;
696 }
697 }
698 }
699
700 DBGC ( phantom, "Phantom %p timed out waiting for firmware to accept "
701 "command\n", phantom );
702 return -ETIMEDOUT;
703 }
704
705 /**
706 * Issue command to firmware
707 *
708 * @v phantom_port Phantom NIC port
709 * @v command Firmware command
710 * @v arg1 Argument 1
711 * @v arg2 Argument 2
712 * @v arg3 Argument 3
713 * @ret rc Return status code
714 */
715 static int phantom_issue_cmd ( struct phantom_nic_port *phantom_port,
716 uint32_t command, uint32_t arg1, uint32_t arg2,
717 uint32_t arg3 ) {
718 struct phantom_nic *phantom = phantom_port->phantom;
719 uint32_t signature;
720 int rc;
721
722 /* Issue command */
723 signature = NX_CDRP_SIGNATURE_MAKE ( phantom_port->port,
724 NXHAL_VERSION );
725 DBGC2 ( phantom, "Phantom %p port %d issuing command %08lx (%08lx, "
726 "%08lx, %08lx)\n", phantom, phantom_port->port,
727 command, arg1, arg2, arg3 );
728 phantom_writel ( phantom, signature, UNM_NIC_REG_NX_SIGN );
729 phantom_writel ( phantom, arg1, UNM_NIC_REG_NX_ARG1 );
730 phantom_writel ( phantom, arg2, UNM_NIC_REG_NX_ARG2 );
731 phantom_writel ( phantom, arg3, UNM_NIC_REG_NX_ARG3 );
732 phantom_writel ( phantom, NX_CDRP_FORM_CMD ( command ),
733 UNM_NIC_REG_NX_CDRP );
734
735 /* Wait for command to be accepted */
736 if ( ( rc = phantom_wait_for_cmd ( phantom ) ) != 0 ) {
737 DBGC ( phantom, "Phantom %p could not issue command: %s\n",
738 phantom, strerror ( rc ) );
739 return rc;
740 }
741
742 return 0;
743 }
744
745 /**
746 * Issue buffer-format command to firmware
747 *
748 * @v phantom_port Phantom NIC port
749 * @v command Firmware command
750 * @v buffer Buffer to pass to firmware
751 * @v len Length of buffer
752 * @ret rc Return status code
753 */
754 static int phantom_issue_buf_cmd ( struct phantom_nic_port *phantom_port,
755 uint32_t command, void *buffer,
756 size_t len ) {
757 uint64_t physaddr;
758
759 physaddr = virt_to_bus ( buffer );
760 return phantom_issue_cmd ( phantom_port, command, ( physaddr >> 32 ),
761 ( physaddr & 0xffffffffUL ), len );
762 }
763
764 /**
765 * Create Phantom RX context
766 *
767 * @v phantom_port Phantom NIC port
768 * @ret rc Return status code
769 */
770 static int phantom_create_rx_ctx ( struct phantom_nic_port *phantom_port ) {
771 struct phantom_nic *phantom = phantom_port->phantom;
772 struct phantom_create_rx_ctx_rqrsp *buf;
773 int rc;
774
775 /* Prepare request */
776 buf = &phantom->dma_buf->create_rx_ctx;
777 memset ( buf, 0, sizeof ( *buf ) );
778 buf->hostrq.rx_ctx.host_rsp_dma_addr =
779 cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
780 buf->hostrq.rx_ctx.capabilities[0] =
781 cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
782 buf->hostrq.rx_ctx.host_int_crb_mode =
783 cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
784 buf->hostrq.rx_ctx.host_rds_crb_mode =
785 cpu_to_le32 ( NX_HOST_RDS_CRB_MODE_UNIQUE );
786 buf->hostrq.rx_ctx.rds_ring_offset = cpu_to_le32 ( 0 );
787 buf->hostrq.rx_ctx.sds_ring_offset =
788 cpu_to_le32 ( sizeof ( buf->hostrq.rds ) );
789 buf->hostrq.rx_ctx.num_rds_rings = cpu_to_le16 ( 1 );
790 buf->hostrq.rx_ctx.num_sds_rings = cpu_to_le16 ( 1 );
791 buf->hostrq.rds.host_phys_addr =
792 cpu_to_le64 ( virt_to_bus ( phantom_port->desc->rds ) );
793 buf->hostrq.rds.buff_size = cpu_to_le64 ( PHN_RX_BUFSIZE );
794 buf->hostrq.rds.ring_size = cpu_to_le32 ( PHN_NUM_RDS );
795 buf->hostrq.rds.ring_kind = cpu_to_le32 ( NX_RDS_RING_TYPE_NORMAL );
796 buf->hostrq.sds.host_phys_addr =
797 cpu_to_le64 ( virt_to_bus ( phantom_port->desc->sds ) );
798 buf->hostrq.sds.ring_size = cpu_to_le32 ( PHN_NUM_SDS );
799
800 DBGC ( phantom, "Phantom %p port %d creating RX context\n",
801 phantom, phantom_port->port );
802 DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
803 &buf->hostrq, sizeof ( buf->hostrq ) );
804
805 /* Issue request */
806 if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
807 NX_CDRP_CMD_CREATE_RX_CTX,
808 &buf->hostrq,
809 sizeof ( buf->hostrq ) ) ) != 0 ) {
810 DBGC ( phantom, "Phantom %p port %d could not create RX "
811 "context: %s\n",
812 phantom, phantom_port->port, strerror ( rc ) );
813 DBGC ( phantom, "Request:\n" );
814 DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
815 &buf->hostrq, sizeof ( buf->hostrq ) );
816 DBGC ( phantom, "Response:\n" );
817 DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
818 &buf->cardrsp, sizeof ( buf->cardrsp ) );
819 return rc;
820 }
821
822 /* Retrieve context parameters */
823 phantom_port->rx_context_id =
824 le16_to_cpu ( buf->cardrsp.rx_ctx.context_id );
825 phantom_port->rds_producer_crb =
826 ( UNM_CAM_RAM +
827 le32_to_cpu ( buf->cardrsp.rds.host_producer_crb ));
828 phantom_port->sds_consumer_crb =
829 ( UNM_CAM_RAM +
830 le32_to_cpu ( buf->cardrsp.sds.host_consumer_crb ));
831
832 DBGC ( phantom, "Phantom %p port %d created RX context (id %04x, "
833 "port phys %02x virt %02x)\n", phantom, phantom_port->port,
834 phantom_port->rx_context_id, buf->cardrsp.rx_ctx.phys_port,
835 buf->cardrsp.rx_ctx.virt_port );
836 DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
837 &buf->cardrsp, sizeof ( buf->cardrsp ) );
838 DBGC ( phantom, "Phantom %p port %d RDS producer CRB is %08lx\n",
839 phantom, phantom_port->port, phantom_port->rds_producer_crb );
840 DBGC ( phantom, "Phantom %p port %d SDS consumer CRB is %08lx\n",
841 phantom, phantom_port->port, phantom_port->sds_consumer_crb );
842
843 return 0;
844 }
845
846 /**
847 * Destroy Phantom RX context
848 *
849 * @v phantom_port Phantom NIC port
850 * @ret rc Return status code
851 */
852 static void phantom_destroy_rx_ctx ( struct phantom_nic_port *phantom_port ) {
853 struct phantom_nic *phantom = phantom_port->phantom;
854 int rc;
855
856 DBGC ( phantom, "Phantom %p port %d destroying RX context (id %04x)\n",
857 phantom, phantom_port->port, phantom_port->rx_context_id );
858
859 /* Issue request */
860 if ( ( rc = phantom_issue_cmd ( phantom_port,
861 NX_CDRP_CMD_DESTROY_RX_CTX,
862 phantom_port->rx_context_id,
863 NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
864 DBGC ( phantom, "Phantom %p port %d could not destroy RX "
865 "context: %s\n",
866 phantom, phantom_port->port, strerror ( rc ) );
867 /* We're probably screwed */
868 return;
869 }
870
871 /* Clear context parameters */
872 phantom_port->rx_context_id = 0;
873 phantom_port->rds_producer_crb = 0;
874 phantom_port->sds_consumer_crb = 0;
875
876 /* Reset software counters */
877 phantom_port->rds_producer_idx = 0;
878 phantom_port->rds_consumer_idx = 0;
879 phantom_port->sds_consumer_idx = 0;
880 }
881
882 /**
883 * Create Phantom TX context
884 *
885 * @v phantom_port Phantom NIC port
886 * @ret rc Return status code
887 */
888 static int phantom_create_tx_ctx ( struct phantom_nic_port *phantom_port ) {
889 struct phantom_nic *phantom = phantom_port->phantom;
890 struct phantom_create_tx_ctx_rqrsp *buf;
891 int rc;
892
893 /* Prepare request */
894 buf = &phantom->dma_buf->create_tx_ctx;
895 memset ( buf, 0, sizeof ( *buf ) );
896 buf->hostrq.tx_ctx.host_rsp_dma_addr =
897 cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
898 buf->hostrq.tx_ctx.cmd_cons_dma_addr =
899 cpu_to_le64 ( virt_to_bus ( &phantom_port->desc->cmd_cons ) );
900 buf->hostrq.tx_ctx.dummy_dma_addr =
901 cpu_to_le64 ( virt_to_bus ( phantom->dma_buf->dummy_dma ) );
902 buf->hostrq.tx_ctx.capabilities[0] =
903 cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
904 buf->hostrq.tx_ctx.host_int_crb_mode =
905 cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
906 buf->hostrq.tx_ctx.cds_ring.host_phys_addr =
907 cpu_to_le64 ( virt_to_bus ( phantom_port->desc->cds ) );
908 buf->hostrq.tx_ctx.cds_ring.ring_size = cpu_to_le32 ( PHN_NUM_CDS );
909
910 DBGC ( phantom, "Phantom %p port %d creating TX context\n",
911 phantom, phantom_port->port );
912 DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
913 &buf->hostrq, sizeof ( buf->hostrq ) );
914
915 /* Issue request */
916 if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
917 NX_CDRP_CMD_CREATE_TX_CTX,
918 &buf->hostrq,
919 sizeof ( buf->hostrq ) ) ) != 0 ) {
920 DBGC ( phantom, "Phantom %p port %d could not create TX "
921 "context: %s\n",
922 phantom, phantom_port->port, strerror ( rc ) );
923 DBGC ( phantom, "Request:\n" );
924 DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
925 &buf->hostrq, sizeof ( buf->hostrq ) );
926 DBGC ( phantom, "Response:\n" );
927 DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
928 &buf->cardrsp, sizeof ( buf->cardrsp ) );
929 return rc;
930 }
931
932 /* Retrieve context parameters */
933 phantom_port->tx_context_id =
934 le16_to_cpu ( buf->cardrsp.tx_ctx.context_id );
935 phantom_port->cds_producer_crb =
936 ( UNM_CAM_RAM +
937 le32_to_cpu(buf->cardrsp.tx_ctx.cds_ring.host_producer_crb));
938
939 DBGC ( phantom, "Phantom %p port %d created TX context (id %04x, "
940 "port phys %02x virt %02x)\n", phantom, phantom_port->port,
941 phantom_port->tx_context_id, buf->cardrsp.tx_ctx.phys_port,
942 buf->cardrsp.tx_ctx.virt_port );
943 DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
944 &buf->cardrsp, sizeof ( buf->cardrsp ) );
945 DBGC ( phantom, "Phantom %p port %d CDS producer CRB is %08lx\n",
946 phantom, phantom_port->port, phantom_port->cds_producer_crb );
947
948 return 0;
949 }
950
951 /**
952 * Destroy Phantom TX context
953 *
954 * @v phantom_port Phantom NIC port
955 * @ret rc Return status code
956 */
957 static void phantom_destroy_tx_ctx ( struct phantom_nic_port *phantom_port ) {
958 struct phantom_nic *phantom = phantom_port->phantom;
959 int rc;
960
961 DBGC ( phantom, "Phantom %p port %d destroying TX context (id %04x)\n",
962 phantom, phantom_port->port, phantom_port->tx_context_id );
963
964 /* Issue request */
965 if ( ( rc = phantom_issue_cmd ( phantom_port,
966 NX_CDRP_CMD_DESTROY_TX_CTX,
967 phantom_port->tx_context_id,
968 NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
969 DBGC ( phantom, "Phantom %p port %d could not destroy TX "
970 "context: %s\n",
971 phantom, phantom_port->port, strerror ( rc ) );
972 /* We're probably screwed */
973 return;
974 }
975
976 /* Clear context parameters */
977 phantom_port->tx_context_id = 0;
978 phantom_port->cds_producer_crb = 0;
979
980 /* Reset software counters */
981 phantom_port->cds_producer_idx = 0;
982 phantom_port->cds_consumer_idx = 0;
983 }
984
985 /***************************************************************************
986 *
987 * Descriptor ring management
988 *
989 */
990
991 /**
992 * Allocate Phantom RX descriptor
993 *
994 * @v phantom_port Phantom NIC port
995 * @ret index RX descriptor index, or negative error
996 */
997 static int phantom_alloc_rds ( struct phantom_nic_port *phantom_port ) {
998 struct phantom_nic *phantom = phantom_port->phantom;
999 unsigned int rds_producer_idx;
1000 unsigned int next_rds_producer_idx;
1001
1002 /* Check for space in the ring. RX descriptors are consumed
1003 * out of order, but they are *read* by the hardware in strict
1004 * order. We maintain a pessimistic consumer index, which is
1005 * guaranteed never to be an overestimate of the number of
1006 * descriptors read by the hardware.
1007 */
1008 rds_producer_idx = phantom_port->rds_producer_idx;
1009 next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
1010 if ( next_rds_producer_idx == phantom_port->rds_consumer_idx ) {
1011 DBGC ( phantom, "Phantom %p port %d RDS ring full (index %d "
1012 "not consumed)\n", phantom, phantom_port->port,
1013 next_rds_producer_idx );
1014 return -ENOBUFS;
1015 }
1016
1017 return rds_producer_idx;
1018 }
1019
1020 /**
1021 * Post Phantom RX descriptor
1022 *
1023 * @v phantom_port Phantom NIC port
1024 * @v rds RX descriptor
1025 */
1026 static void phantom_post_rds ( struct phantom_nic_port *phantom_port,
1027 struct phantom_rds *rds ) {
1028 struct phantom_nic *phantom = phantom_port->phantom;
1029 unsigned int rds_producer_idx;
1030 unsigned int next_rds_producer_idx;
1031 struct phantom_rds *entry;
1032
1033 /* Copy descriptor to ring */
1034 rds_producer_idx = phantom_port->rds_producer_idx;
1035 entry = &phantom_port->desc->rds[rds_producer_idx];
1036 memcpy ( entry, rds, sizeof ( *entry ) );
1037 DBGC2 ( phantom, "Phantom %p port %d posting RDS %ld (slot %d):\n",
1038 phantom, phantom_port->port, NX_GET ( rds, handle ),
1039 rds_producer_idx );
1040 DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
1041
1042 /* Update producer index */
1043 next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
1044 phantom_port->rds_producer_idx = next_rds_producer_idx;
1045 wmb();
1046 phantom_writel ( phantom, phantom_port->rds_producer_idx,
1047 phantom_port->rds_producer_crb );
1048 }
1049
1050 /**
1051 * Allocate Phantom TX descriptor
1052 *
1053 * @v phantom_port Phantom NIC port
1054 * @ret index TX descriptor index, or negative error
1055 */
1056 static int phantom_alloc_cds ( struct phantom_nic_port *phantom_port ) {
1057 struct phantom_nic *phantom = phantom_port->phantom;
1058 unsigned int cds_producer_idx;
1059 unsigned int next_cds_producer_idx;
1060
1061 /* Check for space in the ring. TX descriptors are consumed
1062 * in strict order, so we just check for a collision against
1063 * the consumer index.
1064 */
1065 cds_producer_idx = phantom_port->cds_producer_idx;
1066 next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
1067 if ( next_cds_producer_idx == phantom_port->cds_consumer_idx ) {
1068 DBGC ( phantom, "Phantom %p port %d CDS ring full (index %d "
1069 "not consumed)\n", phantom, phantom_port->port,
1070 next_cds_producer_idx );
1071 return -ENOBUFS;
1072 }
1073
1074 return cds_producer_idx;
1075 }
1076
1077 /**
1078 * Post Phantom TX descriptor
1079 *
1080 * @v phantom_port Phantom NIC port
1081 * @v cds TX descriptor
1082 */
1083 static void phantom_post_cds ( struct phantom_nic_port *phantom_port,
1084 union phantom_cds *cds ) {
1085 struct phantom_nic *phantom = phantom_port->phantom;
1086 unsigned int cds_producer_idx;
1087 unsigned int next_cds_producer_idx;
1088 union phantom_cds *entry;
1089
1090 /* Copy descriptor to ring */
1091 cds_producer_idx = phantom_port->cds_producer_idx;
1092 entry = &phantom_port->desc->cds[cds_producer_idx];
1093 memcpy ( entry, cds, sizeof ( *entry ) );
1094 DBGC2 ( phantom, "Phantom %p port %d posting CDS %d:\n",
1095 phantom, phantom_port->port, cds_producer_idx );
1096 DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
1097
1098 /* Update producer index */
1099 next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
1100 phantom_port->cds_producer_idx = next_cds_producer_idx;
1101 wmb();
1102 phantom_writel ( phantom, phantom_port->cds_producer_idx,
1103 phantom_port->cds_producer_crb );
1104 }
1105
1106 /***************************************************************************
1107 *
1108 * MAC address management
1109 *
1110 */
1111
1112 /**
1113 * Add/remove MAC address
1114 *
1115 * @v phantom_port Phantom NIC port
1116 * @v ll_addr MAC address to add or remove
1117 * @v opcode MAC request opcode
1118 * @ret rc Return status code
1119 */
1120 static int phantom_update_macaddr ( struct phantom_nic_port *phantom_port,
1121 const uint8_t *ll_addr,
1122 unsigned int opcode ) {
1123 union phantom_cds cds;
1124 int index;
1125
1126 /* Get descriptor ring entry */
1127 index = phantom_alloc_cds ( phantom_port );
1128 if ( index < 0 )
1129 return index;
1130
1131 /* Fill descriptor ring entry */
1132 memset ( &cds, 0, sizeof ( cds ) );
1133 NX_FILL_1 ( &cds, 0,
1134 nic_request.common.opcode, UNM_NIC_REQUEST );
1135 NX_FILL_2 ( &cds, 1,
1136 nic_request.header.opcode, UNM_MAC_EVENT,
1137 nic_request.header.context_id, phantom_port->port );
1138 NX_FILL_7 ( &cds, 2,
1139 nic_request.body.mac_request.opcode, opcode,
1140 nic_request.body.mac_request.mac_addr_0, ll_addr[0],
1141 nic_request.body.mac_request.mac_addr_1, ll_addr[1],
1142 nic_request.body.mac_request.mac_addr_2, ll_addr[2],
1143 nic_request.body.mac_request.mac_addr_3, ll_addr[3],
1144 nic_request.body.mac_request.mac_addr_4, ll_addr[4],
1145 nic_request.body.mac_request.mac_addr_5, ll_addr[5] );
1146
1147 /* Post descriptor */
1148 phantom_post_cds ( phantom_port, &cds );
1149
1150 return 0;
1151 }
1152
1153 /**
1154 * Add MAC address
1155 *
1156 * @v phantom_port Phantom NIC port
1157 * @v ll_addr MAC address to add or remove
1158 * @ret rc Return status code
1159 */
1160 static inline int phantom_add_macaddr ( struct phantom_nic_port *phantom_port,
1161 const uint8_t *ll_addr ) {
1162 struct phantom_nic *phantom = phantom_port->phantom;
1163
1164 DBGC ( phantom, "Phantom %p port %d adding MAC address %s\n",
1165 phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
1166
1167 return phantom_update_macaddr ( phantom_port, ll_addr, UNM_MAC_ADD );
1168 }
1169
1170 /**
1171 * Remove MAC address
1172 *
1173 * @v phantom_port Phantom NIC port
1174 * @v ll_addr MAC address to add or remove
1175 * @ret rc Return status code
1176 */
1177 static inline int phantom_del_macaddr ( struct phantom_nic_port *phantom_port,
1178 const uint8_t *ll_addr ) {
1179 struct phantom_nic *phantom = phantom_port->phantom;
1180
1181 DBGC ( phantom, "Phantom %p port %d removing MAC address %s\n",
1182 phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
1183
1184 return phantom_update_macaddr ( phantom_port, ll_addr, UNM_MAC_DEL );
1185 }
1186
1187 /***************************************************************************
1188 *
1189 * Link state detection
1190 *
1191 */
1192
1193 /**
1194 * Poll link state
1195 *
1196 * @v phantom Phantom NIC
1197 */
1198 static void phantom_poll_link_state ( struct phantom_nic *phantom ) {
1199 struct net_device *netdev;
1200 struct phantom_nic_port *phantom_port;
1201 uint32_t xg_state_p3;
1202 unsigned int link;
1203 int i;
1204
1205 /* Read link state */
1206 xg_state_p3 = phantom_readl ( phantom, UNM_NIC_REG_XG_STATE_P3 );
1207
1208 /* If there is no change, do nothing */
1209 if ( phantom->link_state == xg_state_p3 )
1210 return;
1211
1212 /* Record new link state */
1213 DBGC ( phantom, "Phantom %p new link state %08lx (was %08lx)\n",
1214 phantom, xg_state_p3, phantom->link_state );
1215 phantom->link_state = xg_state_p3;
1216
1217 /* Indicate per-port link state to gPXE */
1218 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
1219 netdev = phantom->netdev[i];
1220 phantom_port = netdev_priv ( netdev );
1221 link = UNM_NIC_REG_XG_STATE_P3_LINK ( phantom_port->port,
1222 phantom->link_state );
1223 switch ( link ) {
1224 case UNM_NIC_REG_XG_STATE_P3_LINK_UP:
1225 DBGC ( phantom, "Phantom %p port %d link is up\n",
1226 phantom, phantom_port->port );
1227 netdev_link_up ( netdev );
1228 break;
1229 case UNM_NIC_REG_XG_STATE_P3_LINK_DOWN:
1230 DBGC ( phantom, "Phantom %p port %d link is down\n",
1231 phantom, phantom_port->port );
1232 netdev_link_down ( netdev );
1233 break;
1234 default:
1235 DBGC ( phantom, "Phantom %p port %d bad link state "
1236 "%d\n", phantom, phantom_port->port, link );
1237 break;
1238 }
1239 }
1240 }
1241
1242 /***************************************************************************
1243 *
1244 * Main driver body
1245 *
1246 */
1247
1248 /**
1249 * Refill descriptor ring
1250 *
1251 * @v netdev Net device
1252 */
1253 static void phantom_refill_rx_ring ( struct net_device *netdev ) {
1254 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1255 struct io_buffer *iobuf;
1256 struct phantom_rds rds;
1257 unsigned int handle;
1258 int index;
1259
1260 for ( handle = 0 ; handle < PHN_RDS_MAX_FILL ; handle++ ) {
1261
1262 /* Skip this index if the descriptor has not yet been
1263 * consumed.
1264 */
1265 if ( phantom_port->rds_iobuf[handle] != NULL )
1266 continue;
1267
1268 /* Allocate descriptor ring entry */
1269 index = phantom_alloc_rds ( phantom_port );
1270 assert ( PHN_RDS_MAX_FILL < PHN_NUM_RDS );
1271 assert ( index >= 0 ); /* Guaranteed by MAX_FILL < NUM_RDS ) */
1272
1273 /* Try to allocate an I/O buffer */
1274 iobuf = alloc_iob ( PHN_RX_BUFSIZE );
1275 if ( ! iobuf ) {
1276 /* Failure is non-fatal; we will retry later */
1277 netdev_rx_err ( netdev, NULL, -ENOMEM );
1278 break;
1279 }
1280
1281 /* Fill descriptor ring entry */
1282 memset ( &rds, 0, sizeof ( rds ) );
1283 NX_FILL_2 ( &rds, 0,
1284 handle, handle,
1285 length, iob_len ( iobuf ) );
1286 NX_FILL_1 ( &rds, 1,
1287 dma_addr, virt_to_bus ( iobuf->data ) );
1288
1289 /* Record I/O buffer */
1290 assert ( phantom_port->rds_iobuf[handle] == NULL );
1291 phantom_port->rds_iobuf[handle] = iobuf;
1292
1293 /* Post descriptor */
1294 phantom_post_rds ( phantom_port, &rds );
1295 }
1296 }
1297
1298 /**
1299 * Open NIC
1300 *
1301 * @v netdev Net device
1302 * @ret rc Return status code
1303 */
1304 static int phantom_open ( struct net_device *netdev ) {
1305 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1306 int rc;
1307
1308 /* Allocate and zero descriptor rings */
1309 phantom_port->desc = malloc_dma ( sizeof ( *(phantom_port->desc) ),
1310 UNM_DMA_BUFFER_ALIGN );
1311 if ( ! phantom_port->desc ) {
1312 rc = -ENOMEM;
1313 goto err_alloc_desc;
1314 }
1315 memset ( phantom_port->desc, 0, sizeof ( *(phantom_port->desc) ) );
1316
1317 /* Create RX context */
1318 if ( ( rc = phantom_create_rx_ctx ( phantom_port ) ) != 0 )
1319 goto err_create_rx_ctx;
1320
1321 /* Create TX context */
1322 if ( ( rc = phantom_create_tx_ctx ( phantom_port ) ) != 0 )
1323 goto err_create_tx_ctx;
1324
1325 /* Fill the RX descriptor ring */
1326 phantom_refill_rx_ring ( netdev );
1327
1328 /* Add MAC addresses
1329 *
1330 * BUG5583
1331 *
1332 * We would like to be able to enable receiving all multicast
1333 * packets (or, failing that, promiscuous mode), but the
1334 * firmware doesn't currently support this.
1335 */
1336 if ( ( rc = phantom_add_macaddr ( phantom_port,
1337 netdev->ll_protocol->ll_broadcast ) ) != 0 )
1338 goto err_add_macaddr_broadcast;
1339 if ( ( rc = phantom_add_macaddr ( phantom_port,
1340 netdev->ll_addr ) ) != 0 )
1341 goto err_add_macaddr_unicast;
1342
1343 return 0;
1344
1345 phantom_del_macaddr ( phantom_port, netdev->ll_addr );
1346 err_add_macaddr_unicast:
1347 phantom_del_macaddr ( phantom_port,
1348 netdev->ll_protocol->ll_broadcast );
1349 err_add_macaddr_broadcast:
1350 phantom_destroy_tx_ctx ( phantom_port );
1351 err_create_tx_ctx:
1352 phantom_destroy_rx_ctx ( phantom_port );
1353 err_create_rx_ctx:
1354 free_dma ( phantom_port->desc, sizeof ( *(phantom_port->desc) ) );
1355 phantom_port->desc = NULL;
1356 err_alloc_desc:
1357 return rc;
1358 }
1359
1360 /**
1361 * Close NIC
1362 *
1363 * @v netdev Net device
1364 */
1365 static void phantom_close ( struct net_device *netdev ) {
1366 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1367 struct io_buffer *iobuf;
1368 unsigned int i;
1369
1370 /* Shut down the port */
1371 phantom_del_macaddr ( phantom_port, netdev->ll_addr );
1372 phantom_del_macaddr ( phantom_port,
1373 netdev->ll_protocol->ll_broadcast );
1374 phantom_destroy_tx_ctx ( phantom_port );
1375 phantom_destroy_rx_ctx ( phantom_port );
1376 free_dma ( phantom_port->desc, sizeof ( *(phantom_port->desc) ) );
1377 phantom_port->desc = NULL;
1378
1379 /* Flush any uncompleted descriptors */
1380 for ( i = 0 ; i < PHN_RDS_MAX_FILL ; i++ ) {
1381 iobuf = phantom_port->rds_iobuf[i];
1382 if ( iobuf ) {
1383 free_iob ( iobuf );
1384 phantom_port->rds_iobuf[i] = NULL;
1385 }
1386 }
1387 for ( i = 0 ; i < PHN_NUM_CDS ; i++ ) {
1388 iobuf = phantom_port->cds_iobuf[i];
1389 if ( iobuf ) {
1390 netdev_tx_complete_err ( netdev, iobuf, -ECANCELED );
1391 phantom_port->cds_iobuf[i] = NULL;
1392 }
1393 }
1394 }
1395
1396 /**
1397 * Transmit packet
1398 *
1399 * @v netdev Network device
1400 * @v iobuf I/O buffer
1401 * @ret rc Return status code
1402 */
1403 static int phantom_transmit ( struct net_device *netdev,
1404 struct io_buffer *iobuf ) {
1405 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1406 union phantom_cds cds;
1407 int index;
1408
1409 /* Get descriptor ring entry */
1410 index = phantom_alloc_cds ( phantom_port );
1411 if ( index < 0 )
1412 return index;
1413
1414 /* Fill descriptor ring entry */
1415 memset ( &cds, 0, sizeof ( cds ) );
1416 NX_FILL_3 ( &cds, 0,
1417 tx.opcode, UNM_TX_ETHER_PKT,
1418 tx.num_buffers, 1,
1419 tx.length, iob_len ( iobuf ) );
1420 NX_FILL_2 ( &cds, 2,
1421 tx.port, phantom_port->port,
1422 tx.context_id, phantom_port->port );
1423 NX_FILL_1 ( &cds, 4,
1424 tx.buffer1_dma_addr, virt_to_bus ( iobuf->data ) );
1425 NX_FILL_1 ( &cds, 5,
1426 tx.buffer1_length, iob_len ( iobuf ) );
1427
1428 /* Record I/O buffer */
1429 assert ( phantom_port->cds_iobuf[index] == NULL );
1430 phantom_port->cds_iobuf[index] = iobuf;
1431
1432 /* Post descriptor */
1433 phantom_post_cds ( phantom_port, &cds );
1434
1435 return 0;
1436 }
1437
1438 /**
1439 * Poll for received packets
1440 *
1441 * @v netdev Network device
1442 */
1443 static void phantom_poll ( struct net_device *netdev ) {
1444 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1445 struct phantom_nic *phantom = phantom_port->phantom;
1446 struct io_buffer *iobuf;
1447 unsigned int cds_consumer_idx;
1448 unsigned int raw_new_cds_consumer_idx;
1449 unsigned int new_cds_consumer_idx;
1450 unsigned int rds_consumer_idx;
1451 unsigned int sds_consumer_idx;
1452 struct phantom_sds *sds;
1453 unsigned int sds_handle;
1454 unsigned int sds_opcode;
1455
1456 /* Check for TX completions */
1457 cds_consumer_idx = phantom_port->cds_consumer_idx;
1458 raw_new_cds_consumer_idx = phantom_port->desc->cmd_cons;
1459 new_cds_consumer_idx = le32_to_cpu ( raw_new_cds_consumer_idx );
1460 while ( cds_consumer_idx != new_cds_consumer_idx ) {
1461 DBGC2 ( phantom, "Phantom %p port %d CDS %d complete\n",
1462 phantom, phantom_port->port, cds_consumer_idx );
1463 /* Completions may be for commands other than TX, so
1464 * there may not always be an associated I/O buffer.
1465 */
1466 if ( ( iobuf = phantom_port->cds_iobuf[cds_consumer_idx] ) ) {
1467 netdev_tx_complete ( netdev, iobuf );
1468 phantom_port->cds_iobuf[cds_consumer_idx] = NULL;
1469 }
1470 cds_consumer_idx = ( ( cds_consumer_idx + 1 ) % PHN_NUM_CDS );
1471 phantom_port->cds_consumer_idx = cds_consumer_idx;
1472 }
1473
1474 /* Check for received packets */
1475 rds_consumer_idx = phantom_port->rds_consumer_idx;
1476 sds_consumer_idx = phantom_port->sds_consumer_idx;
1477 while ( 1 ) {
1478 sds = &phantom_port->desc->sds[sds_consumer_idx];
1479 if ( NX_GET ( sds, owner ) == 0 )
1480 break;
1481
1482 DBGC2 ( phantom, "Phantom %p port %d SDS %d status:\n",
1483 phantom, phantom_port->port, sds_consumer_idx );
1484 DBGC2_HDA ( phantom, virt_to_bus ( sds ), sds, sizeof (*sds) );
1485
1486 /* Check received opcode */
1487 sds_opcode = NX_GET ( sds, opcode );
1488 if ( ( sds_opcode == UNM_RXPKT_DESC ) ||
1489 ( sds_opcode == UNM_SYN_OFFLOAD ) ) {
1490
1491 /* Sanity check: ensure that all of the SDS
1492 * descriptor has been written.
1493 */
1494 if ( NX_GET ( sds, total_length ) == 0 ) {
1495 DBGC ( phantom, "Phantom %p port %d SDS %d "
1496 "incomplete; deferring\n", phantom,
1497 phantom_port->port, sds_consumer_idx );
1498 /* Leave for next poll() */
1499 break;
1500 }
1501
1502 /* Process received packet */
1503 sds_handle = NX_GET ( sds, handle );
1504 iobuf = phantom_port->rds_iobuf[sds_handle];
1505 assert ( iobuf != NULL );
1506 iob_put ( iobuf, NX_GET ( sds, total_length ) );
1507 iob_pull ( iobuf, NX_GET ( sds, pkt_offset ) );
1508 DBGC2 ( phantom, "Phantom %p port %d RDS %d "
1509 "complete\n",
1510 phantom, phantom_port->port, sds_handle );
1511 netdev_rx ( netdev, iobuf );
1512 phantom_port->rds_iobuf[sds_handle] = NULL;
1513
1514 /* Update RDS consumer counter. This is a
1515 * lower bound for the number of descriptors
1516 * that have been read by the hardware, since
1517 * the hardware must have read at least one
1518 * descriptor for each completion that we
1519 * receive.
1520 */
1521 rds_consumer_idx =
1522 ( ( rds_consumer_idx + 1 ) % PHN_NUM_RDS );
1523 phantom_port->rds_consumer_idx = rds_consumer_idx;
1524
1525 } else {
1526
1527 DBGC ( phantom, "Phantom %p port %d unexpected SDS "
1528 "opcode %02x\n",
1529 phantom, phantom_port->port, sds_opcode );
1530 DBGC_HDA ( phantom, virt_to_bus ( sds ),
1531 sds, sizeof ( *sds ) );
1532 }
1533
1534 /* Clear status descriptor */
1535 memset ( sds, 0, sizeof ( *sds ) );
1536
1537 /* Update SDS consumer index */
1538 sds_consumer_idx = ( ( sds_consumer_idx + 1 ) % PHN_NUM_SDS );
1539 phantom_port->sds_consumer_idx = sds_consumer_idx;
1540 wmb();
1541 phantom_writel ( phantom, phantom_port->sds_consumer_idx,
1542 phantom_port->sds_consumer_crb );
1543 }
1544
1545 /* Refill the RX descriptor ring */
1546 phantom_refill_rx_ring ( netdev );
1547
1548 /* Occasionally poll the link state */
1549 if ( phantom_port->link_poll_timer-- == 0 ) {
1550 phantom_poll_link_state ( phantom );
1551 /* Reset the link poll timer */
1552 phantom_port->link_poll_timer = PHN_LINK_POLL_FREQUENCY;
1553 }
1554 }
1555
1556 /**
1557 * Enable/disable interrupts
1558 *
1559 * @v netdev Network device
1560 * @v enable Interrupts should be enabled
1561 */
1562 static void phantom_irq ( struct net_device *netdev, int enable ) {
1563 struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
1564 struct phantom_nic *phantom = phantom_port->phantom;
1565 static const unsigned long sw_int_mask_reg[UNM_FLASH_NUM_PORTS] = {
1566 UNM_NIC_REG_SW_INT_MASK_0,
1567 UNM_NIC_REG_SW_INT_MASK_1,
1568 UNM_NIC_REG_SW_INT_MASK_2,
1569 UNM_NIC_REG_SW_INT_MASK_3
1570 };
1571
1572 phantom_writel ( phantom,
1573 ( enable ? 1 : 0 ),
1574 sw_int_mask_reg[phantom_port->port] );
1575 }
1576
1577 /** Phantom net device operations */
1578 static struct net_device_operations phantom_operations = {
1579 .open = phantom_open,
1580 .close = phantom_close,
1581 .transmit = phantom_transmit,
1582 .poll = phantom_poll,
1583 .irq = phantom_irq,
1584 };
1585
1586 /***************************************************************************
1587 *
1588 * CLP settings
1589 *
1590 */
1591
1592 /** Phantom CLP data
1593 *
1594 */
1595 union phantom_clp_data {
1596 /** Data bytes
1597 *
1598 * This field is right-aligned; if only N bytes are present
1599 * then bytes[0]..bytes[7-N] should be zero, and the data
1600 * should be in bytes[7-N+1] to bytes[7];
1601 */
1602 uint8_t bytes[8];
1603 /** Dwords for the CLP interface */
1604 struct {
1605 /** High dword, in network byte order */
1606 uint32_t hi;
1607 /** Low dword, in network byte order */
1608 uint32_t lo;
1609 } dwords;
1610 };
1611 #define PHN_CLP_BLKSIZE ( sizeof ( union phantom_clp_data ) )
1612
1613 /**
1614 * Wait for Phantom CLP command to complete
1615 *
1616 * @v phantom Phantom NIC
1617 * @ret rc Return status code
1618 */
1619 static int phantom_clp_wait ( struct phantom_nic *phantom ) {
1620 unsigned int retries;
1621 uint32_t status;
1622
1623 for ( retries = 0 ; retries < PHN_CLP_CMD_TIMEOUT_MS ; retries++ ) {
1624 status = phantom_readl ( phantom, UNM_CAM_RAM_CLP_STATUS );
1625 if ( status & UNM_CAM_RAM_CLP_STATUS_DONE )
1626 return 0;
1627 mdelay ( 1 );
1628 }
1629
1630 DBGC ( phantom, "Phantom %p timed out waiting for CLP command\n",
1631 phantom );
1632 return -ETIMEDOUT;
1633 }
1634
1635 /**
1636 * Issue Phantom CLP command
1637 *
1638 * @v phantom Phantom NIC
1639 * @v port Virtual port number
1640 * @v opcode Opcode
1641 * @v data_in Data in, or NULL
1642 * @v data_out Data out, or NULL
1643 * @v offset Offset within data
1644 * @v len Data buffer length
1645 * @ret len Total transfer length (for reads), or negative error
1646 */
1647 static int phantom_clp_cmd ( struct phantom_nic *phantom, unsigned int port,
1648 unsigned int opcode, const void *data_in,
1649 void *data_out, size_t offset, size_t len ) {
1650 union phantom_clp_data data;
1651 unsigned int index = ( offset / sizeof ( data ) );
1652 unsigned int last = 0;
1653 size_t in_frag_len;
1654 uint8_t *in_frag;
1655 uint32_t command;
1656 uint32_t status;
1657 size_t read_len;
1658 unsigned int error;
1659 size_t out_frag_len;
1660 uint8_t *out_frag;
1661 int rc;
1662
1663 /* Sanity checks */
1664 assert ( ( offset % sizeof ( data ) ) == 0 );
1665 if ( len > 255 ) {
1666 DBGC ( phantom, "Phantom %p invalid CLP length %zd\n",
1667 phantom, len );
1668 return -EINVAL;
1669 }
1670
1671 /* Check that CLP interface is ready */
1672 if ( ( rc = phantom_clp_wait ( phantom ) ) != 0 )
1673 return rc;
1674
1675 /* Copy data in */
1676 memset ( &data, 0, sizeof ( data ) );
1677 if ( data_in ) {
1678 assert ( offset < len );
1679 in_frag_len = ( len - offset );
1680 if ( in_frag_len > sizeof ( data ) ) {
1681 in_frag_len = sizeof ( data );
1682 } else {
1683 last = 1;
1684 }
1685 in_frag = &data.bytes[ sizeof ( data ) - in_frag_len ];
1686 memcpy ( in_frag, ( data_in + offset ), in_frag_len );
1687 phantom_writel ( phantom, be32_to_cpu ( data.dwords.lo ),
1688 UNM_CAM_RAM_CLP_DATA_LO );
1689 phantom_writel ( phantom, be32_to_cpu ( data.dwords.hi ),
1690 UNM_CAM_RAM_CLP_DATA_HI );
1691 }
1692
1693 /* Issue CLP command */
1694 command = ( ( index << 24 ) | ( ( data_in ? len : 0 ) << 16 ) |
1695 ( port << 8 ) | ( last << 7 ) | ( opcode << 0 ) );
1696 phantom_writel ( phantom, command, UNM_CAM_RAM_CLP_COMMAND );
1697 mb();
1698 phantom_writel ( phantom, UNM_CAM_RAM_CLP_STATUS_START,
1699 UNM_CAM_RAM_CLP_STATUS );
1700
1701 /* Wait for command to complete */
1702 if ( ( rc = phantom_clp_wait ( phantom ) ) != 0 )
1703 return rc;
1704
1705 /* Get command status */
1706 status = phantom_readl ( phantom, UNM_CAM_RAM_CLP_STATUS );
1707 read_len = ( ( status >> 16 ) & 0xff );
1708 error = ( ( status >> 8 ) & 0xff );
1709 if ( error ) {
1710 DBGC ( phantom, "Phantom %p CLP command error %02x\n",
1711 phantom, error );
1712 return -EIO;
1713 }
1714
1715 /* Copy data out */
1716 if ( data_out ) {
1717 data.dwords.lo = cpu_to_be32 ( phantom_readl ( phantom,
1718 UNM_CAM_RAM_CLP_DATA_LO ) );
1719 data.dwords.hi = cpu_to_be32 ( phantom_readl ( phantom,
1720 UNM_CAM_RAM_CLP_DATA_HI ) );
1721 out_frag_len = ( read_len - offset );
1722 if ( out_frag_len > sizeof ( data ) )
1723 out_frag_len = sizeof ( data );
1724 out_frag = &data.bytes[ sizeof ( data ) - out_frag_len ];
1725 if ( out_frag_len > ( len - offset ) )
1726 out_frag_len = ( len - offset );
1727 memcpy ( ( data_out + offset ), out_frag, out_frag_len );
1728 }
1729
1730 return read_len;
1731 }
1732
1733 /**
1734 * Store Phantom CLP setting
1735 *
1736 * @v phantom Phantom NIC
1737 * @v port Virtual port number
1738 * @v setting Setting number
1739 * @v data Data buffer
1740 * @v len Length of data buffer
1741 * @ret rc Return status code
1742 */
1743 static int phantom_clp_store ( struct phantom_nic *phantom, unsigned int port,
1744 unsigned int setting, const void *data,
1745 size_t len ) {
1746 unsigned int opcode = setting;
1747 size_t offset;
1748 int rc;
1749
1750 for ( offset = 0 ; offset < len ; offset += PHN_CLP_BLKSIZE ) {
1751 if ( ( rc = phantom_clp_cmd ( phantom, port, opcode, data,
1752 NULL, offset, len ) ) < 0 )
1753 return rc;
1754 }
1755 return 0;
1756 }
1757
1758 /**
1759 * Fetch Phantom CLP setting
1760 *
1761 * @v phantom Phantom NIC
1762 * @v port Virtual port number
1763 * @v setting Setting number
1764 * @v data Data buffer
1765 * @v len Length of data buffer
1766 * @ret len Length of setting, or negative error
1767 */
1768 static int phantom_clp_fetch ( struct phantom_nic *phantom, unsigned int port,
1769 unsigned int setting, void *data, size_t len ) {
1770 unsigned int opcode = ( setting + 1 );
1771 size_t offset = 0;
1772 int read_len;
1773
1774 while ( 1 ) {
1775 read_len = phantom_clp_cmd ( phantom, port, opcode, NULL,
1776 data, offset, len );
1777 if ( read_len < 0 )
1778 return read_len;
1779 offset += PHN_CLP_BLKSIZE;
1780 if ( offset >= ( unsigned ) read_len )
1781 break;
1782 if ( offset >= len )
1783 break;
1784 }
1785 return read_len;
1786 }
1787
1788 /** A Phantom CLP setting */
1789 struct phantom_clp_setting {
1790 /** gPXE setting */
1791 struct setting *setting;
1792 /** Setting number */
1793 unsigned int number;
1794 };
1795
1796 /** Phantom CLP settings */
1797 static struct phantom_clp_setting clp_settings[] = {
1798 { &mac_setting, 0x01 },
1799 };
1800
1801 /**
1802 * Find Phantom CLP setting
1803 *
1804 * @v setting gPXE setting
1805 * @v clp_setting Equivalent Phantom CLP setting, or NULL
1806 */
1807 static struct phantom_clp_setting *
1808 phantom_find_clp_setting ( struct phantom_nic *phantom,
1809 struct setting *setting ) {
1810 struct phantom_clp_setting *clp_setting;
1811 unsigned int i;
1812
1813 for ( i = 0 ; i < ( sizeof ( clp_settings ) /
1814 sizeof ( clp_settings[0] ) ) ; i++ ) {
1815 clp_setting = &clp_settings[i];
1816 if ( setting_cmp ( setting, clp_setting->setting ) == 0 )
1817 return clp_setting;
1818 }
1819
1820 DBGC2 ( phantom, "Phantom %p has no \"%s\" setting\n",
1821 phantom, setting->name );
1822
1823 return NULL;
1824 }
1825
1826 /**
1827 * Store Phantom CLP setting
1828 *
1829 * @v settings Settings block
1830 * @v setting Setting to store
1831 * @v data Setting data, or NULL to clear setting
1832 * @v len Length of setting data
1833 * @ret rc Return status code
1834 */
1835 static int phantom_store_setting ( struct settings *settings,
1836 struct setting *setting,
1837 const void *data, size_t len ) {
1838 struct phantom_nic_port *phantom_port =
1839 container_of ( settings, struct phantom_nic_port, settings );
1840 struct phantom_nic *phantom = phantom_port->phantom;
1841 struct phantom_clp_setting *clp_setting;
1842 int rc;
1843
1844 /* Find Phantom setting equivalent to gPXE setting */
1845 clp_setting = phantom_find_clp_setting ( phantom, setting );
1846 if ( ! clp_setting )
1847 return -ENOTSUP;
1848
1849 /* Store setting */
1850 if ( ( rc = phantom_clp_store ( phantom, phantom_port->port,
1851 clp_setting->number,
1852 data, len ) ) != 0 ) {
1853 DBGC ( phantom, "Phantom %p could not store setting \"%s\": "
1854 "%s\n", phantom, setting->name, strerror ( rc ) );
1855 return rc;
1856 }
1857
1858 return 0;
1859 }
1860
1861 /**
1862 * Fetch Phantom CLP setting
1863 *
1864 * @v settings Settings block
1865 * @v setting Setting to fetch
1866 * @v data Buffer to fill with setting data
1867 * @v len Length of buffer
1868 * @ret len Length of setting data, or negative error
1869 */
1870 static int phantom_fetch_setting ( struct settings *settings,
1871 struct setting *setting,
1872 void *data, size_t len ) {
1873 struct phantom_nic_port *phantom_port =
1874 container_of ( settings, struct phantom_nic_port, settings );
1875 struct phantom_nic *phantom = phantom_port->phantom;
1876 struct phantom_clp_setting *clp_setting;
1877 int read_len;
1878 int rc;
1879
1880 /* Find Phantom setting equivalent to gPXE setting */
1881 clp_setting = phantom_find_clp_setting ( phantom, setting );
1882 if ( ! clp_setting )
1883 return -ENOTSUP;
1884
1885 /* Fetch setting */
1886 if ( ( read_len = phantom_clp_fetch ( phantom, phantom_port->port,
1887 clp_setting->number,
1888 data, len ) ) < 0 ) {
1889 rc = read_len;
1890 DBGC ( phantom, "Phantom %p could not fetch setting \"%s\": "
1891 "%s\n", phantom, setting->name, strerror ( rc ) );
1892 return rc;
1893 }
1894
1895 return read_len;
1896 }
1897
1898 /** Phantom CLP settings operations */
1899 static struct settings_operations phantom_settings_operations = {
1900 .store = phantom_store_setting,
1901 .fetch = phantom_fetch_setting,
1902 };
1903
1904 /***************************************************************************
1905 *
1906 * Initialisation
1907 *
1908 */
1909
1910 /**
1911 * Map Phantom CRB window
1912 *
1913 * @v phantom Phantom NIC
1914 * @ret rc Return status code
1915 */
1916 static int phantom_map_crb ( struct phantom_nic *phantom,
1917 struct pci_device *pci ) {
1918 unsigned long bar0_start;
1919 unsigned long bar0_size;
1920
1921 bar0_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_0 );
1922 bar0_size = pci_bar_size ( pci, PCI_BASE_ADDRESS_0 );
1923 DBGC ( phantom, "Phantom %p BAR0 is %08lx+%lx\n",
1924 phantom, bar0_start, bar0_size );
1925
1926 switch ( bar0_size ) {
1927 case ( 128 * 1024 * 1024 ) :
1928 DBGC ( phantom, "Phantom %p has 128MB BAR\n", phantom );
1929 phantom->crb_access = phantom_crb_access_128m;
1930 break;
1931 case ( 32 * 1024 * 1024 ) :
1932 DBGC ( phantom, "Phantom %p has 32MB BAR\n", phantom );
1933 phantom->crb_access = phantom_crb_access_32m;
1934 break;
1935 case ( 2 * 1024 * 1024 ) :
1936 DBGC ( phantom, "Phantom %p has 2MB BAR\n", phantom );
1937 phantom->crb_access = phantom_crb_access_2m;
1938 break;
1939 default:
1940 DBGC ( phantom, "Phantom %p has bad BAR size\n", phantom );
1941 return -EINVAL;
1942 }
1943
1944 phantom->bar0 = ioremap ( bar0_start, bar0_size );
1945 if ( ! phantom->bar0 ) {
1946 DBGC ( phantom, "Phantom %p could not map BAR0\n", phantom );
1947 return -EIO;
1948 }
1949
1950 /* Mark current CRB window as invalid, so that the first
1951 * read/write will set the current window.
1952 */
1953 phantom->crb_window = -1UL;
1954
1955 return 0;
1956 }
1957
1958 /**
1959 * Read Phantom flash contents
1960 *
1961 * @v phantom Phantom NIC
1962 * @ret rc Return status code
1963 */
1964 static int phantom_read_flash ( struct phantom_nic *phantom ) {
1965 struct unm_board_info board_info;
1966 int rc;
1967
1968 /* Initialise flash access */
1969 phantom->spi_bus.rw = phantom_spi_rw;
1970 phantom->flash.bus = &phantom->spi_bus;
1971 init_m25p32 ( &phantom->flash );
1972 /* Phantom doesn't support greater than 4-byte block sizes */
1973 phantom->flash.nvs.block_size = UNM_SPI_BLKSIZE;
1974
1975 /* Read and verify board information */
1976 if ( ( rc = nvs_read ( &phantom->flash.nvs, UNM_BRDCFG_START,
1977 &board_info, sizeof ( board_info ) ) ) != 0 ) {
1978 DBGC ( phantom, "Phantom %p could not read board info: %s\n",
1979 phantom, strerror ( rc ) );
1980 return rc;
1981 }
1982 if ( board_info.magic != UNM_BDINFO_MAGIC ) {
1983 DBGC ( phantom, "Phantom %p has bad board info magic %lx\n",
1984 phantom, board_info.magic );
1985 DBGC_HD ( phantom, &board_info, sizeof ( board_info ) );
1986 return -EINVAL;
1987 }
1988 if ( board_info.header_version != UNM_BDINFO_VERSION ) {
1989 DBGC ( phantom, "Phantom %p has bad board info version %lx\n",
1990 phantom, board_info.header_version );
1991 DBGC_HD ( phantom, &board_info, sizeof ( board_info ) );
1992 return -EINVAL;
1993 }
1994
1995 /* Identify board type and number of ports */
1996 switch ( board_info.board_type ) {
1997 case UNM_BRDTYPE_P3_4_GB:
1998 case UNM_BRDTYPE_P3_4_GB_MM:
1999 phantom->num_ports = 4;
2000 break;
2001 case UNM_BRDTYPE_P3_HMEZ:
2002 case UNM_BRDTYPE_P3_IMEZ:
2003 case UNM_BRDTYPE_P3_10G_CX4:
2004 case UNM_BRDTYPE_P3_10G_CX4_LP:
2005 case UNM_BRDTYPE_P3_10G_SFP_PLUS:
2006 case UNM_BRDTYPE_P3_XG_LOM:
2007 phantom->num_ports = 2;
2008 break;
2009 case UNM_BRDTYPE_P3_10000_BASE_T:
2010 case UNM_BRDTYPE_P3_10G_XFP:
2011 phantom->num_ports = 1;
2012 break;
2013 default:
2014 DBGC ( phantom, "Phantom %p unrecognised board type %#lx; "
2015 "assuming single-port\n",
2016 phantom, board_info.board_type );
2017 phantom->num_ports = 1;
2018 break;
2019 }
2020 DBGC ( phantom, "Phantom %p board type is %#lx (%d ports)\n",
2021 phantom, board_info.board_type, phantom->num_ports );
2022
2023 return 0;
2024 }
2025
2026 /**
2027 * Halt all PEGs
2028 *
2029 * @v phantom Phantom NIC
2030 */
2031 static void phantom_halt_pegs ( struct phantom_nic *phantom ) {
2032 phantom_writel ( phantom, 1, UNM_PEG_0_HALT );
2033 phantom_writel ( phantom, 1, UNM_PEG_1_HALT );
2034 phantom_writel ( phantom, 1, UNM_PEG_2_HALT );
2035 phantom_writel ( phantom, 1, UNM_PEG_3_HALT );
2036 phantom_writel ( phantom, 1, UNM_PEG_4_HALT );
2037 }
2038
2039 /**
2040 * Unhalt all PEGs
2041 *
2042 * @v phantom Phantom NIC
2043 */
2044 static void phantom_unhalt_pegs ( struct phantom_nic *phantom ) {
2045 uint32_t halt_status;
2046
2047 halt_status = phantom_readl ( phantom, UNM_PEG_0_HALT_STATUS );
2048 phantom_writel ( phantom, halt_status, UNM_PEG_0_HALT_STATUS );
2049 halt_status = phantom_readl ( phantom, UNM_PEG_1_HALT_STATUS );
2050 phantom_writel ( phantom, halt_status, UNM_PEG_1_HALT_STATUS );
2051 halt_status = phantom_readl ( phantom, UNM_PEG_2_HALT_STATUS );
2052 phantom_writel ( phantom, halt_status, UNM_PEG_2_HALT_STATUS );
2053 halt_status = phantom_readl ( phantom, UNM_PEG_3_HALT_STATUS );
2054 phantom_writel ( phantom, halt_status, UNM_PEG_3_HALT_STATUS );
2055 halt_status = phantom_readl ( phantom, UNM_PEG_4_HALT_STATUS );
2056 phantom_writel ( phantom, halt_status, UNM_PEG_4_HALT_STATUS );
2057 }
2058
2059 /**
2060 * Initialise the Phantom command PEG
2061 *
2062 * @v phantom Phantom NIC
2063 * @ret rc Return status code
2064 */
2065 static int phantom_init_cmdpeg ( struct phantom_nic *phantom ) {
2066 uint32_t cold_boot;
2067 uint32_t sw_reset;
2068 physaddr_t dummy_dma_phys;
2069 unsigned int retries;
2070 uint32_t cmdpeg_state;
2071 uint32_t last_cmdpeg_state = 0;
2072
2073 /* Check for a previous initialisation. This could have
2074 * happened if, for example, the BIOS used the UNDI API to
2075 * drive the NIC prior to a full PXE boot.
2076 */
2077 cmdpeg_state = phantom_readl ( phantom, UNM_NIC_REG_CMDPEG_STATE );
2078 if ( cmdpeg_state == UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK ) {
2079 DBGC ( phantom, "Phantom %p command PEG already initialized\n",
2080 phantom );
2081 /* Unhalt the PEGs. Previous firmware (e.g. BOFM) may
2082 * have halted the PEGs to prevent internal bus
2083 * collisions when the BIOS re-reads the expansion ROM.
2084 */
2085 phantom_unhalt_pegs ( phantom );
2086 return 0;
2087 }
2088
2089 /* If this was a cold boot, check that the hardware came up ok */
2090 cold_boot = phantom_readl ( phantom, UNM_CAM_RAM_COLD_BOOT );
2091 if ( cold_boot == UNM_CAM_RAM_COLD_BOOT_MAGIC ) {
2092 DBGC ( phantom, "Phantom %p coming up from cold boot\n",
2093 phantom );
2094 sw_reset = phantom_readl ( phantom, UNM_ROMUSB_GLB_SW_RESET );
2095 if ( sw_reset != UNM_ROMUSB_GLB_SW_RESET_MAGIC ) {
2096 DBGC ( phantom, "Phantom %p reset failed: %08lx\n",
2097 phantom, sw_reset );
2098 return -EIO;
2099 }
2100 } else {
2101 DBGC ( phantom, "Phantom %p coming up from warm boot "
2102 "(%08lx)\n", phantom, cold_boot );
2103 }
2104 /* Clear cold-boot flag */
2105 phantom_writel ( phantom, 0, UNM_CAM_RAM_COLD_BOOT );
2106
2107 /* Set port modes */
2108 phantom_writel ( phantom, UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G,
2109 UNM_CAM_RAM_WOL_PORT_MODE );
2110
2111 /* Pass dummy DMA area to card */
2112 dummy_dma_phys = virt_to_bus ( phantom->dma_buf->dummy_dma );
2113 DBGC ( phantom, "Phantom %p dummy DMA at %08lx\n",
2114 phantom, dummy_dma_phys );
2115 phantom_write_hilo ( phantom, dummy_dma_phys,
2116 UNM_NIC_REG_DUMMY_BUF_ADDR_LO,
2117 UNM_NIC_REG_DUMMY_BUF_ADDR_HI );
2118 phantom_writel ( phantom, UNM_NIC_REG_DUMMY_BUF_INIT,
2119 UNM_NIC_REG_DUMMY_BUF );
2120
2121 /* Tell the hardware that tuning is complete */
2122 phantom_writel ( phantom, UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC,
2123 UNM_ROMUSB_GLB_PEGTUNE_DONE );
2124
2125 /* Wait for command PEG to finish initialising */
2126 DBGC ( phantom, "Phantom %p initialising command PEG (will take up to "
2127 "%d seconds)...\n", phantom, PHN_CMDPEG_INIT_TIMEOUT_SEC );
2128 for ( retries = 0; retries < PHN_CMDPEG_INIT_TIMEOUT_SEC; retries++ ) {
2129 cmdpeg_state = phantom_readl ( phantom,
2130 UNM_NIC_REG_CMDPEG_STATE );
2131 if ( cmdpeg_state != last_cmdpeg_state ) {
2132 DBGC ( phantom, "Phantom %p command PEG state is "
2133 "%08lx after %d seconds...\n",
2134 phantom, cmdpeg_state, retries );
2135 last_cmdpeg_state = cmdpeg_state;
2136 }
2137 if ( cmdpeg_state == UNM_NIC_REG_CMDPEG_STATE_INITIALIZED ) {
2138 /* Acknowledge the PEG initialisation */
2139 phantom_writel ( phantom,
2140 UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK,
2141 UNM_NIC_REG_CMDPEG_STATE );
2142 return 0;
2143 }
2144 mdelay ( 1000 );
2145 }
2146
2147 DBGC ( phantom, "Phantom %p timed out waiting for command PEG to "
2148 "initialise (status %08lx)\n", phantom, cmdpeg_state );
2149 return -ETIMEDOUT;
2150 }
2151
2152 /**
2153 * Read Phantom MAC address
2154 *
2155 * @v phanton_port Phantom NIC port
2156 * @v ll_addr Buffer to fill with MAC address
2157 */
2158 static void phantom_get_macaddr ( struct phantom_nic_port *phantom_port,
2159 uint8_t *ll_addr ) {
2160 struct phantom_nic *phantom = phantom_port->phantom;
2161 union {
2162 uint8_t mac_addr[2][ETH_ALEN];
2163 uint32_t dwords[3];
2164 } u;
2165 unsigned long offset;
2166 int i;
2167
2168 /* Read the three dwords that include this MAC address and one other */
2169 offset = ( UNM_CAM_RAM_MAC_ADDRS +
2170 ( 12 * ( phantom_port->port / 2 ) ) );
2171 for ( i = 0 ; i < 3 ; i++, offset += 4 ) {
2172 u.dwords[i] = phantom_readl ( phantom, offset );
2173 }
2174
2175 /* Copy out the relevant MAC address */
2176 for ( i = 0 ; i < ETH_ALEN ; i++ ) {
2177 ll_addr[ ETH_ALEN - i - 1 ] =
2178 u.mac_addr[ phantom_port->port & 1 ][i];
2179 }
2180 DBGC ( phantom, "Phantom %p port %d MAC address is %s\n",
2181 phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
2182 }
2183
2184 /**
2185 * Initialise Phantom receive PEG
2186 *
2187 * @v phantom Phantom NIC
2188 * @ret rc Return status code
2189 */
2190 static int phantom_init_rcvpeg ( struct phantom_nic *phantom ) {
2191 unsigned int retries;
2192 uint32_t rcvpeg_state;
2193 uint32_t last_rcvpeg_state = 0;
2194
2195 DBGC ( phantom, "Phantom %p initialising receive PEG (will take up to "
2196 "%d seconds)...\n", phantom, PHN_RCVPEG_INIT_TIMEOUT_SEC );
2197 for ( retries = 0; retries < PHN_RCVPEG_INIT_TIMEOUT_SEC; retries++ ) {
2198 rcvpeg_state = phantom_readl ( phantom,
2199 UNM_NIC_REG_RCVPEG_STATE );
2200 if ( rcvpeg_state != last_rcvpeg_state ) {
2201 DBGC ( phantom, "Phantom %p receive PEG state is "
2202 "%08lx after %d seconds...\n",
2203 phantom, rcvpeg_state, retries );
2204 last_rcvpeg_state = rcvpeg_state;
2205 }
2206 if ( rcvpeg_state == UNM_NIC_REG_RCVPEG_STATE_INITIALIZED )
2207 return 0;
2208 mdelay ( 1000 );
2209 }
2210
2211 DBGC ( phantom, "Phantom %p timed out waiting for receive PEG to "
2212 "initialise (status %08lx)\n", phantom, rcvpeg_state );
2213 return -ETIMEDOUT;
2214 }
2215
2216 /**
2217 * Probe PCI device
2218 *
2219 * @v pci PCI device
2220 * @v id PCI ID
2221 * @ret rc Return status code
2222 */
2223 static int phantom_probe ( struct pci_device *pci,
2224 const struct pci_device_id *id __unused ) {
2225 struct phantom_nic *phantom;
2226 struct net_device *netdev;
2227 struct phantom_nic_port *phantom_port;
2228 struct settings *parent_settings;
2229 int i;
2230 int rc;
2231
2232 /* Phantom NICs expose multiple PCI functions, used for
2233 * virtualisation. Ignore everything except function 0.
2234 */
2235 if ( PCI_FUNC ( pci->devfn ) != 0 )
2236 return -ENODEV;
2237
2238 /* Allocate Phantom device */
2239 phantom = zalloc ( sizeof ( *phantom ) );
2240 if ( ! phantom ) {
2241 rc = -ENOMEM;
2242 goto err_alloc_phantom;
2243 }
2244 pci_set_drvdata ( pci, phantom );
2245
2246 /* Fix up PCI device */
2247 adjust_pci_device ( pci );
2248
2249 /* Map CRB */
2250 if ( ( rc = phantom_map_crb ( phantom, pci ) ) != 0 )
2251 goto err_map_crb;
2252
2253 /* Read flash information */
2254 if ( ( rc = phantom_read_flash ( phantom ) ) != 0 )
2255 goto err_read_flash;
2256
2257 /* Allocate net devices for each port */
2258 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
2259 netdev = alloc_etherdev ( sizeof ( *phantom_port ) );
2260 if ( ! netdev ) {
2261 rc = -ENOMEM;
2262 goto err_alloc_etherdev;
2263 }
2264 phantom->netdev[i] = netdev;
2265 netdev_init ( netdev, &phantom_operations );
2266 phantom_port = netdev_priv ( netdev );
2267 netdev->dev = &pci->dev;
2268 phantom_port->phantom = phantom;
2269 phantom_port->port = i;
2270 settings_init ( &phantom_port->settings,
2271 &phantom_settings_operations,
2272 &netdev->refcnt, "clp" );
2273 }
2274
2275 /* BUG5945 - need to hack PCI config space on P3 B1 silicon.
2276 * B2 will have this fixed; remove this hack when B1 is no
2277 * longer in use.
2278 */
2279 for ( i = 0 ; i < 8 ; i++ ) {
2280 uint32_t temp;
2281 pci->devfn = PCI_DEVFN ( PCI_SLOT ( pci->devfn ), i );
2282 pci_read_config_dword ( pci, 0xc8, &temp );
2283 pci_read_config_dword ( pci, 0xc8, &temp );
2284 pci_write_config_dword ( pci, 0xc8, 0xf1000 );
2285 }
2286 pci->devfn = PCI_DEVFN ( PCI_SLOT ( pci->devfn ), 0 );
2287
2288 /* Allocate dummy DMA buffer and perform initial hardware handshake */
2289 phantom->dma_buf = malloc_dma ( sizeof ( *(phantom->dma_buf) ),
2290 UNM_DMA_BUFFER_ALIGN );
2291 if ( ! phantom->dma_buf )
2292 goto err_dma_buf;
2293 if ( ( rc = phantom_init_cmdpeg ( phantom ) ) != 0 )
2294 goto err_init_cmdpeg;
2295
2296 /* Initialise the receive firmware */
2297 if ( ( rc = phantom_init_rcvpeg ( phantom ) ) != 0 )
2298 goto err_init_rcvpeg;
2299
2300 /* Read MAC addresses */
2301 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
2302 phantom_port = netdev_priv ( phantom->netdev[i] );
2303 phantom_get_macaddr ( phantom_port,
2304 phantom->netdev[i]->ll_addr );
2305 }
2306
2307 /* Register network devices */
2308 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
2309 if ( ( rc = register_netdev ( phantom->netdev[i] ) ) != 0 ) {
2310 DBGC ( phantom, "Phantom %p could not register port "
2311 "%d: %s\n", phantom, i, strerror ( rc ) );
2312 goto err_register_netdev;
2313 }
2314 }
2315
2316 /* Register settings blocks */
2317 for ( i = 0 ; i < phantom->num_ports ; i++ ) {
2318 phantom_port = netdev_priv ( phantom->netdev[i] );
2319 parent_settings = netdev_settings ( phantom->netdev[i] );
2320 if ( ( rc = register_settings ( &phantom_port->settings,
2321 parent_settings ) ) != 0 ) {
2322 DBGC ( phantom, "Phantom %p could not register port "
2323 "%d settings: %s\n",
2324 phantom, i, strerror ( rc ) );
2325 goto err_register_settings;
2326 }
2327 }
2328
2329 return 0;
2330
2331 i = ( phantom->num_ports - 1 );
2332 err_register_settings:
2333 for ( ; i >= 0 ; i-- ) {
2334 phantom_port = netdev_priv ( phantom->netdev[i] );
2335 unregister_settings ( &phantom_port->settings );
2336 }
2337 i = ( phantom->num_ports - 1 );
2338 err_register_netdev:
2339 for ( ; i >= 0 ; i-- )
2340 unregister_netdev ( phantom->netdev[i] );
2341 err_init_rcvpeg:
2342 phantom_halt_pegs ( phantom );
2343 err_init_cmdpeg:
2344 free_dma ( phantom->dma_buf, sizeof ( *(phantom->dma_buf) ) );
2345 phantom->dma_buf = NULL;
2346 err_dma_buf:
2347 i = ( phantom->num_ports - 1 );
2348 err_alloc_etherdev:
2349 for ( ; i >= 0 ; i-- ) {
2350 netdev_nullify ( phantom->netdev[i] );
2351 netdev_put ( phantom->netdev[i] );
2352 }
2353 err_read_flash:
2354 err_map_crb:
2355 free ( phantom );
2356 err_alloc_phantom:
2357 return rc;
2358 }
2359
2360 /**
2361 * Remove PCI device
2362 *
2363 * @v pci PCI device
2364 */
2365 static void phantom_remove ( struct pci_device *pci ) {
2366 struct phantom_nic *phantom = pci_get_drvdata ( pci );
2367 struct phantom_nic_port *phantom_port;
2368 int i;
2369
2370 for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- ) {
2371 phantom_port = netdev_priv ( phantom->netdev[i] );
2372 unregister_settings ( &phantom_port->settings );
2373 }
2374 for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- )
2375 unregister_netdev ( phantom->netdev[i] );
2376 phantom_halt_pegs ( phantom );
2377 free_dma ( phantom->dma_buf, sizeof ( *(phantom->dma_buf) ) );
2378 phantom->dma_buf = NULL;
2379 for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- ) {
2380 netdev_nullify ( phantom->netdev[i] );
2381 netdev_put ( phantom->netdev[i] );
2382 }
2383 free ( phantom );
2384 }
2385
2386 /** Phantom PCI IDs */
2387 static struct pci_device_id phantom_nics[] = {
2388 PCI_ROM ( 0x4040, 0x0100, "nx", "NX" ),
2389 };
2390
2391 /** Phantom PCI driver */
2392 struct pci_driver phantom_driver __pci_driver = {
2393 .ids = phantom_nics,
2394 .id_count = ( sizeof ( phantom_nics ) / sizeof ( phantom_nics[0] ) ),
2395 .probe = phantom_probe,
2396 .remove = phantom_remove,
2397 };