[phantom] Add CLP settings interface
[ipxe.git] / src / drivers / net / phantom / phantom.h
1 #ifndef _PHANTOM_H
2 #define _PHANTOM_H
3
4 /*
5 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
6 * Copyright (C) 2008 NetXen, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /**
24 * @file
25 *
26 * NetXen Phantom NICs
27 *
28 */
29
30 #include <stdint.h>
31
32 /* Drag in hardware definitions */
33 #include "nx_bitops.h"
34 #include "phantom_hw.h"
35 struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
36 struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
37 union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
38
39 /* Drag in firmware interface definitions */
40 typedef uint8_t U8;
41 typedef uint16_t U16;
42 typedef uint32_t U32;
43 typedef uint64_t U64;
44 typedef uint32_t nx_rcode_t;
45 #define NXHAL_VERSION 1
46 #include "nxhal_nic_interface.h"
47
48 /** SPI controller maximum block size */
49 #define UNM_SPI_BLKSIZE 4
50
51 /** DMA buffer alignment */
52 #define UNM_DMA_BUFFER_ALIGN 16
53
54 /** Mark structure as DMA-aligned */
55 #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
56
57 /** Dummy DMA buffer size */
58 #define UNM_DUMMY_DMA_SIZE 1024
59
60 /******************************************************************************
61 *
62 * Register definitions
63 *
64 */
65
66 #define UNM_128M_CRB_WINDOW 0x6110210UL
67 #define UNM_32M_CRB_WINDOW 0x0110210UL
68 #define UNM_2M_CRB_WINDOW 0x0130060UL
69
70 /**
71 * Phantom register blocks
72 *
73 * The upper address bits vary between cards. We define an abstract
74 * address space in which the upper 8 bits of the 32-bit register
75 * address encode the register block. This gets translated to a bus
76 * address by the phantom_crb_access_xxx() methods.
77 */
78 enum unm_reg_blocks {
79 UNM_CRB_BLK_PCIE = 0x01,
80 UNM_CRB_BLK_CAM = 0x22,
81 UNM_CRB_BLK_ROMUSB = 0x33,
82 UNM_CRB_BLK_TEST = 0x02,
83 UNM_CRB_BLK_PEG_0 = 0x11,
84 UNM_CRB_BLK_PEG_1 = 0x12,
85 UNM_CRB_BLK_PEG_2 = 0x13,
86 UNM_CRB_BLK_PEG_3 = 0x14,
87 UNM_CRB_BLK_PEG_4 = 0x0f,
88 };
89 #define UNM_CRB_BASE(blk) ( (blk) << 20 )
90 #define UNM_CRB_BLK(reg) ( (reg) >> 20 )
91 #define UNM_CRB_OFFSET(reg) ( (reg) & 0x000fffff )
92
93 #define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
94 #define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
95 #define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
96
97 #define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
98
99 #define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
100 #define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
101 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
102 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
103 #define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
104 #define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
105 #define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
106 #define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
107 #define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
108 #define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
109 #define UNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 )
110 #define UNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL
111 #define UNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 )
112 #define UNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 )
113 #define UNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc )
114 #define UNM_CAM_RAM_CLP_STATUS_START 0x00000001UL
115 #define UNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL
116 #define UNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL
117 #define UNM_CAM_RAM_CLP_STATUS_UNINITIALISED 0xffffffffUL
118 #define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
119 #define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
120 #define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
121 #define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
122
123 #define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
124 #define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
125 #define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
126 #define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
127 #define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
128 #define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
129 #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
130 #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
131 #define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
132 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
133 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
134 #define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
135 #define UNM_NIC_REG_DUMMY_BUF_INIT 0
136 #define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
137 #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
138 ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
139 #define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
140 #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
141 #define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
142 #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
143 #define UNM_NIC_REG_SW_INT_MASK_0 ( UNM_NIC_REG + 0x001d8 )
144 #define UNM_NIC_REG_SW_INT_MASK_1 ( UNM_NIC_REG + 0x001e0 )
145 #define UNM_NIC_REG_SW_INT_MASK_2 ( UNM_NIC_REG + 0x001e4 )
146 #define UNM_NIC_REG_SW_INT_MASK_3 ( UNM_NIC_REG + 0x001e8 )
147
148 #define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
149
150 #define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
151 #define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
152 #define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
153 #define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
154 #define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
155 #define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
156 #define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31
157
158 #define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
159 #define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
160 #define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
161 #define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
162 #define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
163 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
164 #define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
165
166 #define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
167
168 #define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
169 #define UNM_TEST_CONTROL_START 0x01
170 #define UNM_TEST_CONTROL_ENABLE 0x02
171 #define UNM_TEST_CONTROL_BUSY 0x08
172 #define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
173 #define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
174 #define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
175 #define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
176
177 #define UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 )
178 #define UNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 )
179 #define UNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c )
180
181 #define UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 )
182 #define UNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 )
183 #define UNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c )
184
185 #define UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 )
186 #define UNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 )
187 #define UNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c )
188
189 #define UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 )
190 #define UNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 )
191 #define UNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c )
192
193 #define UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 )
194 #define UNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 )
195 #define UNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c )
196
197 /******************************************************************************
198 *
199 * Flash layout
200 *
201 */
202
203 /* Board configuration */
204
205 #define UNM_BRDCFG_START 0x4000
206
207 struct unm_board_info {
208 uint32_t header_version;
209 uint32_t board_mfg;
210 uint32_t board_type;
211 uint32_t board_num;
212 uint32_t chip_id;
213 uint32_t chip_minor;
214 uint32_t chip_major;
215 uint32_t chip_pkg;
216 uint32_t chip_lot;
217 uint32_t port_mask;
218 uint32_t peg_mask;
219 uint32_t icache_ok;
220 uint32_t dcache_ok;
221 uint32_t casper_ok;
222 uint32_t mac_addr_lo_0;
223 uint32_t mac_addr_lo_1;
224 uint32_t mac_addr_lo_2;
225 uint32_t mac_addr_lo_3;
226 uint32_t mn_sync_mode;
227 uint32_t mn_sync_shift_cclk;
228 uint32_t mn_sync_shift_mclk;
229 uint32_t mn_wb_en;
230 uint32_t mn_crystal_freq;
231 uint32_t mn_speed;
232 uint32_t mn_org;
233 uint32_t mn_depth;
234 uint32_t mn_ranks_0;
235 uint32_t mn_ranks_1;
236 uint32_t mn_rd_latency_0;
237 uint32_t mn_rd_latency_1;
238 uint32_t mn_rd_latency_2;
239 uint32_t mn_rd_latency_3;
240 uint32_t mn_rd_latency_4;
241 uint32_t mn_rd_latency_5;
242 uint32_t mn_rd_latency_6;
243 uint32_t mn_rd_latency_7;
244 uint32_t mn_rd_latency_8;
245 uint32_t mn_dll_val[18];
246 uint32_t mn_mode_reg;
247 uint32_t mn_ext_mode_reg;
248 uint32_t mn_timing_0;
249 uint32_t mn_timing_1;
250 uint32_t mn_timing_2;
251 uint32_t sn_sync_mode;
252 uint32_t sn_pt_mode;
253 uint32_t sn_ecc_en;
254 uint32_t sn_wb_en;
255 uint32_t sn_crystal_freq;
256 uint32_t sn_speed;
257 uint32_t sn_org;
258 uint32_t sn_depth;
259 uint32_t sn_dll_tap;
260 uint32_t sn_rd_latency;
261 uint32_t mac_addr_hi_0;
262 uint32_t mac_addr_hi_1;
263 uint32_t mac_addr_hi_2;
264 uint32_t mac_addr_hi_3;
265 uint32_t magic;
266 uint32_t mn_rdimm;
267 uint32_t mn_dll_override;
268 };
269
270 #define UNM_BDINFO_VERSION 1
271 #define UNM_BRDTYPE_P3_HMEZ 0x0022
272 #define UNM_BRDTYPE_P3_10G_CX4_LP 0x0023
273 #define UNM_BRDTYPE_P3_4_GB 0x0024
274 #define UNM_BRDTYPE_P3_IMEZ 0x0025
275 #define UNM_BRDTYPE_P3_10G_SFP_PLUS 0x0026
276 #define UNM_BRDTYPE_P3_10000_BASE_T 0x0027
277 #define UNM_BRDTYPE_P3_XG_LOM 0x0028
278 #define UNM_BRDTYPE_P3_4_GB_MM 0x0029
279 #define UNM_BRDTYPE_P3_10G_CX4 0x0031
280 #define UNM_BRDTYPE_P3_10G_XFP 0x0032
281 #define UNM_BDINFO_MAGIC 0x12345678
282
283 /* User defined region */
284
285 #define UNM_USER_START 0x3e8000
286
287 #define UNM_FLASH_NUM_PORTS 4
288 #define UNM_FLASH_NUM_MAC_PER_PORT 32
289
290 struct unm_user_info {
291 uint8_t flash_md5[16 * 64];
292 uint32_t bootld_version;
293 uint32_t bootld_size;
294 uint32_t image_version;
295 uint32_t image_size;
296 uint32_t primary_status;
297 uint32_t secondary_present;
298 /* MAC address , 4 ports, 32 address per port */
299 uint64_t mac_addr[UNM_FLASH_NUM_PORTS * UNM_FLASH_NUM_MAC_PER_PORT];
300 uint32_t sub_sys_id;
301 uint8_t serial_num[32];
302 uint32_t bios_version;
303 uint32_t pxe_enable;
304 uint32_t vlan_tag[UNM_FLASH_NUM_PORTS];
305 };
306
307 #endif /* _PHANTOM_H */