[rhine] Fix usage of mii_read()
[ipxe.git] / src / drivers / net / rhine.c
1 /*
2 * Copyright (C) 2012 Adrian Jamroz <adrian.jamroz@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17 * 02110-1301, USA.
18 */
19
20 FILE_LICENCE ( GPL2_OR_LATER );
21
22 #include <stdint.h>
23 #include <string.h>
24 #include <unistd.h>
25 #include <errno.h>
26 #include <byteswap.h>
27 #include <ipxe/netdevice.h>
28 #include <ipxe/ethernet.h>
29 #include <ipxe/if_ether.h>
30 #include <ipxe/iobuf.h>
31 #include <ipxe/malloc.h>
32 #include <ipxe/pci.h>
33 #include <ipxe/mii.h>
34 #include "rhine.h"
35
36 /** @file
37 *
38 * VIA Rhine network driver
39 *
40 */
41
42 /******************************************************************************
43 *
44 * MII interface
45 *
46 ******************************************************************************
47 */
48
49 /**
50 * Read from MII register
51 *
52 * @v mii MII interface
53 * @v reg Register address
54 * @ret value Data read, or negative error
55 */
56 static int rhine_mii_read ( struct mii_interface *mii, unsigned int reg ) {
57 struct rhine_nic *rhn = container_of ( mii, struct rhine_nic, mii );
58 unsigned int timeout = RHINE_TIMEOUT_US;
59 uint8_t cr;
60
61 DBGC2 ( rhn, "RHINE %p MII read reg %d\n", rhn, reg );
62
63 /* Initiate read */
64 writeb ( reg, rhn->regs + RHINE_MII_ADDR );
65 cr = readb ( rhn->regs + RHINE_MII_CR );
66 writeb ( ( cr | RHINE_MII_CR_RDEN ), rhn->regs + RHINE_MII_CR );
67
68 /* Wait for read to complete */
69 while ( timeout-- ) {
70 udelay ( 1 );
71 cr = readb ( rhn->regs + RHINE_MII_CR );
72 if ( ! ( cr & RHINE_MII_CR_RDEN ) )
73 return readw ( rhn->regs + RHINE_MII_RDWR );
74 }
75
76 DBGC ( rhn, "RHINE %p MII read timeout\n", rhn );
77 return -ETIMEDOUT;
78 }
79
80 /**
81 * Write to MII register
82 *
83 * @v mii MII interface
84 * @v reg Register address
85 * @v data Data to write
86 * @ret rc Return status code
87 */
88 static int rhine_mii_write ( struct mii_interface *mii, unsigned int reg,
89 unsigned int data ) {
90 struct rhine_nic *rhn = container_of ( mii, struct rhine_nic, mii );
91 unsigned int timeout = RHINE_TIMEOUT_US;
92 uint8_t cr;
93
94 DBGC2 ( rhn, "RHINE %p MII write reg %d data 0x%04x\n",
95 rhn, reg, data );
96
97 /* Initiate write */
98 writeb ( reg, rhn->regs + RHINE_MII_ADDR );
99 writew ( data, rhn->regs + RHINE_MII_RDWR );
100 cr = readb ( rhn->regs + RHINE_MII_CR );
101 writeb ( ( cr | RHINE_MII_CR_WREN ), rhn->regs + RHINE_MII_CR );
102
103 /* Wait for write to complete */
104 while ( timeout-- ) {
105 udelay ( 1 );
106 cr = readb ( rhn->regs + RHINE_MII_CR );
107 if ( ! ( cr & RHINE_MII_CR_WREN ) )
108 return 0;
109 }
110
111 DBGC ( rhn, "RHINE %p MII write timeout\n", rhn );
112 return -ETIMEDOUT;
113 }
114
115 /** Rhine MII operations */
116 static struct mii_operations rhine_mii_operations = {
117 .read = rhine_mii_read,
118 .write = rhine_mii_write,
119 };
120
121 /**
122 * Enable auto-polling
123 *
124 * @v rhn Rhine device
125 * @ret rc Return status code
126 *
127 * This is voodoo. There seems to be no documentation on exactly what
128 * we are waiting for, or why we have to do anything other than simply
129 * turn the feature on.
130 */
131 static int rhine_mii_autopoll ( struct rhine_nic *rhn ) {
132 unsigned int timeout = RHINE_TIMEOUT_US;
133 uint8_t addr;
134
135 /* Initiate auto-polling */
136 writeb ( MII_BMSR, rhn->regs + RHINE_MII_ADDR );
137 writeb ( RHINE_MII_CR_AUTOPOLL, rhn->regs + RHINE_MII_CR );
138
139 /* Wait for auto-polling to complete */
140 while ( timeout-- ) {
141 udelay ( 1 );
142 addr = readb ( rhn->regs + RHINE_MII_ADDR );
143 if ( ! ( addr & RHINE_MII_ADDR_MDONE ) ) {
144 writeb ( ( MII_BMSR | RHINE_MII_ADDR_MSRCEN ),
145 rhn->regs + RHINE_MII_ADDR );
146 return 0;
147 }
148 }
149
150 DBGC ( rhn, "RHINE %p MII auto-poll timeout\n", rhn );
151 return -ETIMEDOUT;
152 }
153
154 /******************************************************************************
155 *
156 * Device reset
157 *
158 ******************************************************************************
159 */
160
161 /**
162 * Reset hardware
163 *
164 * @v rhn Rhine device
165 * @ret rc Return status code
166 *
167 * We're using PIO because this might reset the MMIO enable bit.
168 */
169 static int rhine_reset ( struct rhine_nic *rhn ) {
170 unsigned int timeout = RHINE_TIMEOUT_US;
171 uint8_t cr1;
172
173 DBGC ( rhn, "RHINE %p reset\n", rhn );
174
175 /* Initiate reset */
176 outb ( RHINE_CR1_RESET, rhn->ioaddr + RHINE_CR1 );
177
178 /* Wait for reset to complete */
179 while ( timeout-- ) {
180 udelay ( 1 );
181 cr1 = inb ( rhn->ioaddr + RHINE_CR1 );
182 if ( ! ( cr1 & RHINE_CR1_RESET ) )
183 return 0;
184 }
185
186 DBGC ( rhn, "RHINE %p reset timeout\n", rhn );
187 return -ETIMEDOUT;
188 }
189
190 /**
191 * Enable MMIO register access
192 *
193 * @v rhn Rhine device
194 * @v revision Card revision
195 */
196 static void rhine_enable_mmio ( struct rhine_nic *rhn, int revision ) {
197 uint8_t conf;
198
199 if ( revision < RHINE_REVISION_OLD ) {
200 conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_A );
201 outb ( ( conf | RHINE_CHIPCFG_A_MMIO ),
202 rhn->ioaddr + RHINE_CHIPCFG_A );
203 } else {
204 conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_D );
205 outb ( ( conf | RHINE_CHIPCFG_D_MMIO ),
206 rhn->ioaddr + RHINE_CHIPCFG_D );
207 }
208 }
209
210 /**
211 * Reload EEPROM contents
212 *
213 * @v rhn Rhine device
214 * @ret rc Return status code
215 *
216 * We're using PIO because this might reset the MMIO enable bit.
217 */
218 static int rhine_reload_eeprom ( struct rhine_nic *rhn ) {
219 unsigned int timeout = RHINE_TIMEOUT_US;
220 uint8_t eeprom;
221
222 /* Initiate reload */
223 eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
224 outb ( ( eeprom | RHINE_EEPROM_CTRL_RELOAD ),
225 rhn->ioaddr + RHINE_EEPROM_CTRL );
226
227 /* Wait for reload to complete */
228 while ( timeout-- ) {
229 udelay ( 1 );
230 eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
231 if ( ! ( eeprom & RHINE_EEPROM_CTRL_RELOAD ) )
232 return 0;
233 }
234
235 DBGC ( rhn, "RHINE %p EEPROM reload timeout\n", rhn );
236 return -ETIMEDOUT;
237 }
238
239 /******************************************************************************
240 *
241 * Link state
242 *
243 ******************************************************************************
244 */
245
246 /**
247 * Check link state
248 *
249 * @v netdev Network device
250 */
251 static void rhine_check_link ( struct net_device *netdev ) {
252 struct rhine_nic *rhn = netdev->priv;
253 uint8_t mii_sr;
254
255 /* Read MII status register */
256 mii_sr = readb ( rhn->regs + RHINE_MII_SR );
257 DBGC ( rhn, "RHINE %p link status %02x\n", rhn, mii_sr );
258
259 /* Report link state */
260 if ( ! ( mii_sr & RHINE_MII_SR_LINKPOLL ) ) {
261 netdev_link_up ( netdev );
262 } else if ( mii_sr & RHINE_MII_SR_PHYERR ) {
263 netdev_link_err ( netdev, -EIO );
264 } else {
265 netdev_link_down ( netdev );
266 }
267 }
268
269 /******************************************************************************
270 *
271 * Network device interface
272 *
273 ******************************************************************************
274 */
275
276 /**
277 * Create descriptor ring
278 *
279 * @v rhn Rhine device
280 * @v ring Descriptor ring
281 * @ret rc Return status code
282 */
283 static int rhine_create_ring ( struct rhine_nic *rhn,
284 struct rhine_ring *ring ) {
285 size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
286 struct rhine_descriptor *next;
287 physaddr_t address;
288 unsigned int i;
289
290 /* Allocate descriptors */
291 ring->desc = malloc_dma ( len, RHINE_RING_ALIGN );
292 if ( ! ring->desc )
293 return -ENOMEM;
294
295 /* Initialise descriptor ring */
296 memset ( ring->desc, 0, len );
297 for ( i = 0 ; i < ring->count ; i++ ) {
298 next = &ring->desc[ ( i + 1 ) % ring->count ];
299 ring->desc[i].next = cpu_to_le32 ( virt_to_bus ( next ) );
300 }
301
302 /* Program ring address */
303 address = virt_to_bus ( ring->desc );
304 writel ( address, rhn->regs + ring->reg );
305
306 DBGC ( rhn, "RHINE %p ring %02x is at [%08llx,%08llx)\n",
307 rhn, ring->reg, ( ( unsigned long long ) address ),
308 ( ( unsigned long long ) address + len ) );
309
310 return 0;
311 }
312
313 /**
314 * Destroy descriptor ring
315 *
316 * @v rhn Rhine device
317 * @v ring Descriptor ring
318 */
319 static void rhine_destroy_ring ( struct rhine_nic *rhn,
320 struct rhine_ring *ring ) {
321 size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
322
323 /* Clear ring address */
324 writel ( 0, rhn->regs + ring->reg );
325
326 /* Free descriptor ring */
327 free_dma ( ring->desc, len );
328 ring->desc = NULL;
329 ring->prod = 0;
330 ring->cons = 0;
331 }
332
333 /**
334 * Refill RX descriptor ring
335 *
336 * @v rhn Rhine device
337 */
338 static void rhine_refill_rx ( struct rhine_nic *rhn ) {
339 struct rhine_descriptor *desc;
340 struct io_buffer *iobuf;
341 unsigned int rx_idx;
342 physaddr_t address;
343
344 while ( ( rhn->rx.prod - rhn->rx.cons ) < RHINE_RXDESC_NUM ) {
345
346 /* Allocate I/O buffer */
347 iobuf = alloc_iob ( RHINE_RX_MAX_LEN );
348 if ( ! iobuf ) {
349 /* Wait for next refill */
350 return;
351 }
352
353 /* Populate next receive descriptor */
354 rx_idx = ( rhn->rx.prod++ % RHINE_RXDESC_NUM );
355 desc = &rhn->rx.desc[rx_idx];
356 address = virt_to_bus ( iobuf->data );
357 desc->buffer = cpu_to_le32 ( address );
358 desc->des1 =
359 cpu_to_le32 ( RHINE_DES1_SIZE ( RHINE_RX_MAX_LEN - 1) |
360 RHINE_DES1_CHAIN | RHINE_DES1_IC );
361 wmb();
362 desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
363
364 /* Record I/O buffer */
365 rhn->rx_iobuf[rx_idx] = iobuf;
366
367 DBGC2 ( rhn, "RHINE %p RX %d is [%llx,%llx)\n", rhn, rx_idx,
368 ( ( unsigned long long ) address ),
369 ( ( unsigned long long ) address + RHINE_RX_MAX_LEN ) );
370 }
371 }
372
373 /**
374 * Open network device
375 *
376 * @v netdev Network device
377 * @ret rc Return status code
378 */
379 static int rhine_open ( struct net_device *netdev ) {
380 struct rhine_nic *rhn = netdev->priv;
381 int rc;
382
383 /* Create transmit ring */
384 if ( ( rc = rhine_create_ring ( rhn, &rhn->tx ) ) != 0 )
385 goto err_create_tx;
386
387 /* Create receive ring */
388 if ( ( rc = rhine_create_ring ( rhn, &rhn->rx ) ) != 0 )
389 goto err_create_rx;
390
391 /* Set receive configuration */
392 writeb ( ( RHINE_RCR_PHYS_ACCEPT | RHINE_RCR_BCAST_ACCEPT |
393 RHINE_RCR_RUNT_ACCEPT ), rhn->regs + RHINE_RCR );
394
395 /* Enable link status monitoring */
396 if ( ( rc = rhine_mii_autopoll ( rhn ) ) != 0 )
397 goto err_mii_autopoll;
398
399 /* Some cards need an extra delay(observed with VT6102) */
400 mdelay ( 10 );
401
402 /* Enable RX/TX of packets */
403 writeb ( ( RHINE_CR0_STARTNIC | RHINE_CR0_RXEN | RHINE_CR0_TXEN ),
404 rhn->regs + RHINE_CR0 );
405
406 /* Enable auto polling and full duplex operation */
407 rhn->cr1 = RHINE_CR1_FDX;
408 writeb ( rhn->cr1, rhn->regs + RHINE_CR1 );
409
410 /* Refill RX ring */
411 rhine_refill_rx ( rhn );
412
413 /* Update link state */
414 rhine_check_link ( netdev );
415
416 return 0;
417
418 err_mii_autopoll:
419 rhine_destroy_ring ( rhn, &rhn->rx );
420 err_create_rx:
421 rhine_destroy_ring ( rhn, &rhn->tx );
422 err_create_tx:
423 return rc;
424 }
425
426 /**
427 * Close network device
428 *
429 * @v netdev Network device
430 */
431 static void rhine_close ( struct net_device *netdev ) {
432 struct rhine_nic *rhn = netdev->priv;
433 unsigned int i;
434
435 /* Disable interrupts */
436 writeb ( 0, RHINE_IMR0 );
437 writeb ( 0, RHINE_IMR1 );
438
439 /* Stop card, clear RXON and TXON bits */
440 writeb ( RHINE_CR0_STOPNIC, rhn->regs + RHINE_CR0 );
441
442 /* Destroy receive ring */
443 rhine_destroy_ring ( rhn, &rhn->rx );
444
445 /* Discard any unused receive buffers */
446 for ( i = 0 ; i < RHINE_RXDESC_NUM ; i++ ) {
447 if ( rhn->rx_iobuf[i] )
448 free_iob ( rhn->rx_iobuf[i] );
449 rhn->rx_iobuf[i] = NULL;
450 }
451
452 /* Destroy transmit ring */
453 rhine_destroy_ring ( rhn, &rhn->tx );
454 }
455
456 /**
457 * Transmit packet
458 *
459 * @v netdev Network device
460 * @v iobuf I/O buffer
461 * @ret rc Return status code
462 */
463 static int rhine_transmit ( struct net_device *netdev,
464 struct io_buffer *iobuf ) {
465 struct rhine_nic *rhn = netdev->priv;
466 struct rhine_descriptor *desc;
467 physaddr_t address;
468 unsigned int tx_idx;
469
470 /* Get next transmit descriptor */
471 if ( ( rhn->tx.prod - rhn->tx.cons ) >= RHINE_TXDESC_NUM )
472 return -ENOBUFS;
473 tx_idx = ( rhn->tx.prod++ % RHINE_TXDESC_NUM );
474 desc = &rhn->tx.desc[tx_idx];
475
476 /* Pad and align packet */
477 iob_pad ( iobuf, ETH_ZLEN );
478 address = virt_to_bus ( iobuf->data );
479
480 /* Populate transmit descriptor */
481 desc->buffer = cpu_to_le32 ( address );
482 desc->des1 = cpu_to_le32 ( RHINE_DES1_IC | RHINE_TDES1_STP |
483 RHINE_TDES1_EDP | RHINE_DES1_CHAIN |
484 RHINE_DES1_SIZE ( iob_len ( iobuf ) ) );
485 wmb();
486 desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
487 wmb();
488
489 /* Notify card that there are packets ready to transmit */
490 writeb ( ( rhn->cr1 | RHINE_CR1_TXPOLL ), rhn->regs + RHINE_CR1 );
491
492 DBGC2 ( rhn, "RHINE %p TX %d is [%llx,%llx)\n", rhn, tx_idx,
493 ( ( unsigned long long ) address ),
494 ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
495
496 return 0;
497 }
498
499 /**
500 * Poll for completed packets
501 *
502 * @v netdev Network device
503 */
504 static void rhine_poll_tx ( struct net_device *netdev ) {
505 struct rhine_nic *rhn = netdev->priv;
506 struct rhine_descriptor *desc;
507 unsigned int tx_idx;
508 uint32_t des0;
509
510 /* Check for completed packets */
511 while ( rhn->tx.cons != rhn->tx.prod ) {
512
513 /* Get next transmit descriptor */
514 tx_idx = ( rhn->tx.cons % RHINE_TXDESC_NUM );
515 desc = &rhn->tx.desc[tx_idx];
516
517 /* Stop if descriptor is still in use */
518 if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
519 return;
520
521 /* Complete TX descriptor */
522 des0 = le32_to_cpu ( desc->des0 );
523 if ( des0 & RHINE_TDES0_TERR ) {
524 DBGC ( rhn, "RHINE %p TX %d error (DES0 %08x)\n",
525 rhn, tx_idx, des0 );
526 netdev_tx_complete_next_err ( netdev, -EIO );
527 } else {
528 DBGC2 ( rhn, "RHINE %p TX %d complete\n", rhn, tx_idx );
529 netdev_tx_complete_next ( netdev );
530 }
531 rhn->tx.cons++;
532 }
533 }
534
535 /**
536 * Poll for received packets
537 *
538 * @v netdev Network device
539 */
540 static void rhine_poll_rx ( struct net_device *netdev ) {
541 struct rhine_nic *rhn = netdev->priv;
542 struct rhine_descriptor *desc;
543 struct io_buffer *iobuf;
544 unsigned int rx_idx;
545 uint32_t des0;
546 size_t len;
547
548 /* Check for received packets */
549 while ( rhn->rx.cons != rhn->rx.prod ) {
550
551 /* Get next receive descriptor */
552 rx_idx = ( rhn->rx.cons % RHINE_RXDESC_NUM );
553 desc = &rhn->rx.desc[rx_idx];
554
555 /* Stop if descriptor is still in use */
556 if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
557 return;
558
559 /* Populate I/O buffer */
560 iobuf = rhn->rx_iobuf[rx_idx];
561 rhn->rx_iobuf[rx_idx] = NULL;
562 des0 = le32_to_cpu ( desc->des0 );
563 len = ( RHINE_DES0_GETSIZE ( des0 ) - 4 /* strip CRC */ );
564 iob_put ( iobuf, len );
565
566 /* Hand off to network stack */
567 if ( des0 & RHINE_RDES0_RXOK ) {
568 DBGC2 ( rhn, "RHINE %p RX %d complete (length %zd)\n",
569 rhn, rx_idx, len );
570 netdev_rx ( netdev, iobuf );
571 } else {
572 DBGC ( rhn, "RHINE %p RX %d error (length %zd, DES0 "
573 "%08x)\n", rhn, rx_idx, len, des0 );
574 netdev_rx_err ( netdev, iobuf, -EIO );
575 }
576 rhn->rx.cons++;
577 }
578 }
579
580 /**
581 * Poll for completed and received packets
582 *
583 * @v netdev Network device
584 */
585 static void rhine_poll ( struct net_device *netdev ) {
586 struct rhine_nic *rhn = netdev->priv;
587 uint8_t isr0;
588 uint8_t isr1;
589
590 /* Read and acknowledge interrupts */
591 isr0 = readb ( rhn->regs + RHINE_ISR0 );
592 isr1 = readb ( rhn->regs + RHINE_ISR1 );
593 if ( isr0 )
594 writeb ( isr0, rhn->regs + RHINE_ISR0 );
595 if ( isr1 )
596 writeb ( isr1, rhn->regs + RHINE_ISR1 );
597
598 /* Report unexpected errors */
599 if ( ( isr0 & ( RHINE_ISR0_MIBOVFL | RHINE_ISR0_PCIERR |
600 RHINE_ISR0_RXRINGERR | RHINE_ISR0_TXRINGERR ) ) ||
601 ( isr1 & ( RHINE_ISR1_GPI | RHINE_ISR1_TXABORT |
602 RHINE_ISR1_RXFIFOOVFL | RHINE_ISR1_RXFIFOUNFL |
603 RHINE_ISR1_TXFIFOUNFL ) ) ) {
604 DBGC ( rhn, "RHINE %p unexpected ISR0 %02x ISR1 %02x\n",
605 rhn, isr0, isr1 );
606 /* Report as a TX error */
607 netdev_tx_err ( netdev, NULL, -EIO );
608 }
609
610 /* Poll for TX completions, if applicable */
611 if ( isr0 & ( RHINE_ISR0_TXDONE | RHINE_ISR0_TXERR ) )
612 rhine_poll_tx ( netdev );
613
614 /* Poll for RX completions, if applicable */
615 if ( isr0 & ( RHINE_ISR0_RXDONE | RHINE_ISR0_RXERR ) )
616 rhine_poll_rx ( netdev );
617
618 /* Handle RX buffer exhaustion */
619 if ( isr1 & RHINE_ISR1_RXNOBUF ) {
620 rhine_poll_rx ( netdev );
621 netdev_rx_err ( netdev, NULL, -ENOBUFS );
622 }
623
624 /* Check link state, if applicable */
625 if ( isr1 & RHINE_ISR1_PORTSTATE )
626 rhine_check_link ( netdev );
627
628 /* Refill RX ring */
629 rhine_refill_rx ( rhn );
630 }
631
632 /**
633 * Enable or disable interrupts
634 *
635 * @v netdev Network device
636 * @v enable Interrupts should be enabled
637 */
638 static void rhine_irq ( struct net_device *netdev, int enable ) {
639 struct rhine_nic *nic = netdev->priv;
640
641 if ( enable ) {
642 /* Enable interrupts */
643 writeb ( 0xff, nic->regs + RHINE_IMR0 );
644 writeb ( 0xff, nic->regs + RHINE_IMR1 );
645 } else {
646 /* Disable interrupts */
647 writeb ( 0, nic->regs + RHINE_IMR0 );
648 writeb ( 0, nic->regs + RHINE_IMR1 );
649 }
650 }
651
652 /** Rhine network device operations */
653 static struct net_device_operations rhine_operations = {
654 .open = rhine_open,
655 .close = rhine_close,
656 .transmit = rhine_transmit,
657 .poll = rhine_poll,
658 .irq = rhine_irq,
659 };
660
661 /******************************************************************************
662 *
663 * PCI interface
664 *
665 ******************************************************************************
666 */
667
668 /**
669 * Probe PCI device
670 *
671 * @v pci PCI device
672 * @ret rc Return status code
673 */
674 static int rhine_probe ( struct pci_device *pci ) {
675 struct net_device *netdev;
676 struct rhine_nic *rhn;
677 uint8_t revision;
678 unsigned int i;
679 int rc;
680
681 /* Allocate and initialise net device */
682 netdev = alloc_etherdev ( sizeof ( *rhn ) );
683 if ( ! netdev ) {
684 rc = -ENOMEM;
685 goto err_alloc;
686 }
687 netdev_init ( netdev, &rhine_operations );
688 rhn = netdev->priv;
689 pci_set_drvdata ( pci, netdev );
690 netdev->dev = &pci->dev;
691 memset ( rhn, 0, sizeof ( *rhn ) );
692 rhine_init_ring ( &rhn->tx, RHINE_TXDESC_NUM, RHINE_TXQUEUE_BASE );
693 rhine_init_ring ( &rhn->rx, RHINE_RXDESC_NUM, RHINE_RXQUEUE_BASE );
694
695 /* Fix up PCI device */
696 adjust_pci_device ( pci );
697
698 /* Map registers */
699 rhn->regs = ioremap ( pci->membase, RHINE_BAR_SIZE );
700 rhn->ioaddr = pci->ioaddr;
701 DBGC ( rhn, "RHINE %p regs at %08lx, I/O at %04lx\n", rhn,
702 pci->membase, pci->ioaddr );
703
704 /* Reset the NIC */
705 if ( ( rc = rhine_reset ( rhn ) ) != 0 )
706 goto err_reset;
707
708 /* Reload EEPROM */
709 if ( ( rc = rhine_reload_eeprom ( rhn ) ) != 0 )
710 goto err_reload_eeprom;
711
712 /* Read card revision and enable MMIO */
713 pci_read_config_byte ( pci, PCI_REVISION, &revision );
714 DBGC ( rhn, "RHINE %p revision %#02x detected\n", rhn, revision );
715 rhine_enable_mmio ( rhn, revision );
716
717 /* Read MAC address */
718 for ( i = 0 ; i < ETH_ALEN ; i++ )
719 netdev->hw_addr[i] = readb ( rhn->regs + RHINE_MAC + i );
720
721 /* Initialise and reset MII interface */
722 mii_init ( &rhn->mii, &rhine_mii_operations );
723 if ( ( rc = mii_reset ( &rhn->mii ) ) != 0 ) {
724 DBGC ( rhn, "RHINE %p could not reset MII: %s\n",
725 rhn, strerror ( rc ) );
726 goto err_mii_reset;
727 }
728 DBGC ( rhn, "RHINE PHY vendor %04x device %04x\n",
729 mii_read ( &rhn->mii, 0x02 ), mii_read ( &rhn->mii, 0x03 ) );
730
731 /* Register network device */
732 if ( ( rc = register_netdev ( netdev ) ) != 0 )
733 goto err_register_netdev;
734
735 /* Set initial link state */
736 rhine_check_link ( netdev );
737
738 return 0;
739
740 err_register_netdev:
741 err_mii_reset:
742 err_reload_eeprom:
743 rhine_reset ( rhn );
744 err_reset:
745 netdev_nullify ( netdev );
746 netdev_put ( netdev );
747 err_alloc:
748 return rc;
749 }
750
751 /**
752 * Remove PCI device
753 *
754 * @v pci PCI device
755 */
756 static void rhine_remove ( struct pci_device *pci ) {
757 struct net_device *netdev = pci_get_drvdata ( pci );
758 struct rhine_nic *nic = netdev->priv;
759
760 /* Unregister network device */
761 unregister_netdev ( netdev );
762
763 /* Reset card */
764 rhine_reset ( nic );
765
766 /* Free network device */
767 netdev_nullify ( netdev );
768 netdev_put ( netdev );
769 }
770
771 /** Rhine PCI device IDs */
772 static struct pci_device_id rhine_nics[] = {
773 PCI_ROM ( 0x1106, 0x3065, "dlink-530tx", "VIA VT6102", 0 ),
774 PCI_ROM ( 0x1106, 0x3106, "vt6105", "VIA VT6105", 0 ),
775 PCI_ROM ( 0x1106, 0x3043, "dlink-530tx-old", "VIA VT3043", 0 ),
776 PCI_ROM ( 0x1106, 0x3053, "vt6105m", "VIA VT6105M", 0 ),
777 PCI_ROM ( 0x1106, 0x6100, "via-rhine-old", "VIA 86C100A", 0 )
778 };
779
780 /** Rhine PCI driver */
781 struct pci_driver rhine_driver __pci_driver = {
782 .ids = rhine_nics,
783 .id_count = ( sizeof ( rhine_nics ) / sizeof ( rhine_nics[0] ) ),
784 .probe = rhine_probe,
785 .remove = rhine_remove,
786 };