[pci] Add support for PCI MSI-X interrupts
[ipxe.git] / src / include / ipxe / pci.h
1 #ifndef _IPXE_PCI_H
2 #define _IPXE_PCI_H
3
4 /** @file
5 *
6 * PCI bus
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/device.h>
14 #include <ipxe/tables.h>
15 #include <ipxe/pci_io.h>
16
17 /** PCI vendor ID */
18 #define PCI_VENDOR_ID 0x00
19
20 /** PCI device ID */
21 #define PCI_DEVICE_ID 0x02
22
23 /** PCI command */
24 #define PCI_COMMAND 0x04
25 #define PCI_COMMAND_IO 0x0001 /**< I/O space */
26 #define PCI_COMMAND_MEM 0x0002 /**< Memory space */
27 #define PCI_COMMAND_MASTER 0x0004 /**< Bus master */
28 #define PCI_COMMAND_INVALIDATE 0x0010 /**< Mem. write & invalidate */
29 #define PCI_COMMAND_PARITY 0x0040 /**< Parity error response */
30 #define PCI_COMMAND_SERR 0x0100 /**< SERR# enable */
31 #define PCI_COMMAND_INTX_DISABLE 0x0400 /**< Interrupt disable */
32
33 /** PCI status */
34 #define PCI_STATUS 0x06
35 #define PCI_STATUS_CAP_LIST 0x0010 /**< Capabilities list */
36 #define PCI_STATUS_PARITY 0x0100 /**< Master data parity error */
37 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /**< Received target abort */
38 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /**< Received master abort */
39 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /**< Signalled system error */
40 #define PCI_STATUS_DETECTED_PARITY 0x8000 /**< Detected parity error */
41
42 /** PCI revision */
43 #define PCI_REVISION 0x08
44
45 /** PCI cache line size */
46 #define PCI_CACHE_LINE_SIZE 0x0c
47
48 /** PCI latency timer */
49 #define PCI_LATENCY_TIMER 0x0d
50
51 /** PCI header type */
52 #define PCI_HEADER_TYPE 0x0e
53 #define PCI_HEADER_TYPE_NORMAL 0x00 /**< Normal header */
54 #define PCI_HEADER_TYPE_BRIDGE 0x01 /**< PCI-to-PCI bridge header */
55 #define PCI_HEADER_TYPE_CARDBUS 0x02 /**< CardBus header */
56 #define PCI_HEADER_TYPE_MASK 0x7f /**< Header type mask */
57 #define PCI_HEADER_TYPE_MULTI 0x80 /**< Multi-function device */
58
59 /** PCI base address registers */
60 #define PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) )
61 #define PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )
62 #define PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )
63 #define PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )
64 #define PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )
65 #define PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )
66 #define PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )
67 #define PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL /**< I/O BAR */
68 #define PCI_BASE_ADDRESS_IO_MASK 0x00000003UL /**< I/O BAR mask */
69 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL /**< 64-bit memory */
70 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL /**< Memory type mask */
71 #define PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL /**< Memory BAR mask */
72
73 /** PCI subsystem vendor ID */
74 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
75
76 /** PCI subsystem ID */
77 #define PCI_SUBSYSTEM_ID 0x2e
78
79 /** PCI expansion ROM base address */
80 #define PCI_ROM_ADDRESS 0x30
81
82 /** PCI capabilities pointer */
83 #define PCI_CAPABILITY_LIST 0x34
84
85 /** CardBus capabilities pointer */
86 #define PCI_CB_CAPABILITY_LIST 0x14
87
88 /** PCI interrupt line */
89 #define PCI_INTERRUPT_LINE 0x3c
90
91 /** Capability ID */
92 #define PCI_CAP_ID 0x00
93 #define PCI_CAP_ID_PM 0x01 /**< Power management */
94 #define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
95 #define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
96 #define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
97 #define PCI_CAP_ID_MSIX 0x11 /**< MSI-X */
98 #define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */
99
100 /** Next capability */
101 #define PCI_CAP_NEXT 0x01
102
103 /** Power management control and status */
104 #define PCI_PM_CTRL 0x04
105 #define PCI_PM_CTRL_STATE_MASK 0x0003 /**< Current power state */
106 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
107 #define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
108
109 /** PCI Express */
110 #define PCI_EXP_DEVCTL 0x08
111 #define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
112
113 /** MSI-X interrupts */
114 #define PCI_MSIX_CTRL 0x02
115 #define PCI_MSIX_CTRL_ENABLE 0x8000 /**< Enable MSI-X */
116 #define PCI_MSIX_CTRL_MASK 0x4000 /**< Mask all interrupts */
117 #define PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff ) /**< Table size */
118 #define PCI_MSIX_DESC_TABLE 0x04
119 #define PCI_MSIX_DESC_PBA 0x08
120 #define PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 ) /**< BAR index */
121 #define PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) /**< BAR offset */
122
123 /** Uncorrectable error status */
124 #define PCI_ERR_UNCOR_STATUS 0x04
125
126 /** Network controller */
127 #define PCI_CLASS_NETWORK 0x02
128
129 /** Serial bus controller */
130 #define PCI_CLASS_SERIAL 0x0c
131 #define PCI_CLASS_SERIAL_USB 0x03 /**< USB controller */
132 #define PCI_CLASS_SERIAL_USB_UHCI 0x00 /**< UHCI USB controller */
133 #define PCI_CLASS_SERIAL_USB_OHCI 0x10 /**< OHCI USB controller */
134 #define PCI_CLASS_SERIAL_USB_EHCI 0x20 /**< ECHI USB controller */
135 #define PCI_CLASS_SERIAL_USB_XHCI 0x30 /**< xHCI USB controller */
136
137 /** Construct PCI class
138 *
139 * @v base Base class (or PCI_ANY_ID)
140 * @v sub Subclass (or PCI_ANY_ID)
141 * @v progif Programming interface (or PCI_ANY_ID)
142 */
143 #define PCI_CLASS( base, sub, progif ) \
144 ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
145 ( ( (progif) & 0xff) << 0 ) )
146
147 /** PCI Express function level reset delay (in ms) */
148 #define PCI_EXP_FLR_DELAY_MS 100
149
150 /** A PCI device ID list entry */
151 struct pci_device_id {
152 /** Name */
153 const char *name;
154 /** PCI vendor ID */
155 uint16_t vendor;
156 /** PCI device ID */
157 uint16_t device;
158 /** Arbitrary driver data */
159 unsigned long driver_data;
160 };
161
162 /** Match-anything ID */
163 #define PCI_ANY_ID 0xffff
164
165 /** A PCI class ID */
166 struct pci_class_id {
167 /** Class */
168 uint32_t class;
169 /** Class mask */
170 uint32_t mask;
171 };
172
173 /** Construct PCI class ID
174 *
175 * @v base Base class (or PCI_ANY_ID)
176 * @v sub Subclass (or PCI_ANY_ID)
177 * @v progif Programming interface (or PCI_ANY_ID)
178 */
179 #define PCI_CLASS_ID( base, sub, progif ) { \
180 .class = PCI_CLASS ( base, sub, progif ), \
181 .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) | \
182 ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) | \
183 ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
184 }
185
186 /** A PCI device */
187 struct pci_device {
188 /** Generic device */
189 struct device dev;
190 /** Memory base
191 *
192 * This is the physical address of the first valid memory BAR.
193 */
194 unsigned long membase;
195 /**
196 * I/O address
197 *
198 * This is the physical address of the first valid I/O BAR.
199 */
200 unsigned long ioaddr;
201 /** Vendor ID */
202 uint16_t vendor;
203 /** Device ID */
204 uint16_t device;
205 /** Device class */
206 uint32_t class;
207 /** Interrupt number */
208 uint8_t irq;
209 /** Segment, bus, device, and function (bus:dev.fn) number */
210 uint32_t busdevfn;
211 /** Driver for this device */
212 struct pci_driver *driver;
213 /** Driver-private data
214 *
215 * Use pci_set_drvdata() and pci_get_drvdata() to access this
216 * field.
217 */
218 void *priv;
219 /** Driver device ID */
220 struct pci_device_id *id;
221 };
222
223 /** A PCI driver */
224 struct pci_driver {
225 /** PCI ID table */
226 struct pci_device_id *ids;
227 /** Number of entries in PCI ID table */
228 unsigned int id_count;
229 /** PCI class ID */
230 struct pci_class_id class;
231 /**
232 * Probe device
233 *
234 * @v pci PCI device
235 * @ret rc Return status code
236 */
237 int ( * probe ) ( struct pci_device *pci );
238 /**
239 * Remove device
240 *
241 * @v pci PCI device
242 */
243 void ( * remove ) ( struct pci_device *pci );
244 };
245
246 /** PCI driver table */
247 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
248
249 /** Declare a PCI driver */
250 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
251
252 /** Declare a fallback PCI driver */
253 #define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
254
255 #define PCI_SEG( busdevfn ) ( ( (busdevfn) >> 16 ) & 0xffff )
256 #define PCI_BUS( busdevfn ) ( ( (busdevfn) >> 8 ) & 0xff )
257 #define PCI_SLOT( busdevfn ) ( ( (busdevfn) >> 3 ) & 0x1f )
258 #define PCI_FUNC( busdevfn ) ( ( (busdevfn) >> 0 ) & 0x07 )
259 #define PCI_BUSDEVFN( segment, bus, slot, func ) \
260 ( ( (segment) << 16 ) | ( (bus) << 8 ) | \
261 ( (slot) << 3 ) | ( (func) << 0 ) )
262 #define PCI_FIRST_FUNC( busdevfn ) ( (busdevfn) & ~0x07 )
263 #define PCI_LAST_FUNC( busdevfn ) ( (busdevfn) | 0x07 )
264
265 #define PCI_BASE_CLASS( class ) ( (class) >> 16 )
266 #define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
267 #define PCI_PROG_INTF( class ) ( (class) & 0xff )
268
269 /*
270 * PCI_ROM is used to build up entries in a struct pci_id array. It
271 * is also parsed by parserom.pl to generate Makefile rules and files
272 * for rom-o-matic.
273 *
274 * PCI_ID can be used to generate entries without creating a
275 * corresponding ROM in the build process.
276 */
277 #define PCI_ID( _vendor, _device, _name, _description, _data ) { \
278 .vendor = _vendor, \
279 .device = _device, \
280 .name = _name, \
281 .driver_data = _data \
282 }
283 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
284 PCI_ID( _vendor, _device, _name, _description, _data )
285
286 /** PCI device debug message format */
287 #define PCI_FMT "%04x:%02x:%02x.%x"
288
289 /** PCI device debug message arguments */
290 #define PCI_ARGS( pci ) \
291 PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ), \
292 PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )
293
294 extern void adjust_pci_device ( struct pci_device *pci );
295 extern unsigned long pci_bar_start ( struct pci_device *pci,
296 unsigned int reg );
297 extern int pci_read_config ( struct pci_device *pci );
298 extern int pci_find_next ( struct pci_device *pci, unsigned int busdevfn );
299 extern int pci_find_driver ( struct pci_device *pci );
300 extern int pci_probe ( struct pci_device *pci );
301 extern void pci_remove ( struct pci_device *pci );
302 extern int pci_find_capability ( struct pci_device *pci, int capability );
303 extern int pci_find_next_capability ( struct pci_device *pci,
304 int pos, int capability );
305 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
306
307 /**
308 * Initialise PCI device
309 *
310 * @v pci PCI device
311 * @v busdevfn PCI bus:dev.fn address
312 */
313 static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
314 pci->busdevfn = busdevfn;
315 }
316
317 /**
318 * Set PCI driver
319 *
320 * @v pci PCI device
321 * @v driver PCI driver
322 * @v id PCI device ID
323 */
324 static inline void pci_set_driver ( struct pci_device *pci,
325 struct pci_driver *driver,
326 struct pci_device_id *id ) {
327 pci->driver = driver;
328 pci->id = id;
329 pci->dev.driver_name = id->name;
330 }
331
332 /**
333 * Set PCI driver-private data
334 *
335 * @v pci PCI device
336 * @v priv Private data
337 */
338 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
339 pci->priv = priv;
340 }
341
342 /**
343 * Get PCI driver-private data
344 *
345 * @v pci PCI device
346 * @ret priv Private data
347 */
348 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
349 return pci->priv;
350 }
351
352 #endif /* _IPXE_PCI_H */