opensbi.git
12 days agolib: utils/fdt: rename fdt_parse_max_hart_id master
Jan Remes [Fri, 13 May 2022 10:58:43 +0000 (12:58 +0200)] 
lib: utils/fdt: rename fdt_parse_max_hart_id

The function returns the highest hart-id of the harts actually used in
the system (enabled). Change the name to reflect this fact.

Signed-off-by: Jan Remes <jan.remes@codasip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
12 days agoplatform: generic: check if CPU node is enabled
Jan Remes [Fri, 13 May 2022 10:58:42 +0000 (12:58 +0200)] 
platform: generic: check if CPU node is enabled

Ignore CPU nodes in FDT which are not enabled.

Signed-off-by: Jan Remes <jan.remes@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
12 days agolib: utils: check if CPU node is enabled
Jan Remes [Fri, 13 May 2022 10:58:41 +0000 (12:58 +0200)] 
lib: utils: check if CPU node is enabled

Ignore CPU nodes in FDT that are not enabled.

Signed-off-by: Jan Remes <jan.remes@codasip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
12 days agolib: utils/fdt: introduce fdt_node_is_enabled()
Jan Remes [Fri, 13 May 2022 10:58:40 +0000 (12:58 +0200)] 
lib: utils/fdt: introduce fdt_node_is_enabled()

If an FDT node contains a "status" property and this property is not
"ok" or "okay", this node should be ignored. Introduce a function that
checks this.

Signed-off-by: Jan Remes <jan.remes@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
13 days agolib: utils/irqchip: fix typo when checking for CPU node
Jan Remes [Fri, 13 May 2022 04:28:54 +0000 (09:58 +0530)] 
lib: utils/irqchip: fix typo when checking for CPU node

Fix typo in irqchip_imsic_update_hartid_table() when checking for CPU
node.

Signed-off-by: Jan Remes <jan.remes@codasip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
13 days agoplatform: generic: Move Sifive platform overrides into own directory
Anup Patel [Fri, 13 May 2022 03:57:23 +0000 (09:27 +0530)] 
platform: generic: Move Sifive platform overrides into own directory

Let us move SiFive platform overrides for FU540 and FU740 into a separate
directory so better maintainability. Other SoC vendors can also create
their own directory under platform/generic.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agoplatform: generic: Generate platform override module list at compile-time
Anup Patel [Fri, 13 May 2022 03:57:18 +0000 (09:27 +0530)] 
platform: generic: Generate platform override module list at compile-time

Instead of having platform override module list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/gpio: Generate FDT gpio driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:57:12 +0000 (09:27 +0530)] 
lib: utils/gpio: Generate FDT gpio driver list at compile-time

Instead of having FDT gpio driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/i2c: Generate FDT i2c adapter driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:56:45 +0000 (09:26 +0530)] 
lib: utils/i2c: Generate FDT i2c adapter driver list at compile-time

Instead of having FDT i2c adapter driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/ipi: Generate FDT ipi driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:56:35 +0000 (09:26 +0530)] 
lib: utils/ipi: Generate FDT ipi driver list at compile-time

Instead of having FDT ipi driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/irqchip: Generate FDT irqchip driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:56:27 +0000 (09:26 +0530)] 
lib: utils/irqchip: Generate FDT irqchip driver list at compile-time

Instead of having FDT irqchip driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/timer: Generate FDT timer driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:56:20 +0000 (09:26 +0530)] 
lib: utils/timer: Generate FDT timer driver list at compile-time

Instead of having FDT timer driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/serial: Generate FDT serial driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:56:13 +0000 (09:26 +0530)] 
lib: utils/serial: Generate FDT serial driver list at compile-time

Instead of having FDT serial driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agolib: utils/reset: Generate FDT reset driver list at compile-time
Anup Patel [Fri, 13 May 2022 03:56:06 +0000 (09:26 +0530)] 
lib: utils/reset: Generate FDT reset driver list at compile-time

Instead of having FDT reset driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agoMakefile: Add support for generating C array at compile time
Anup Patel [Fri, 13 May 2022 03:56:00 +0000 (09:26 +0530)] 
Makefile: Add support for generating C array at compile time

Generating C array at compile time based on details provided by
objects.mk is a very useful feature which will help us compile
only a subset of drivers or modules.

We add a bash script (carray.sh) which takes array details and
object/variable list from command-line to generate a C source
containing array of object/variable pointers. We also extend
top-level makefile to use carray.sh whenever specified through
objects.mk.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
13 days agoMakefile: Allow generated C source to be anywhere in build directory
Anup Patel [Fri, 13 May 2022 03:55:50 +0000 (09:25 +0530)] 
Makefile: Allow generated C source to be anywhere in build directory

The generated C source could be anywhere within build directory so
let us update the make rule to comple generated C source accordingly.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi_platform: Add callback to populate HART extensions
Anup Patel [Fri, 29 Apr 2022 15:32:24 +0000 (21:02 +0530)] 
lib: sbi_platform: Add callback to populate HART extensions

We add platform specific extensions_init() callback which allows
platforms to populate HART extensions for each HART. For example,
the generic platform can populate HART extensions from HART ISA
string described in DeviceTree.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Add sbi_hart_update_extension() function
Anup Patel [Fri, 29 Apr 2022 15:17:04 +0000 (20:47 +0530)] 
lib: sbi: Add sbi_hart_update_extension() function

We add sbi_hart_update_extension() function which allow platforms
to enable/disable hart extensions.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Detect hart features only once for each hart
Anup Patel [Fri, 29 Apr 2022 13:08:05 +0000 (18:38 +0530)] 
lib: sbi: Detect hart features only once for each hart

Currently, the hart_detect_features() is called everytime a hart
is stopped and started again which is unnecessary work.

We update hart_detect_features() to detect hart features only
once for each hart.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Convert hart features into hart extensions
Anup Patel [Thu, 28 Apr 2022 15:59:22 +0000 (21:29 +0530)] 
lib: sbi: Convert hart features into hart extensions

Since past few years, we have been using "hart features" in OpenSBI
to represent all optionalities and multi-letter extensions defined
by the RISC-V specifications.

The RISC-V profiles specification has taken a different approach and
started assigning extension names for all optionalities which did not
have any extension name previously.
(Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

Inspired from the RISC-V profiles specification, we convert OpenSBI
hart features into hart extensions. Going forward, we align the
extension naming with RISC-V profiles specification. Currently, only
"time CSR" and "AIA CSR" have not been assigned extension name but
for everything else we have a name.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Fix AIA feature detection
Anup Patel [Thu, 28 Apr 2022 14:05:39 +0000 (19:35 +0530)] 
lib: sbi: Fix AIA feature detection

The AIA feature detection uses unnecessary goto which is not need
and AIA case in sbi_hart_feature_id2string() does not break. This
patch fixes both issues in AIA feature detection.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Remove MENVCFG hart feature
Anup Patel [Thu, 28 Apr 2022 13:48:17 +0000 (19:18 +0530)] 
lib: sbi: Remove MENVCFG hart feature

If a hart implements privileged spec v1.12 (or higher) then we can
safely assume that menvcfg CSR is present and we don't need MENVCFG
as a hart feature.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Remove MCOUNTINHIBT hart feature
Anup Patel [Thu, 28 Apr 2022 13:29:14 +0000 (18:59 +0530)] 
lib: sbi: Remove MCOUNTINHIBT hart feature

If a hart implements privileged spec v1.11 (or higher) then we can
safely assume that mcountinhibit CSR is present and we don't need
MCOUNTINHIBT as a hart feature.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features
Anup Patel [Thu, 28 Apr 2022 13:01:57 +0000 (18:31 +0530)] 
lib: sbi: Remove MCOUNTEREN and SCOUNTEREN hart features

If a hart implements privileged spec v1.10 (or higher) then we can
safely assume that [m|s]counteren CSR are present and we don't need
MCOUNTEREN and SCOUNTEREN as hart features.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Update the name of ISA string printed at boot time
Anup Patel [Thu, 28 Apr 2022 12:41:02 +0000 (18:11 +0530)] 
lib: sbi: Update the name of ISA string printed at boot time

The ISA string printed at boot time is not the complete ISA string
representing all single letter and multi-letter extensions rather
it is base ISA string derived from misa CSR so let us update the
boot print accordingly.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Remove 's' and 'u' from misa_string() output
Anup Patel [Thu, 28 Apr 2022 12:20:59 +0000 (17:50 +0530)] 
lib: sbi: Remove 's' and 'u' from misa_string() output

Both 's' and 'u' are not treated as ISA extensions since these are
privilege modes so let's remove it from misa_string() output.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Detect and print privileged spec version
Anup Patel [Thu, 28 Apr 2022 12:00:02 +0000 (17:30 +0530)] 
lib: sbi: Detect and print privileged spec version

It is possible to guess privileged spec versions based on the CSRs
that where introduced in different privileged spec versions. In
future, if we are not able guess privileged spec version then we
can have platform provide it.

We add privileged spec version as per-hart feature and try to guess
it based on presence of mcounteren, mcountinhibit, and menvcfg CSRs.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
2 weeks agolib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmf
Atish Patra [Thu, 28 Apr 2022 18:48:29 +0000 (11:48 -0700)] 
lib: sbi: Fix mhpmeventh access for rv32 in absence of sscofpmf

MHPMEVENT3H-31H are defined in sscofpmf extension. Thus, they should be
accessed only if sscofpmf is present.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2 weeks agoinclude: sbi: Define SBI_PMU_HW_EVENT_MAX to 256
Jun Liang Tan [Thu, 28 Apr 2022 09:45:02 +0000 (17:45 +0800)] 
include: sbi: Define SBI_PMU_HW_EVENT_MAX to 256

Increase maximum number of PMU hardware events that can be mapped
by OpenSBI to 256

Signed-off-by: Jun Liang Tan <junliang.tan@linux.starfivetech.com>
Signed-off-by: Wei Liang Lim <weiliang.lim@linux.starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
4 weeks agolib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not available
Anup Patel [Thu, 28 Apr 2022 07:43:59 +0000 (13:13 +0530)] 
lib: sbi: Fix mstatus_init() for RV32 when Sscofpmf is not available

The mhpmevent3h to mhpmevent31h CSRs are available on RV32 only when
Sscofpmf extension is available so mstatus_init() should set this
CSRs only when Sscofpmf extension is available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
4 weeks agolib: sbi: Implement Sstc extension
Atish Patra [Tue, 26 Apr 2022 06:29:22 +0000 (23:29 -0700)] 
lib: sbi: Implement Sstc extension

Recently, Sstc extension was ratified. It defines stimecmp which allows
the supervisor mode to directly update the timecmp value without the
need of the SBI call. The hardware also can inject the S-mode timer
interrupt direclty to the supervisor without going through the M-mode.
To maintain backward compatibility with the older software, SBI call
now uses stimecmp directly if the hardware supports.

Implement the Sstc extension.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
4 weeks agodocs: pmu: Improve the PMU DT bindings
Atish Patra [Thu, 21 Apr 2022 02:48:56 +0000 (19:48 -0700)] 
docs: pmu: Improve the PMU DT bindings

The current DT binding description is misleading and confusing. Clarify
the text and provide more examples.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 weeks agolib: sbi/hart: preserve csr validation value
Dmitry Dunaev [Sun, 17 Apr 2022 09:13:08 +0000 (14:43 +0530)] 
lib: sbi/hart: preserve csr validation value

The OpenSBI hart init function hart_detect_features() try to read
important CSRs but reasign the last read value to the variable that
initially contains write probe value. So for series of CSRs (like
PMPADDRx) the second CSR probe value will became the initial value of
first probing CSR. To avoid of this issue the CSR read value should be
saved in different variable. In this configuration the count of PMP
will detect rightly if any PMPADDR is hardwired to zero.

Signed-off-by: Dmitry Dunaev <dunaich@mail.ru>
Signed-off-by: Anup Patel <anup@brainfault.org>
5 weeks agoinclude: correct the definition of MSTATUS_VS
Vincent Chen [Tue, 12 Apr 2022 01:16:53 +0000 (09:16 +0800)] 
include: correct the definition of MSTATUS_VS

Accordind to the RISC-V privileged specification, the VS filed is
mstatus[10:9] instead of mstatus[24:23]. Modify the MSTATUS_VS
to the correct value.

Reported-by: I-Cheng Cheng <i-cheng.cheng@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 weeks agolib: utils/serial: support 'reg-offset' property
Zong Li [Fri, 15 Apr 2022 02:24:20 +0000 (02:24 +0000)] 
lib: utils/serial: support 'reg-offset' property

reg-offset property is used for offset to apply to the mapbase
from the start of the registers in 8250 UART. In Linux kernel,
it has been handled in 8250 UART driver.

dt-bindings:
<linux>/Documentation/devicetree/bindings/serial/8250.yaml

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
6 weeks agolib: irqchip/imsic: configure mstateen
Mayuresh Chitale [Mon, 11 Apr 2022 03:04:17 +0000 (08:34 +0530)] 
lib: irqchip/imsic: configure mstateen

When mstateen registers are implemented, the AIA related
configurations need to be done in mstateen for the IMSIC
initialization to succeed.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
6 weeks agolib: sbi: Detect Smstateen CSRs at boot-time
Mayuresh Chitale [Mon, 11 Apr 2022 03:04:10 +0000 (08:34 +0530)] 
lib: sbi: Detect Smstateen CSRs at boot-time

Extend HART feature detection to discover Smstateen CSRs at boot-time
and configure mstateen envcfg bit depending on availability of
menvcfg CSR.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
6 weeks agolib: sbi: Add Smstateen extension defines
Mayuresh Chitale [Mon, 11 Apr 2022 03:04:02 +0000 (08:34 +0530)] 
lib: sbi: Add Smstateen extension defines

Smstateen extension provides a mechanism to plug potential
covert channels which are opened by extensions that add to
processor state that may not get context-switched.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
7 weeks agolib: sbi: Enable Svpbmt extension in the menvcfg CSR
Anup Patel [Tue, 29 Mar 2022 14:25:23 +0000 (19:55 +0530)] 
lib: sbi: Enable Svpbmt extension in the menvcfg CSR

The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
available so we try to enable menvcfg.PBMTE bit irrespective whether
Svpbmt is available or not.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
7 weeks agolib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR
Anup Patel [Tue, 29 Mar 2022 14:12:22 +0000 (19:42 +0530)] 
lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR

The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
CSR are WARL. We try to enable these bits irrespective whether
these extensions are available or not because writes to these
bits will be ignored if these extensions are not available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
7 weeks agolib: sbi: Detect menvcfg CSR at boot time
Atish Patra [Tue, 29 Mar 2022 13:55:36 +0000 (19:25 +0530)] 
lib: sbi: Detect menvcfg CSR at boot time

We add the menvcfg CSR as a HART feature and detect it at boot time
using traping mechanism.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
7 weeks agoinclude: Add defines for [m|h|s]envcfg CSRs
Anup Patel [Tue, 29 Mar 2022 13:30:37 +0000 (19:00 +0530)] 
include: Add defines for [m|h|s]envcfg CSRs

The latest RISC-V privileged specification introduces xenvcfg CSRs
to enable/disable certain features/extensions for lower privilege
modes. This patch adds defines for these new [m|h|s]envcfg CSRs.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
8 weeks agoinclude: Use static asserts for FW_DYNAMIC_INFO_xxx_OFFSET defines
Xiang W [Wed, 16 Mar 2022 10:19:18 +0000 (18:19 +0800)] 
include: Use static asserts for FW_DYNAMIC_INFO_xxx_OFFSET defines

Add static detection to prevent the modification of struct fw_dynamic_info
from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
8 weeks agoinclude: Use static asserts for SBI_SCRATCH_xxx_OFFSET defines
Xiang W [Wed, 16 Mar 2022 10:16:48 +0000 (18:16 +0800)] 
include: Use static asserts for SBI_SCRATCH_xxx_OFFSET defines

Add static detection to prevent the modification of struct sbi_scratch
from forgetting the modification of SBI_SCRATCH_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
8 weeks agoinclude: Use static asserts for SBI_PLATFORM_xxx_OFFSET defines
Xiang W [Wed, 16 Mar 2022 01:45:25 +0000 (09:45 +0800)] 
include: Use static asserts for SBI_PLATFORM_xxx_OFFSET defines

Add static detection to prevent the modification of struct sbi_platform
from forgetting the modification of SBI_PLATFORM_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
8 weeks agolib: Add error messages via conditional compilation for the future
Xiang W [Tue, 15 Mar 2022 16:22:40 +0000 (00:22 +0800)] 
lib: Add error messages via conditional compilation for the future

On 128-bit machines, sbi_load_xx/sbi_store_xx needs to be improved.
Through this conditional compile, the corresponding implementation
can be prompted to be added.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
8 weeks agofirmware: Fix code for accessing hart_count and stack_size
Xiang W [Tue, 15 Mar 2022 16:22:39 +0000 (00:22 +0800)] 
firmware: Fix code for accessing hart_count and stack_size

lwu exists under the current rv64 and should also exist under the rv128
in the future, so I modified the conditions of conditional compilation
so that it can adapt to the future situation

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
8 weeks agolib: pmp_set/pmp_get moved errors from runtime to compile time
Xiang W [Tue, 15 Mar 2022 16:22:38 +0000 (00:22 +0800)] 
lib: pmp_set/pmp_get moved errors from runtime to compile time

pmp_set/pmp_get calculates the location of the CSR register separately
through conditional compilation. In the case of non-32-bit and 64-bit,
we can report an error directly through #error without putting it at
runtime

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2 months agolib: utils: serial: Initial commit of xlnx-uartlite
Alistair Francis [Thu, 24 Feb 2022 05:01:46 +0000 (15:01 +1000)] 
lib: utils: serial: Initial commit of xlnx-uartlite

Initial commit of the xlnx-uartlite device and FDT support. This was
tested by running OpenSBI on a modified QEMU virt machine using the
xlnx-uartlite for serial.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2 months agolib: sbi: Add a simple external interrupt handling framework
Anup Patel [Fri, 18 Feb 2022 17:48:41 +0000 (23:18 +0530)] 
lib: sbi: Add a simple external interrupt handling framework

Currently, the external interrupt handling is scattered between
sbi_init and sbi_trap. This patch moves all external interrupt
handling into a simple framework called sbi_irqchip.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: sbi: verbose sbi_domain_root_add_memregion
Nikita Shubin [Fri, 11 Feb 2022 11:11:54 +0000 (14:11 +0300)] 
lib: sbi: verbose sbi_domain_root_add_memregion

Be more verbose on region confict, print addresses in conflict.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agolib: sbi: fix typo in is_region_subset
Nikita Shubin [Fri, 11 Feb 2022 11:11:53 +0000 (14:11 +0300)] 
lib: sbi: fix typo in is_region_subset

Fix typo in is_region_subset, regB_end should be calculated from regB.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agolib: utils: Disable appropriate APLIC DT nodes in fdt_fixups()
Anup Patel [Tue, 15 Jun 2021 06:07:59 +0000 (11:37 +0530)] 
lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups()

We should disable APLIC DT nodes in fdt_fixups() which are not
accessible to the next booting stage based on currently assigned
domain.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils/irqchip: Add FDT based driver for APLIC
Anup Patel [Thu, 8 Apr 2021 12:40:16 +0000 (18:10 +0530)] 
lib: utils/irqchip: Add FDT based driver for APLIC

We add simple FDT irqchip driver for APLIC so that generic platform (and
other FDT based platforms) can utilize common APLIC initialization library.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils/irqchip: Add APLIC initialization library
Anup Patel [Thu, 8 Apr 2021 05:58:02 +0000 (11:28 +0530)] 
lib: utils/irqchip: Add APLIC initialization library

We add simple APLIC initialization library which is independent of
hardware description format (FDT or ACPI). This APLIC initialization
library can be used by custom OpenSBI platform support to setup
APLIC domains.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups()
Anup Patel [Tue, 15 Jun 2021 05:49:40 +0000 (11:19 +0530)] 
lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups()

We should disable IMSIC DT nodes in fdt_fixups() which are not
accessible to the next booting stage based on currently assigned
domain.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils/irqchip: Add FDT based driver for IMSIC
Anup Patel [Wed, 21 Apr 2021 09:57:29 +0000 (15:27 +0530)] 
lib: utils/irqchip: Add FDT based driver for IMSIC

We add simple FDT irqchip driver for IMSIC so that generic platform
(and other FDT based platforms) can utilize common IMIC library.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils/irqchip: Add IMSIC library
Anup Patel [Tue, 20 Apr 2021 11:03:40 +0000 (16:33 +0530)] 
lib: utils/irqchip: Add IMSIC library

We add simple IMSIC library which is independent of hardware description
format (FDT or ACPI). This IMSIC library can be used by custom OpenSBI
platform support to setup IMSIC for external interrupts.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: sbi: Enable mie.MEIE bit for IPIs based on external interrupts.
Anup Patel [Tue, 29 Jun 2021 07:59:52 +0000 (13:29 +0530)] 
lib: sbi: Enable mie.MEIE bit for IPIs based on external interrupts.

We can have IPIs based on external interrupts provided by devices
such as AIA IMSIC so we should enable mie.MEIE bit at appropriate
places in generic library.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agoinclude: sbi: Introduce nascent_init() platform callback
Anup Patel [Tue, 29 Jun 2021 07:44:04 +0000 (13:14 +0530)] 
include: sbi: Introduce nascent_init() platform callback

We introduce nascent_init() platform callback which will allow
platforms to do very early initialization of platform specific
per-HART CSRs and per-HART devices.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils/irqchip: Allow multiple FDT irqchip drivers
Anup Patel [Tue, 20 Apr 2021 06:22:47 +0000 (11:52 +0530)] 
lib: utils/irqchip: Allow multiple FDT irqchip drivers

We can have multiple FDT irqchip drivers to be probed when a RISC-V
system has different types of interrupt controller in a hierarchy.

This will be certainly the case when a RISC-V system has both
RISC-V AIA IMSIC and RISC-V AIA APLIC implemented.

We extend simple FDT irqchip framework to allow multiple FDT
irqchip drivers to be used for same RISC-V platform.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: sbi: Add sbi_trap_set_external_irqfn() API
Anup Patel [Tue, 6 Apr 2021 11:37:42 +0000 (17:07 +0530)] 
lib: sbi: Add sbi_trap_set_external_irqfn() API

This patch adds sbi_trap_set_external_irqfn() API which can be used by
OpenSBI platform code to set a callback function for external interrupts.
The RISC-V AIA IMSIC driver will use this API to implement inter-processor
interrupts on-top-of MSIs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: sbi: Use AIA CSRs for local interrupts when available
Anup Patel [Tue, 6 Apr 2021 10:40:00 +0000 (16:10 +0530)] 
lib: sbi: Use AIA CSRs for local interrupts when available

We should use AIA CSRs to process local interrupts whenever AIA
is available.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: sbi: Detect AIA CSRs at boot-time
Anup Patel [Tue, 6 Apr 2021 07:36:47 +0000 (13:06 +0530)] 
lib: sbi: Detect AIA CSRs at boot-time

We extend HART feature detection to discover AIA CSRs at boot-time.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agoinclude: sbi: Add AIA related CSR defines
Anup Patel [Mon, 5 Apr 2021 11:43:20 +0000 (17:13 +0530)] 
include: sbi: Add AIA related CSR defines

The RISC-V AIA specification improves handling of per-HART local
interrupts in a backward compatible manner. This patch adds defines
for the new RISC-V AIA CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
3 months agolib: utils/serial: Round UART8250 baud rate divisor to nearest integer
Jakub Luzny [Fri, 21 Jan 2022 15:06:14 +0000 (16:06 +0100)] 
lib: utils/serial: Round UART8250 baud rate divisor to nearest integer

Previously, it was rounded down and that gives suboptimal results when
non-standard clock sources or baud rates are used.

Signed-off-by: Jakub Luzny <jakub.luzny@codasip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agolib: fix compilation when strings.h is included
Petro Karashchenko [Fri, 28 Jan 2022 07:13:23 +0000 (09:13 +0200)] 
lib: fix compilation when strings.h is included

In a systems that provide strings.h and it is included
together with sbi_bitops.h the compilation error appears.
The ffs() and fls() are provided by strings.h

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agoMakefile: fix build with binutils 2.38
Aurelien Jarno [Fri, 28 Jan 2022 17:33:46 +0000 (18:33 +0100)] 
Makefile: fix build with binutils 2.38

From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:

 CC        lib/sbi/sbi_tlb.o
<<BUILDDIR>>/lib/sbi/sbi_tlb.c: Assembler messages:
<<BUILDDIR>>/lib/sbi/sbi_tlb.c:190: Error: unrecognized opcode `fence.i'
make: *** [Makefile:431: <<BUILDDIR>>/build/lib/sbi/sbi_tlb.o] Error 1

The fix is to specify those extensions explicitly in -march. However as
older binutils version do not support this, we first need to detect
that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agolib: sbi: Disable interrupt and inhibit counting in M-mode during init
Atish Patra [Fri, 7 Jan 2022 18:54:09 +0000 (10:54 -0800)] 
lib: sbi: Disable interrupt and inhibit counting in M-mode during init

Currently, the mhpmevent CSRs are untouched during hart init during
cold/warm boot. Ideally, we should clear out all the bits except
overflow and MINH bit. That is required to disable overflow
interrupt and inhibit counting in M-mode to avoid any spurious
interrupts before perf start.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agolib: sbi: Disable interrupt during config matching
Atish Patra [Fri, 7 Jan 2022 18:54:08 +0000 (10:54 -0800)] 
lib: sbi: Disable interrupt during config matching

PMU overflow interrupt should be disabled durinig initial configuration of
counters. They should be enabled while starting counters.

Fixes: 730f01bb41a6 ("lib: sbi: Support sscofpmf extension in OpenSBI")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
3 months agolib: sbi: Map only the counters enabled in hardware
Atish Patra [Fri, 7 Jan 2022 18:54:07 +0000 (10:54 -0800)] 
lib: sbi: Map only the counters enabled in hardware

The counter mapping in DT may be incorrect if all the counters specified
in the mapping are actually not physically present in the hardware.
OpenSBI should only keep a mapping of counters enabled in hardware and
defined in DT. This assume that all the programmable hpmcounters are
consecutive as it doesn't make sense to build a system with sparse
hpmcounters.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
4 months agolib: fix pointer of type 'void *' used in arithmetic
Jukka Laitinen [Wed, 19 Jan 2022 09:20:17 +0000 (11:20 +0200)] 
lib: fix pointer of type 'void *' used in arithmetic

Using "void *" in arithmetic causes errors with strict compiler settings:
"error: pointer of type 'void *' used in arithmetic [-Werror=pointer-arith]"

Avoid these by calculating on "char *" where 1-byte data size is assumed.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
4 months agoplatform: sifive_fu740: fix reset when watchdog is running
Aurelien Jarno [Wed, 5 Jan 2022 07:20:39 +0000 (08:20 +0100)] 
platform: sifive_fu740: fix reset when watchdog is running

When the watchdog is running the HiFive Unmatched board does not reboot
properly and shuts down itself a few seconds after reboot, in the early
stages of the u-boot loading. On a Linux kernel this happens when the
da9063_wdt module is loaded. This does not happen if the module is
unloaded before reboot or if the watchdog module is loaded with
"stop_on_reboot=1".

Fix that by stopping the watchdog before attempting to reset the board.
This is done by zeroing the TWDSCALE field of CONTROL_D register, unless
it was already set to 0.

Reported-by: Tianon Gravi <tianon@debian.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Nikita Shubin <n.shubin@yadro.com>
Tested-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
4 months agoplatform: sifive_fu740: do not use a global in da9063_reset/shutdown
Aurelien Jarno [Wed, 5 Jan 2022 07:20:38 +0000 (08:20 +0100)] 
platform: sifive_fu740: do not use a global in da9063_reset/shutdown

da9063_reset() and da9063_shutdown() take the chip address in argument
(like similar functions), but in practice use the da9063 global struct
instead. Fix that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Xiang W <wxjstz@126.com>
4 months agolib: utils/sys: Extend HTIF library to allow custom base address
Anup Patel [Thu, 6 Jan 2022 03:46:55 +0000 (09:16 +0530)] 
lib: utils/sys: Extend HTIF library to allow custom base address

Some of RISC-V emulators provide HTIF at fixed base address so for
such emulators users have to hard-code HTIF base address in the
linker script.

To address this problem, we let users optionally provide fixed HTIF
base address via platform support (or device tree).

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
4 months agolib: utils/ipi: Fix size check in aclint_mswi_cold_init()
Anup Patel [Thu, 6 Jan 2022 03:32:45 +0000 (09:02 +0530)] 
lib: utils/ipi: Fix size check in aclint_mswi_cold_init()

Currently, the ACLINT MSWI size check is forcing size to be at least
0x4000. This is inappropriate check because most systems will never
utilize full 16KB for a single ACLINT MSWI device so instead we should
check that ACLINT MSWI size is enough for on the associated HARTs.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5 months agoinclude: Bump-up version to 1.0 v1.0
Anup Patel [Fri, 24 Dec 2021 11:57:44 +0000 (17:27 +0530)] 
include: Bump-up version to 1.0

This patch updates OpenSBI version to 1.0 as part of
release preparation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
5 months agofirmware: Move memcpy/memset mapping to fw_base.S
Anup Patel [Wed, 22 Dec 2021 12:31:23 +0000 (18:01 +0530)] 
firmware: Move memcpy/memset mapping to fw_base.S

Some of the external firmwares using OpenSBI as library are facing
issues with the weak memcpy() and memset() aliases in libsbi.a so
we move these to fw_base.S. This way mapping of implicit memcpy()
or memset() calls to sbi_memcpy() or sbi_memset() will only be done
for OpenSBI firmwares.
(Refer, https://github.com/riscv-software-src/opensbi/issues/234)

In addition, we also add memmove() and memcmp() mappings in fw_base.S
because as-per the GCC documentation the freestanding environment must
provide memcpy(), memmove(), memset(), and memcmp().

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
5 months agolib: sbi: simplify pmp_set(), pmp_get()
Heinrich Schuchardt [Fri, 17 Dec 2021 17:02:58 +0000 (18:02 +0100)] 
lib: sbi: simplify pmp_set(), pmp_get()

pmpcfg_csr and pmpcfg_shift are only negative for an unexpected value of
__riscv_xlen. We can immediately return in this case.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 months agoMakefile: Improve the method to disable -m(no-)save-restore option
Xiang W [Sun, 12 Dec 2021 12:39:33 +0000 (20:39 +0800)] 
Makefile: Improve the method to disable -m(no-)save-restore option

The commit 69d7e53 disables the -m(no-)save-restore option for
clang, but clang11 supports this option. This patch uses the
output information of the compiler to check whether the compiler
supports this option.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 months agolib: sbi: Fix compile errors using -Os option
Anup Patel [Thu, 2 Dec 2021 11:22:16 +0000 (16:52 +0530)] 
lib: sbi: Fix compile errors using -Os option

When compiling with -Os option along with -ffreestanding, both GCC
and clang will add implicit calls to memcpy() and memset() for stack
variables initialized in declaration.

The C standard as per Clause 4, the compiler cannot necessarily
assume that anything beyond:

 * float.h
 * iso646.h
 * limits.h
 * stdalign.h
 * stdarg.h
 * stdbool.h
 * stddef.h
 * stdint.h
 * stdnoreturn.h
 * fenv.h
 * math.h
 * and the numeric conversion functions of stdlib.h.

This patch maps memcpy() and memset() as weak-alias of sbi_memcpy()
and sbi_memset() respectively so that implicit calls to memcpy()
and memset() will compile properly.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Xiang W <wxjstz@126.com>
5 months agoMakefile: Fix -msave-restore compile warning with CLANG-10 (or lower)
Anup Patel [Thu, 2 Dec 2021 05:00:28 +0000 (10:30 +0530)] 
Makefile: Fix -msave-restore compile warning with CLANG-10 (or lower)

The riscv target of CLANG-10 (or lower) does not support the
-m(no-)save-restore option so we get compile warnings. This patch
fixes compile warning by using -m(no-)save-restore option only
for GCC.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
5 months agolib: pmu: check SSCOF before masking
Nikita Shubin [Wed, 8 Dec 2021 11:16:54 +0000 (14:16 +0300)] 
lib: pmu: check SSCOF before masking

We should check if SSCOF extension is present,
before applying inhibit mask and clearing overflow,
otherwise undesirable value can be written
in MHPMEVENT_N CSR.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
5 months agodocs/platform: spike: Enhance Spike examples
Tsukasa OI [Fri, 3 Dec 2021 01:13:56 +0000 (10:13 +0900)] 
docs/platform: spike: Enhance Spike examples

This commit makes Spike usable as QEMU (in fact, those are based on
QEMU examples).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 months agolib: pmu: support the event ID encoded by a bitmap.
Vincent Chen [Thu, 2 Dec 2021 01:45:42 +0000 (17:45 -0800)] 
lib: pmu: support the event ID encoded by a bitmap.

RISC-V privilege specification does not specify how to encode the event ID.
Therefore, each platform is allowed to customize its own encoding rule.
The common encoding methods are as follow, directly assigning a number to an
event, or every bit in the mphmevent CSR controls one specified event or
mixes the above two methods.

To enable OpenSBI to support the above three encoding methods simultaneously,
this patch repurpose the dt property "riscv,raw-event-to-mhpmcounters". The
"riscv,raw-event-to-mhpmcounters" will describes the one or multiple raw
events that could be counted by a set of counters. But, the column number
of "riscv,raw-event-to-mhpmcounters" is extended from 2 to 3. The 1st column
(64bit) is the ID of the raw events. The 2nd column (64bit) represents a
select_mask now to represent the bits used for event ID encoding.
If a platform directly encodes each raw PMU event as a unique ID,
the value of select_mask will be 0xffffffff_ffffffff.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Atish Patra<atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 months agolib: sbi: Improve fatal error handling
Jessica Clarke [Sun, 21 Nov 2021 17:30:22 +0000 (17:30 +0000)] 
lib: sbi: Improve fatal error handling

BUG and BUG_ON are not informative and are rather lazy interfaces, only
telling the user that something went wrong in a given function, but not
what, requiring the user to find the sources corresponding to their
firmware (which may not be available) and figure out how that BUG(_ON)
was hit. Even SBI_ASSERT in its current form, which does include the
condition that triggered it in the output, isn't necessarily very
informative. In some cases, the error may be fixable by the user, but
they need to know the problem in order to have any hope of fixing it.
It's also a nuisance for developers, whose development trees may have
changed significantly since the release in question being used, and so
line numbers can make it harder for them to understand which error case
a user has hit.

This patch introduces a new sbi_panic function which is printf-like,
allowing detailed error messages to be printed to the console. BUG and
BUG_ON are removed, since the former is just a worse form of sbi_panic
and the latter is a worse version of SBI_ASSERT. Finally, SBI_ASSERT is
augmented to take a set of arguments to pass to sbi_panic on failure,
used like so (sbi_boot_print_hart's current error case, which currently
manually calls sbi_printf and sbi_hart_hang):

  SBI_ASSERT(xlen >= 1, ("Error %d getting MISA XLEN\n", xlen));

The existing users of BUG are replaced with calls to sbi_panic along
with informative error messages. BUG_ON and SBI_ASSERT were unused (and,
in the case of SBI_ASSERT, remain unused).

Many existing users of sbi_hart_hang should be converted to use either
sbi_panic or SBI_ASSERT after this commit.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
5 months agolib: sbi: Resolve the uninitialized complaint in sbi_pmu
Dong Du [Thu, 25 Nov 2021 10:38:17 +0000 (18:38 +0800)] 
lib: sbi: Resolve the uninitialized complaint in sbi_pmu

A recent commit (b28f0700) turns to read from CSR_MCOUNTINHIBIT after
checking the SBI_HART_HAS_MCOUNTINHIBIT HART feature, which leaves the
mctr_inhbt uninitialized in pmu_ctr_find_hw().
As a result, compiler will complain:
error: 'mctr_inhbt' may be used uninitialized in this function.

This commit resolves the issue by assigning an initial value to mctr_inhbt.

Signed-off-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
5 months agolib: sbi: Fix missing space
Nikita Shubin [Thu, 25 Nov 2021 10:00:16 +0000 (13:00 +0300)] 
lib: sbi: Fix missing space

Fix missing space in sbi_hart_pmp_configure
error printing.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Xiang w <wxjstz@126.com>
6 months agolib: sbi: Fix spelling of "address" in sbi_domain.c
Vagrant Cascadian [Fri, 19 Nov 2021 19:37:21 +0000 (11:37 -0800)] 
lib: sbi: Fix spelling of "address" in sbi_domain.c

Fix a spelling typo in error print.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
6 months agolib: utils: Add LiteX UART support
Gabriel Somlo [Tue, 16 Nov 2021 19:17:04 +0000 (14:17 -0500)] 
lib: utils: Add LiteX UART support

Add support for the UART provided by the LiteX SoC
framework (https://github.com/enjoy-digital/litex),
based on its FDT info (described in the Linux tree at
Documentation/devicetree/bindings/serial/litex,liteuart.yaml).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
6 months agolib: sbi: clear pmpcfg.A before setting in pmp_set()
Xiang W [Mon, 8 Nov 2021 09:43:03 +0000 (17:43 +0800)] 
lib: sbi: clear pmpcfg.A before setting in pmp_set()

We should clear A bits in prot variable before enabling A_NA4 or A_NAPOT.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
6 months agoplatform: sifive_fu740: add platform reset driver
Nikita Shubin [Wed, 10 Nov 2021 09:42:30 +0000 (12:42 +0300)] 
platform: sifive_fu740: add platform reset driver

da9063 PMIC can be used to reset/shutdown the
Sifive Unmatched board.

shutdown is done simply by writing SHUTDOWN bit to
DA9063_REG_CONTROL_F register.

reset via setting WAKEUP bit in DA9063_REG_CONTROL_F
register followed by masking POWER and POWER1 domains
and setting STANDBY bit in DA9063_REG_CONTROL_A,
originally discovered by Alexandre Ghiti on linux-riscv
maillists.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
6 months agolib: utils/i2c: Add minimal SiFive I2C driver
Nikita Shubin [Wed, 10 Nov 2021 09:42:29 +0000 (12:42 +0300)] 
lib: utils/i2c: Add minimal SiFive I2C driver

Minimum SiFive I2C driver to read/send bytes over I2C bus.

This allows querying information and perform operation of onboard PMIC,
as well as power-off and reset.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
6 months agolib: utils/i2c: Add simple FDT based I2C framework
Nikita Shubin [Wed, 10 Nov 2021 09:42:28 +0000 (12:42 +0300)] 
lib: utils/i2c: Add simple FDT based I2C framework

FDT based I2C framework on the top of I2C library.

The drivers are probed on demand by fdt_i2c_adapter_get
function.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
6 months agolib: utils/i2c: Add generic I2C configuration library
Nikita Shubin [Wed, 10 Nov 2021 09:42:27 +0000 (12:42 +0300)] 
lib: utils/i2c: Add generic I2C configuration library

Helper library to keep track of registered I2C adapters,
identified by dts offset, basic send/read functions and
adapter configuration (enable, set dividers, etc...).

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
6 months agolib: utils/reset: separate driver init func
Nikita Shubin [Wed, 10 Nov 2021 09:42:26 +0000 (12:42 +0300)] 
lib: utils/reset: separate driver init func

Move driver init code to separate function, so it can be reused
elsewhere.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
6 months agolib: utils/reset: add priority to gpio reset
Nikita Shubin [Wed, 10 Nov 2021 09:42:25 +0000 (12:42 +0300)] 
lib: utils/reset: add priority to gpio reset

Make gpio_system_reset_check return priority instead of just true/false.

Make default 128 priority for reset/shutdown.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
6 months agolib: sbi: Fix PMP address bits detection
Vasan VS [Mon, 8 Nov 2021 04:54:56 +0000 (10:24 +0530)] 
lib: sbi: Fix PMP address bits detection

We should ensure that pmpcfg0.pmp0cfg is set to zero before using
pmpaddr0 CSR for detecting implemented PMP address bits.

Fixes: bf21632860b4 ("lib: sbi: Detect PMP granularity and number
of address bits")
Signed-off-by: Vasan VS <vasan.vs@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
6 months agolib: sbi: Fix initial value mask while updating the counters
Atish Patra [Mon, 8 Nov 2021 18:53:07 +0000 (10:53 -0800)] 
lib: sbi: Fix initial value mask while updating the counters

The first 32 bits of the initial value for the counter should be
preserved while updating the mhpmcounter for 32bit.

Fixes: 13d40f21d588e ("lib: sbi: Add PMU support")
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
6 months agolib: utils: Rename the prefix in PMU DT properties
Atish Patra [Mon, 8 Nov 2021 18:53:06 +0000 (10:53 -0800)] 
lib: utils: Rename the prefix in PMU DT properties

As per the DT schema rules, the prefix should be vendor. As the PMU
properties are generic for all vendors, change the prefix to riscv
instead of pmu.

Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>