145389aa58f23a8ff242a2d0a842278fdd4eb783
[qemu.git] / hw / i386 / acpi-build.c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/erst.h"
47 #include "hw/acpi/piix4.h"
48 #include "sysemu/tpm_backend.h"
49 #include "hw/rtc/mc146818rtc_regs.h"
50 #include "migration/vmstate.h"
51 #include "hw/mem/memory-device.h"
52 #include "hw/mem/nvdimm.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "hw/hyperv/vmbus-bridge.h"
56
57 /* Supported chipsets: */
58 #include "hw/southbridge/piix.h"
59 #include "hw/acpi/pcihp.h"
60 #include "hw/i386/fw_cfg.h"
61 #include "hw/i386/ich9.h"
62 #include "hw/pci/pci_bus.h"
63 #include "hw/pci-host/i440fx.h"
64 #include "hw/pci-host/q35.h"
65 #include "hw/i386/x86-iommu.h"
66
67 #include "hw/acpi/aml-build.h"
68 #include "hw/acpi/utils.h"
69 #include "hw/acpi/pci.h"
70 #include "hw/acpi/cxl.h"
71
72 #include "qom/qom-qobject.h"
73 #include "hw/i386/amd_iommu.h"
74 #include "hw/i386/intel_iommu.h"
75 #include "hw/virtio/virtio-iommu.h"
76
77 #include "hw/acpi/hmat.h"
78 #include "hw/acpi/viot.h"
79 #include "hw/acpi/cxl.h"
80
81 #include CONFIG_DEVICES
82
83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
85 * a little bit, there should be plenty of free space since the DSDT
86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
87 */
88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
89 #define ACPI_BUILD_ALIGN_SIZE 0x1000
90
91 #define ACPI_BUILD_TABLE_SIZE 0x20000
92
93 /* #define DEBUG_ACPI_BUILD */
94 #ifdef DEBUG_ACPI_BUILD
95 #define ACPI_BUILD_DPRINTF(fmt, ...) \
96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
97 #else
98 #define ACPI_BUILD_DPRINTF(fmt, ...)
99 #endif
100
101 typedef struct AcpiPmInfo {
102 bool s3_disabled;
103 bool s4_disabled;
104 bool pcihp_bridge_en;
105 bool smi_on_cpuhp;
106 bool smi_on_cpu_unplug;
107 bool pcihp_root_en;
108 uint8_t s4_val;
109 AcpiFadtData fadt;
110 uint16_t cpu_hp_io_base;
111 uint16_t pcihp_io_base;
112 uint16_t pcihp_io_len;
113 } AcpiPmInfo;
114
115 typedef struct AcpiMiscInfo {
116 bool has_hpet;
117 #ifdef CONFIG_TPM
118 TPMVersion tpm_version;
119 #endif
120 } AcpiMiscInfo;
121
122 typedef struct FwCfgTPMConfig {
123 uint32_t tpmppi_address;
124 uint8_t tpm_version;
125 uint8_t tpmppi_version;
126 } QEMU_PACKED FwCfgTPMConfig;
127
128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
129
130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
131 .space_id = AML_AS_SYSTEM_IO,
132 .address = NVDIMM_ACPI_IO_BASE,
133 .bit_width = NVDIMM_ACPI_IO_LEN << 3
134 };
135
136 static void init_common_fadt_data(MachineState *ms, Object *o,
137 AcpiFadtData *data)
138 {
139 X86MachineState *x86ms = X86_MACHINE(ms);
140 /*
141 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
142 * behavior for compatibility irrelevant to smm_enabled, which doesn't
143 * comforms to ACPI spec.
144 */
145 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
146 true : x86_machine_is_smm_enabled(x86ms);
147 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
148 AmlAddressSpace as = AML_AS_SYSTEM_IO;
149 AcpiFadtData fadt = {
150 .rev = 3,
151 .flags =
152 (1 << ACPI_FADT_F_WBINVD) |
153 (1 << ACPI_FADT_F_PROC_C1) |
154 (1 << ACPI_FADT_F_SLP_BUTTON) |
155 (1 << ACPI_FADT_F_RTC_S4) |
156 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
157 /* APIC destination mode ("Flat Logical") has an upper limit of 8
158 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
159 * used
160 */
161 ((ms->smp.max_cpus > 8) ?
162 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
163 .int_model = 1 /* Multiple APIC */,
164 .rtc_century = RTC_CENTURY,
165 .plvl2_lat = 0xfff /* C2 state not supported */,
166 .plvl3_lat = 0xfff /* C3 state not supported */,
167 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
168 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
169 .acpi_enable_cmd =
170 smm_enabled ?
171 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
172 0,
173 .acpi_disable_cmd =
174 smm_enabled ?
175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
176 0,
177 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
178 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
179 .address = io + 0x04 },
180 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
181 .gpe0_blk = { .space_id = as, .bit_width =
182 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
183 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
184 },
185 };
186
187 /*
188 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
189 * Flags, bit offset 1 - 8042.
190 */
191 fadt.iapc_boot_arch = iapc_boot_arch_8042();
192
193 *data = fadt;
194 }
195
196 static Object *object_resolve_type_unambiguous(const char *typename)
197 {
198 bool ambig;
199 Object *o = object_resolve_path_type("", typename, &ambig);
200
201 if (ambig || !o) {
202 return NULL;
203 }
204 return o;
205 }
206
207 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
208 {
209 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
210 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
211 Object *obj = piix ? piix : lpc;
212 QObject *o;
213 pm->cpu_hp_io_base = 0;
214 pm->pcihp_io_base = 0;
215 pm->pcihp_io_len = 0;
216 pm->smi_on_cpuhp = false;
217 pm->smi_on_cpu_unplug = false;
218
219 assert(obj);
220 init_common_fadt_data(machine, obj, &pm->fadt);
221 if (piix) {
222 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
223 pm->fadt.rev = 1;
224 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
225 }
226 if (lpc) {
227 uint64_t smi_features = object_property_get_uint(lpc,
228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
231 pm->fadt.reset_reg = r;
232 pm->fadt.reset_val = 0xf;
233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
235 pm->smi_on_cpuhp =
236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
237 pm->smi_on_cpu_unplug =
238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
239 }
240 pm->pcihp_io_base =
241 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
242 pm->pcihp_io_len =
243 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
244
245 /* The above need not be conditional on machine type because the reset port
246 * happens to be the same on PIIX (pc) and ICH9 (q35). */
247 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
248
249 /* Fill in optional s3/s4 related properties */
250 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
251 if (o) {
252 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
253 } else {
254 pm->s3_disabled = false;
255 }
256 qobject_unref(o);
257 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
258 if (o) {
259 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
260 } else {
261 pm->s4_disabled = false;
262 }
263 qobject_unref(o);
264 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
265 if (o) {
266 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
267 } else {
268 pm->s4_val = false;
269 }
270 qobject_unref(o);
271
272 pm->pcihp_bridge_en =
273 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
274 NULL);
275 pm->pcihp_root_en =
276 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
277 NULL);
278 }
279
280 static void acpi_get_misc_info(AcpiMiscInfo *info)
281 {
282 info->has_hpet = hpet_find();
283 #ifdef CONFIG_TPM
284 info->tpm_version = tpm_get_version(tpm_find());
285 #endif
286 }
287
288 /*
289 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
290 * On i386 arch we only have two pci hosts, so we can look only for them.
291 */
292 Object *acpi_get_i386_pci_host(void)
293 {
294 PCIHostState *host;
295
296 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
297 if (!host) {
298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
299 }
300
301 return OBJECT(host);
302 }
303
304 static void acpi_get_pci_holes(Range *hole, Range *hole64)
305 {
306 Object *pci_host;
307
308 pci_host = acpi_get_i386_pci_host();
309
310 if (!pci_host) {
311 return;
312 }
313
314 range_set_bounds1(hole,
315 object_property_get_uint(pci_host,
316 PCI_HOST_PROP_PCI_HOLE_START,
317 NULL),
318 object_property_get_uint(pci_host,
319 PCI_HOST_PROP_PCI_HOLE_END,
320 NULL));
321 range_set_bounds1(hole64,
322 object_property_get_uint(pci_host,
323 PCI_HOST_PROP_PCI_HOLE64_START,
324 NULL),
325 object_property_get_uint(pci_host,
326 PCI_HOST_PROP_PCI_HOLE64_END,
327 NULL));
328 }
329
330 static void acpi_align_size(GArray *blob, unsigned align)
331 {
332 /* Align size to multiple of given size. This reduces the chance
333 * we need to change size in the future (breaking cross version migration).
334 */
335 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
336 }
337
338 /*
339 * ACPI spec 1.0b,
340 * 5.2.6 Firmware ACPI Control Structure
341 */
342 static void
343 build_facs(GArray *table_data)
344 {
345 const char *sig = "FACS";
346 const uint8_t reserved[40] = {};
347
348 g_array_append_vals(table_data, sig, 4); /* Signature */
349 build_append_int_noprefix(table_data, 64, 4); /* Length */
350 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
351 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
352 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
353 build_append_int_noprefix(table_data, 0, 4); /* Flags */
354 g_array_append_vals(table_data, reserved, 40); /* Reserved */
355 }
356
357 Aml *aml_pci_device_dsm(void)
358 {
359 Aml *method;
360
361 method = aml_method("_DSM", 4, AML_SERIALIZED);
362 {
363 Aml *params = aml_local(0);
364 Aml *pkg = aml_package(2);
365 aml_append(pkg, aml_name("BSEL"));
366 aml_append(pkg, aml_name("ASUN"));
367 aml_append(method, aml_store(pkg, params));
368 aml_append(method,
369 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
370 aml_arg(2), aml_arg(3), params))
371 );
372 }
373 return method;
374 }
375
376 static void build_append_pcihp_notify_entry(Aml *method, int slot)
377 {
378 Aml *if_ctx;
379 int32_t devfn = PCI_DEVFN(slot, 0);
380
381 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
382 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
383 aml_append(method, if_ctx);
384 }
385
386 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
387 {
388 const PCIDevice *pdev = bus->devices[devfn];
389
390 if (PCI_FUNC(devfn)) {
391 if (IS_PCI_BRIDGE(pdev)) {
392 /*
393 * Ignore only hotplugged PCI bridges on !0 functions, but
394 * allow describing cold plugged bridges on all functions
395 */
396 if (DEVICE(pdev)->hotplugged) {
397 return true;
398 }
399 } else if (!get_dev_aml_func(DEVICE(pdev))) {
400 /*
401 * Ignore all other devices on !0 functions unless they
402 * have AML description (i.e have get_dev_aml_func() != 0)
403 */
404 return true;
405 }
406 }
407 return false;
408 }
409
410 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
411 {
412 PCIDevice *pdev = bus->devices[devfn];
413 if (pdev) {
414 return is_devfn_ignored_generic(devfn, bus) ||
415 !DEVICE_GET_CLASS(pdev)->hotpluggable ||
416 /* Cold plugged bridges aren't themselves hot-pluggable */
417 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
418 } else { /* non populated slots */
419 /*
420 * hotplug is supported only for non-multifunction device
421 * so generate device description only for function 0
422 */
423 if (PCI_FUNC(devfn) ||
424 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
425 return true;
426 }
427 }
428 return false;
429 }
430
431 static void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus,
432 QObject *bsel)
433 {
434 int devfn;
435 Aml *dev, *notify_method = NULL, *method;
436 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
437
438 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
439 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
440
441 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
442 int slot = PCI_SLOT(devfn);
443 int adr = slot << 16 | PCI_FUNC(devfn);
444
445 if (is_devfn_ignored_hotplug(devfn, bus)) {
446 continue;
447 }
448
449 if (bus->devices[devfn]) {
450 dev = aml_scope("S%.02X", devfn);
451 } else {
452 dev = aml_device("S%.02X", devfn);
453 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
454 }
455
456 /*
457 * Can't declare _SUN here for every device as it changes 'slot'
458 * enumeration order in linux kernel, so use another variable for it
459 */
460 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
461 aml_append(dev, aml_pci_device_dsm());
462
463 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
464 /* add _EJ0 to make slot hotpluggable */
465 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
466 aml_append(method,
467 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
468 );
469 aml_append(dev, method);
470
471 build_append_pcihp_notify_entry(notify_method, slot);
472
473 /* device descriptor has been composed, add it into parent context */
474 aml_append(parent_scope, dev);
475 }
476 aml_append(parent_scope, notify_method);
477 }
478
479 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
480 {
481 QObject *bsel;
482 int devfn;
483 Aml *dev;
484
485 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
486
487 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
488 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
489 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
490 PCIDevice *pdev = bus->devices[devfn];
491
492 if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
493 continue;
494 }
495
496 /* start to compose PCI device descriptor */
497 dev = aml_device("S%.02X", devfn);
498 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
499
500 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
501
502 /* device descriptor has been composed, add it into parent context */
503 aml_append(parent_scope, dev);
504 }
505
506 if (bsel) {
507 build_append_pcihp_slots(parent_scope, bus, bsel);
508 }
509
510 qobject_unref(bsel);
511 }
512
513 static bool build_append_notfication_callback(Aml *parent_scope,
514 const PCIBus *bus)
515 {
516 Aml *method;
517 PCIBus *sec;
518 QObject *bsel;
519 int nr_notifiers = 0;
520
521 QLIST_FOREACH(sec, &bus->child, sibling) {
522 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
523 if (pci_bus_is_root(sec) ||
524 !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) {
525 continue;
526 }
527 nr_notifiers = nr_notifiers +
528 build_append_notfication_callback(br_scope, sec);
529 aml_append(parent_scope, br_scope);
530 }
531
532 /*
533 * Append PCNT method to notify about events on local and child buses.
534 * ps: hostbridge might not have hotplug (bsel) enabled but might have
535 * child bridges that do have bsel.
536 */
537 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
538
539 /* If bus supports hotplug select it and notify about local events */
540 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
541 if (bsel) {
542 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
543
544 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
545 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
546 aml_int(1))); /* Device Check */
547 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
548 aml_int(3))); /* Eject Request */
549 nr_notifiers++;
550 }
551
552 /* Notify about child bus events in any case */
553 QLIST_FOREACH(sec, &bus->child, sibling) {
554 if (pci_bus_is_root(sec) ||
555 !object_property_find(OBJECT(sec), ACPI_PCIHP_PROP_BSEL)) {
556 continue;
557 }
558
559 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
560 }
561
562 aml_append(parent_scope, method);
563 qobject_unref(bsel);
564 return !!nr_notifiers;
565 }
566
567 static Aml *aml_pci_pdsm(void)
568 {
569 Aml *method, *UUID, *ifctx, *ifctx1;
570 Aml *ret = aml_local(0);
571 Aml *caps = aml_local(1);
572 Aml *acpi_index = aml_local(2);
573 Aml *zero = aml_int(0);
574 Aml *one = aml_int(1);
575 Aml *func = aml_arg(2);
576 Aml *rev = aml_arg(1);
577 Aml *params = aml_arg(4);
578 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
579 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
580
581 method = aml_method("PDSM", 5, AML_SERIALIZED);
582
583 /* get supported functions */
584 ifctx = aml_if(aml_equal(func, zero));
585 {
586 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
587 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret));
588 aml_append(ifctx, aml_store(zero, caps));
589
590 /*
591 * PCI Firmware Specification 3.1
592 * 4.6. _DSM Definitions for PCI
593 */
594 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
595 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
596 {
597 /* call is for unsupported UUID, bail out */
598 aml_append(ifctx1, aml_return(ret));
599 }
600 aml_append(ifctx, ifctx1);
601
602 ifctx1 = aml_if(aml_lless(rev, aml_int(2)));
603 {
604 /* call is for unsupported REV, bail out */
605 aml_append(ifctx1, aml_return(ret));
606 }
607 aml_append(ifctx, ifctx1);
608
609 aml_append(ifctx,
610 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
611 /*
612 * advertise function 7 if device has acpi-index
613 * acpi_index values:
614 * 0: not present (default value)
615 * FFFFFFFF: not supported (old QEMU without PIDX reg)
616 * other: device's acpi-index
617 */
618 ifctx1 = aml_if(aml_lnot(
619 aml_or(aml_equal(acpi_index, zero),
620 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
621 ));
622 {
623 /* have supported functions */
624 aml_append(ifctx1, aml_or(caps, one, caps));
625 /* support for function 7 */
626 aml_append(ifctx1,
627 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
628 }
629 aml_append(ifctx, ifctx1);
630
631 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
632 aml_append(ifctx, aml_return(ret));
633 }
634 aml_append(method, ifctx);
635
636 /* handle specific functions requests */
637 /*
638 * PCI Firmware Specification 3.1
639 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
640 * Operating Systems
641 */
642 ifctx = aml_if(aml_equal(func, aml_int(7)));
643 {
644 Aml *pkg = aml_package(2);
645
646 aml_append(pkg, zero);
647 /*
648 * optional, if not impl. should return null string
649 */
650 aml_append(pkg, aml_string("%s", ""));
651 aml_append(ifctx, aml_store(pkg, ret));
652
653 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
654 /*
655 * update acpi-index to actual value
656 */
657 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
658 aml_append(ifctx, aml_return(ret));
659 }
660
661 aml_append(method, ifctx);
662 return method;
663 }
664
665 /**
666 * build_prt_entry:
667 * @link_name: link name for PCI route entry
668 *
669 * build AML package containing a PCI route entry for @link_name
670 */
671 static Aml *build_prt_entry(const char *link_name)
672 {
673 Aml *a_zero = aml_int(0);
674 Aml *pkg = aml_package(4);
675 aml_append(pkg, a_zero);
676 aml_append(pkg, a_zero);
677 aml_append(pkg, aml_name("%s", link_name));
678 aml_append(pkg, a_zero);
679 return pkg;
680 }
681
682 /*
683 * initialize_route - Initialize the interrupt routing rule
684 * through a specific LINK:
685 * if (lnk_idx == idx)
686 * route using link 'link_name'
687 */
688 static Aml *initialize_route(Aml *route, const char *link_name,
689 Aml *lnk_idx, int idx)
690 {
691 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
692 Aml *pkg = build_prt_entry(link_name);
693
694 aml_append(if_ctx, aml_store(pkg, route));
695
696 return if_ctx;
697 }
698
699 /*
700 * build_prt - Define interrupt rounting rules
701 *
702 * Returns an array of 128 routes, one for each device,
703 * based on device location.
704 * The main goal is to equaly distribute the interrupts
705 * over the 4 existing ACPI links (works only for i440fx).
706 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
707 *
708 */
709 static Aml *build_prt(bool is_pci0_prt)
710 {
711 Aml *method, *while_ctx, *pin, *res;
712
713 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
714 res = aml_local(0);
715 pin = aml_local(1);
716 aml_append(method, aml_store(aml_package(128), res));
717 aml_append(method, aml_store(aml_int(0), pin));
718
719 /* while (pin < 128) */
720 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
721 {
722 Aml *slot = aml_local(2);
723 Aml *lnk_idx = aml_local(3);
724 Aml *route = aml_local(4);
725
726 /* slot = pin >> 2 */
727 aml_append(while_ctx,
728 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
729 /* lnk_idx = (slot + pin) & 3 */
730 aml_append(while_ctx,
731 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
732 lnk_idx));
733
734 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
735 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
736 if (is_pci0_prt) {
737 Aml *if_device_1, *if_pin_4, *else_pin_4;
738
739 /* device 1 is the power-management device, needs SCI */
740 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
741 {
742 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
743 {
744 aml_append(if_pin_4,
745 aml_store(build_prt_entry("LNKS"), route));
746 }
747 aml_append(if_device_1, if_pin_4);
748 else_pin_4 = aml_else();
749 {
750 aml_append(else_pin_4,
751 aml_store(build_prt_entry("LNKA"), route));
752 }
753 aml_append(if_device_1, else_pin_4);
754 }
755 aml_append(while_ctx, if_device_1);
756 } else {
757 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
758 }
759 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
760 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
761
762 /* route[0] = 0x[slot]FFFF */
763 aml_append(while_ctx,
764 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
765 NULL),
766 aml_index(route, aml_int(0))));
767 /* route[1] = pin & 3 */
768 aml_append(while_ctx,
769 aml_store(aml_and(pin, aml_int(3), NULL),
770 aml_index(route, aml_int(1))));
771 /* res[pin] = route */
772 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
773 /* pin++ */
774 aml_append(while_ctx, aml_increment(pin));
775 }
776 aml_append(method, while_ctx);
777 /* return res*/
778 aml_append(method, aml_return(res));
779
780 return method;
781 }
782
783 static void build_hpet_aml(Aml *table)
784 {
785 Aml *crs;
786 Aml *field;
787 Aml *method;
788 Aml *if_ctx;
789 Aml *scope = aml_scope("_SB");
790 Aml *dev = aml_device("HPET");
791 Aml *zero = aml_int(0);
792 Aml *id = aml_local(0);
793 Aml *period = aml_local(1);
794
795 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
796 aml_append(dev, aml_name_decl("_UID", zero));
797
798 aml_append(dev,
799 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
800 HPET_LEN));
801 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
802 aml_append(field, aml_named_field("VEND", 32));
803 aml_append(field, aml_named_field("PRD", 32));
804 aml_append(dev, field);
805
806 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
807 aml_append(method, aml_store(aml_name("VEND"), id));
808 aml_append(method, aml_store(aml_name("PRD"), period));
809 aml_append(method, aml_shiftright(id, aml_int(16), id));
810 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
811 aml_equal(id, aml_int(0xffff))));
812 {
813 aml_append(if_ctx, aml_return(zero));
814 }
815 aml_append(method, if_ctx);
816
817 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
818 aml_lgreater(period, aml_int(100000000))));
819 {
820 aml_append(if_ctx, aml_return(zero));
821 }
822 aml_append(method, if_ctx);
823
824 aml_append(method, aml_return(aml_int(0x0F)));
825 aml_append(dev, method);
826
827 crs = aml_resource_template();
828 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
829 aml_append(dev, aml_name_decl("_CRS", crs));
830
831 aml_append(scope, dev);
832 aml_append(table, scope);
833 }
834
835 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
836 {
837 Aml *dev;
838 Aml *method;
839 Aml *crs;
840
841 dev = aml_device("VMBS");
842 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
843 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
844 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
845 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
846
847 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
848 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
849 aml_name("STA")));
850 aml_append(dev, method);
851
852 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
853 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
854 aml_name("STA")));
855 aml_append(dev, method);
856
857 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
858 aml_append(method, aml_return(aml_name("STA")));
859 aml_append(dev, method);
860
861 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
862
863 crs = aml_resource_template();
864 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
865 aml_append(dev, aml_name_decl("_CRS", crs));
866
867 return dev;
868 }
869
870 static void build_dbg_aml(Aml *table)
871 {
872 Aml *field;
873 Aml *method;
874 Aml *while_ctx;
875 Aml *scope = aml_scope("\\");
876 Aml *buf = aml_local(0);
877 Aml *len = aml_local(1);
878 Aml *idx = aml_local(2);
879
880 aml_append(scope,
881 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
882 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
883 aml_append(field, aml_named_field("DBGB", 8));
884 aml_append(scope, field);
885
886 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
887
888 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
889 aml_append(method, aml_to_buffer(buf, buf));
890 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
891 aml_append(method, aml_store(aml_int(0), idx));
892
893 while_ctx = aml_while(aml_lless(idx, len));
894 aml_append(while_ctx,
895 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
896 aml_append(while_ctx, aml_increment(idx));
897 aml_append(method, while_ctx);
898
899 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
900 aml_append(scope, method);
901
902 aml_append(table, scope);
903 }
904
905 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
906 {
907 Aml *dev;
908 Aml *crs;
909 Aml *method;
910 uint32_t irqs[] = {5, 10, 11};
911
912 dev = aml_device("%s", name);
913 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
914 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
915
916 crs = aml_resource_template();
917 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
918 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
919 aml_append(dev, aml_name_decl("_PRS", crs));
920
921 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
922 aml_append(method, aml_return(aml_call1("IQST", reg)));
923 aml_append(dev, method);
924
925 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
926 aml_append(method, aml_or(reg, aml_int(0x80), reg));
927 aml_append(dev, method);
928
929 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
930 aml_append(method, aml_return(aml_call1("IQCR", reg)));
931 aml_append(dev, method);
932
933 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
934 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
935 aml_append(method, aml_store(aml_name("PRRI"), reg));
936 aml_append(dev, method);
937
938 return dev;
939 }
940
941 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
942 {
943 Aml *dev;
944 Aml *crs;
945 Aml *method;
946 uint32_t irqs;
947
948 dev = aml_device("%s", name);
949 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
950 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
951
952 crs = aml_resource_template();
953 irqs = gsi;
954 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
955 AML_SHARED, &irqs, 1));
956 aml_append(dev, aml_name_decl("_PRS", crs));
957
958 aml_append(dev, aml_name_decl("_CRS", crs));
959
960 /*
961 * _DIS can be no-op because the interrupt cannot be disabled.
962 */
963 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
964 aml_append(dev, method);
965
966 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
967 aml_append(dev, method);
968
969 return dev;
970 }
971
972 /* _CRS method - get current settings */
973 static Aml *build_iqcr_method(bool is_piix4)
974 {
975 Aml *if_ctx;
976 uint32_t irqs;
977 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
978 Aml *crs = aml_resource_template();
979
980 irqs = 0;
981 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
982 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
983 aml_append(method, aml_name_decl("PRR0", crs));
984
985 aml_append(method,
986 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
987
988 if (is_piix4) {
989 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
990 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
991 aml_append(method, if_ctx);
992 } else {
993 aml_append(method,
994 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
995 aml_name("PRRI")));
996 }
997
998 aml_append(method, aml_return(aml_name("PRR0")));
999 return method;
1000 }
1001
1002 /* _STA method - get status */
1003 static Aml *build_irq_status_method(void)
1004 {
1005 Aml *if_ctx;
1006 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1007
1008 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1009 aml_append(if_ctx, aml_return(aml_int(0x09)));
1010 aml_append(method, if_ctx);
1011 aml_append(method, aml_return(aml_int(0x0B)));
1012 return method;
1013 }
1014
1015 static void build_piix4_pci0_int(Aml *table)
1016 {
1017 Aml *dev;
1018 Aml *crs;
1019 Aml *method;
1020 uint32_t irqs;
1021 Aml *sb_scope = aml_scope("_SB");
1022 Aml *pci0_scope = aml_scope("PCI0");
1023
1024 aml_append(pci0_scope, build_prt(true));
1025 aml_append(sb_scope, pci0_scope);
1026
1027 aml_append(sb_scope, build_irq_status_method());
1028 aml_append(sb_scope, build_iqcr_method(true));
1029
1030 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1031 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1032 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1033 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1034
1035 dev = aml_device("LNKS");
1036 {
1037 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1038 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1039
1040 crs = aml_resource_template();
1041 irqs = 9;
1042 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1043 AML_ACTIVE_HIGH, AML_SHARED,
1044 &irqs, 1));
1045 aml_append(dev, aml_name_decl("_PRS", crs));
1046
1047 /* The SCI cannot be disabled and is always attached to GSI 9,
1048 * so these are no-ops. We only need this link to override the
1049 * polarity to active high and match the content of the MADT.
1050 */
1051 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1052 aml_append(method, aml_return(aml_int(0x0b)));
1053 aml_append(dev, method);
1054
1055 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1056 aml_append(dev, method);
1057
1058 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1059 aml_append(method, aml_return(aml_name("_PRS")));
1060 aml_append(dev, method);
1061
1062 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1063 aml_append(dev, method);
1064 }
1065 aml_append(sb_scope, dev);
1066
1067 aml_append(table, sb_scope);
1068 }
1069
1070 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1071 {
1072 int i;
1073 int head;
1074 Aml *pkg;
1075 char base = name[3] < 'E' ? 'A' : 'E';
1076 char *s = g_strdup(name);
1077 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1078
1079 assert(strlen(s) == 4);
1080
1081 head = name[3] - base;
1082 for (i = 0; i < 4; i++) {
1083 if (head + i > 3) {
1084 head = i * -1;
1085 }
1086 s[3] = base + head + i;
1087 pkg = aml_package(4);
1088 aml_append(pkg, a_nr);
1089 aml_append(pkg, aml_int(i));
1090 aml_append(pkg, aml_name("%s", s));
1091 aml_append(pkg, aml_int(0));
1092 aml_append(ctx, pkg);
1093 }
1094 g_free(s);
1095 }
1096
1097 static Aml *build_q35_routing_table(const char *str)
1098 {
1099 int i;
1100 Aml *pkg;
1101 char *name = g_strdup_printf("%s ", str);
1102
1103 pkg = aml_package(128);
1104 for (i = 0; i < 0x18; i++) {
1105 name[3] = 'E' + (i & 0x3);
1106 append_q35_prt_entry(pkg, i, name);
1107 }
1108
1109 name[3] = 'E';
1110 append_q35_prt_entry(pkg, 0x18, name);
1111
1112 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1113 for (i = 0x0019; i < 0x1e; i++) {
1114 name[3] = 'A';
1115 append_q35_prt_entry(pkg, i, name);
1116 }
1117
1118 /* PCIe->PCI bridge. use PIRQ[E-H] */
1119 name[3] = 'E';
1120 append_q35_prt_entry(pkg, 0x1e, name);
1121 name[3] = 'A';
1122 append_q35_prt_entry(pkg, 0x1f, name);
1123
1124 g_free(name);
1125 return pkg;
1126 }
1127
1128 static void build_q35_pci0_int(Aml *table)
1129 {
1130 Aml *method;
1131 Aml *sb_scope = aml_scope("_SB");
1132 Aml *pci0_scope = aml_scope("PCI0");
1133
1134 /* Zero => PIC mode, One => APIC Mode */
1135 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1136 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1137 {
1138 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1139 }
1140 aml_append(table, method);
1141
1142 aml_append(pci0_scope,
1143 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1144 aml_append(pci0_scope,
1145 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1146
1147 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1148 {
1149 Aml *if_ctx;
1150 Aml *else_ctx;
1151
1152 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1153 section 6.2.8.1 */
1154 /* Note: we provide the same info as the PCI routing
1155 table of the Bochs BIOS */
1156 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1157 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1158 aml_append(method, if_ctx);
1159 else_ctx = aml_else();
1160 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1161 aml_append(method, else_ctx);
1162 }
1163 aml_append(pci0_scope, method);
1164 aml_append(sb_scope, pci0_scope);
1165
1166 aml_append(sb_scope, build_irq_status_method());
1167 aml_append(sb_scope, build_iqcr_method(false));
1168
1169 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1170 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1171 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1172 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1173 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1174 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1175 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1176 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1177
1178 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1179 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1180 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1181 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1182 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1183 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1184 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1185 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1186
1187 aml_append(table, sb_scope);
1188 }
1189
1190 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1191 {
1192 Aml *dev;
1193 Aml *resource_template;
1194
1195 /* DRAM controller */
1196 dev = aml_device("DRAC");
1197 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1198
1199 resource_template = aml_resource_template();
1200 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1201 aml_append(resource_template,
1202 aml_qword_memory(AML_POS_DECODE,
1203 AML_MIN_FIXED,
1204 AML_MAX_FIXED,
1205 AML_NON_CACHEABLE,
1206 AML_READ_WRITE,
1207 0x0000000000000000,
1208 mcfg->base,
1209 mcfg->base + mcfg->size - 1,
1210 0x0000000000000000,
1211 mcfg->size));
1212 } else {
1213 aml_append(resource_template,
1214 aml_dword_memory(AML_POS_DECODE,
1215 AML_MIN_FIXED,
1216 AML_MAX_FIXED,
1217 AML_NON_CACHEABLE,
1218 AML_READ_WRITE,
1219 0x0000000000000000,
1220 mcfg->base,
1221 mcfg->base + mcfg->size - 1,
1222 0x0000000000000000,
1223 mcfg->size));
1224 }
1225 aml_append(dev, aml_name_decl("_CRS", resource_template));
1226
1227 return dev;
1228 }
1229
1230 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1231 {
1232 Aml *scope;
1233 Aml *field;
1234 Aml *method;
1235
1236 scope = aml_scope("_SB.PCI0");
1237
1238 aml_append(scope,
1239 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1240 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1241 aml_append(field, aml_named_field("PCIU", 32));
1242 aml_append(field, aml_named_field("PCID", 32));
1243 aml_append(scope, field);
1244
1245 aml_append(scope,
1246 aml_operation_region("SEJ", AML_SYSTEM_IO,
1247 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1248 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1249 aml_append(field, aml_named_field("B0EJ", 32));
1250 aml_append(scope, field);
1251
1252 aml_append(scope,
1253 aml_operation_region("BNMR", AML_SYSTEM_IO,
1254 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1255 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1256 aml_append(field, aml_named_field("BNUM", 32));
1257 aml_append(field, aml_named_field("PIDX", 32));
1258 aml_append(scope, field);
1259
1260 aml_append(scope, aml_mutex("BLCK", 0));
1261
1262 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1263 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1264 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1265 aml_append(method,
1266 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1267 aml_append(method, aml_release(aml_name("BLCK")));
1268 aml_append(method, aml_return(aml_int(0)));
1269 aml_append(scope, method);
1270
1271 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1272 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1273 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1274 aml_append(method,
1275 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1276 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1277 aml_append(method, aml_release(aml_name("BLCK")));
1278 aml_append(method, aml_return(aml_local(0)));
1279 aml_append(scope, method);
1280
1281 aml_append(scope, aml_pci_pdsm());
1282
1283 aml_append(table, scope);
1284 }
1285
1286 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1287 {
1288 Aml *if_ctx;
1289 Aml *if_ctx2;
1290 Aml *else_ctx;
1291 Aml *method;
1292 Aml *a_cwd1 = aml_name("CDW1");
1293 Aml *a_ctrl = aml_local(0);
1294
1295 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1296 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1297
1298 if_ctx = aml_if(aml_equal(
1299 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1300 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1301 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1302
1303 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1304
1305 /*
1306 * Always allow native PME, AER (no dependencies)
1307 * Allow SHPC (PCI bridges can have SHPC controller)
1308 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1309 */
1310 aml_append(if_ctx, aml_and(a_ctrl,
1311 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1312
1313 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1314 /* Unknown revision */
1315 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1316 aml_append(if_ctx, if_ctx2);
1317
1318 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1319 /* Capabilities bits were masked */
1320 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1321 aml_append(if_ctx, if_ctx2);
1322
1323 /* Update DWORD3 in the buffer */
1324 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1325 aml_append(method, if_ctx);
1326
1327 else_ctx = aml_else();
1328 /* Unrecognized UUID */
1329 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1330 aml_append(method, else_ctx);
1331
1332 aml_append(method, aml_return(aml_arg(3)));
1333 return method;
1334 }
1335
1336 static void build_acpi0017(Aml *table)
1337 {
1338 Aml *dev, *scope, *method;
1339
1340 scope = aml_scope("_SB");
1341 dev = aml_device("CXLM");
1342 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1343
1344 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1345 aml_append(method, aml_return(aml_int(0x01)));
1346 aml_append(dev, method);
1347
1348 aml_append(scope, dev);
1349 aml_append(table, scope);
1350 }
1351
1352 static void
1353 build_dsdt(GArray *table_data, BIOSLinker *linker,
1354 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1355 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1356 {
1357 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE);
1358 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE);
1359 CrsRangeEntry *entry;
1360 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1361 CrsRangeSet crs_range_set;
1362 PCMachineState *pcms = PC_MACHINE(machine);
1363 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1364 X86MachineState *x86ms = X86_MACHINE(machine);
1365 AcpiMcfgInfo mcfg;
1366 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1367 uint32_t nr_mem = machine->ram_slots;
1368 int root_bus_limit = 0xFF;
1369 PCIBus *bus = NULL;
1370 #ifdef CONFIG_TPM
1371 TPMIf *tpm = tpm_find();
1372 #endif
1373 bool cxl_present = false;
1374 int i;
1375 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1376 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1377 .oem_table_id = x86ms->oem_table_id };
1378
1379 assert(!!i440fx != !!q35);
1380
1381 acpi_table_begin(&table, table_data);
1382 dsdt = init_aml_allocator();
1383
1384 build_dbg_aml(dsdt);
1385 if (i440fx) {
1386 sb_scope = aml_scope("_SB");
1387 dev = aml_device("PCI0");
1388 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1389 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1390 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1391 aml_append(sb_scope, dev);
1392 aml_append(dsdt, sb_scope);
1393
1394 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1395 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1396 }
1397 build_piix4_pci0_int(dsdt);
1398 } else if (q35) {
1399 sb_scope = aml_scope("_SB");
1400 dev = aml_device("PCI0");
1401 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1402 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1403 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1404 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1405 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1406 aml_append(sb_scope, dev);
1407 if (mcfg_valid) {
1408 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1409 }
1410
1411 if (pm->smi_on_cpuhp) {
1412 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1413 dev = aml_device("PCI0.SMI0");
1414 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1415 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1416 crs = aml_resource_template();
1417 aml_append(crs,
1418 aml_io(
1419 AML_DECODE16,
1420 ACPI_PORT_SMI_CMD,
1421 ACPI_PORT_SMI_CMD,
1422 1,
1423 2)
1424 );
1425 aml_append(dev, aml_name_decl("_CRS", crs));
1426 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1427 aml_int(ACPI_PORT_SMI_CMD), 2));
1428 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1429 AML_WRITE_AS_ZEROS);
1430 aml_append(field, aml_named_field("SMIC", 8));
1431 aml_append(field, aml_reserved_field(8));
1432 aml_append(dev, field);
1433 aml_append(sb_scope, dev);
1434 }
1435
1436 aml_append(dsdt, sb_scope);
1437
1438 if (pm->pcihp_bridge_en) {
1439 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1440 }
1441 build_q35_pci0_int(dsdt);
1442 }
1443
1444 if (misc->has_hpet) {
1445 build_hpet_aml(dsdt);
1446 }
1447
1448 if (vmbus_bridge) {
1449 sb_scope = aml_scope("_SB");
1450 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1451 aml_append(dsdt, sb_scope);
1452 }
1453
1454 scope = aml_scope("_GPE");
1455 {
1456 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1457 if (machine->nvdimms_state->is_enabled) {
1458 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1459 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1460 aml_int(0x80)));
1461 aml_append(scope, method);
1462 }
1463 }
1464 aml_append(dsdt, scope);
1465
1466 if (pcmc->legacy_cpu_hotplug) {
1467 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1468 } else {
1469 CPUHotplugFeatures opts = {
1470 .acpi_1_compatible = true, .has_legacy_cphp = true,
1471 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1472 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1473 };
1474 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1475 "\\_SB.PCI0", "\\_GPE._E02");
1476 }
1477
1478 if (pcms->memhp_io_base && nr_mem) {
1479 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1480 "\\_GPE._E03", AML_SYSTEM_IO,
1481 pcms->memhp_io_base);
1482 }
1483
1484 crs_range_set_init(&crs_range_set);
1485 bus = PC_MACHINE(machine)->bus;
1486 if (bus) {
1487 QLIST_FOREACH(bus, &bus->child, sibling) {
1488 uint8_t bus_num = pci_bus_num(bus);
1489 uint8_t numa_node = pci_bus_numa_node(bus);
1490
1491 /* look only for expander root buses */
1492 if (!pci_bus_is_root(bus)) {
1493 continue;
1494 }
1495
1496 if (bus_num < root_bus_limit) {
1497 root_bus_limit = bus_num - 1;
1498 }
1499
1500 scope = aml_scope("\\_SB");
1501
1502 if (pci_bus_is_cxl(bus)) {
1503 dev = aml_device("CL%.02X", bus_num);
1504 } else {
1505 dev = aml_device("PC%.02X", bus_num);
1506 }
1507 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1508 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1509 if (pci_bus_is_cxl(bus)) {
1510 struct Aml *pkg = aml_package(2);
1511
1512 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1513 aml_append(pkg, aml_eisaid("PNP0A08"));
1514 aml_append(pkg, aml_eisaid("PNP0A03"));
1515 aml_append(dev, aml_name_decl("_CID", pkg));
1516 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1517 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1518 build_cxl_osc_method(dev);
1519 } else if (pci_bus_is_express(bus)) {
1520 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1521 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1522
1523 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1524 aml_append(dev, build_q35_osc_method(true));
1525 } else {
1526 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1527 }
1528
1529 if (numa_node != NUMA_NODE_UNASSIGNED) {
1530 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1531 }
1532
1533 aml_append(dev, build_prt(false));
1534 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1535 0, 0, 0, 0);
1536 aml_append(dev, aml_name_decl("_CRS", crs));
1537 aml_append(scope, dev);
1538 aml_append(dsdt, scope);
1539
1540 /* Handle the ranges for the PXB expanders */
1541 if (pci_bus_is_cxl(bus)) {
1542 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1543 uint64_t base = mr->addr;
1544
1545 cxl_present = true;
1546 crs_range_insert(crs_range_set.mem_ranges, base,
1547 base + memory_region_size(mr) - 1);
1548 }
1549 }
1550 }
1551
1552 if (cxl_present) {
1553 build_acpi0017(dsdt);
1554 }
1555
1556 /*
1557 * At this point crs_range_set has all the ranges used by pci
1558 * busses *other* than PCI0. These ranges will be excluded from
1559 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1560 * too.
1561 */
1562 if (mcfg_valid) {
1563 crs_range_insert(crs_range_set.mem_ranges,
1564 mcfg.base, mcfg.base + mcfg.size - 1);
1565 }
1566
1567 scope = aml_scope("\\_SB.PCI0");
1568 /* build PCI0._CRS */
1569 crs = aml_resource_template();
1570 aml_append(crs,
1571 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1572 0x0000, 0x0, root_bus_limit,
1573 0x0000, root_bus_limit + 1));
1574 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1575
1576 aml_append(crs,
1577 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1578 AML_POS_DECODE, AML_ENTIRE_RANGE,
1579 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1580
1581 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1582 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1583 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1584 aml_append(crs,
1585 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1586 AML_POS_DECODE, AML_ENTIRE_RANGE,
1587 0x0000, entry->base, entry->limit,
1588 0x0000, entry->limit - entry->base + 1));
1589 }
1590
1591 aml_append(crs,
1592 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1593 AML_CACHEABLE, AML_READ_WRITE,
1594 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1595
1596 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1597 range_lob(pci_hole),
1598 range_upb(pci_hole));
1599 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1600 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1601 aml_append(crs,
1602 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1603 AML_NON_CACHEABLE, AML_READ_WRITE,
1604 0, entry->base, entry->limit,
1605 0, entry->limit - entry->base + 1));
1606 }
1607
1608 if (!range_is_empty(pci_hole64)) {
1609 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1610 range_lob(pci_hole64),
1611 range_upb(pci_hole64));
1612 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1613 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1614 aml_append(crs,
1615 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1616 AML_MAX_FIXED,
1617 AML_CACHEABLE, AML_READ_WRITE,
1618 0, entry->base, entry->limit,
1619 0, entry->limit - entry->base + 1));
1620 }
1621 }
1622
1623 #ifdef CONFIG_TPM
1624 if (TPM_IS_TIS_ISA(tpm_find())) {
1625 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1626 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1627 }
1628 #endif
1629 aml_append(scope, aml_name_decl("_CRS", crs));
1630
1631 /* reserve GPE0 block resources */
1632 dev = aml_device("GPE0");
1633 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1634 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1635 /* device present, functioning, decoding, not shown in UI */
1636 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1637 crs = aml_resource_template();
1638 aml_append(crs,
1639 aml_io(
1640 AML_DECODE16,
1641 pm->fadt.gpe0_blk.address,
1642 pm->fadt.gpe0_blk.address,
1643 1,
1644 pm->fadt.gpe0_blk.bit_width / 8)
1645 );
1646 aml_append(dev, aml_name_decl("_CRS", crs));
1647 aml_append(scope, dev);
1648
1649 crs_range_set_free(&crs_range_set);
1650
1651 /* reserve PCIHP resources */
1652 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1653 dev = aml_device("PHPR");
1654 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1655 aml_append(dev,
1656 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1657 /* device present, functioning, decoding, not shown in UI */
1658 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1659 crs = aml_resource_template();
1660 aml_append(crs,
1661 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1662 pm->pcihp_io_len)
1663 );
1664 aml_append(dev, aml_name_decl("_CRS", crs));
1665 aml_append(scope, dev);
1666 }
1667 aml_append(dsdt, scope);
1668
1669 /* create S3_ / S4_ / S5_ packages if necessary */
1670 scope = aml_scope("\\");
1671 if (!pm->s3_disabled) {
1672 pkg = aml_package(4);
1673 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1674 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1675 aml_append(pkg, aml_int(0)); /* reserved */
1676 aml_append(pkg, aml_int(0)); /* reserved */
1677 aml_append(scope, aml_name_decl("_S3", pkg));
1678 }
1679
1680 if (!pm->s4_disabled) {
1681 pkg = aml_package(4);
1682 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1683 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1684 aml_append(pkg, aml_int(pm->s4_val));
1685 aml_append(pkg, aml_int(0)); /* reserved */
1686 aml_append(pkg, aml_int(0)); /* reserved */
1687 aml_append(scope, aml_name_decl("_S4", pkg));
1688 }
1689
1690 pkg = aml_package(4);
1691 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1692 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1693 aml_append(pkg, aml_int(0)); /* reserved */
1694 aml_append(pkg, aml_int(0)); /* reserved */
1695 aml_append(scope, aml_name_decl("_S5", pkg));
1696 aml_append(dsdt, scope);
1697
1698 /* create fw_cfg node, unconditionally */
1699 {
1700 scope = aml_scope("\\_SB.PCI0");
1701 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1702 aml_append(dsdt, scope);
1703 }
1704
1705 sb_scope = aml_scope("\\_SB");
1706 {
1707 Object *pci_host = acpi_get_i386_pci_host();
1708
1709 if (pci_host) {
1710 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
1711 Aml *scope = aml_scope("PCI0");
1712 /* Scan all PCI buses. Generate tables to support hotplug. */
1713 build_append_pci_bus_devices(scope, bus);
1714 aml_append(sb_scope, scope);
1715 }
1716 }
1717
1718 #ifdef CONFIG_TPM
1719 if (TPM_IS_CRB(tpm)) {
1720 dev = aml_device("TPM");
1721 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1722 aml_append(dev, aml_name_decl("_STR",
1723 aml_string("TPM 2.0 Device")));
1724 crs = aml_resource_template();
1725 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1726 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1727 aml_append(dev, aml_name_decl("_CRS", crs));
1728
1729 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1730 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1731
1732 tpm_build_ppi_acpi(tpm, dev);
1733
1734 aml_append(sb_scope, dev);
1735 }
1736 #endif
1737
1738 if (pcms->sgx_epc.size != 0) {
1739 uint64_t epc_base = pcms->sgx_epc.base;
1740 uint64_t epc_size = pcms->sgx_epc.size;
1741
1742 dev = aml_device("EPC");
1743 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1744 aml_append(dev, aml_name_decl("_STR",
1745 aml_unicode("Enclave Page Cache 1.0")));
1746 crs = aml_resource_template();
1747 aml_append(crs,
1748 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1749 AML_MAX_FIXED, AML_NON_CACHEABLE,
1750 AML_READ_WRITE, 0, epc_base,
1751 epc_base + epc_size - 1, 0, epc_size));
1752 aml_append(dev, aml_name_decl("_CRS", crs));
1753
1754 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1755 aml_append(method, aml_return(aml_int(0x0f)));
1756 aml_append(dev, method);
1757
1758 aml_append(sb_scope, dev);
1759 }
1760 aml_append(dsdt, sb_scope);
1761
1762 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1763 bool has_pcnt;
1764
1765 Object *pci_host = acpi_get_i386_pci_host();
1766 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
1767
1768 scope = aml_scope("\\_SB.PCI0");
1769 has_pcnt = build_append_notfication_callback(scope, bus);
1770 if (has_pcnt) {
1771 aml_append(dsdt, scope);
1772 }
1773
1774 scope = aml_scope("_GPE");
1775 {
1776 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1777 if (has_pcnt) {
1778 aml_append(method,
1779 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1780 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1781 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1782 }
1783 aml_append(scope, method);
1784 }
1785 aml_append(dsdt, scope);
1786 }
1787
1788 /* copy AML table into ACPI tables blob and patch header there */
1789 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1790 acpi_table_end(linker, &table);
1791 free_aml_allocator();
1792 }
1793
1794 /*
1795 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1796 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1797 */
1798 static void
1799 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1800 const char *oem_table_id)
1801 {
1802 AcpiTable table = { .sig = "HPET", .rev = 1,
1803 .oem_id = oem_id, .oem_table_id = oem_table_id };
1804
1805 acpi_table_begin(&table, table_data);
1806 /* Note timer_block_id value must be kept in sync with value advertised by
1807 * emulated hpet
1808 */
1809 /* Event Timer Block ID */
1810 build_append_int_noprefix(table_data, 0x8086a201, 4);
1811 /* BASE_ADDRESS */
1812 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1813 /* HPET Number */
1814 build_append_int_noprefix(table_data, 0, 1);
1815 /* Main Counter Minimum Clock_tick in Periodic Mode */
1816 build_append_int_noprefix(table_data, 0, 2);
1817 /* Page Protection And OEM Attribute */
1818 build_append_int_noprefix(table_data, 0, 1);
1819 acpi_table_end(linker, &table);
1820 }
1821
1822 #ifdef CONFIG_TPM
1823 /*
1824 * TCPA Description Table
1825 *
1826 * Following Level 00, Rev 00.37 of specs:
1827 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1828 * 7.1.2 ACPI Table Layout
1829 */
1830 static void
1831 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1832 const char *oem_id, const char *oem_table_id)
1833 {
1834 unsigned log_addr_offset;
1835 AcpiTable table = { .sig = "TCPA", .rev = 2,
1836 .oem_id = oem_id, .oem_table_id = oem_table_id };
1837
1838 acpi_table_begin(&table, table_data);
1839 /* Platform Class */
1840 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1841 /* Log Area Minimum Length (LAML) */
1842 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1843 /* Log Area Start Address (LASA) */
1844 log_addr_offset = table_data->len;
1845 build_append_int_noprefix(table_data, 0, 8);
1846
1847 /* allocate/reserve space for TPM log area */
1848 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1849 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1850 false /* high memory */);
1851 /* log area start address to be filled by Guest linker */
1852 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1853 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1854
1855 acpi_table_end(linker, &table);
1856 }
1857 #endif
1858
1859 #define HOLE_640K_START (640 * KiB)
1860 #define HOLE_640K_END (1 * MiB)
1861
1862 /*
1863 * ACPI spec, Revision 3.0
1864 * 5.2.15 System Resource Affinity Table (SRAT)
1865 */
1866 static void
1867 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1868 {
1869 int i;
1870 int numa_mem_start, slots;
1871 uint64_t mem_len, mem_base, next_base;
1872 MachineClass *mc = MACHINE_GET_CLASS(machine);
1873 X86MachineState *x86ms = X86_MACHINE(machine);
1874 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1875 PCMachineState *pcms = PC_MACHINE(machine);
1876 int nb_numa_nodes = machine->numa_state->num_nodes;
1877 NodeInfo *numa_info = machine->numa_state->nodes;
1878 ram_addr_t hotpluggable_address_space_size =
1879 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1880 NULL);
1881 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1882 .oem_table_id = x86ms->oem_table_id };
1883
1884 acpi_table_begin(&table, table_data);
1885 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1886 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1887
1888 for (i = 0; i < apic_ids->len; i++) {
1889 int node_id = apic_ids->cpus[i].props.node_id;
1890 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1891
1892 if (apic_id < 255) {
1893 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1894 build_append_int_noprefix(table_data, 0, 1); /* Type */
1895 build_append_int_noprefix(table_data, 16, 1); /* Length */
1896 /* Proximity Domain [7:0] */
1897 build_append_int_noprefix(table_data, node_id, 1);
1898 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1899 /* Flags, Table 5-36 */
1900 build_append_int_noprefix(table_data, 1, 4);
1901 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1902 /* Proximity Domain [31:8] */
1903 build_append_int_noprefix(table_data, 0, 3);
1904 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1905 } else {
1906 /*
1907 * ACPI spec, Revision 4.0
1908 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1909 */
1910 build_append_int_noprefix(table_data, 2, 1); /* Type */
1911 build_append_int_noprefix(table_data, 24, 1); /* Length */
1912 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1913 /* Proximity Domain */
1914 build_append_int_noprefix(table_data, node_id, 4);
1915 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1916 /* Flags, Table 5-39 */
1917 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1918 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1919 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1920 }
1921 }
1922
1923 /* the memory map is a bit tricky, it contains at least one hole
1924 * from 640k-1M and possibly another one from 3.5G-4G.
1925 */
1926 next_base = 0;
1927 numa_mem_start = table_data->len;
1928
1929 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1930 mem_base = next_base;
1931 mem_len = numa_info[i - 1].node_mem;
1932 next_base = mem_base + mem_len;
1933
1934 /* Cut out the 640K hole */
1935 if (mem_base <= HOLE_640K_START &&
1936 next_base > HOLE_640K_START) {
1937 mem_len -= next_base - HOLE_640K_START;
1938 if (mem_len > 0) {
1939 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1940 MEM_AFFINITY_ENABLED);
1941 }
1942
1943 /* Check for the rare case: 640K < RAM < 1M */
1944 if (next_base <= HOLE_640K_END) {
1945 next_base = HOLE_640K_END;
1946 continue;
1947 }
1948 mem_base = HOLE_640K_END;
1949 mem_len = next_base - HOLE_640K_END;
1950 }
1951
1952 /* Cut out the ACPI_PCI hole */
1953 if (mem_base <= x86ms->below_4g_mem_size &&
1954 next_base > x86ms->below_4g_mem_size) {
1955 mem_len -= next_base - x86ms->below_4g_mem_size;
1956 if (mem_len > 0) {
1957 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1958 MEM_AFFINITY_ENABLED);
1959 }
1960 mem_base = x86ms->above_4g_mem_start;
1961 mem_len = next_base - x86ms->below_4g_mem_size;
1962 next_base = mem_base + mem_len;
1963 }
1964
1965 if (mem_len > 0) {
1966 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1967 MEM_AFFINITY_ENABLED);
1968 }
1969 }
1970
1971 if (machine->nvdimms_state->is_enabled) {
1972 nvdimm_build_srat(table_data);
1973 }
1974
1975 sgx_epc_build_srat(table_data);
1976
1977 /*
1978 * TODO: this part is not in ACPI spec and current linux kernel boots fine
1979 * without these entries. But I recall there were issues the last time I
1980 * tried to remove it with some ancient guest OS, however I can't remember
1981 * what that was so keep this around for now
1982 */
1983 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
1984 for (; slots < nb_numa_nodes + 2; slots++) {
1985 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1986 }
1987
1988 /*
1989 * Entry is required for Windows to enable memory hotplug in OS
1990 * and for Linux to enable SWIOTLB when booted with less than
1991 * 4G of RAM. Windows works better if the entry sets proximity
1992 * to the highest NUMA node in the machine.
1993 * Memory devices may override proximity set by this entry,
1994 * providing _PXM method if necessary.
1995 */
1996 if (hotpluggable_address_space_size) {
1997 build_srat_memory(table_data, machine->device_memory->base,
1998 hotpluggable_address_space_size, nb_numa_nodes - 1,
1999 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2000 }
2001
2002 acpi_table_end(linker, &table);
2003 }
2004
2005 /*
2006 * Insert DMAR scope for PCI bridges and endpoint devcie
2007 */
2008 static void
2009 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2010 {
2011 const size_t device_scope_size = 6 /* device scope structure */ +
2012 2 /* 1 path entry */;
2013 GArray *scope_blob = opaque;
2014
2015 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2016 /* Dmar Scope Type: 0x02 for PCI Bridge */
2017 build_append_int_noprefix(scope_blob, 0x02, 1);
2018 } else {
2019 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2020 build_append_int_noprefix(scope_blob, 0x01, 1);
2021 }
2022
2023 /* length */
2024 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2025 /* reserved */
2026 build_append_int_noprefix(scope_blob, 0, 2);
2027 /* enumeration_id */
2028 build_append_int_noprefix(scope_blob, 0, 1);
2029 /* bus */
2030 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2031 /* device */
2032 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2033 /* function */
2034 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2035 }
2036
2037 /* For a given PCI host bridge, walk and insert DMAR scope */
2038 static int
2039 dmar_host_bridges(Object *obj, void *opaque)
2040 {
2041 GArray *scope_blob = opaque;
2042
2043 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2044 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2045
2046 if (bus && !pci_bus_bypass_iommu(bus)) {
2047 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2048 }
2049 }
2050
2051 return 0;
2052 }
2053
2054 /*
2055 * Intel ® Virtualization Technology for Directed I/O
2056 * Architecture Specification. Revision 3.3
2057 * 8.1 DMA Remapping Reporting Structure
2058 */
2059 static void
2060 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2061 const char *oem_table_id)
2062 {
2063 uint8_t dmar_flags = 0;
2064 uint8_t rsvd10[10] = {};
2065 /* Root complex IOAPIC uses one path only */
2066 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2067 2 /* 1 path entry */;
2068 X86IOMMUState *iommu = x86_iommu_get_default();
2069 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2070 GArray *scope_blob = g_array_new(false, true, 1);
2071
2072 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2073 .oem_table_id = oem_table_id };
2074
2075 /*
2076 * A PCI bus walk, for each PCI host bridge.
2077 * Insert scope for each PCI bridge and endpoint device which
2078 * is attached to a bus with iommu enabled.
2079 */
2080 object_child_foreach_recursive(object_get_root(),
2081 dmar_host_bridges, scope_blob);
2082
2083 assert(iommu);
2084 if (x86_iommu_ir_supported(iommu)) {
2085 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2086 }
2087
2088 acpi_table_begin(&table, table_data);
2089 /* Host Address Width */
2090 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2091 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2092 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2093
2094 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2095 build_append_int_noprefix(table_data, 0, 2); /* Type */
2096 /* Length */
2097 build_append_int_noprefix(table_data,
2098 16 + ioapic_scope_size + scope_blob->len, 2);
2099 /* Flags */
2100 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2101 1);
2102 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2103 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2104 /* Register Base Address */
2105 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2106
2107 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2108 * 8.3.1 (version Oct. 2014 or later). */
2109 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2110 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2111 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2112 /* Enumeration ID */
2113 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2114 /* Start Bus Number */
2115 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2116 /* Path, {Device, Function} pair */
2117 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2118 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2119
2120 /* Add scope found above */
2121 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2122 g_array_free(scope_blob, true);
2123
2124 if (iommu->dt_supported) {
2125 /* 8.5 Root Port ATS Capability Reporting Structure */
2126 build_append_int_noprefix(table_data, 2, 2); /* Type */
2127 build_append_int_noprefix(table_data, 8, 2); /* Length */
2128 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2129 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2130 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2131 }
2132
2133 acpi_table_end(linker, &table);
2134 }
2135
2136 /*
2137 * Windows ACPI Emulated Devices Table
2138 * (Version 1.0 - April 6, 2009)
2139 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2140 *
2141 * Helpful to speedup Windows guests and ignored by others.
2142 */
2143 static void
2144 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2145 const char *oem_table_id)
2146 {
2147 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2148 .oem_table_id = oem_table_id };
2149
2150 acpi_table_begin(&table, table_data);
2151 /*
2152 * Set "ACPI PM timer good" flag.
2153 *
2154 * Tells Windows guests that our ACPI PM timer is reliable in the
2155 * sense that guest can read it only once to obtain a reliable value.
2156 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2157 */
2158 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2159 acpi_table_end(linker, &table);
2160 }
2161
2162 /*
2163 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2164 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2165 */
2166 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2167
2168 /*
2169 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2170 * necessary for the PCI topology.
2171 */
2172 static void
2173 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2174 {
2175 GArray *table_data = opaque;
2176 uint32_t entry;
2177
2178 /* "Select" IVHD entry, type 0x2 */
2179 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2180 build_append_int_noprefix(table_data, entry, 4);
2181
2182 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2183 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2184 uint8_t sec = pci_bus_num(sec_bus);
2185 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2186
2187 if (pci_bus_is_express(sec_bus)) {
2188 /*
2189 * Walk the bus if there are subordinates, otherwise use a range
2190 * to cover an entire leaf bus. We could potentially also use a
2191 * range for traversed buses, but we'd need to take care not to
2192 * create both Select and Range entries covering the same device.
2193 * This is easier and potentially more compact.
2194 *
2195 * An example bare metal system seems to use Select entries for
2196 * root ports without a slot (ie. built-ins) and Range entries
2197 * when there is a slot. The same system also only hard-codes
2198 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2199 * making no effort to support nested bridges. We attempt to
2200 * be more thorough here.
2201 */
2202 if (sec == sub) { /* leaf bus */
2203 /* "Start of Range" IVHD entry, type 0x3 */
2204 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2205 build_append_int_noprefix(table_data, entry, 4);
2206 /* "End of Range" IVHD entry, type 0x4 */
2207 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2208 build_append_int_noprefix(table_data, entry, 4);
2209 } else {
2210 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2211 }
2212 } else {
2213 /*
2214 * If the secondary bus is conventional, then we need to create an
2215 * Alias range for everything downstream. The range covers the
2216 * first devfn on the secondary bus to the last devfn on the
2217 * subordinate bus. The alias target depends on legacy versus
2218 * express bridges, just as in pci_device_iommu_address_space().
2219 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2220 */
2221 uint16_t dev_id_a, dev_id_b;
2222
2223 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2224
2225 if (pci_is_express(dev) &&
2226 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2227 dev_id_b = dev_id_a;
2228 } else {
2229 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2230 }
2231
2232 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2233 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2234 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2235
2236 /* "End of Range" IVHD entry, type 0x4 */
2237 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2238 build_append_int_noprefix(table_data, entry, 4);
2239 }
2240 }
2241 }
2242
2243 /* For all PCI host bridges, walk and insert IVHD entries */
2244 static int
2245 ivrs_host_bridges(Object *obj, void *opaque)
2246 {
2247 GArray *ivhd_blob = opaque;
2248
2249 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2250 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2251
2252 if (bus && !pci_bus_bypass_iommu(bus)) {
2253 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2254 }
2255 }
2256
2257 return 0;
2258 }
2259
2260 static void
2261 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2262 const char *oem_table_id)
2263 {
2264 int ivhd_table_len = 24;
2265 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2266 GArray *ivhd_blob = g_array_new(false, true, 1);
2267 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2268 .oem_table_id = oem_table_id };
2269
2270 acpi_table_begin(&table, table_data);
2271 /* IVinfo - IO virtualization information common to all
2272 * IOMMU units in a system
2273 */
2274 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2275 /* reserved */
2276 build_append_int_noprefix(table_data, 0, 8);
2277
2278 /* IVHD definition - type 10h */
2279 build_append_int_noprefix(table_data, 0x10, 1);
2280 /* virtualization flags */
2281 build_append_int_noprefix(table_data,
2282 (1UL << 0) | /* HtTunEn */
2283 (1UL << 4) | /* iotblSup */
2284 (1UL << 6) | /* PrefSup */
2285 (1UL << 7), /* PPRSup */
2286 1);
2287
2288 /*
2289 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2290 * complete set of IVHD entries. Do this into a separate blob so that we
2291 * can calculate the total IVRS table length here and then append the new
2292 * blob further below. Fall back to an entry covering all devices, which
2293 * is sufficient when no aliases are present.
2294 */
2295 object_child_foreach_recursive(object_get_root(),
2296 ivrs_host_bridges, ivhd_blob);
2297
2298 if (!ivhd_blob->len) {
2299 /*
2300 * Type 1 device entry reporting all devices
2301 * These are 4-byte device entries currently reporting the range of
2302 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2303 */
2304 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2305 }
2306
2307 ivhd_table_len += ivhd_blob->len;
2308
2309 /*
2310 * When interrupt remapping is supported, we add a special IVHD device
2311 * for type IO-APIC.
2312 */
2313 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2314 ivhd_table_len += 8;
2315 }
2316
2317 /* IVHD length */
2318 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2319 /* DeviceID */
2320 build_append_int_noprefix(table_data, s->devid, 2);
2321 /* Capability offset */
2322 build_append_int_noprefix(table_data, s->capab_offset, 2);
2323 /* IOMMU base address */
2324 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2325 /* PCI Segment Group */
2326 build_append_int_noprefix(table_data, 0, 2);
2327 /* IOMMU info */
2328 build_append_int_noprefix(table_data, 0, 2);
2329 /* IOMMU Feature Reporting */
2330 build_append_int_noprefix(table_data,
2331 (48UL << 30) | /* HATS */
2332 (48UL << 28) | /* GATS */
2333 (1UL << 2) | /* GTSup */
2334 (1UL << 6), /* GASup */
2335 4);
2336
2337 /* IVHD entries as found above */
2338 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2339 g_array_free(ivhd_blob, TRUE);
2340
2341 /*
2342 * Add a special IVHD device type.
2343 * Refer to spec - Table 95: IVHD device entry type codes
2344 *
2345 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2346 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2347 */
2348 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2349 build_append_int_noprefix(table_data,
2350 (0x1ull << 56) | /* type IOAPIC */
2351 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2352 0x48, /* special device */
2353 8);
2354 }
2355 acpi_table_end(linker, &table);
2356 }
2357
2358 typedef
2359 struct AcpiBuildState {
2360 /* Copy of table in RAM (for patching). */
2361 MemoryRegion *table_mr;
2362 /* Is table patched? */
2363 uint8_t patched;
2364 void *rsdp;
2365 MemoryRegion *rsdp_mr;
2366 MemoryRegion *linker_mr;
2367 } AcpiBuildState;
2368
2369 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2370 {
2371 Object *pci_host;
2372 QObject *o;
2373
2374 pci_host = acpi_get_i386_pci_host();
2375 if (!pci_host) {
2376 return false;
2377 }
2378
2379 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2380 if (!o) {
2381 return false;
2382 }
2383 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2384 qobject_unref(o);
2385 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2386 return false;
2387 }
2388
2389 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2390 assert(o);
2391 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2392 qobject_unref(o);
2393 return true;
2394 }
2395
2396 static
2397 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2398 {
2399 PCMachineState *pcms = PC_MACHINE(machine);
2400 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2401 X86MachineState *x86ms = X86_MACHINE(machine);
2402 DeviceState *iommu = pcms->iommu;
2403 GArray *table_offsets;
2404 unsigned facs, dsdt, rsdt, fadt;
2405 AcpiPmInfo pm;
2406 AcpiMiscInfo misc;
2407 AcpiMcfgInfo mcfg;
2408 Range pci_hole = {}, pci_hole64 = {};
2409 uint8_t *u;
2410 size_t aml_len = 0;
2411 GArray *tables_blob = tables->table_data;
2412 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2413 Object *vmgenid_dev;
2414 char *oem_id;
2415 char *oem_table_id;
2416
2417 acpi_get_pm_info(machine, &pm);
2418 acpi_get_misc_info(&misc);
2419 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2420 acpi_get_slic_oem(&slic_oem);
2421
2422 if (slic_oem.id) {
2423 oem_id = slic_oem.id;
2424 } else {
2425 oem_id = x86ms->oem_id;
2426 }
2427
2428 if (slic_oem.table_id) {
2429 oem_table_id = slic_oem.table_id;
2430 } else {
2431 oem_table_id = x86ms->oem_table_id;
2432 }
2433
2434 table_offsets = g_array_new(false, true /* clear */,
2435 sizeof(uint32_t));
2436 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2437
2438 bios_linker_loader_alloc(tables->linker,
2439 ACPI_BUILD_TABLE_FILE, tables_blob,
2440 64 /* Ensure FACS is aligned */,
2441 false /* high memory */);
2442
2443 /*
2444 * FACS is pointed to by FADT.
2445 * We place it first since it's the only table that has alignment
2446 * requirements.
2447 */
2448 facs = tables_blob->len;
2449 build_facs(tables_blob);
2450
2451 /* DSDT is pointed to by FADT */
2452 dsdt = tables_blob->len;
2453 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2454 &pci_hole, &pci_hole64, machine);
2455
2456 /* Count the size of the DSDT and SSDT, we will need it for legacy
2457 * sizing of ACPI tables.
2458 */
2459 aml_len += tables_blob->len - dsdt;
2460
2461 /* ACPI tables pointed to by RSDT */
2462 fadt = tables_blob->len;
2463 acpi_add_table(table_offsets, tables_blob);
2464 pm.fadt.facs_tbl_offset = &facs;
2465 pm.fadt.dsdt_tbl_offset = &dsdt;
2466 pm.fadt.xdsdt_tbl_offset = &dsdt;
2467 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2468 aml_len += tables_blob->len - fadt;
2469
2470 acpi_add_table(table_offsets, tables_blob);
2471 acpi_build_madt(tables_blob, tables->linker, x86ms,
2472 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2473 x86ms->oem_table_id);
2474
2475 #ifdef CONFIG_ACPI_ERST
2476 {
2477 Object *erst_dev;
2478 erst_dev = find_erst_dev();
2479 if (erst_dev) {
2480 acpi_add_table(table_offsets, tables_blob);
2481 build_erst(tables_blob, tables->linker, erst_dev,
2482 x86ms->oem_id, x86ms->oem_table_id);
2483 }
2484 }
2485 #endif
2486
2487 vmgenid_dev = find_vmgenid_dev();
2488 if (vmgenid_dev) {
2489 acpi_add_table(table_offsets, tables_blob);
2490 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2491 tables->vmgenid, tables->linker, x86ms->oem_id);
2492 }
2493
2494 if (misc.has_hpet) {
2495 acpi_add_table(table_offsets, tables_blob);
2496 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2497 x86ms->oem_table_id);
2498 }
2499 #ifdef CONFIG_TPM
2500 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2501 if (misc.tpm_version == TPM_VERSION_1_2) {
2502 acpi_add_table(table_offsets, tables_blob);
2503 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2504 x86ms->oem_id, x86ms->oem_table_id);
2505 } else { /* TPM_VERSION_2_0 */
2506 acpi_add_table(table_offsets, tables_blob);
2507 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2508 x86ms->oem_id, x86ms->oem_table_id);
2509 }
2510 }
2511 #endif
2512 if (machine->numa_state->num_nodes) {
2513 acpi_add_table(table_offsets, tables_blob);
2514 build_srat(tables_blob, tables->linker, machine);
2515 if (machine->numa_state->have_numa_distance) {
2516 acpi_add_table(table_offsets, tables_blob);
2517 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2518 x86ms->oem_table_id);
2519 }
2520 if (machine->numa_state->hmat_enabled) {
2521 acpi_add_table(table_offsets, tables_blob);
2522 build_hmat(tables_blob, tables->linker, machine->numa_state,
2523 x86ms->oem_id, x86ms->oem_table_id);
2524 }
2525 }
2526 if (acpi_get_mcfg(&mcfg)) {
2527 acpi_add_table(table_offsets, tables_blob);
2528 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2529 x86ms->oem_table_id);
2530 }
2531 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2532 acpi_add_table(table_offsets, tables_blob);
2533 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2534 x86ms->oem_table_id);
2535 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2536 acpi_add_table(table_offsets, tables_blob);
2537 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2538 x86ms->oem_table_id);
2539 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2540 PCIDevice *pdev = PCI_DEVICE(iommu);
2541
2542 acpi_add_table(table_offsets, tables_blob);
2543 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2544 x86ms->oem_id, x86ms->oem_table_id);
2545 }
2546 if (machine->nvdimms_state->is_enabled) {
2547 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2548 machine->nvdimms_state, machine->ram_slots,
2549 x86ms->oem_id, x86ms->oem_table_id);
2550 }
2551 if (pcms->cxl_devices_state.is_enabled) {
2552 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2553 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2554 }
2555
2556 acpi_add_table(table_offsets, tables_blob);
2557 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2558
2559 /* Add tables supplied by user (if any) */
2560 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2561 unsigned len = acpi_table_len(u);
2562
2563 acpi_add_table(table_offsets, tables_blob);
2564 g_array_append_vals(tables_blob, u, len);
2565 }
2566
2567 /* RSDT is pointed to by RSDP */
2568 rsdt = tables_blob->len;
2569 build_rsdt(tables_blob, tables->linker, table_offsets,
2570 oem_id, oem_table_id);
2571
2572 /* RSDP is in FSEG memory, so allocate it separately */
2573 {
2574 AcpiRsdpData rsdp_data = {
2575 .revision = 0,
2576 .oem_id = x86ms->oem_id,
2577 .xsdt_tbl_offset = NULL,
2578 .rsdt_tbl_offset = &rsdt,
2579 };
2580 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2581 if (!pcmc->rsdp_in_ram) {
2582 /* We used to allocate some extra space for RSDP revision 2 but
2583 * only used the RSDP revision 0 space. The extra bytes were
2584 * zeroed out and not used.
2585 * Here we continue wasting those extra 16 bytes to make sure we
2586 * don't break migration for machine types 2.2 and older due to
2587 * RSDP blob size mismatch.
2588 */
2589 build_append_int_noprefix(tables->rsdp, 0, 16);
2590 }
2591 }
2592
2593 /* We'll expose it all to Guest so we want to reduce
2594 * chance of size changes.
2595 *
2596 * We used to align the tables to 4k, but of course this would
2597 * too simple to be enough. 4k turned out to be too small an
2598 * alignment very soon, and in fact it is almost impossible to
2599 * keep the table size stable for all (max_cpus, max_memory_slots)
2600 * combinations. So the table size is always 64k for pc-i440fx-2.1
2601 * and we give an error if the table grows beyond that limit.
2602 *
2603 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2604 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2605 * than 2.0 and we can always pad the smaller tables with zeros. We can
2606 * then use the exact size of the 2.0 tables.
2607 *
2608 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2609 */
2610 if (pcmc->legacy_acpi_table_size) {
2611 /* Subtracting aml_len gives the size of fixed tables. Then add the
2612 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2613 */
2614 int legacy_aml_len =
2615 pcmc->legacy_acpi_table_size +
2616 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2617 int legacy_table_size =
2618 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2619 ACPI_BUILD_ALIGN_SIZE);
2620 if (tables_blob->len > legacy_table_size) {
2621 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2622 warn_report("ACPI table size %u exceeds %d bytes,"
2623 " migration may not work",
2624 tables_blob->len, legacy_table_size);
2625 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2626 " or PCI bridges.");
2627 }
2628 g_array_set_size(tables_blob, legacy_table_size);
2629 } else {
2630 /* Make sure we have a buffer in case we need to resize the tables. */
2631 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2632 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2633 warn_report("ACPI table size %u exceeds %d bytes,"
2634 " migration may not work",
2635 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2636 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2637 " or PCI bridges.");
2638 }
2639 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2640 }
2641
2642 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2643
2644 /* Cleanup memory that's no longer used. */
2645 g_array_free(table_offsets, true);
2646 g_free(slic_oem.id);
2647 g_free(slic_oem.table_id);
2648 }
2649
2650 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2651 {
2652 uint32_t size = acpi_data_len(data);
2653
2654 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2655 memory_region_ram_resize(mr, size, &error_abort);
2656
2657 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2658 memory_region_set_dirty(mr, 0, size);
2659 }
2660
2661 static void acpi_build_update(void *build_opaque)
2662 {
2663 AcpiBuildState *build_state = build_opaque;
2664 AcpiBuildTables tables;
2665
2666 /* No state to update or already patched? Nothing to do. */
2667 if (!build_state || build_state->patched) {
2668 return;
2669 }
2670 build_state->patched = 1;
2671
2672 acpi_build_tables_init(&tables);
2673
2674 acpi_build(&tables, MACHINE(qdev_get_machine()));
2675
2676 acpi_ram_update(build_state->table_mr, tables.table_data);
2677
2678 if (build_state->rsdp) {
2679 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2680 } else {
2681 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2682 }
2683
2684 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2685 acpi_build_tables_cleanup(&tables, true);
2686 }
2687
2688 static void acpi_build_reset(void *build_opaque)
2689 {
2690 AcpiBuildState *build_state = build_opaque;
2691 build_state->patched = 0;
2692 }
2693
2694 static const VMStateDescription vmstate_acpi_build = {
2695 .name = "acpi_build",
2696 .version_id = 1,
2697 .minimum_version_id = 1,
2698 .fields = (VMStateField[]) {
2699 VMSTATE_UINT8(patched, AcpiBuildState),
2700 VMSTATE_END_OF_LIST()
2701 },
2702 };
2703
2704 void acpi_setup(void)
2705 {
2706 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2707 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2708 X86MachineState *x86ms = X86_MACHINE(pcms);
2709 AcpiBuildTables tables;
2710 AcpiBuildState *build_state;
2711 Object *vmgenid_dev;
2712 #ifdef CONFIG_TPM
2713 TPMIf *tpm;
2714 static FwCfgTPMConfig tpm_config;
2715 #endif
2716
2717 if (!x86ms->fw_cfg) {
2718 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2719 return;
2720 }
2721
2722 if (!pcms->acpi_build_enabled) {
2723 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2724 return;
2725 }
2726
2727 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2728 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2729 return;
2730 }
2731
2732 build_state = g_malloc0(sizeof *build_state);
2733
2734 acpi_build_tables_init(&tables);
2735 acpi_build(&tables, MACHINE(pcms));
2736
2737 /* Now expose it all to Guest */
2738 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2739 build_state, tables.table_data,
2740 ACPI_BUILD_TABLE_FILE);
2741 assert(build_state->table_mr != NULL);
2742
2743 build_state->linker_mr =
2744 acpi_add_rom_blob(acpi_build_update, build_state,
2745 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2746
2747 #ifdef CONFIG_TPM
2748 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2749 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2750
2751 tpm = tpm_find();
2752 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2753 tpm_config = (FwCfgTPMConfig) {
2754 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2755 .tpm_version = tpm_get_version(tpm),
2756 .tpmppi_version = TPM_PPI_VERSION_1_30
2757 };
2758 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2759 &tpm_config, sizeof tpm_config);
2760 }
2761 #endif
2762
2763 vmgenid_dev = find_vmgenid_dev();
2764 if (vmgenid_dev) {
2765 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2766 tables.vmgenid);
2767 }
2768
2769 if (!pcmc->rsdp_in_ram) {
2770 /*
2771 * Keep for compatibility with old machine types.
2772 * Though RSDP is small, its contents isn't immutable, so
2773 * we'll update it along with the rest of tables on guest access.
2774 */
2775 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2776
2777 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2778 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2779 acpi_build_update, NULL, build_state,
2780 build_state->rsdp, rsdp_size, true);
2781 build_state->rsdp_mr = NULL;
2782 } else {
2783 build_state->rsdp = NULL;
2784 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2785 build_state, tables.rsdp,
2786 ACPI_BUILD_RSDP_FILE);
2787 }
2788
2789 qemu_register_reset(acpi_build_reset, build_state);
2790 acpi_build_reset(build_state);
2791 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2792
2793 /* Cleanup tables but don't free the memory: we track it
2794 * in build_state.
2795 */
2796 acpi_build_tables_cleanup(&tables, false);
2797 }