cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / cpu-exec.c
1 /*
2 * emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "config.h"
20 #include "cpu.h"
21 #include "disas/disas.h"
22 #include "tcg.h"
23 #include "qemu/atomic.h"
24 #include "sysemu/qtest.h"
25
26 //#define CONFIG_DEBUG_EXEC
27
28 bool qemu_cpu_has_work(CPUState *cpu)
29 {
30 return cpu_has_work(cpu);
31 }
32
33 void cpu_loop_exit(CPUArchState *env)
34 {
35 CPUState *cpu = ENV_GET_CPU(env);
36
37 cpu->current_tb = NULL;
38 siglongjmp(env->jmp_env, 1);
39 }
40
41 /* exit the current TB from a signal handler. The host registers are
42 restored in a state compatible with the CPU emulator
43 */
44 #if defined(CONFIG_SOFTMMU)
45 void cpu_resume_from_signal(CPUArchState *env, void *puc)
46 {
47 /* XXX: restore cpu registers saved in host registers */
48
49 env->exception_index = -1;
50 siglongjmp(env->jmp_env, 1);
51 }
52 #endif
53
54 /* Execute a TB, and fix up the CPU state afterwards if necessary */
55 static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
56 {
57 CPUArchState *env = cpu->env_ptr;
58 tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr);
59 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
60 /* We didn't start executing this TB (eg because the instruction
61 * counter hit zero); we must restore the guest PC to the address
62 * of the start of the TB.
63 */
64 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
65 cpu_pc_from_tb(env, tb);
66 }
67 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
68 /* We were asked to stop executing TBs (probably a pending
69 * interrupt. We've now stopped, so clear the flag.
70 */
71 cpu->tcg_exit_req = 0;
72 }
73 return next_tb;
74 }
75
76 /* Execute the code without caching the generated code. An interpreter
77 could be used if available. */
78 static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
79 TranslationBlock *orig_tb)
80 {
81 CPUState *cpu = ENV_GET_CPU(env);
82 TranslationBlock *tb;
83
84 /* Should never happen.
85 We only end up here when an existing TB is too long. */
86 if (max_cycles > CF_COUNT_MASK)
87 max_cycles = CF_COUNT_MASK;
88
89 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
90 max_cycles);
91 cpu->current_tb = tb;
92 /* execute the generated code */
93 cpu_tb_exec(cpu, tb->tc_ptr);
94 cpu->current_tb = NULL;
95 tb_phys_invalidate(tb, -1);
96 tb_free(tb);
97 }
98
99 static TranslationBlock *tb_find_slow(CPUArchState *env,
100 target_ulong pc,
101 target_ulong cs_base,
102 uint64_t flags)
103 {
104 TranslationBlock *tb, **ptb1;
105 unsigned int h;
106 tb_page_addr_t phys_pc, phys_page1;
107 target_ulong virt_page2;
108
109 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
110
111 /* find translated block using physical mappings */
112 phys_pc = get_page_addr_code(env, pc);
113 phys_page1 = phys_pc & TARGET_PAGE_MASK;
114 h = tb_phys_hash_func(phys_pc);
115 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
116 for(;;) {
117 tb = *ptb1;
118 if (!tb)
119 goto not_found;
120 if (tb->pc == pc &&
121 tb->page_addr[0] == phys_page1 &&
122 tb->cs_base == cs_base &&
123 tb->flags == flags) {
124 /* check next page if needed */
125 if (tb->page_addr[1] != -1) {
126 tb_page_addr_t phys_page2;
127
128 virt_page2 = (pc & TARGET_PAGE_MASK) +
129 TARGET_PAGE_SIZE;
130 phys_page2 = get_page_addr_code(env, virt_page2);
131 if (tb->page_addr[1] == phys_page2)
132 goto found;
133 } else {
134 goto found;
135 }
136 }
137 ptb1 = &tb->phys_hash_next;
138 }
139 not_found:
140 /* if no translated code available, then translate it now */
141 tb = tb_gen_code(env, pc, cs_base, flags, 0);
142
143 found:
144 /* Move the last found TB to the head of the list */
145 if (likely(*ptb1)) {
146 *ptb1 = tb->phys_hash_next;
147 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
148 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
149 }
150 /* we add the TB in the virtual pc hash table */
151 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
152 return tb;
153 }
154
155 static inline TranslationBlock *tb_find_fast(CPUArchState *env)
156 {
157 TranslationBlock *tb;
158 target_ulong cs_base, pc;
159 int flags;
160
161 /* we record a subset of the CPU state. It will
162 always be the same before a given translated block
163 is executed. */
164 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
165 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
166 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
167 tb->flags != flags)) {
168 tb = tb_find_slow(env, pc, cs_base, flags);
169 }
170 return tb;
171 }
172
173 static CPUDebugExcpHandler *debug_excp_handler;
174
175 void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
176 {
177 debug_excp_handler = handler;
178 }
179
180 static void cpu_handle_debug_exception(CPUArchState *env)
181 {
182 CPUWatchpoint *wp;
183
184 if (!env->watchpoint_hit) {
185 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
186 wp->flags &= ~BP_WATCHPOINT_HIT;
187 }
188 }
189 if (debug_excp_handler) {
190 debug_excp_handler(env);
191 }
192 }
193
194 /* main execution loop */
195
196 volatile sig_atomic_t exit_request;
197
198 int cpu_exec(CPUArchState *env)
199 {
200 CPUState *cpu = ENV_GET_CPU(env);
201 int ret, interrupt_request;
202 TranslationBlock *tb;
203 uint8_t *tc_ptr;
204 tcg_target_ulong next_tb;
205
206 if (cpu->halted) {
207 if (!cpu_has_work(cpu)) {
208 return EXCP_HALTED;
209 }
210
211 cpu->halted = 0;
212 }
213
214 cpu_single_env = env;
215
216 if (unlikely(exit_request)) {
217 cpu->exit_request = 1;
218 }
219
220 #if defined(TARGET_I386)
221 /* put eflags in CPU temporary format */
222 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
223 DF = 1 - (2 * ((env->eflags >> 10) & 1));
224 CC_OP = CC_OP_EFLAGS;
225 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
226 #elif defined(TARGET_SPARC)
227 #elif defined(TARGET_M68K)
228 env->cc_op = CC_OP_FLAGS;
229 env->cc_dest = env->sr & 0xf;
230 env->cc_x = (env->sr >> 4) & 1;
231 #elif defined(TARGET_ALPHA)
232 #elif defined(TARGET_ARM)
233 #elif defined(TARGET_UNICORE32)
234 #elif defined(TARGET_PPC)
235 env->reserve_addr = -1;
236 #elif defined(TARGET_LM32)
237 #elif defined(TARGET_MICROBLAZE)
238 #elif defined(TARGET_MIPS)
239 #elif defined(TARGET_OPENRISC)
240 #elif defined(TARGET_SH4)
241 #elif defined(TARGET_CRIS)
242 #elif defined(TARGET_S390X)
243 #elif defined(TARGET_XTENSA)
244 /* XXXXX */
245 #else
246 #error unsupported target CPU
247 #endif
248 env->exception_index = -1;
249
250 /* prepare setjmp context for exception handling */
251 for(;;) {
252 if (sigsetjmp(env->jmp_env, 0) == 0) {
253 /* if an exception is pending, we execute it here */
254 if (env->exception_index >= 0) {
255 if (env->exception_index >= EXCP_INTERRUPT) {
256 /* exit request from the cpu execution loop */
257 ret = env->exception_index;
258 if (ret == EXCP_DEBUG) {
259 cpu_handle_debug_exception(env);
260 }
261 break;
262 } else {
263 #if defined(CONFIG_USER_ONLY)
264 /* if user mode only, we simulate a fake exception
265 which will be handled outside the cpu execution
266 loop */
267 #if defined(TARGET_I386)
268 do_interrupt(env);
269 #endif
270 ret = env->exception_index;
271 break;
272 #else
273 do_interrupt(env);
274 env->exception_index = -1;
275 #endif
276 }
277 }
278
279 next_tb = 0; /* force lookup of first TB */
280 for(;;) {
281 interrupt_request = cpu->interrupt_request;
282 if (unlikely(interrupt_request)) {
283 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
284 /* Mask out external interrupts for this step. */
285 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
286 }
287 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
288 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
289 env->exception_index = EXCP_DEBUG;
290 cpu_loop_exit(env);
291 }
292 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
293 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
294 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
295 if (interrupt_request & CPU_INTERRUPT_HALT) {
296 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
297 cpu->halted = 1;
298 env->exception_index = EXCP_HLT;
299 cpu_loop_exit(env);
300 }
301 #endif
302 #if defined(TARGET_I386)
303 #if !defined(CONFIG_USER_ONLY)
304 if (interrupt_request & CPU_INTERRUPT_POLL) {
305 cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
306 apic_poll_irq(env->apic_state);
307 }
308 #endif
309 if (interrupt_request & CPU_INTERRUPT_INIT) {
310 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
311 0);
312 do_cpu_init(x86_env_get_cpu(env));
313 env->exception_index = EXCP_HALTED;
314 cpu_loop_exit(env);
315 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
316 do_cpu_sipi(x86_env_get_cpu(env));
317 } else if (env->hflags2 & HF2_GIF_MASK) {
318 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
319 !(env->hflags & HF_SMM_MASK)) {
320 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
321 0);
322 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
323 do_smm_enter(env);
324 next_tb = 0;
325 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
326 !(env->hflags2 & HF2_NMI_MASK)) {
327 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
328 env->hflags2 |= HF2_NMI_MASK;
329 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
330 next_tb = 0;
331 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
332 cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
333 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
334 next_tb = 0;
335 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
336 (((env->hflags2 & HF2_VINTR_MASK) &&
337 (env->hflags2 & HF2_HIF_MASK)) ||
338 (!(env->hflags2 & HF2_VINTR_MASK) &&
339 (env->eflags & IF_MASK &&
340 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
341 int intno;
342 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
343 0);
344 cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
345 CPU_INTERRUPT_VIRQ);
346 intno = cpu_get_pic_interrupt(env);
347 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
348 do_interrupt_x86_hardirq(env, intno, 1);
349 /* ensure that no TB jump will be modified as
350 the program flow was changed */
351 next_tb = 0;
352 #if !defined(CONFIG_USER_ONLY)
353 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
354 (env->eflags & IF_MASK) &&
355 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
356 int intno;
357 /* FIXME: this should respect TPR */
358 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
359 0);
360 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
361 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
362 do_interrupt_x86_hardirq(env, intno, 1);
363 cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
364 next_tb = 0;
365 #endif
366 }
367 }
368 #elif defined(TARGET_PPC)
369 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
370 cpu_reset(cpu);
371 }
372 if (interrupt_request & CPU_INTERRUPT_HARD) {
373 ppc_hw_interrupt(env);
374 if (env->pending_interrupts == 0) {
375 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
376 }
377 next_tb = 0;
378 }
379 #elif defined(TARGET_LM32)
380 if ((interrupt_request & CPU_INTERRUPT_HARD)
381 && (env->ie & IE_IE)) {
382 env->exception_index = EXCP_IRQ;
383 do_interrupt(env);
384 next_tb = 0;
385 }
386 #elif defined(TARGET_MICROBLAZE)
387 if ((interrupt_request & CPU_INTERRUPT_HARD)
388 && (env->sregs[SR_MSR] & MSR_IE)
389 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
390 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
391 env->exception_index = EXCP_IRQ;
392 do_interrupt(env);
393 next_tb = 0;
394 }
395 #elif defined(TARGET_MIPS)
396 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
397 cpu_mips_hw_interrupts_pending(env)) {
398 /* Raise it */
399 env->exception_index = EXCP_EXT_INTERRUPT;
400 env->error_code = 0;
401 do_interrupt(env);
402 next_tb = 0;
403 }
404 #elif defined(TARGET_OPENRISC)
405 {
406 int idx = -1;
407 if ((interrupt_request & CPU_INTERRUPT_HARD)
408 && (env->sr & SR_IEE)) {
409 idx = EXCP_INT;
410 }
411 if ((interrupt_request & CPU_INTERRUPT_TIMER)
412 && (env->sr & SR_TEE)) {
413 idx = EXCP_TICK;
414 }
415 if (idx >= 0) {
416 env->exception_index = idx;
417 do_interrupt(env);
418 next_tb = 0;
419 }
420 }
421 #elif defined(TARGET_SPARC)
422 if (interrupt_request & CPU_INTERRUPT_HARD) {
423 if (cpu_interrupts_enabled(env) &&
424 env->interrupt_index > 0) {
425 int pil = env->interrupt_index & 0xf;
426 int type = env->interrupt_index & 0xf0;
427
428 if (((type == TT_EXTINT) &&
429 cpu_pil_allowed(env, pil)) ||
430 type != TT_EXTINT) {
431 env->exception_index = env->interrupt_index;
432 do_interrupt(env);
433 next_tb = 0;
434 }
435 }
436 }
437 #elif defined(TARGET_ARM)
438 if (interrupt_request & CPU_INTERRUPT_FIQ
439 && !(env->uncached_cpsr & CPSR_F)) {
440 env->exception_index = EXCP_FIQ;
441 do_interrupt(env);
442 next_tb = 0;
443 }
444 /* ARMv7-M interrupt return works by loading a magic value
445 into the PC. On real hardware the load causes the
446 return to occur. The qemu implementation performs the
447 jump normally, then does the exception return when the
448 CPU tries to execute code at the magic address.
449 This will cause the magic PC value to be pushed to
450 the stack if an interrupt occurred at the wrong time.
451 We avoid this by disabling interrupts when
452 pc contains a magic address. */
453 if (interrupt_request & CPU_INTERRUPT_HARD
454 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
455 || !(env->uncached_cpsr & CPSR_I))) {
456 env->exception_index = EXCP_IRQ;
457 do_interrupt(env);
458 next_tb = 0;
459 }
460 #elif defined(TARGET_UNICORE32)
461 if (interrupt_request & CPU_INTERRUPT_HARD
462 && !(env->uncached_asr & ASR_I)) {
463 env->exception_index = UC32_EXCP_INTR;
464 do_interrupt(env);
465 next_tb = 0;
466 }
467 #elif defined(TARGET_SH4)
468 if (interrupt_request & CPU_INTERRUPT_HARD) {
469 do_interrupt(env);
470 next_tb = 0;
471 }
472 #elif defined(TARGET_ALPHA)
473 {
474 int idx = -1;
475 /* ??? This hard-codes the OSF/1 interrupt levels. */
476 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
477 case 0 ... 3:
478 if (interrupt_request & CPU_INTERRUPT_HARD) {
479 idx = EXCP_DEV_INTERRUPT;
480 }
481 /* FALLTHRU */
482 case 4:
483 if (interrupt_request & CPU_INTERRUPT_TIMER) {
484 idx = EXCP_CLK_INTERRUPT;
485 }
486 /* FALLTHRU */
487 case 5:
488 if (interrupt_request & CPU_INTERRUPT_SMP) {
489 idx = EXCP_SMP_INTERRUPT;
490 }
491 /* FALLTHRU */
492 case 6:
493 if (interrupt_request & CPU_INTERRUPT_MCHK) {
494 idx = EXCP_MCHK;
495 }
496 }
497 if (idx >= 0) {
498 env->exception_index = idx;
499 env->error_code = 0;
500 do_interrupt(env);
501 next_tb = 0;
502 }
503 }
504 #elif defined(TARGET_CRIS)
505 if (interrupt_request & CPU_INTERRUPT_HARD
506 && (env->pregs[PR_CCS] & I_FLAG)
507 && !env->locked_irq) {
508 env->exception_index = EXCP_IRQ;
509 do_interrupt(env);
510 next_tb = 0;
511 }
512 if (interrupt_request & CPU_INTERRUPT_NMI) {
513 unsigned int m_flag_archval;
514 if (env->pregs[PR_VR] < 32) {
515 m_flag_archval = M_FLAG_V10;
516 } else {
517 m_flag_archval = M_FLAG_V32;
518 }
519 if ((env->pregs[PR_CCS] & m_flag_archval)) {
520 env->exception_index = EXCP_NMI;
521 do_interrupt(env);
522 next_tb = 0;
523 }
524 }
525 #elif defined(TARGET_M68K)
526 if (interrupt_request & CPU_INTERRUPT_HARD
527 && ((env->sr & SR_I) >> SR_I_SHIFT)
528 < env->pending_level) {
529 /* Real hardware gets the interrupt vector via an
530 IACK cycle at this point. Current emulated
531 hardware doesn't rely on this, so we
532 provide/save the vector when the interrupt is
533 first signalled. */
534 env->exception_index = env->pending_vector;
535 do_interrupt_m68k_hardirq(env);
536 next_tb = 0;
537 }
538 #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
539 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
540 (env->psw.mask & PSW_MASK_EXT)) {
541 do_interrupt(env);
542 next_tb = 0;
543 }
544 #elif defined(TARGET_XTENSA)
545 if (interrupt_request & CPU_INTERRUPT_HARD) {
546 env->exception_index = EXC_IRQ;
547 do_interrupt(env);
548 next_tb = 0;
549 }
550 #endif
551 /* Don't use the cached interrupt_request value,
552 do_interrupt may have updated the EXITTB flag. */
553 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
554 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
555 /* ensure that no TB jump will be modified as
556 the program flow was changed */
557 next_tb = 0;
558 }
559 }
560 if (unlikely(cpu->exit_request)) {
561 cpu->exit_request = 0;
562 env->exception_index = EXCP_INTERRUPT;
563 cpu_loop_exit(env);
564 }
565 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
566 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
567 /* restore flags in standard format */
568 #if defined(TARGET_I386)
569 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
570 | (DF & DF_MASK);
571 log_cpu_state(env, CPU_DUMP_CCOP);
572 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
573 #elif defined(TARGET_M68K)
574 cpu_m68k_flush_flags(env, env->cc_op);
575 env->cc_op = CC_OP_FLAGS;
576 env->sr = (env->sr & 0xffe0)
577 | env->cc_dest | (env->cc_x << 4);
578 log_cpu_state(env, 0);
579 #else
580 log_cpu_state(env, 0);
581 #endif
582 }
583 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
584 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
585 tb = tb_find_fast(env);
586 /* Note: we do it here to avoid a gcc bug on Mac OS X when
587 doing it in tb_find_slow */
588 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
589 /* as some TB could have been invalidated because
590 of memory exceptions while generating the code, we
591 must recompute the hash index here */
592 next_tb = 0;
593 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
594 }
595 #ifdef CONFIG_DEBUG_EXEC
596 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
597 tb->tc_ptr, tb->pc,
598 lookup_symbol(tb->pc));
599 #endif
600 /* see if we can patch the calling TB. When the TB
601 spans two pages, we cannot safely do a direct
602 jump. */
603 if (next_tb != 0 && tb->page_addr[1] == -1) {
604 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
605 next_tb & TB_EXIT_MASK, tb);
606 }
607 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
608
609 /* cpu_interrupt might be called while translating the
610 TB, but before it is linked into a potentially
611 infinite loop and becomes env->current_tb. Avoid
612 starting execution if there is a pending interrupt. */
613 cpu->current_tb = tb;
614 barrier();
615 if (likely(!cpu->exit_request)) {
616 tc_ptr = tb->tc_ptr;
617 /* execute the generated code */
618 next_tb = cpu_tb_exec(cpu, tc_ptr);
619 switch (next_tb & TB_EXIT_MASK) {
620 case TB_EXIT_REQUESTED:
621 /* Something asked us to stop executing
622 * chained TBs; just continue round the main
623 * loop. Whatever requested the exit will also
624 * have set something else (eg exit_request or
625 * interrupt_request) which we will handle
626 * next time around the loop.
627 */
628 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
629 next_tb = 0;
630 break;
631 case TB_EXIT_ICOUNT_EXPIRED:
632 {
633 /* Instruction counter expired. */
634 int insns_left;
635 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
636 insns_left = env->icount_decr.u32;
637 if (env->icount_extra && insns_left >= 0) {
638 /* Refill decrementer and continue execution. */
639 env->icount_extra += insns_left;
640 if (env->icount_extra > 0xffff) {
641 insns_left = 0xffff;
642 } else {
643 insns_left = env->icount_extra;
644 }
645 env->icount_extra -= insns_left;
646 env->icount_decr.u16.low = insns_left;
647 } else {
648 if (insns_left > 0) {
649 /* Execute remaining instructions. */
650 cpu_exec_nocache(env, insns_left, tb);
651 }
652 env->exception_index = EXCP_INTERRUPT;
653 next_tb = 0;
654 cpu_loop_exit(env);
655 }
656 break;
657 }
658 default:
659 break;
660 }
661 }
662 cpu->current_tb = NULL;
663 /* reset soft MMU for next block (it can currently
664 only be set by a memory fault) */
665 } /* for(;;) */
666 } else {
667 /* Reload env after longjmp - the compiler may have smashed all
668 * local variables as longjmp is marked 'noreturn'. */
669 env = cpu_single_env;
670 }
671 } /* for(;;) */
672
673
674 #if defined(TARGET_I386)
675 /* restore flags in standard format */
676 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
677 | (DF & DF_MASK);
678 #elif defined(TARGET_ARM)
679 /* XXX: Save/restore host fpu exception state?. */
680 #elif defined(TARGET_UNICORE32)
681 #elif defined(TARGET_SPARC)
682 #elif defined(TARGET_PPC)
683 #elif defined(TARGET_LM32)
684 #elif defined(TARGET_M68K)
685 cpu_m68k_flush_flags(env, env->cc_op);
686 env->cc_op = CC_OP_FLAGS;
687 env->sr = (env->sr & 0xffe0)
688 | env->cc_dest | (env->cc_x << 4);
689 #elif defined(TARGET_MICROBLAZE)
690 #elif defined(TARGET_MIPS)
691 #elif defined(TARGET_OPENRISC)
692 #elif defined(TARGET_SH4)
693 #elif defined(TARGET_ALPHA)
694 #elif defined(TARGET_CRIS)
695 #elif defined(TARGET_S390X)
696 #elif defined(TARGET_XTENSA)
697 /* XXXXX */
698 #else
699 #error unsupported target CPU
700 #endif
701
702 /* fail safe : never use cpu_single_env outside cpu_exec() */
703 cpu_single_env = NULL;
704 return ret;
705 }