block: User BdrvChild callback for device name
[qemu.git] / cputlb.c
1 /*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/memory.h"
24 #include "exec/address-spaces.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/cputlb.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "tcg/tcg.h"
32
33 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
34 /* #define DEBUG_TLB */
35 /* #define DEBUG_TLB_LOG */
36
37 #ifdef DEBUG_TLB
38 # define DEBUG_TLB_GATE 1
39 # ifdef DEBUG_TLB_LOG
40 # define DEBUG_TLB_LOG_GATE 1
41 # else
42 # define DEBUG_TLB_LOG_GATE 0
43 # endif
44 #else
45 # define DEBUG_TLB_GATE 0
46 # define DEBUG_TLB_LOG_GATE 0
47 #endif
48
49 #define tlb_debug(fmt, ...) do { \
50 if (DEBUG_TLB_LOG_GATE) { \
51 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
52 ## __VA_ARGS__); \
53 } else if (DEBUG_TLB_GATE) { \
54 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
55 } \
56 } while (0)
57
58 /* statistics */
59 int tlb_flush_count;
60
61 /* NOTE:
62 * If flush_global is true (the usual case), flush all tlb entries.
63 * If flush_global is false, flush (at least) all tlb entries not
64 * marked global.
65 *
66 * Since QEMU doesn't currently implement a global/not-global flag
67 * for tlb entries, at the moment tlb_flush() will also flush all
68 * tlb entries in the flush_global == false case. This is OK because
69 * CPU architectures generally permit an implementation to drop
70 * entries from the TLB at any time, so flushing more entries than
71 * required is only an efficiency issue, not a correctness issue.
72 */
73 void tlb_flush(CPUState *cpu, int flush_global)
74 {
75 CPUArchState *env = cpu->env_ptr;
76
77 tlb_debug("(%d)\n", flush_global);
78
79 memset(env->tlb_table, -1, sizeof(env->tlb_table));
80 memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
81 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
82
83 env->vtlb_index = 0;
84 env->tlb_flush_addr = -1;
85 env->tlb_flush_mask = 0;
86 tlb_flush_count++;
87 }
88
89 static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
90 {
91 CPUArchState *env = cpu->env_ptr;
92
93 tlb_debug("start\n");
94
95 for (;;) {
96 int mmu_idx = va_arg(argp, int);
97
98 if (mmu_idx < 0) {
99 break;
100 }
101
102 tlb_debug("%d\n", mmu_idx);
103
104 memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
105 memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
106 }
107
108 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
109 }
110
111 void tlb_flush_by_mmuidx(CPUState *cpu, ...)
112 {
113 va_list argp;
114 va_start(argp, cpu);
115 v_tlb_flush_by_mmuidx(cpu, argp);
116 va_end(argp);
117 }
118
119 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
120 {
121 if (addr == (tlb_entry->addr_read &
122 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
123 addr == (tlb_entry->addr_write &
124 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
125 addr == (tlb_entry->addr_code &
126 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
127 memset(tlb_entry, -1, sizeof(*tlb_entry));
128 }
129 }
130
131 void tlb_flush_page(CPUState *cpu, target_ulong addr)
132 {
133 CPUArchState *env = cpu->env_ptr;
134 int i;
135 int mmu_idx;
136
137 tlb_debug("page :" TARGET_FMT_lx "\n", addr);
138
139 /* Check if we need to flush due to large pages. */
140 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
141 tlb_debug("forcing full flush ("
142 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
143 env->tlb_flush_addr, env->tlb_flush_mask);
144
145 tlb_flush(cpu, 1);
146 return;
147 }
148
149 addr &= TARGET_PAGE_MASK;
150 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
151 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
152 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
153 }
154
155 /* check whether there are entries that need to be flushed in the vtlb */
156 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
157 int k;
158 for (k = 0; k < CPU_VTLB_SIZE; k++) {
159 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
160 }
161 }
162
163 tb_flush_jmp_cache(cpu, addr);
164 }
165
166 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
167 {
168 CPUArchState *env = cpu->env_ptr;
169 int i, k;
170 va_list argp;
171
172 va_start(argp, addr);
173
174 tlb_debug("addr "TARGET_FMT_lx"\n", addr);
175
176 /* Check if we need to flush due to large pages. */
177 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
178 tlb_debug("forced full flush ("
179 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
180 env->tlb_flush_addr, env->tlb_flush_mask);
181
182 v_tlb_flush_by_mmuidx(cpu, argp);
183 va_end(argp);
184 return;
185 }
186
187 addr &= TARGET_PAGE_MASK;
188 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
189
190 for (;;) {
191 int mmu_idx = va_arg(argp, int);
192
193 if (mmu_idx < 0) {
194 break;
195 }
196
197 tlb_debug("idx %d\n", mmu_idx);
198
199 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
200
201 /* check whether there are vltb entries that need to be flushed */
202 for (k = 0; k < CPU_VTLB_SIZE; k++) {
203 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
204 }
205 }
206 va_end(argp);
207
208 tb_flush_jmp_cache(cpu, addr);
209 }
210
211 /* update the TLBs so that writes to code in the virtual page 'addr'
212 can be detected */
213 void tlb_protect_code(ram_addr_t ram_addr)
214 {
215 cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
216 DIRTY_MEMORY_CODE);
217 }
218
219 /* update the TLB so that writes in physical page 'phys_addr' are no longer
220 tested for self modifying code */
221 void tlb_unprotect_code(ram_addr_t ram_addr)
222 {
223 cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
224 }
225
226 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
227 {
228 return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
229 }
230
231 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
232 uintptr_t length)
233 {
234 uintptr_t addr;
235
236 if (tlb_is_dirty_ram(tlb_entry)) {
237 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
238 if ((addr - start) < length) {
239 tlb_entry->addr_write |= TLB_NOTDIRTY;
240 }
241 }
242 }
243
244 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
245 {
246 ram_addr_t ram_addr;
247
248 if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
249 fprintf(stderr, "Bad ram pointer %p\n", ptr);
250 abort();
251 }
252 return ram_addr;
253 }
254
255 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
256 {
257 CPUArchState *env;
258
259 int mmu_idx;
260
261 env = cpu->env_ptr;
262 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
263 unsigned int i;
264
265 for (i = 0; i < CPU_TLB_SIZE; i++) {
266 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
267 start1, length);
268 }
269
270 for (i = 0; i < CPU_VTLB_SIZE; i++) {
271 tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
272 start1, length);
273 }
274 }
275 }
276
277 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
278 {
279 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
280 tlb_entry->addr_write = vaddr;
281 }
282 }
283
284 /* update the TLB corresponding to virtual page vaddr
285 so that it is no longer dirty */
286 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
287 {
288 CPUArchState *env = cpu->env_ptr;
289 int i;
290 int mmu_idx;
291
292 vaddr &= TARGET_PAGE_MASK;
293 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
294 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
295 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
296 }
297
298 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
299 int k;
300 for (k = 0; k < CPU_VTLB_SIZE; k++) {
301 tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
302 }
303 }
304 }
305
306 /* Our TLB does not support large pages, so remember the area covered by
307 large pages and trigger a full TLB flush if these are invalidated. */
308 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
309 target_ulong size)
310 {
311 target_ulong mask = ~(size - 1);
312
313 if (env->tlb_flush_addr == (target_ulong)-1) {
314 env->tlb_flush_addr = vaddr & mask;
315 env->tlb_flush_mask = mask;
316 return;
317 }
318 /* Extend the existing region to include the new page.
319 This is a compromise between unnecessary flushes and the cost
320 of maintaining a full variable size TLB. */
321 mask &= env->tlb_flush_mask;
322 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
323 mask <<= 1;
324 }
325 env->tlb_flush_addr &= mask;
326 env->tlb_flush_mask = mask;
327 }
328
329 /* Add a new TLB entry. At most one entry for a given virtual address
330 * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
331 * supplied size is only used by tlb_flush_page.
332 *
333 * Called from TCG-generated code, which is under an RCU read-side
334 * critical section.
335 */
336 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
337 hwaddr paddr, MemTxAttrs attrs, int prot,
338 int mmu_idx, target_ulong size)
339 {
340 CPUArchState *env = cpu->env_ptr;
341 MemoryRegionSection *section;
342 unsigned int index;
343 target_ulong address;
344 target_ulong code_address;
345 uintptr_t addend;
346 CPUTLBEntry *te;
347 hwaddr iotlb, xlat, sz;
348 unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
349 int asidx = cpu_asidx_from_attrs(cpu, attrs);
350
351 assert(size >= TARGET_PAGE_SIZE);
352 if (size != TARGET_PAGE_SIZE) {
353 tlb_add_large_page(env, vaddr, size);
354 }
355
356 sz = size;
357 section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);
358 assert(sz >= TARGET_PAGE_SIZE);
359
360 tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
361 " prot=%x idx=%d\n",
362 vaddr, paddr, prot, mmu_idx);
363
364 address = vaddr;
365 if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
366 /* IO memory case */
367 address |= TLB_MMIO;
368 addend = 0;
369 } else {
370 /* TLB_MMIO for rom/romd handled below */
371 addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
372 }
373
374 code_address = address;
375 iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
376 prot, &address);
377
378 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
379 te = &env->tlb_table[mmu_idx][index];
380
381 /* do not discard the translation in te, evict it into a victim tlb */
382 env->tlb_v_table[mmu_idx][vidx] = *te;
383 env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
384
385 /* refill the tlb */
386 env->iotlb[mmu_idx][index].addr = iotlb - vaddr;
387 env->iotlb[mmu_idx][index].attrs = attrs;
388 te->addend = addend - vaddr;
389 if (prot & PAGE_READ) {
390 te->addr_read = address;
391 } else {
392 te->addr_read = -1;
393 }
394
395 if (prot & PAGE_EXEC) {
396 te->addr_code = code_address;
397 } else {
398 te->addr_code = -1;
399 }
400 if (prot & PAGE_WRITE) {
401 if ((memory_region_is_ram(section->mr) && section->readonly)
402 || memory_region_is_romd(section->mr)) {
403 /* Write access calls the I/O callback. */
404 te->addr_write = address | TLB_MMIO;
405 } else if (memory_region_is_ram(section->mr)
406 && cpu_physical_memory_is_clean(
407 memory_region_get_ram_addr(section->mr) + xlat)) {
408 te->addr_write = address | TLB_NOTDIRTY;
409 } else {
410 te->addr_write = address;
411 }
412 } else {
413 te->addr_write = -1;
414 }
415 }
416
417 /* Add a new TLB entry, but without specifying the memory
418 * transaction attributes to be used.
419 */
420 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
421 hwaddr paddr, int prot,
422 int mmu_idx, target_ulong size)
423 {
424 tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED,
425 prot, mmu_idx, size);
426 }
427
428 /* NOTE: this function can trigger an exception */
429 /* NOTE2: the returned address is not exactly the physical address: it
430 * is actually a ram_addr_t (in system mode; the user mode emulation
431 * version of this function returns a guest virtual address).
432 */
433 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
434 {
435 int mmu_idx, page_index, pd;
436 void *p;
437 MemoryRegion *mr;
438 CPUState *cpu = ENV_GET_CPU(env1);
439 CPUIOTLBEntry *iotlbentry;
440
441 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
442 mmu_idx = cpu_mmu_index(env1, true);
443 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
444 (addr & TARGET_PAGE_MASK))) {
445 cpu_ldub_code(env1, addr);
446 }
447 iotlbentry = &env1->iotlb[mmu_idx][page_index];
448 pd = iotlbentry->addr & ~TARGET_PAGE_MASK;
449 mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);
450 if (memory_region_is_unassigned(mr)) {
451 CPUClass *cc = CPU_GET_CLASS(cpu);
452
453 if (cc->do_unassigned_access) {
454 cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
455 } else {
456 cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
457 TARGET_FMT_lx "\n", addr);
458 }
459 }
460 p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
461 return qemu_ram_addr_from_host_nofail(p);
462 }
463
464 #define MMUSUFFIX _mmu
465
466 #define SHIFT 0
467 #include "softmmu_template.h"
468
469 #define SHIFT 1
470 #include "softmmu_template.h"
471
472 #define SHIFT 2
473 #include "softmmu_template.h"
474
475 #define SHIFT 3
476 #include "softmmu_template.h"
477 #undef MMUSUFFIX
478
479 #define MMUSUFFIX _cmmu
480 #undef GETPC_ADJ
481 #define GETPC_ADJ 0
482 #undef GETRA
483 #define GETRA() ((uintptr_t)0)
484 #define SOFTMMU_CODE_ACCESS
485
486 #define SHIFT 0
487 #include "softmmu_template.h"
488
489 #define SHIFT 1
490 #include "softmmu_template.h"
491
492 #define SHIFT 2
493 #include "softmmu_template.h"
494
495 #define SHIFT 3
496 #include "softmmu_template.h"