MAINTAINERS: add section for QEMU Guest Agent
[qemu.git] / cputlb.c
1 /*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "config.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/memory.h"
24 #include "exec/address-spaces.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/cputlb.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "tcg/tcg.h"
32
33 //#define DEBUG_TLB
34 //#define DEBUG_TLB_CHECK
35
36 /* statistics */
37 int tlb_flush_count;
38
39 /* NOTE:
40 * If flush_global is true (the usual case), flush all tlb entries.
41 * If flush_global is false, flush (at least) all tlb entries not
42 * marked global.
43 *
44 * Since QEMU doesn't currently implement a global/not-global flag
45 * for tlb entries, at the moment tlb_flush() will also flush all
46 * tlb entries in the flush_global == false case. This is OK because
47 * CPU architectures generally permit an implementation to drop
48 * entries from the TLB at any time, so flushing more entries than
49 * required is only an efficiency issue, not a correctness issue.
50 */
51 void tlb_flush(CPUState *cpu, int flush_global)
52 {
53 CPUArchState *env = cpu->env_ptr;
54
55 #if defined(DEBUG_TLB)
56 printf("tlb_flush:\n");
57 #endif
58 /* must reset current TB so that interrupts cannot modify the
59 links while we are modifying them */
60 cpu->current_tb = NULL;
61
62 memset(env->tlb_table, -1, sizeof(env->tlb_table));
63 memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
64 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
65
66 env->vtlb_index = 0;
67 env->tlb_flush_addr = -1;
68 env->tlb_flush_mask = 0;
69 tlb_flush_count++;
70 }
71
72 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
73 {
74 if (addr == (tlb_entry->addr_read &
75 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
76 addr == (tlb_entry->addr_write &
77 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
78 addr == (tlb_entry->addr_code &
79 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
80 memset(tlb_entry, -1, sizeof(*tlb_entry));
81 }
82 }
83
84 void tlb_flush_page(CPUState *cpu, target_ulong addr)
85 {
86 CPUArchState *env = cpu->env_ptr;
87 int i;
88 int mmu_idx;
89
90 #if defined(DEBUG_TLB)
91 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
92 #endif
93 /* Check if we need to flush due to large pages. */
94 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
95 #if defined(DEBUG_TLB)
96 printf("tlb_flush_page: forced full flush ("
97 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
98 env->tlb_flush_addr, env->tlb_flush_mask);
99 #endif
100 tlb_flush(cpu, 1);
101 return;
102 }
103 /* must reset current TB so that interrupts cannot modify the
104 links while we are modifying them */
105 cpu->current_tb = NULL;
106
107 addr &= TARGET_PAGE_MASK;
108 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
109 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
110 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
111 }
112
113 /* check whether there are entries that need to be flushed in the vtlb */
114 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
115 int k;
116 for (k = 0; k < CPU_VTLB_SIZE; k++) {
117 tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
118 }
119 }
120
121 tb_flush_jmp_cache(cpu, addr);
122 }
123
124 /* update the TLBs so that writes to code in the virtual page 'addr'
125 can be detected */
126 void tlb_protect_code(ram_addr_t ram_addr)
127 {
128 cpu_physical_memory_reset_dirty(ram_addr, TARGET_PAGE_SIZE,
129 DIRTY_MEMORY_CODE);
130 }
131
132 /* update the TLB so that writes in physical page 'phys_addr' are no longer
133 tested for self modifying code */
134 void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
135 target_ulong vaddr)
136 {
137 cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
138 }
139
140 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
141 {
142 return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
143 }
144
145 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
146 uintptr_t length)
147 {
148 uintptr_t addr;
149
150 if (tlb_is_dirty_ram(tlb_entry)) {
151 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
152 if ((addr - start) < length) {
153 tlb_entry->addr_write |= TLB_NOTDIRTY;
154 }
155 }
156 }
157
158 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
159 {
160 ram_addr_t ram_addr;
161
162 if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
163 fprintf(stderr, "Bad ram pointer %p\n", ptr);
164 abort();
165 }
166 return ram_addr;
167 }
168
169 void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
170 {
171 CPUState *cpu;
172 CPUArchState *env;
173
174 CPU_FOREACH(cpu) {
175 int mmu_idx;
176
177 env = cpu->env_ptr;
178 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
179 unsigned int i;
180
181 for (i = 0; i < CPU_TLB_SIZE; i++) {
182 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
183 start1, length);
184 }
185
186 for (i = 0; i < CPU_VTLB_SIZE; i++) {
187 tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
188 start1, length);
189 }
190 }
191 }
192 }
193
194 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
195 {
196 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
197 tlb_entry->addr_write = vaddr;
198 }
199 }
200
201 /* update the TLB corresponding to virtual page vaddr
202 so that it is no longer dirty */
203 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
204 {
205 int i;
206 int mmu_idx;
207
208 vaddr &= TARGET_PAGE_MASK;
209 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
210 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
211 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
212 }
213
214 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
215 int k;
216 for (k = 0; k < CPU_VTLB_SIZE; k++) {
217 tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr);
218 }
219 }
220 }
221
222 /* Our TLB does not support large pages, so remember the area covered by
223 large pages and trigger a full TLB flush if these are invalidated. */
224 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
225 target_ulong size)
226 {
227 target_ulong mask = ~(size - 1);
228
229 if (env->tlb_flush_addr == (target_ulong)-1) {
230 env->tlb_flush_addr = vaddr & mask;
231 env->tlb_flush_mask = mask;
232 return;
233 }
234 /* Extend the existing region to include the new page.
235 This is a compromise between unnecessary flushes and the cost
236 of maintaining a full variable size TLB. */
237 mask &= env->tlb_flush_mask;
238 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
239 mask <<= 1;
240 }
241 env->tlb_flush_addr &= mask;
242 env->tlb_flush_mask = mask;
243 }
244
245 /* Add a new TLB entry. At most one entry for a given virtual address
246 is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
247 supplied size is only used by tlb_flush_page. */
248 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
249 hwaddr paddr, int prot,
250 int mmu_idx, target_ulong size)
251 {
252 CPUArchState *env = cpu->env_ptr;
253 MemoryRegionSection *section;
254 unsigned int index;
255 target_ulong address;
256 target_ulong code_address;
257 uintptr_t addend;
258 CPUTLBEntry *te;
259 hwaddr iotlb, xlat, sz;
260 unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
261
262 assert(size >= TARGET_PAGE_SIZE);
263 if (size != TARGET_PAGE_SIZE) {
264 tlb_add_large_page(env, vaddr, size);
265 }
266
267 sz = size;
268 section = address_space_translate_for_iotlb(cpu->as, paddr,
269 &xlat, &sz);
270 assert(sz >= TARGET_PAGE_SIZE);
271
272 #if defined(DEBUG_TLB)
273 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
274 " prot=%x idx=%d\n",
275 vaddr, paddr, prot, mmu_idx);
276 #endif
277
278 address = vaddr;
279 if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
280 /* IO memory case */
281 address |= TLB_MMIO;
282 addend = 0;
283 } else {
284 /* TLB_MMIO for rom/romd handled below */
285 addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
286 }
287
288 code_address = address;
289 iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
290 prot, &address);
291
292 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
293 te = &env->tlb_table[mmu_idx][index];
294
295 /* do not discard the translation in te, evict it into a victim tlb */
296 env->tlb_v_table[mmu_idx][vidx] = *te;
297 env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
298
299 /* refill the tlb */
300 env->iotlb[mmu_idx][index] = iotlb - vaddr;
301 te->addend = addend - vaddr;
302 if (prot & PAGE_READ) {
303 te->addr_read = address;
304 } else {
305 te->addr_read = -1;
306 }
307
308 if (prot & PAGE_EXEC) {
309 te->addr_code = code_address;
310 } else {
311 te->addr_code = -1;
312 }
313 if (prot & PAGE_WRITE) {
314 if ((memory_region_is_ram(section->mr) && section->readonly)
315 || memory_region_is_romd(section->mr)) {
316 /* Write access calls the I/O callback. */
317 te->addr_write = address | TLB_MMIO;
318 } else if (memory_region_is_ram(section->mr)
319 && cpu_physical_memory_is_clean(section->mr->ram_addr
320 + xlat)) {
321 te->addr_write = address | TLB_NOTDIRTY;
322 } else {
323 te->addr_write = address;
324 }
325 } else {
326 te->addr_write = -1;
327 }
328 }
329
330 /* NOTE: this function can trigger an exception */
331 /* NOTE2: the returned address is not exactly the physical address: it
332 * is actually a ram_addr_t (in system mode; the user mode emulation
333 * version of this function returns a guest virtual address).
334 */
335 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
336 {
337 int mmu_idx, page_index, pd;
338 void *p;
339 MemoryRegion *mr;
340 CPUState *cpu = ENV_GET_CPU(env1);
341
342 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
343 mmu_idx = cpu_mmu_index(env1);
344 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
345 (addr & TARGET_PAGE_MASK))) {
346 cpu_ldub_code(env1, addr);
347 }
348 pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
349 mr = iotlb_to_region(cpu->as, pd);
350 if (memory_region_is_unassigned(mr)) {
351 CPUClass *cc = CPU_GET_CLASS(cpu);
352
353 if (cc->do_unassigned_access) {
354 cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
355 } else {
356 cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
357 TARGET_FMT_lx "\n", addr);
358 }
359 }
360 p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
361 return qemu_ram_addr_from_host_nofail(p);
362 }
363
364 #define MMUSUFFIX _mmu
365
366 #define SHIFT 0
367 #include "softmmu_template.h"
368
369 #define SHIFT 1
370 #include "softmmu_template.h"
371
372 #define SHIFT 2
373 #include "softmmu_template.h"
374
375 #define SHIFT 3
376 #include "softmmu_template.h"
377 #undef MMUSUFFIX
378
379 #define MMUSUFFIX _cmmu
380 #undef GETPC_ADJ
381 #define GETPC_ADJ 0
382 #undef GETRA
383 #define GETRA() ((uintptr_t)0)
384 #define SOFTMMU_CODE_ACCESS
385
386 #define SHIFT 0
387 #include "softmmu_template.h"
388
389 #define SHIFT 1
390 #include "softmmu_template.h"
391
392 #define SHIFT 2
393 #include "softmmu_template.h"
394
395 #define SHIFT 3
396 #include "softmmu_template.h"