cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / cputlb.c
1 /*
2 * Common CPU TLB handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "config.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/memory.h"
24 #include "exec/address-spaces.h"
25
26 #include "exec/cputlb.h"
27
28 #include "exec/memory-internal.h"
29 #include "exec/ram_addr.h"
30
31 //#define DEBUG_TLB
32 //#define DEBUG_TLB_CHECK
33
34 /* statistics */
35 int tlb_flush_count;
36
37 /* NOTE:
38 * If flush_global is true (the usual case), flush all tlb entries.
39 * If flush_global is false, flush (at least) all tlb entries not
40 * marked global.
41 *
42 * Since QEMU doesn't currently implement a global/not-global flag
43 * for tlb entries, at the moment tlb_flush() will also flush all
44 * tlb entries in the flush_global == false case. This is OK because
45 * CPU architectures generally permit an implementation to drop
46 * entries from the TLB at any time, so flushing more entries than
47 * required is only an efficiency issue, not a correctness issue.
48 */
49 void tlb_flush(CPUState *cpu, int flush_global)
50 {
51 CPUArchState *env = cpu->env_ptr;
52
53 #if defined(DEBUG_TLB)
54 printf("tlb_flush:\n");
55 #endif
56 /* must reset current TB so that interrupts cannot modify the
57 links while we are modifying them */
58 cpu->current_tb = NULL;
59
60 memset(env->tlb_table, -1, sizeof(env->tlb_table));
61 memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
62
63 env->tlb_flush_addr = -1;
64 env->tlb_flush_mask = 0;
65 tlb_flush_count++;
66 }
67
68 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
69 {
70 if (addr == (tlb_entry->addr_read &
71 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
72 addr == (tlb_entry->addr_write &
73 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
74 addr == (tlb_entry->addr_code &
75 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
76 memset(tlb_entry, -1, sizeof(*tlb_entry));
77 }
78 }
79
80 void tlb_flush_page(CPUState *cpu, target_ulong addr)
81 {
82 CPUArchState *env = cpu->env_ptr;
83 int i;
84 int mmu_idx;
85
86 #if defined(DEBUG_TLB)
87 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
88 #endif
89 /* Check if we need to flush due to large pages. */
90 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
91 #if defined(DEBUG_TLB)
92 printf("tlb_flush_page: forced full flush ("
93 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
94 env->tlb_flush_addr, env->tlb_flush_mask);
95 #endif
96 tlb_flush(cpu, 1);
97 return;
98 }
99 /* must reset current TB so that interrupts cannot modify the
100 links while we are modifying them */
101 cpu->current_tb = NULL;
102
103 addr &= TARGET_PAGE_MASK;
104 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
105 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
106 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
107 }
108
109 tb_flush_jmp_cache(cpu, addr);
110 }
111
112 /* update the TLBs so that writes to code in the virtual page 'addr'
113 can be detected */
114 void tlb_protect_code(ram_addr_t ram_addr)
115 {
116 cpu_physical_memory_reset_dirty(ram_addr, TARGET_PAGE_SIZE,
117 DIRTY_MEMORY_CODE);
118 }
119
120 /* update the TLB so that writes in physical page 'phys_addr' are no longer
121 tested for self modifying code */
122 void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
123 target_ulong vaddr)
124 {
125 cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
126 }
127
128 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
129 {
130 return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
131 }
132
133 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
134 uintptr_t length)
135 {
136 uintptr_t addr;
137
138 if (tlb_is_dirty_ram(tlb_entry)) {
139 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
140 if ((addr - start) < length) {
141 tlb_entry->addr_write |= TLB_NOTDIRTY;
142 }
143 }
144 }
145
146 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
147 {
148 ram_addr_t ram_addr;
149
150 if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
151 fprintf(stderr, "Bad ram pointer %p\n", ptr);
152 abort();
153 }
154 return ram_addr;
155 }
156
157 void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
158 {
159 CPUState *cpu;
160 CPUArchState *env;
161
162 CPU_FOREACH(cpu) {
163 int mmu_idx;
164
165 env = cpu->env_ptr;
166 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
167 unsigned int i;
168
169 for (i = 0; i < CPU_TLB_SIZE; i++) {
170 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
171 start1, length);
172 }
173 }
174 }
175 }
176
177 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
178 {
179 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
180 tlb_entry->addr_write = vaddr;
181 }
182 }
183
184 /* update the TLB corresponding to virtual page vaddr
185 so that it is no longer dirty */
186 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
187 {
188 int i;
189 int mmu_idx;
190
191 vaddr &= TARGET_PAGE_MASK;
192 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
193 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
194 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
195 }
196 }
197
198 /* Our TLB does not support large pages, so remember the area covered by
199 large pages and trigger a full TLB flush if these are invalidated. */
200 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
201 target_ulong size)
202 {
203 target_ulong mask = ~(size - 1);
204
205 if (env->tlb_flush_addr == (target_ulong)-1) {
206 env->tlb_flush_addr = vaddr & mask;
207 env->tlb_flush_mask = mask;
208 return;
209 }
210 /* Extend the existing region to include the new page.
211 This is a compromise between unnecessary flushes and the cost
212 of maintaining a full variable size TLB. */
213 mask &= env->tlb_flush_mask;
214 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
215 mask <<= 1;
216 }
217 env->tlb_flush_addr &= mask;
218 env->tlb_flush_mask = mask;
219 }
220
221 /* Add a new TLB entry. At most one entry for a given virtual address
222 is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
223 supplied size is only used by tlb_flush_page. */
224 void tlb_set_page(CPUArchState *env, target_ulong vaddr,
225 hwaddr paddr, int prot,
226 int mmu_idx, target_ulong size)
227 {
228 MemoryRegionSection *section;
229 unsigned int index;
230 target_ulong address;
231 target_ulong code_address;
232 uintptr_t addend;
233 CPUTLBEntry *te;
234 hwaddr iotlb, xlat, sz;
235 CPUState *cpu = ENV_GET_CPU(env);
236
237 assert(size >= TARGET_PAGE_SIZE);
238 if (size != TARGET_PAGE_SIZE) {
239 tlb_add_large_page(env, vaddr, size);
240 }
241
242 sz = size;
243 section = address_space_translate_for_iotlb(cpu->as, paddr,
244 &xlat, &sz);
245 assert(sz >= TARGET_PAGE_SIZE);
246
247 #if defined(DEBUG_TLB)
248 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
249 " prot=%x idx=%d\n",
250 vaddr, paddr, prot, mmu_idx);
251 #endif
252
253 address = vaddr;
254 if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
255 /* IO memory case */
256 address |= TLB_MMIO;
257 addend = 0;
258 } else {
259 /* TLB_MMIO for rom/romd handled below */
260 addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
261 }
262
263 code_address = address;
264 iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
265 prot, &address);
266
267 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
268 env->iotlb[mmu_idx][index] = iotlb - vaddr;
269 te = &env->tlb_table[mmu_idx][index];
270 te->addend = addend - vaddr;
271 if (prot & PAGE_READ) {
272 te->addr_read = address;
273 } else {
274 te->addr_read = -1;
275 }
276
277 if (prot & PAGE_EXEC) {
278 te->addr_code = code_address;
279 } else {
280 te->addr_code = -1;
281 }
282 if (prot & PAGE_WRITE) {
283 if ((memory_region_is_ram(section->mr) && section->readonly)
284 || memory_region_is_romd(section->mr)) {
285 /* Write access calls the I/O callback. */
286 te->addr_write = address | TLB_MMIO;
287 } else if (memory_region_is_ram(section->mr)
288 && cpu_physical_memory_is_clean(section->mr->ram_addr
289 + xlat)) {
290 te->addr_write = address | TLB_NOTDIRTY;
291 } else {
292 te->addr_write = address;
293 }
294 } else {
295 te->addr_write = -1;
296 }
297 }
298
299 /* NOTE: this function can trigger an exception */
300 /* NOTE2: the returned address is not exactly the physical address: it
301 * is actually a ram_addr_t (in system mode; the user mode emulation
302 * version of this function returns a guest virtual address).
303 */
304 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
305 {
306 int mmu_idx, page_index, pd;
307 void *p;
308 MemoryRegion *mr;
309 CPUState *cpu = ENV_GET_CPU(env1);
310
311 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
312 mmu_idx = cpu_mmu_index(env1);
313 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
314 (addr & TARGET_PAGE_MASK))) {
315 cpu_ldub_code(env1, addr);
316 }
317 pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
318 mr = iotlb_to_region(cpu->as, pd);
319 if (memory_region_is_unassigned(mr)) {
320 CPUClass *cc = CPU_GET_CLASS(cpu);
321
322 if (cc->do_unassigned_access) {
323 cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
324 } else {
325 cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
326 TARGET_FMT_lx "\n", addr);
327 }
328 }
329 p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
330 return qemu_ram_addr_from_host_nofail(p);
331 }
332
333 #define MMUSUFFIX _cmmu
334 #undef GETPC
335 #define GETPC() ((uintptr_t)0)
336 #define SOFTMMU_CODE_ACCESS
337
338 #define SHIFT 0
339 #include "exec/softmmu_template.h"
340
341 #define SHIFT 1
342 #include "exec/softmmu_template.h"
343
344 #define SHIFT 2
345 #include "exec/softmmu_template.h"
346
347 #define SHIFT 3
348 #include "exec/softmmu_template.h"
349
350 #undef env