disas/ia64.c

   1 /* ia64-dis.c -- Disassemble ia64 instructions
   2    Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
   3    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    2, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, see
  19    <http://www.gnu.org/licenses/>. */
  20
  21 #include "qemu/osdep.h"
  22
  23 #include "disas/bfd.h"
  24
  25 /* ia64.h -- Header file for ia64 opcode table
  26    Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
  27    Free Software Foundation, Inc.
  28    Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
  29
  30
  31 typedef uint64_t ia64_insn;
  32
  33 enum ia64_insn_type
  34   {
  35     IA64_TYPE_NIL = 0,  /* illegal type */
  36     IA64_TYPE_A,        /* integer alu (I- or M-unit) */
  37     IA64_TYPE_I,        /* non-alu integer (I-unit) */
  38     IA64_TYPE_M,        /* memory (M-unit) */
  39     IA64_TYPE_B,        /* branch (B-unit) */
  40     IA64_TYPE_F,        /* floating-point (F-unit) */
  41     IA64_TYPE_X,        /* long encoding (X-unit) */
  42     IA64_TYPE_DYN,      /* Dynamic opcode */
  43     IA64_NUM_TYPES
  44   };
  45
  46 enum ia64_unit
  47   {
  48     IA64_UNIT_NIL = 0,  /* illegal unit */
  49     IA64_UNIT_I,        /* integer unit */
  50     IA64_UNIT_M,        /* memory unit */
  51     IA64_UNIT_B,        /* branching unit */
  52     IA64_UNIT_F,        /* floating-point unit */
  53     IA64_UNIT_L,        /* long "unit" */
  54     IA64_UNIT_X,        /* may be integer or branch unit */
  55     IA64_NUM_UNITS
  56   };
  57
  58 /* Changes to this enumeration must be propagated to the operand table in
  59    bfd/cpu-ia64-opc.c
  60  */
  61 enum ia64_opnd
  62   {
  63     IA64_OPND_NIL,      /* no operand---MUST BE FIRST!*/
  64
  65     /* constants */
  66     IA64_OPND_AR_CSD,   /* application register csd (ar.csd) */
  67     IA64_OPND_AR_CCV,   /* application register ccv (ar.ccv) */
  68     IA64_OPND_AR_PFS,   /* application register pfs (ar.pfs) */
  69     IA64_OPND_C1,       /* the constant 1 */
  70     IA64_OPND_C8,       /* the constant 8 */
  71     IA64_OPND_C16,      /* the constant 16 */
  72     IA64_OPND_GR0,      /* gr0 */
  73     IA64_OPND_IP,       /* instruction pointer (ip) */
  74     IA64_OPND_PR,       /* predicate register (pr) */
  75     IA64_OPND_PR_ROT,   /* rotating predicate register (pr.rot) */
  76     IA64_OPND_PSR,      /* processor status register (psr) */
  77     IA64_OPND_PSR_L,    /* processor status register L (psr.l) */
  78     IA64_OPND_PSR_UM,   /* processor status register UM (psr.um) */
  79
  80     /* register operands: */
  81     IA64_OPND_AR3,      /* third application register # (bits 20-26) */
  82     IA64_OPND_B1,       /* branch register # (bits 6-8) */
  83     IA64_OPND_B2,       /* branch register # (bits 13-15) */
  84     IA64_OPND_CR3,      /* third control register # (bits 20-26) */
  85     IA64_OPND_F1,       /* first floating-point register # */
  86     IA64_OPND_F2,       /* second floating-point register # */
  87     IA64_OPND_F3,       /* third floating-point register # */
  88     IA64_OPND_F4,       /* fourth floating-point register # */
  89     IA64_OPND_P1,       /* first predicate # */
  90     IA64_OPND_P2,       /* second predicate # */
  91     IA64_OPND_R1,       /* first register # */
  92     IA64_OPND_R2,       /* second register # */
  93     IA64_OPND_R3,       /* third register # */
  94     IA64_OPND_R3_2,     /* third register # (limited to gr0-gr3) */
  95
  96     /* memory operands: */
  97     IA64_OPND_MR3,      /* memory at addr of third register # */
  98
  99     /* indirect operands: */
 100     IA64_OPND_CPUID_R3, /* cpuid[reg] */
 101     IA64_OPND_DBR_R3,   /* dbr[reg] */
 102     IA64_OPND_DTR_R3,   /* dtr[reg] */
 103     IA64_OPND_ITR_R3,   /* itr[reg] */
 104     IA64_OPND_IBR_R3,   /* ibr[reg] */
 105     IA64_OPND_MSR_R3,   /* msr[reg] */
 106     IA64_OPND_PKR_R3,   /* pkr[reg] */
 107     IA64_OPND_PMC_R3,   /* pmc[reg] */
 108     IA64_OPND_PMD_R3,   /* pmd[reg] */
 109     IA64_OPND_RR_R3,    /* rr[reg] */
 110
 111     /* immediate operands: */
 112     IA64_OPND_CCNT5,    /* 5-bit count (31 - bits 20-24) */
 113     IA64_OPND_CNT2a,    /* 2-bit count (1 + bits 27-28) */
 114     IA64_OPND_CNT2b,    /* 2-bit count (bits 27-28): 1, 2, 3 */
 115     IA64_OPND_CNT2c,    /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
 116     IA64_OPND_CNT5,     /* 5-bit count (bits 14-18) */
 117     IA64_OPND_CNT6,     /* 6-bit count (bits 27-32) */
 118     IA64_OPND_CPOS6a,   /* 6-bit count (63 - bits 20-25) */
 119     IA64_OPND_CPOS6b,   /* 6-bit count (63 - bits 14-19) */
 120     IA64_OPND_CPOS6c,   /* 6-bit count (63 - bits 31-36) */
 121     IA64_OPND_IMM1,     /* signed 1-bit immediate (bit 36) */
 122     IA64_OPND_IMMU2,    /* unsigned 2-bit immediate (bits 13-14) */
 123     IA64_OPND_IMMU5b,   /* unsigned 5-bit immediate (32 + bits 14-18) */
 124     IA64_OPND_IMMU7a,   /* unsigned 7-bit immediate (bits 13-19) */
 125     IA64_OPND_IMMU7b,   /* unsigned 7-bit immediate (bits 20-26) */
 126     IA64_OPND_SOF,      /* 8-bit stack frame size */
 127     IA64_OPND_SOL,      /* 8-bit size of locals */
 128     IA64_OPND_SOR,      /* 6-bit number of rotating registers (scaled by 8) */
 129     IA64_OPND_IMM8,     /* signed 8-bit immediate (bits 13-19 & 36) */
 130     IA64_OPND_IMM8U4,   /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
 131     IA64_OPND_IMM8M1,   /* signed 8-bit immediate -1 (bits 13-19 & 36) */
 132     IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
 133     IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
 134     IA64_OPND_IMMU9,    /* unsigned 9-bit immediate (bits 33-34, 20-26) */
 135     IA64_OPND_IMM9a,    /* signed 9-bit immediate (bits 6-12, 27, 36) */
 136     IA64_OPND_IMM9b,    /* signed 9-bit immediate (bits 13-19, 27, 36) */
 137     IA64_OPND_IMM14,    /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
 138     IA64_OPND_IMM17,    /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
 139     IA64_OPND_IMMU21,   /* unsigned 21-bit immediate (bits 6-25, 36) */
 140     IA64_OPND_IMM22,    /* signed 22-bit immediate (bits 13-19, 22-36) */
 141     IA64_OPND_IMMU24,   /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
 142     IA64_OPND_IMM44,    /* signed 44-bit immediate (2^16*bits 6-32, 36) */
 143     IA64_OPND_IMMU62,   /* unsigned 62-bit immediate */
 144     IA64_OPND_IMMU64,   /* unsigned 64-bit immediate (lotsa bits...) */
 145     IA64_OPND_INC3,     /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
 146     IA64_OPND_LEN4,     /* 4-bit count (bits 27-30 + 1) */
 147     IA64_OPND_LEN6,     /* 6-bit count (bits 27-32 + 1) */
 148     IA64_OPND_MBTYPE4,  /* 4-bit mux type (bits 20-23) */
 149     IA64_OPND_MHTYPE8,  /* 8-bit mux type (bits 20-27) */
 150     IA64_OPND_POS6,     /* 6-bit count (bits 14-19) */
 151     IA64_OPND_TAG13,    /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
 152     IA64_OPND_TAG13b,   /* signed 13-bit tag (ip + 16*bits 24-32) */
 153     IA64_OPND_TGT25,    /* signed 25-bit (ip + 16*bits 6-25, 36) */
 154     IA64_OPND_TGT25b,   /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
 155     IA64_OPND_TGT25c,   /* signed 25-bit (ip + 16*bits 13-32, 36) */
 156     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
 157     IA64_OPND_LDXMOV,   /* any symbol, generates R_IA64_LDXMOV.  */
 158
 159     IA64_OPND_COUNT     /* # of operand types (MUST BE LAST!) */
 160   };
 161
 162 enum ia64_dependency_mode
 163 {
 164   IA64_DV_RAW,
 165   IA64_DV_WAW,
 166   IA64_DV_WAR,
 167 };
 168
 169 enum ia64_dependency_semantics
 170 {
 171   IA64_DVS_NONE,
 172   IA64_DVS_IMPLIED,
 173   IA64_DVS_IMPLIEDF,
 174   IA64_DVS_DATA,
 175   IA64_DVS_INSTR,
 176   IA64_DVS_SPECIFIC,
 177   IA64_DVS_STOP,
 178   IA64_DVS_OTHER,
 179 };
 180
 181 enum ia64_resource_specifier
 182 {
 183   IA64_RS_ANY,
 184   IA64_RS_AR_K,
 185   IA64_RS_AR_UNAT,
 186   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
 187   IA64_RS_ARb, /* 48-63, 112-127 */
 188   IA64_RS_BR,
 189   IA64_RS_CFM,
 190   IA64_RS_CPUID,
 191   IA64_RS_CR_IRR,
 192   IA64_RS_CR_LRR,
 193   IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
 194   IA64_RS_DBR,
 195   IA64_RS_FR,
 196   IA64_RS_FRb,
 197   IA64_RS_GR0,
 198   IA64_RS_GR,
 199   IA64_RS_IBR,
 200   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
 201   IA64_RS_MSR,
 202   IA64_RS_PKR,
 203   IA64_RS_PMC,
 204   IA64_RS_PMD,
 205   IA64_RS_PR,  /* non-rotating, 1-15 */
 206   IA64_RS_PRr, /* rotating, 16-62 */
 207   IA64_RS_PR63,
 208   IA64_RS_RR,
 209
 210   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
 211   IA64_RS_CRX, /* CRs not in RS_CR */
 212   IA64_RS_PSR, /* PSR bits */
 213   IA64_RS_RSE, /* implementation-specific RSE resources */
 214   IA64_RS_AR_FPSR,
 215 };
 216
 217 enum ia64_rse_resource
 218 {
 219   IA64_RSE_N_STACKED_PHYS,
 220   IA64_RSE_BOF,
 221   IA64_RSE_STORE_REG,
 222   IA64_RSE_LOAD_REG,
 223   IA64_RSE_BSPLOAD,
 224   IA64_RSE_RNATBITINDEX,
 225   IA64_RSE_CFLE,
 226   IA64_RSE_NDIRTY,
 227 };
 228
 229 /* Information about a given resource dependency */
 230 struct ia64_dependency
 231 {
 232   /* Name of the resource */
 233   const char *name;
 234   /* Does this dependency need further specification? */
 235   enum ia64_resource_specifier specifier;
 236   /* Mode of dependency */
 237   enum ia64_dependency_mode mode;
 238   /* Dependency semantics */
 239   enum ia64_dependency_semantics semantics;
 240   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
 241 #define REG_NONE (-1)
 242   int regindex;
 243   /* Special info on semantics */
 244   const char *info;
 245 };
 246
 247 /* Two arrays of indexes into the ia64_dependency table.
 248    chks are dependencies to check for conflicts when an opcode is
 249    encountered; regs are dependencies to register (mark as used) when an
 250    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
 251    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
 252    readers (WAR) of a resource.  */
 253 struct ia64_opcode_dependency
 254 {
 255   int nchks;
 256   const unsigned short *chks;
 257   int nregs;
 258   const unsigned short *regs;
 259 };
 260
 261 /* encode/extract the note/index for a dependency */
 262 #define RDEP(N,X) (((N)<<11)|(X))
 263 #define NOTE(X) (((X)>>11)&0x1F)
 264 #define DEP(X) ((X)&0x7FF)
 265
 266 /* A template descriptor describes the execution units that are active
 267    for each of the three slots.  It also specifies the location of
 268    instruction group boundaries that may be present between two slots.  */
 269 struct ia64_templ_desc
 270   {
 271     int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
 272     enum ia64_unit exec_unit[3];
 273     const char *name;
 274   };
 275
 276 /* The opcode table is an array of struct ia64_opcode.  */
 277
 278 struct ia64_opcode
 279   {
 280     /* The opcode name.  */
 281     const char *name;
 282
 283     /* The type of the instruction: */
 284     enum ia64_insn_type type;
 285
 286     /* Number of output operands: */
 287     int num_outputs;
 288
 289     /* The opcode itself.  Those bits which will be filled in with
 290        operands are zeroes.  */
 291     ia64_insn opcode;
 292
 293     /* The opcode mask.  This is used by the disassembler.  This is a
 294        mask containing ones indicating those bits which must match the
 295        opcode field, and zeroes indicating those bits which need not
 296        match (and are presumably filled in by operands).  */
 297     ia64_insn mask;
 298
 299     /* An array of operand codes.  Each code is an index into the
 300        operand table.  They appear in the order which the operands must
 301        appear in assembly code, and are terminated by a zero.  */
 302     enum ia64_opnd operands[5];
 303
 304     /* One bit flags for the opcode.  These are primarily used to
 305        indicate specific processors and environments support the
 306        instructions.  The defined values are listed below. */
 307     unsigned int flags;
 308
 309     /* Used by ia64_find_next_opcode (). */
 310     short ent_index;
 311
 312     /* Opcode dependencies. */
 313     const struct ia64_opcode_dependency *dependencies;
 314   };
 315
 316 /* Values defined for the flags field of a struct ia64_opcode.  */
 317
 318 #define IA64_OPCODE_FIRST       (1<<0)  /* must be first in an insn group */
 319 #define IA64_OPCODE_X_IN_MLX    (1<<1)  /* insn is allowed in X slot of MLX */
 320 #define IA64_OPCODE_LAST        (1<<2)  /* must be last in an insn group */
 321 #define IA64_OPCODE_PRIV        (1<<3)  /* privileged instruct */
 322 #define IA64_OPCODE_SLOT2       (1<<4)  /* insn allowed in slot 2 only */
 323 #define IA64_OPCODE_NO_PRED     (1<<5)  /* insn cannot be predicated */
 324 #define IA64_OPCODE_PSEUDO      (1<<6)  /* insn is a pseudo-op */
 325 #define IA64_OPCODE_F2_EQ_F3    (1<<7)  /* constraint: F2 == F3 */
 326 #define IA64_OPCODE_LEN_EQ_64MCNT       (1<<8)  /* constraint: LEN == 64-CNT */
 327 #define IA64_OPCODE_MOD_RRBS    (1<<9)  /* modifies all rrbs in CFM */
 328 #define IA64_OPCODE_POSTINC     (1<<10) /* postincrement MR3 operand */
 329
 330 /* A macro to extract the major opcode from an instruction.  */
 331 #define IA64_OP(i)      (((i) >> 37) & 0xf)
 332
 333 enum ia64_operand_class
 334   {
 335     IA64_OPND_CLASS_CST,        /* constant */
 336     IA64_OPND_CLASS_REG,        /* register */
 337     IA64_OPND_CLASS_IND,        /* indirect register */
 338     IA64_OPND_CLASS_ABS,        /* absolute value */
 339     IA64_OPND_CLASS_REL,        /* IP-relative value */
 340   };
 341
 342 /* The operands table is an array of struct ia64_operand.  */
 343
 344 struct ia64_operand
 345 {
 346   enum ia64_operand_class class;
 347
 348   /* Set VALUE as the operand bits for the operand of type SELF in the
 349      instruction pointed to by CODE.  If an error occurs, *CODE is not
 350      modified and the returned string describes the cause of the
 351      error.  If no error occurs, NULL is returned.  */
 352   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
 353                          ia64_insn *code);
 354
 355   /* Extract the operand bits for an operand of type SELF from
 356      instruction CODE store them in *VALUE.  If an error occurs, the
 357      cause of the error is described by the string returned.  If no
 358      error occurs, NULL is returned.  */
 359   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
 360                           ia64_insn *value);
 361
 362   /* A string whose meaning depends on the operand class.  */
 363
 364   const char *str;
 365
 366   struct bit_field
 367     {
 368       /* The number of bits in the operand.  */
 369       int bits;
 370
 371       /* How far the operand is left shifted in the instruction.  */
 372       int shift;
 373     }
 374   field[4];             /* no operand has more than this many bit-fields */
 375
 376   unsigned int flags;
 377
 378   const char *desc;     /* brief description */
 379 };
 380
 381 /* Values defined for the flags field of a struct ia64_operand.  */
 382
 383 /* Disassemble as signed decimal (instead of hex): */
 384 #define IA64_OPND_FLAG_DECIMAL_SIGNED   (1<<0)
 385 /* Disassemble as unsigned decimal (instead of hex): */
 386 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
 387
 388 #define NELEMS(a)       ((int) (sizeof (a) / sizeof (a[0])))
 389
 390 static const char*
 391 ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
 392           ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
 393 {
 394   return "internal error---this shouldn't happen";
 395 }
 396
 397 static const char*
 398 ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
 399           ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
 400 {
 401   return "internal error---this shouldn't happen";
 402 }
 403
 404 static const char*
 405 ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
 406            ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
 407 {
 408   return 0;
 409 }
 410
 411 static const char*
 412 ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
 413            ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
 414 {
 415   return 0;
 416 }
 417
 418 static const char*
 419 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 420 {
 421   if (value >= 1u << self->field[0].bits)
 422     return "register number out of range";
 423
 424   *code |= value << self->field[0].shift;
 425   return 0;
 426 }
 427
 428 static const char*
 429 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 430 {
 431   *valuep = ((code >> self->field[0].shift)
 432              & ((1u << self->field[0].bits) - 1));
 433   return 0;
 434 }
 435
 436 static const char*
 437 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 438 {
 439   ia64_insn new = 0;
 440   int i;
 441
 442   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 443     {
 444       new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
 445               << self->field[i].shift);
 446       value >>= self->field[i].bits;
 447     }
 448   if (value)
 449     return "integer operand out of range";
 450
 451   *code |= new;
 452   return 0;
 453 }
 454
 455 static const char*
 456 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 457 {
 458   uint64_t value = 0;
 459   int i, bits = 0, total = 0;
 460
 461   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 462     {
 463       bits = self->field[i].bits;
 464       value |= ((code >> self->field[i].shift)
 465                 & ((((uint64_t) 1) << bits) - 1)) << total;
 466       total += bits;
 467     }
 468   *valuep = value;
 469   return 0;
 470 }
 471
 472 static const char*
 473 ins_immu5b (const struct ia64_operand *self, ia64_insn value,
 474             ia64_insn *code)
 475 {
 476   if (value < 32 || value > 63)
 477     return "value must be between 32 and 63";
 478   return ins_immu (self, value - 32, code);
 479 }
 480
 481 static const char*
 482 ext_immu5b (const struct ia64_operand *self, ia64_insn code,
 483             ia64_insn *valuep)
 484 {
 485   const char *result;
 486
 487   result = ext_immu (self, code, valuep);
 488   if (result)
 489     return result;
 490
 491   *valuep = *valuep + 32;
 492   return 0;
 493 }
 494
 495 static const char*
 496 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 497 {
 498   if (value & 0x7)
 499     return "value not an integer multiple of 8";
 500   return ins_immu (self, value >> 3, code);
 501 }
 502
 503 static const char*
 504 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 505 {
 506   const char *result;
 507
 508   result = ext_immu (self, code, valuep);
 509   if (result)
 510     return result;
 511
 512   *valuep = *valuep << 3;
 513   return 0;
 514 }
 515
 516 static const char*
 517 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
 518                  ia64_insn *code, int scale)
 519 {
 520   int64_t svalue = value, sign_bit = 0;
 521   ia64_insn new = 0;
 522   int i;
 523
 524   svalue >>= scale;
 525
 526   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 527     {
 528       new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
 529               << self->field[i].shift);
 530       sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
 531       svalue >>= self->field[i].bits;
 532     }
 533   if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
 534     return "integer operand out of range";
 535
 536   *code |= new;
 537   return 0;
 538 }
 539
 540 static const char*
 541 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
 542                  ia64_insn *valuep, int scale)
 543 {
 544   int i, bits = 0, total = 0;
 545   int64_t val = 0, sign;
 546
 547   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 548     {
 549       bits = self->field[i].bits;
 550       val |= ((code >> self->field[i].shift)
 551               & ((((uint64_t) 1) << bits) - 1)) << total;
 552       total += bits;
 553     }
 554   /* sign extend: */
 555   sign = (int64_t) 1 << (total - 1);
 556   val = (val ^ sign) - sign;
 557
 558   *valuep = (val << scale);
 559   return 0;
 560 }
 561
 562 static const char*
 563 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 564 {
 565   return ins_imms_scaled (self, value, code, 0);
 566 }
 567
 568 static const char*
 569 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 570 {
 571   value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
 572
 573   return ins_imms_scaled (self, value, code, 0);
 574 }
 575
 576 static const char*
 577 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 578 {
 579   return ext_imms_scaled (self, code, valuep, 0);
 580 }
 581
 582 static const char*
 583 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 584 {
 585   --value;
 586   return ins_imms_scaled (self, value, code, 0);
 587 }
 588
 589 static const char*
 590 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
 591               ia64_insn *code)
 592 {
 593   value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
 594
 595   --value;
 596   return ins_imms_scaled (self, value, code, 0);
 597 }
 598
 599 static const char*
 600 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 601 {
 602   const char *res = ext_imms_scaled (self, code, valuep, 0);
 603
 604   ++*valuep;
 605   return res;
 606 }
 607
 608 static const char*
 609 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 610 {
 611   return ins_imms_scaled (self, value, code, 1);
 612 }
 613
 614 static const char*
 615 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 616 {
 617   return ext_imms_scaled (self, code, valuep, 1);
 618 }
 619
 620 static const char*
 621 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 622 {
 623   return ins_imms_scaled (self, value, code, 4);
 624 }
 625
 626 static const char*
 627 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 628 {
 629   return ext_imms_scaled (self, code, valuep, 4);
 630 }
 631
 632 static const char*
 633 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 634 {
 635   return ins_imms_scaled (self, value, code, 16);
 636 }
 637
 638 static const char*
 639 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 640 {
 641   return ext_imms_scaled (self, code, valuep, 16);
 642 }
 643
 644 static const char*
 645 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 646 {
 647   ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 648   return ins_immu (self, value ^ mask, code);
 649 }
 650
 651 static const char*
 652 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 653 {
 654   const char *result;
 655   ia64_insn mask;
 656
 657   mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 658   result = ext_immu (self, code, valuep);
 659   if (!result)
 660     {
 661       mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 662       *valuep ^= mask;
 663     }
 664   return result;
 665 }
 666
 667 static const char*
 668 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 669 {
 670   --value;
 671   if (value >= ((uint64_t) 1) << self->field[0].bits)
 672     return "count out of range";
 673
 674   *code |= value << self->field[0].shift;
 675   return 0;
 676 }
 677
 678 static const char*
 679 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 680 {
 681   *valuep = ((code >> self->field[0].shift)
 682              & ((((uint64_t) 1) << self->field[0].bits) - 1)) + 1;
 683   return 0;
 684 }
 685
 686 static const char*
 687 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 688 {
 689   --value;
 690
 691   if (value > 2)
 692     return "count must be in range 1..3";
 693
 694   *code |= value << self->field[0].shift;
 695   return 0;
 696 }
 697
 698 static const char*
 699 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 700 {
 701   *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
 702   return 0;
 703 }
 704
 705 static const char*
 706 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 707 {
 708   switch (value)
 709     {
 710     case 0:     value = 0; break;
 711     case 7:     value = 1; break;
 712     case 15:    value = 2; break;
 713     case 16:    value = 3; break;
 714     default:    return "count must be 0, 7, 15, or 16";
 715     }
 716   *code |= value << self->field[0].shift;
 717   return 0;
 718 }
 719
 720 static const char*
 721 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 722 {
 723   ia64_insn value;
 724
 725   value = (code >> self->field[0].shift) & 0x3;
 726   switch (value)
 727     {
 728     case 0: value =  0; break;
 729     case 1: value =  7; break;
 730     case 2: value = 15; break;
 731     case 3: value = 16; break;
 732     }
 733   *valuep = value;
 734   return 0;
 735 }
 736
 737 static const char*
 738 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 739 {
 740   int64_t val = value;
 741   uint64_t sign = 0;
 742
 743   if (val < 0)
 744     {
 745       sign = 0x4;
 746       value = -value;
 747     }
 748   switch (value)
 749     {
 750     case  1:    value = 3; break;
 751     case  4:    value = 2; break;
 752     case  8:    value = 1; break;
 753     case 16:    value = 0; break;
 754     default:    return "count must be +/- 1, 4, 8, or 16";
 755     }
 756   *code |= (sign | value) << self->field[0].shift;
 757   return 0;
 758 }
 759
 760 static const char*
 761 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 762 {
 763   int64_t val;
 764   int negate;
 765
 766   val = (code >> self->field[0].shift) & 0x7;
 767   negate = val & 0x4;
 768   switch (val & 0x3)
 769     {
 770     case 0: val = 16; break;
 771     case 1: val =  8; break;
 772     case 2: val =  4; break;
 773     case 3: val =  1; break;
 774     }
 775   if (negate)
 776     val = -val;
 777
 778   *valuep = val;
 779   return 0;
 780 }
 781
 782 /* glib.h defines ABS so we must undefine it to avoid a clash */
 783 #undef ABS
 784
 785 #define CST     IA64_OPND_CLASS_CST
 786 #define REG     IA64_OPND_CLASS_REG
 787 #define IND     IA64_OPND_CLASS_IND
 788 #define ABS     IA64_OPND_CLASS_ABS
 789 #define REL     IA64_OPND_CLASS_REL
 790
 791 #define SDEC    IA64_OPND_FLAG_DECIMAL_SIGNED
 792 #define UDEC    IA64_OPND_FLAG_DECIMAL_UNSIGNED
 793
 794 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
 795   {
 796     /* constants: */
 797     { CST, ins_const, ext_const, "NIL",         {{ 0, 0}}, 0, "<none>" },
 798     { CST, ins_const, ext_const, "ar.csd",      {{ 0, 0}}, 0, "ar.csd" },
 799     { CST, ins_const, ext_const, "ar.ccv",      {{ 0, 0}}, 0, "ar.ccv" },
 800     { CST, ins_const, ext_const, "ar.pfs",      {{ 0, 0}}, 0, "ar.pfs" },
 801     { CST, ins_const, ext_const, "1",           {{ 0, 0}}, 0, "1" },
 802     { CST, ins_const, ext_const, "8",           {{ 0, 0}}, 0, "8" },
 803     { CST, ins_const, ext_const, "16",          {{ 0, 0}}, 0, "16" },
 804     { CST, ins_const, ext_const, "r0",          {{ 0, 0}}, 0, "r0" },
 805     { CST, ins_const, ext_const, "ip",          {{ 0, 0}}, 0, "ip" },
 806     { CST, ins_const, ext_const, "pr",          {{ 0, 0}}, 0, "pr" },
 807     { CST, ins_const, ext_const, "pr.rot",      {{ 0, 0}}, 0, "pr.rot" },
 808     { CST, ins_const, ext_const, "psr",         {{ 0, 0}}, 0, "psr" },
 809     { CST, ins_const, ext_const, "psr.l",       {{ 0, 0}}, 0, "psr.l" },
 810     { CST, ins_const, ext_const, "psr.um",      {{ 0, 0}}, 0, "psr.um" },
 811
 812     /* register operands: */
 813     { REG, ins_reg,   ext_reg,  "ar", {{ 7, 20}}, 0,            /* AR3 */
 814       "an application register" },
 815     { REG, ins_reg,   ext_reg,   "b", {{ 3,  6}}, 0,            /* B1 */
 816       "a branch register" },
 817     { REG, ins_reg,   ext_reg,   "b", {{ 3, 13}}, 0,            /* B2 */
 818       "a branch register"},
 819     { REG, ins_reg,   ext_reg,  "cr", {{ 7, 20}}, 0,            /* CR */
 820       "a control register"},
 821     { REG, ins_reg,   ext_reg,   "f", {{ 7,  6}}, 0,            /* F1 */
 822       "a floating-point register" },
 823     { REG, ins_reg,   ext_reg,   "f", {{ 7, 13}}, 0,            /* F2 */
 824       "a floating-point register" },
 825     { REG, ins_reg,   ext_reg,   "f", {{ 7, 20}}, 0,            /* F3 */
 826       "a floating-point register" },
 827     { REG, ins_reg,   ext_reg,   "f", {{ 7, 27}}, 0,            /* F4 */
 828       "a floating-point register" },
 829     { REG, ins_reg,   ext_reg,   "p", {{ 6,  6}}, 0,            /* P1 */
 830       "a predicate register" },
 831     { REG, ins_reg,   ext_reg,   "p", {{ 6, 27}}, 0,            /* P2 */
 832       "a predicate register" },
 833     { REG, ins_reg,   ext_reg,   "r", {{ 7,  6}}, 0,            /* R1 */
 834       "a general register" },
 835     { REG, ins_reg,   ext_reg,   "r", {{ 7, 13}}, 0,            /* R2 */
 836       "a general register" },
 837     { REG, ins_reg,   ext_reg,   "r", {{ 7, 20}}, 0,            /* R3 */
 838       "a general register" },
 839     { REG, ins_reg,   ext_reg,   "r", {{ 2, 20}}, 0,            /* R3_2 */
 840       "a general register r0-r3" },
 841
 842     /* memory operands: */
 843     { IND, ins_reg,   ext_reg,  "",      {{7, 20}}, 0,          /* MR3 */
 844       "a memory address" },
 845
 846     /* indirect operands: */
 847     { IND, ins_reg,   ext_reg,  "cpuid", {{7, 20}}, 0,          /* CPUID_R3 */
 848       "a cpuid register" },
 849     { IND, ins_reg,   ext_reg,  "dbr",   {{7, 20}}, 0,          /* DBR_R3 */
 850       "a dbr register" },
 851     { IND, ins_reg,   ext_reg,  "dtr",   {{7, 20}}, 0,          /* DTR_R3 */
 852       "a dtr register" },
 853     { IND, ins_reg,   ext_reg,  "itr",   {{7, 20}}, 0,          /* ITR_R3 */
 854       "an itr register" },
 855     { IND, ins_reg,   ext_reg,  "ibr",   {{7, 20}}, 0,          /* IBR_R3 */
 856       "an ibr register" },
 857     { IND, ins_reg,   ext_reg,  "msr",   {{7, 20}}, 0,          /* MSR_R3 */
 858       "an msr register" },
 859     { IND, ins_reg,   ext_reg,  "pkr",   {{7, 20}}, 0,          /* PKR_R3 */
 860       "a pkr register" },
 861     { IND, ins_reg,   ext_reg,  "pmc",   {{7, 20}}, 0,          /* PMC_R3 */
 862       "a pmc register" },
 863     { IND, ins_reg,   ext_reg,  "pmd",   {{7, 20}}, 0,          /* PMD_R3 */
 864       "a pmd register" },
 865     { IND, ins_reg,   ext_reg,  "rr",    {{7, 20}}, 0,          /* RR_R3 */
 866       "an rr register" },
 867
 868     /* immediate operands: */
 869     { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,          /* CCNT5 */
 870       "a 5-bit count (0-31)" },
 871     { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,          /* CNT2a */
 872       "a 2-bit count (1-4)" },
 873     { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,          /* CNT2b */
 874       "a 2-bit count (1-3)" },
 875     { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,          /* CNT2c */
 876       "a count (0, 7, 15, or 16)" },
 877     { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,           /* CNT5 */
 878       "a 5-bit count (0-31)" },
 879     { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,           /* CNT6 */
 880       "a 6-bit count (0-63)" },
 881     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,           /* CPOS6a */
 882       "a 6-bit bit pos (0-63)" },
 883     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,           /* CPOS6b */
 884       "a 6-bit bit pos (0-63)" },
 885     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,           /* CPOS6c */
 886       "a 6-bit bit pos (0-63)" },
 887     { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,           /* IMM1 */
 888       "a 1-bit integer (-1, 0)" },
 889     { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,           /* IMMU2 */
 890       "a 2-bit unsigned (0-3)" },
 891     { ABS, ins_immu5b,  ext_immu5b,  0, {{ 5, 14}}, UDEC,       /* IMMU5b */
 892       "a 5-bit unsigned (32 + (0-31))" },
 893     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,              /* IMMU7a */
 894       "a 7-bit unsigned (0-127)" },
 895     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,              /* IMMU7b */
 896       "a 7-bit unsigned (0-127)" },
 897     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,           /* SOF */
 898       "a frame size (register count)" },
 899     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,           /* SOL */
 900       "a local register count" },
 901     { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,           /* SOR */
 902       "a rotating register count (integer multiple of 8)" },
 903     { ABS, ins_imms,  ext_imms,  0,                             /* IMM8 */
 904       {{ 7, 13}, { 1, 36}}, SDEC,
 905       "an 8-bit integer (-128-127)" },
 906     { ABS, ins_immsu4,  ext_imms,  0,                           /* IMM8U4 */
 907       {{ 7, 13}, { 1, 36}}, SDEC,
 908       "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
 909     { ABS, ins_immsm1,  ext_immsm1,  0,                         /* IMM8M1 */
 910       {{ 7, 13}, { 1, 36}}, SDEC,
 911       "an 8-bit integer (-127-128)" },
 912     { ABS, ins_immsm1u4,  ext_immsm1,  0,                       /* IMM8M1U4 */
 913       {{ 7, 13}, { 1, 36}}, SDEC,
 914       "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
 915     { ABS, ins_immsm1,  ext_immsm1,  0,                         /* IMM8M1U8 */
 916       {{ 7, 13}, { 1, 36}}, SDEC,
 917       "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
 918     { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,    /* IMMU9 */
 919       "a 9-bit unsigned (0-511)" },
 920     { ABS, ins_imms,  ext_imms,  0,                             /* IMM9a */
 921       {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,
 922       "a 9-bit integer (-256-255)" },
 923     { ABS, ins_imms,  ext_imms, 0,                              /* IMM9b */
 924       {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
 925       "a 9-bit integer (-256-255)" },
 926     { ABS, ins_imms,  ext_imms, 0,                              /* IMM14 */
 927       {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
 928       "a 14-bit integer (-8192-8191)" },
 929     { ABS, ins_imms1, ext_imms1, 0,                             /* IMM17 */
 930       {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
 931       "a 17-bit integer (-65536-65535)" },
 932     { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,    /* IMMU21 */
 933       "a 21-bit unsigned" },
 934     { ABS, ins_imms,  ext_imms,  0,                             /* IMM22 */
 935       {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
 936       "a 22-bit signed integer" },
 937     { ABS, ins_immu,  ext_immu,  0,                             /* IMMU24 */
 938       {{21,  6}, { 2, 31}, { 1, 36}}, 0,
 939       "a 24-bit unsigned" },
 940     { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,    /* IMM44 */
 941       "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
 942     { ABS, ins_rsvd,  ext_rsvd, 0, {{0,  0}}, 0,                /* IMMU62 */
 943       "a 62-bit unsigned" },
 944     { ABS, ins_rsvd,  ext_rsvd, 0, {{0,  0}}, 0,                /* IMMU64 */
 945       "a 64-bit unsigned" },
 946     { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,           /* INC3 */
 947       "an increment (+/- 1, 4, 8, or 16)" },
 948     { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,           /* LEN4 */
 949       "a 4-bit length (1-16)" },
 950     { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,           /* LEN6 */
 951       "a 6-bit length (1-64)" },
 952     { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}}, 0,              /* MBTYPE4 */
 953       "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
 954     { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}}, 0,              /* MBTYPE8 */
 955       "an 8-bit mix type" },
 956     { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,           /* POS6 */
 957       "a 6-bit bit pos (0-63)" },
 958     { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,    /* TAG13 */
 959       "a branch tag" },
 960     { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,              /* TAG13b */
 961       "a branch tag" },
 962     { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,    /* TGT25 */
 963       "a branch target" },
 964     { REL, ins_imms4, ext_imms4, 0,                             /* TGT25b */
 965       {{ 7,  6}, {13, 20}, { 1, 36}}, 0,
 966       "a branch target" },
 967     { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,    /* TGT25c */
 968       "a branch target" },
 969     { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */
 970       "a branch target" },
 971
 972     { ABS, ins_const, ext_const, 0, {{0, 0}}, 0,                /* LDXMOV */
 973       "ldxmov target" },
 974   };
 975
 976
 977 /* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
 978    Copyright 1999, 2000 Free Software Foundation, Inc.
 979    Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
 980
 981    This file is part of GDB, GAS, and the GNU binutils.
 982
 983    GDB, GAS, and the GNU binutils are free software; you can redistribute
 984    them and/or modify them under the terms of the GNU General Public
 985    License as published by the Free Software Foundation; either version
 986    2, or (at your option) any later version.
 987
 988    GDB, GAS, and the GNU binutils are distributed in the hope that they
 989    will be useful, but WITHOUT ANY WARRANTY; without even the implied
 990    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
 991    the GNU General Public License for more details.
 992
 993    You should have received a copy of the GNU General Public License
 994    along with this file; see the file COPYING.  If not, see
 995    <http://www.gnu.org/licenses/>. */
 996
 997 /* The primary opcode table is made up of the following: */
 998 struct ia64_main_table
 999 {
1000   /* The entry in the string table that corresponds to the name of this
1001      opcode. */
1002   unsigned short name_index;
1003
1004   /* The type of opcode; corresponds to the TYPE field in
1005      struct ia64_opcode. */
1006   unsigned char opcode_type;
1007
1008   /* The number of outputs for this opcode. */
1009   unsigned char num_outputs;
1010
1011   /* The base insn value for this opcode.  It may be modified by completers. */
1012   ia64_insn opcode;
1013
1014   /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
1015   ia64_insn mask;
1016
1017   /* The operands of this instruction.  Corresponds to the OPERANDS field
1018      in struct ia64_opcode. */
1019   unsigned char operands[5];
1020
1021   /* The flags for this instruction.  Corresponds to the FLAGS field in
1022      struct ia64_opcode. */
1023   short flags;
1024
1025   /* The tree of completers for this instruction; this is an offset into
1026      completer_table. */
1027   short completers;
1028 };
1029
1030 /* Each instruction has a set of possible "completers", or additional
1031    suffixes that can alter the instruction's behavior, and which has
1032    potentially different dependencies.
1033
1034    The completer entries modify certain bits in the instruction opcode.
1035    Which bits are to be modified are marked by the BITS, MASK and
1036    OFFSET fields.  The completer entry may also note dependencies for the
1037    opcode.
1038
1039    These completers are arranged in a DAG; the pointers are indexes
1040    into the completer_table array.  The completer DAG is searched by
1041    find_completer () and ia64_find_matching_opcode ().
1042
1043    Note that each completer needs to be applied in turn, so that if we
1044    have the instruction
1045         cmp.lt.unc
1046    the completer entries for both "lt" and "unc" would need to be applied
1047    to the opcode's value.
1048
1049    Some instructions do not require any completers; these contain an
1050    empty completer entry.  Instructions that require a completer do
1051    not contain an empty entry.
1052
1053    Terminal completers (those completers that validly complete an
1054    instruction) are marked by having the TERMINAL_COMPLETER flag set.
1055
1056    Only dependencies listed in the terminal completer for an opcode are
1057    considered to apply to that opcode instance. */
1058
1059 struct ia64_completer_table
1060 {
1061   /* The bit value that this completer sets. */
1062   unsigned int bits;
1063
1064   /* And its mask. 1s are bits that are to be modified in the
1065      instruction. */
1066   unsigned int mask;
1067
1068   /* The entry in the string table that corresponds to the name of this
1069      completer. */
1070   unsigned short name_index;
1071
1072   /* An alternative completer, or -1 if this is the end of the chain. */
1073   short alternative;
1074
1075   /* A pointer to the DAG of completers that can potentially follow
1076      this one, or -1. */
1077   short subentries;
1078
1079   /* The bit offset in the instruction where BITS and MASK should be
1080      applied. */
1081   unsigned char offset : 7;
1082
1083   unsigned char terminal_completer : 1;
1084
1085   /* Index into the dependency list table */
1086   short dependencies;
1087 };
1088
1089 /* This contains sufficient information for the disassembler to resolve
1090    the complete name of the original instruction.  */
1091 struct ia64_dis_names
1092 {
1093   /* COMPLETER_INDEX represents the tree of completers that make up
1094      the instruction.  The LSB represents the top of the tree for the
1095      specified instruction.
1096
1097      A 0 bit indicates to go to the next alternate completer via the
1098      alternative field; a 1 bit indicates that the current completer
1099      is part of the instruction, and to go down the subentries index.
1100      We know we've reached the final completer when we run out of 1
1101      bits.
1102
1103      There is always at least one 1 bit. */
1104   unsigned int completer_index : 20;
1105
1106   /* The index in the main_table[] array for the instruction. */
1107   unsigned short insn_index : 11;
1108
1109   /* If set, the next entry in this table is an alternate possibility
1110      for this instruction encoding.  Which one to use is determined by
1111      the instruction type and other factors (see opcode_verify ()).  */
1112   unsigned int next_flag : 1;
1113
1114   /* The disassembly priority of this entry among instructions. */
1115   unsigned short priority;
1116 };
1117
1118 static const char * const ia64_strings[] = {
1119   "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
1120   "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
1121   "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16",
1122   "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop",
1123   "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl",
1124   "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand",
1125   "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt",
1126   "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax",
1127   "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma",
1128   "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp",
1129   "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg",
1130   "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta",
1131   "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu",
1132   "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia",
1133   "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8",
1134   "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le",
1135   "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many",
1136   "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne",
1137   "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1",
1138   "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1",
1139   "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1",
1140   "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2",
1141   "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2",
1142   "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz",
1143   "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3",
1144   "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig",
1145   "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2",
1146   "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1",
1147   "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa",
1148   "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4",
1149   "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2",
1150   "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2",
1151   "zxt4",
1152 };
1153
1154 static const struct ia64_dependency
1155 dependencies[] = {
1156   { "ALAT", 0, 0, 0, -1, NULL, },
1157   { "AR[BSP]", 26, 0, 2, 17, NULL, },
1158   { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },
1159   { "AR[CCV]", 26, 0, 2, 32, NULL, },
1160   { "AR[CFLG]", 26, 0, 2, 27, NULL, },
1161   { "AR[CSD]", 26, 0, 2, 25, NULL, },
1162   { "AR[EC]", 26, 0, 2, 66, NULL, },
1163   { "AR[EFLAG]", 26, 0, 2, 24, NULL, },
1164   { "AR[FCR]", 26, 0, 2, 21, NULL, },
1165   { "AR[FDR]", 26, 0, 2, 30, NULL, },
1166   { "AR[FIR]", 26, 0, 2, 29, NULL, },
1167   { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },
1168   { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },
1169   { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },
1170   { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },
1171   { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },
1172   { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },
1173   { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },
1174   { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },
1175   { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },
1176   { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },
1177   { "AR[FSR]", 26, 0, 2, 28, NULL, },
1178   { "AR[ITC]", 26, 0, 2, 44, NULL, },
1179   { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },
1180   { "AR[LC]", 26, 0, 2, 65, NULL, },
1181   { "AR[PFS]", 26, 0, 2, 64, NULL, },
1182   { "AR[PFS]", 26, 0, 2, 64, NULL, },
1183   { "AR[PFS]", 26, 0, 0, 64, NULL, },
1184   { "AR[RNAT]", 26, 0, 2, 19, NULL, },
1185   { "AR[RSC]", 26, 0, 2, 16, NULL, },
1186   { "AR[SSD]", 26, 0, 2, 26, NULL, },
1187   { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },
1188   { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },
1189   { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },
1190   { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
1191   { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },
1192   { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
1193   { "CFM", 6, 0, 2, -1, NULL, },
1194   { "CFM", 6, 0, 2, -1, NULL, },
1195   { "CFM", 6, 0, 2, -1, NULL, },
1196   { "CFM", 6, 0, 2, -1, NULL, },
1197   { "CFM", 6, 0, 0, -1, NULL, },
1198   { "CPUID#", 7, 0, 5, -1, NULL, },
1199   { "CR[CMCV]", 27, 0, 3, 74, NULL, },
1200   { "CR[DCR]", 27, 0, 3, 0, NULL, },
1201   { "CR[EOI]", 27, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", },
1202   { "CR[GPTA]", 27, 0, 3, 9, NULL, },
1203   { "CR[IFA]", 27, 0, 1, 20, NULL, },
1204   { "CR[IFA]", 27, 0, 3, 20, NULL, },
1205   { "CR[IFS]", 27, 0, 3, 23, NULL, },
1206   { "CR[IFS]", 27, 0, 1, 23, NULL, },
1207   { "CR[IFS]", 27, 0, 1, 23, NULL, },
1208   { "CR[IHA]", 27, 0, 3, 25, NULL, },
1209   { "CR[IIM]", 27, 0, 3, 24, NULL, },
1210   { "CR[IIP]", 27, 0, 3, 19, NULL, },
1211   { "CR[IIP]", 27, 0, 1, 19, NULL, },
1212   { "CR[IIPA]", 27, 0, 3, 22, NULL, },
1213   { "CR[IPSR]", 27, 0, 3, 16, NULL, },
1214   { "CR[IPSR]", 27, 0, 1, 16, NULL, },
1215   { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, },
1216   { "CR[ISR]", 27, 0, 3, 17, NULL, },
1217   { "CR[ITIR]", 27, 0, 3, 21, NULL, },
1218   { "CR[ITIR]", 27, 0, 1, 21, NULL, },
1219   { "CR[ITM]", 27, 0, 3, 1, NULL, },
1220   { "CR[ITV]", 27, 0, 3, 72, NULL, },
1221   { "CR[IVA]", 27, 0, 4, 2, NULL, },
1222   { "CR[IVR]", 27, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR Ð CR65)\" on page 2:118", },
1223   { "CR[LID]", 27, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID Ð CR64)\" on page 2:117", },
1224   { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, },
1225   { "CR[PMV]", 27, 0, 3, 73, NULL, },
1226   { "CR[PTA]", 27, 0, 3, 8, NULL, },
1227   { "CR[TPR]", 27, 0, 3, 66, NULL, },
1228   { "CR[TPR]", 27, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR Ð CR66)\" on page 2:119", },
1229   { "CR[TPR]", 27, 0, 1, 66, NULL, },
1230   { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, },
1231   { "DBR#", 11, 0, 2, -1, NULL, },
1232   { "DBR#", 11, 0, 3, -1, NULL, },
1233   { "DTC", 0, 0, 3, -1, NULL, },
1234   { "DTC", 0, 0, 2, -1, NULL, },
1235   { "DTC", 0, 0, 0, -1, NULL, },
1236   { "DTC", 0, 0, 2, -1, NULL, },
1237   { "DTC_LIMIT*", 0, 0, 2, -1, NULL, },
1238   { "DTR", 0, 0, 3, -1, NULL, },
1239   { "DTR", 0, 0, 2, -1, NULL, },
1240   { "DTR", 0, 0, 3, -1, NULL, },
1241   { "DTR", 0, 0, 0, -1, NULL, },
1242   { "DTR", 0, 0, 2, -1, NULL, },
1243   { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, },
1244   { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, },
1245   { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, },
1246   { "GR0", 14, 0, 0, -1, NULL, },
1247   { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, },
1248   { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, },
1249   { "IBR#", 16, 0, 2, -1, NULL, },
1250   { "InService*", 17, 0, 3, -1, NULL, },
1251   { "InService*", 17, 0, 2, -1, NULL, },
1252   { "InService*", 17, 0, 2, -1, NULL, },
1253   { "IP", 0, 0, 0, -1, NULL, },
1254   { "ITC", 0, 0, 4, -1, NULL, },
1255   { "ITC", 0, 0, 2, -1, NULL, },
1256   { "ITC", 0, 0, 0, -1, NULL, },
1257   { "ITC", 0, 0, 4, -1, NULL, },
1258   { "ITC", 0, 0, 2, -1, NULL, },
1259   { "ITC_LIMIT*", 0, 0, 2, -1, NULL, },
1260   { "ITR", 0, 0, 2, -1, NULL, },
1261   { "ITR", 0, 0, 4, -1, NULL, },
1262   { "ITR", 0, 0, 2, -1, NULL, },
1263   { "ITR", 0, 0, 0, -1, NULL, },
1264   { "ITR", 0, 0, 4, -1, NULL, },
1265   { "memory", 0, 0, 0, -1, NULL, },
1266   { "MSR#", 18, 0, 5, -1, NULL, },
1267   { "PKR#", 19, 0, 3, -1, NULL, },
1268   { "PKR#", 19, 0, 0, -1, NULL, },
1269   { "PKR#", 19, 0, 2, -1, NULL, },
1270   { "PKR#", 19, 0, 2, -1, NULL, },
1271   { "PMC#", 20, 0, 2, -1, NULL, },
1272   { "PMC#", 20, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", },
1273   { "PMD#", 21, 0, 2, -1, NULL, },
1274   { "PR0", 0, 0, 0, -1, NULL, },
1275   { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
1276   { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
1277   { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, },
1278   { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
1279   { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
1280   { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, },
1281   { "PR63", 24, 0, 2, -1, NULL, },
1282   { "PR63", 24, 0, 2, -1, NULL, },
1283   { "PR63", 24, 0, 0, -1, NULL, },
1284   { "PSR.ac", 28, 0, 1, 3, NULL, },
1285   { "PSR.ac", 28, 0, 3, 3, NULL, },
1286   { "PSR.ac", 28, 0, 2, 3, NULL, },
1287   { "PSR.ac", 28, 0, 2, 3, NULL, },
1288   { "PSR.be", 28, 0, 1, 1, NULL, },
1289   { "PSR.be", 28, 0, 3, 1, NULL, },
1290   { "PSR.be", 28, 0, 2, 1, NULL, },
1291   { "PSR.be", 28, 0, 2, 1, NULL, },
1292   { "PSR.bn", 28, 0, 2, 44, NULL, },
1293   { "PSR.cpl", 28, 0, 1, 32, NULL, },
1294   { "PSR.cpl", 28, 0, 2, 32, NULL, },
1295   { "PSR.da", 28, 0, 2, 38, NULL, },
1296   { "PSR.db", 28, 0, 3, 24, NULL, },
1297   { "PSR.db", 28, 0, 2, 24, NULL, },
1298   { "PSR.db", 28, 0, 2, 24, NULL, },
1299   { "PSR.dd", 28, 0, 2, 39, NULL, },
1300   { "PSR.dfh", 28, 0, 3, 19, NULL, },
1301   { "PSR.dfh", 28, 0, 2, 19, NULL, },
1302   { "PSR.dfh", 28, 0, 2, 19, NULL, },
1303   { "PSR.dfl", 28, 0, 3, 18, NULL, },
1304   { "PSR.dfl", 28, 0, 2, 18, NULL, },
1305   { "PSR.dfl", 28, 0, 2, 18, NULL, },
1306   { "PSR.di", 28, 0, 3, 22, NULL, },
1307   { "PSR.di", 28, 0, 2, 22, NULL, },
1308   { "PSR.di", 28, 0, 2, 22, NULL, },
1309   { "PSR.dt", 28, 0, 3, 17, NULL, },
1310   { "PSR.dt", 28, 0, 2, 17, NULL, },
1311   { "PSR.dt", 28, 0, 2, 17, NULL, },
1312   { "PSR.ed", 28, 0, 2, 43, NULL, },
1313   { "PSR.i", 28, 0, 2, 14, NULL, },
1314   { "PSR.ia", 28, 0, 0, 14, NULL, },
1315   { "PSR.ic", 28, 0, 2, 13, NULL, },
1316   { "PSR.ic", 28, 0, 3, 13, NULL, },
1317   { "PSR.ic", 28, 0, 2, 13, NULL, },
1318   { "PSR.id", 28, 0, 0, 14, NULL, },
1319   { "PSR.is", 28, 0, 0, 14, NULL, },
1320   { "PSR.it", 28, 0, 2, 14, NULL, },
1321   { "PSR.lp", 28, 0, 2, 25, NULL, },
1322   { "PSR.lp", 28, 0, 3, 25, NULL, },
1323   { "PSR.lp", 28, 0, 2, 25, NULL, },
1324   { "PSR.mc", 28, 0, 2, 35, NULL, },
1325   { "PSR.mfh", 28, 0, 2, 5, NULL, },
1326   { "PSR.mfl", 28, 0, 2, 4, NULL, },
1327   { "PSR.pk", 28, 0, 3, 15, NULL, },
1328   { "PSR.pk", 28, 0, 2, 15, NULL, },
1329   { "PSR.pk", 28, 0, 2, 15, NULL, },
1330   { "PSR.pp", 28, 0, 2, 21, NULL, },
1331   { "PSR.ri", 28, 0, 0, 41, NULL, },
1332   { "PSR.rt", 28, 0, 2, 27, NULL, },
1333   { "PSR.rt", 28, 0, 3, 27, NULL, },
1334   { "PSR.rt", 28, 0, 2, 27, NULL, },
1335   { "PSR.si", 28, 0, 2, 23, NULL, },
1336   { "PSR.si", 28, 0, 3, 23, NULL, },
1337   { "PSR.si", 28, 0, 2, 23, NULL, },
1338   { "PSR.sp", 28, 0, 2, 20, NULL, },
1339   { "PSR.sp", 28, 0, 3, 20, NULL, },
1340   { "PSR.sp", 28, 0, 2, 20, NULL, },
1341   { "PSR.ss", 28, 0, 2, 40, NULL, },
1342   { "PSR.tb", 28, 0, 3, 26, NULL, },
1343   { "PSR.tb", 28, 0, 2, 26, NULL, },
1344   { "PSR.tb", 28, 0, 2, 26, NULL, },
1345   { "PSR.up", 28, 0, 2, 2, NULL, },
1346   { "PSR.vm", 28, 0, 1, 46, NULL, },
1347   { "PSR.vm", 28, 0, 2, 46, NULL, },
1348   { "RR#", 25, 0, 3, -1, NULL, },
1349   { "RR#", 25, 0, 2, -1, NULL, },
1350   { "RSE", 29, 0, 2, -1, NULL, },
1351   { "ALAT", 0, 1, 0, -1, NULL, },
1352   { "AR[BSP]", 26, 1, 2, 17, NULL, },
1353   { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, },
1354   { "AR[CCV]", 26, 1, 2, 32, NULL, },
1355   { "AR[CFLG]", 26, 1, 2, 27, NULL, },
1356   { "AR[CSD]", 26, 1, 2, 25, NULL, },
1357   { "AR[EC]", 26, 1, 2, 66, NULL, },
1358   { "AR[EFLAG]", 26, 1, 2, 24, NULL, },
1359   { "AR[FCR]", 26, 1, 2, 21, NULL, },
1360   { "AR[FDR]", 26, 1, 2, 30, NULL, },
1361   { "AR[FIR]", 26, 1, 2, 29, NULL, },
1362   { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, },
1363   { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, },
1364   { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, },
1365   { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, },
1366   { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, },
1367   { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
1368   { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
1369   { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, },
1370   { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
1371   { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
1372   { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, },
1373   { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
1374   { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
1375   { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, },
1376   { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
1377   { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
1378   { "AR[FPSR].rv", 30, 1, 2, -1, NULL, },
1379   { "AR[FPSR].traps", 30, 1, 2, -1, NULL, },
1380   { "AR[FSR]", 26, 1, 2, 28, NULL, },
1381   { "AR[ITC]", 26, 1, 2, 44, NULL, },
1382   { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, },
1383   { "AR[LC]", 26, 1, 2, 65, NULL, },
1384   { "AR[PFS]", 26, 1, 0, 64, NULL, },
1385   { "AR[PFS]", 26, 1, 2, 64, NULL, },
1386   { "AR[PFS]", 26, 1, 2, 64, NULL, },
1387   { "AR[RNAT]", 26, 1, 2, 19, NULL, },
1388   { "AR[RSC]", 26, 1, 2, 16, NULL, },
1389   { "AR[SSD]", 26, 1, 2, 26, NULL, },
1390   { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, },
1391   { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, },
1392   { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, },
1393   { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
1394   { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
1395   { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
1396   { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, },
1397   { "CFM", 6, 1, 2, -1, NULL, },
1398   { "CPUID#", 7, 1, 0, -1, NULL, },
1399   { "CR[CMCV]", 27, 1, 2, 74, NULL, },
1400   { "CR[DCR]", 27, 1, 2, 0, NULL, },
1401   { "CR[EOI]", 27, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", },
1402   { "CR[GPTA]", 27, 1, 2, 9, NULL, },
1403   { "CR[IFA]", 27, 1, 2, 20, NULL, },
1404   { "CR[IFS]", 27, 1, 2, 23, NULL, },
1405   { "CR[IHA]", 27, 1, 2, 25, NULL, },
1406   { "CR[IIM]", 27, 1, 2, 24, NULL, },
1407   { "CR[IIP]", 27, 1, 2, 19, NULL, },
1408   { "CR[IIPA]", 27, 1, 2, 22, NULL, },
1409   { "CR[IPSR]", 27, 1, 2, 16, NULL, },
1410   { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, },
1411   { "CR[ISR]", 27, 1, 2, 17, NULL, },
1412   { "CR[ITIR]", 27, 1, 2, 21, NULL, },
1413   { "CR[ITM]", 27, 1, 2, 1, NULL, },
1414   { "CR[ITV]", 27, 1, 2, 72, NULL, },
1415   { "CR[IVA]", 27, 1, 2, 2, NULL, },
1416   { "CR[IVR]", 27, 1, 7, 65, "SC", },
1417   { "CR[LID]", 27, 1, 7, 64, "SC", },
1418   { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, },
1419   { "CR[PMV]", 27, 1, 2, 73, NULL, },
1420   { "CR[PTA]", 27, 1, 2, 8, NULL, },
1421   { "CR[TPR]", 27, 1, 2, 66, NULL, },
1422   { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, },
1423   { "DBR#", 11, 1, 2, -1, NULL, },
1424   { "DTC", 0, 1, 0, -1, NULL, },
1425   { "DTC", 0, 1, 2, -1, NULL, },
1426   { "DTC", 0, 1, 2, -1, NULL, },
1427   { "DTC_LIMIT*", 0, 1, 2, -1, NULL, },
1428   { "DTR", 0, 1, 2, -1, NULL, },
1429   { "DTR", 0, 1, 2, -1, NULL, },
1430   { "DTR", 0, 1, 2, -1, NULL, },
1431   { "DTR", 0, 1, 0, -1, NULL, },
1432   { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, },
1433   { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, },
1434   { "GR0", 14, 1, 0, -1, NULL, },
1435   { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, },
1436   { "IBR#", 16, 1, 2, -1, NULL, },
1437   { "InService*", 17, 1, 7, -1, "SC", },
1438   { "IP", 0, 1, 0, -1, NULL, },
1439   { "ITC", 0, 1, 0, -1, NULL, },
1440   { "ITC", 0, 1, 2, -1, NULL, },
1441   { "ITC", 0, 1, 2, -1, NULL, },
1442   { "ITR", 0, 1, 2, -1, NULL, },
1443   { "ITR", 0, 1, 2, -1, NULL, },
1444   { "ITR", 0, 1, 0, -1, NULL, },
1445   { "memory", 0, 1, 0, -1, NULL, },
1446   { "MSR#", 18, 1, 7, -1, "SC", },
1447   { "PKR#", 19, 1, 0, -1, NULL, },
1448   { "PKR#", 19, 1, 0, -1, NULL, },
1449   { "PKR#", 19, 1, 2, -1, NULL, },
1450   { "PMC#", 20, 1, 2, -1, NULL, },
1451   { "PMD#", 21, 1, 2, -1, NULL, },
1452   { "PR0", 0, 1, 0, -1, NULL, },
1453   { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
1454   { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
1455   { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
1456   { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
1457   { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
1458   { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
1459   { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
1460   { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
1461   { "PR63", 24, 1, 0, -1, NULL, },
1462   { "PR63", 24, 1, 0, -1, NULL, },
1463   { "PR63", 24, 1, 2, -1, NULL, },
1464   { "PR63", 24, 1, 2, -1, NULL, },
1465   { "PSR.ac", 28, 1, 2, 3, NULL, },
1466   { "PSR.be", 28, 1, 2, 1, NULL, },
1467   { "PSR.bn", 28, 1, 2, 44, NULL, },
1468   { "PSR.cpl", 28, 1, 2, 32, NULL, },
1469   { "PSR.da", 28, 1, 2, 38, NULL, },
1470   { "PSR.db", 28, 1, 2, 24, NULL, },
1471   { "PSR.dd", 28, 1, 2, 39, NULL, },
1472   { "PSR.dfh", 28, 1, 2, 19, NULL, },
1473   { "PSR.dfl", 28, 1, 2, 18, NULL, },
1474   { "PSR.di", 28, 1, 2, 22, NULL, },
1475   { "PSR.dt", 28, 1, 2, 17, NULL, },
1476   { "PSR.ed", 28, 1, 2, 43, NULL, },
1477   { "PSR.i", 28, 1, 2, 14, NULL, },
1478   { "PSR.ia", 28, 1, 2, 14, NULL, },
1479   { "PSR.ic", 28, 1, 2, 13, NULL, },
1480   { "PSR.id", 28, 1, 2, 14, NULL, },
1481   { "PSR.is", 28, 1, 2, 14, NULL, },
1482   { "PSR.it", 28, 1, 2, 14, NULL, },
1483   { "PSR.lp", 28, 1, 2, 25, NULL, },
1484   { "PSR.mc", 28, 1, 2, 35, NULL, },
1485   { "PSR.mfh", 28, 1, 0, 5, NULL, },
1486   { "PSR.mfh", 28, 1, 2, 5, NULL, },
1487   { "PSR.mfh", 28, 1, 2, 5, NULL, },
1488   { "PSR.mfl", 28, 1, 0, 4, NULL, },
1489   { "PSR.mfl", 28, 1, 2, 4, NULL, },
1490   { "PSR.mfl", 28, 1, 2, 4, NULL, },
1491   { "PSR.pk", 28, 1, 2, 15, NULL, },
1492   { "PSR.pp", 28, 1, 2, 21, NULL, },
1493   { "PSR.ri", 28, 1, 2, 41, NULL, },
1494   { "PSR.rt", 28, 1, 2, 27, NULL, },
1495   { "PSR.si", 28, 1, 2, 23, NULL, },
1496   { "PSR.sp", 28, 1, 2, 20, NULL, },
1497   { "PSR.ss", 28, 1, 2, 40, NULL, },
1498   { "PSR.tb", 28, 1, 2, 26, NULL, },
1499   { "PSR.up", 28, 1, 2, 2, NULL, },
1500   { "PSR.vm", 28, 1, 2, 46, NULL, },
1501   { "RR#", 25, 1, 2, -1, NULL, },
1502   { "RSE", 29, 1, 2, -1, NULL, },
1503   { "PR63", 24, 2, 6, -1, NULL, },
1504 };
1505
1506 static const unsigned short dep0[] = {
1507   97, 282, 2140, 2327,
1508 };
1509
1510 static const unsigned short dep1[] = {
1511   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1512   2327, 4135, 20616,
1513 };
1514
1515 static const unsigned short dep2[] = {
1516   97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2347, 2348, 2351,
1517   2352, 2355, 2356,
1518 };
1519
1520 static const unsigned short dep3[] = {
1521   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1522   2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 20616,
1523 };
1524
1525 static const unsigned short dep4[] = {
1526   97, 282, 22646, 22647, 22649, 22650, 22652, 22653, 22655, 22824, 22827, 22828,
1527   22831, 22832, 22835, 22836,
1528 };
1529
1530 static const unsigned short dep5[] = {
1531   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1532   4135, 20616, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1533 };
1534
1535 static const unsigned short dep6[] = {
1536   97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2347, 2349,
1537   2351, 2353, 2355,
1538 };
1539
1540 static const unsigned short dep7[] = {
1541   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1542   2344, 2345, 2348, 2349, 2352, 2353, 2356, 4135, 20616,
1543 };
1544
1545 static const unsigned short dep8[] = {
1546   97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2346, 2348, 2350,
1547   2352, 2354, 2356,
1548 };
1549
1550 static const unsigned short dep9[] = {
1551   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1552   2344, 2346, 2347, 2350, 2351, 2354, 2355, 4135, 20616,
1553 };
1554
1555 static const unsigned short dep10[] = {
1556   97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2346, 2347,
1557   2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356,
1558 };
1559
1560 static const unsigned short dep11[] = {
1561   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
1562   2344, 2345, 2346, 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356,
1563   4135, 20616,
1564 };
1565
1566 static const unsigned short dep12[] = {
1567   97, 282, 2395,
1568 };
1569
1570 static const unsigned short dep13[] = {
1571   40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2082, 2083, 2166, 2168,
1572   2169, 2171, 2172, 2174, 2175, 4135,
1573 };
1574
1575 static const unsigned short dep14[] = {
1576   97, 163, 282, 325, 2395, 28866, 29018,
1577 };
1578
1579 static const unsigned short dep15[] = {
1580   1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
1581   22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 40, 41, 97, 150, 152, 158, 162,
1582   164, 175, 185, 186, 188, 282, 325, 2082, 2083, 2166, 2168, 2169, 2171, 2172,
1583   2174, 2175, 4135, 28866, 29018,
1584 };
1585
1586 static const unsigned short dep16[] = {
1587   1, 6, 40, 97, 137, 196, 201, 241, 282, 312, 2395, 28866, 29018,
1588 };
1589
1590 static const unsigned short dep17[] = {
1591   1, 25, 27, 38, 40, 41, 97, 158, 162, 164, 166, 167, 175, 185, 186, 188, 196,
1592   201, 241, 282, 312, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175,
1593   4135, 28866, 29018,
1594 };
1595
1596 static const unsigned short dep18[] = {
1597   1, 40, 51, 97, 196, 241, 248, 282, 28866, 29018,
1598 };
1599
1600 static const unsigned short dep19[] = {
1601   1, 38, 40, 41, 97, 158, 160, 161, 162, 175, 185, 190, 191, 196, 241, 248,
1602   282, 4135, 28866, 29018,
1603 };
1604
1605 static const unsigned short dep20[] = {
1606   40, 97, 241, 282,
1607 };
1608
1609 static const unsigned short dep21[] = {
1610   97, 158, 162, 175, 185, 241, 282,
1611 };
1612
1613 static const unsigned short dep22[] = {
1614   1, 40, 97, 131, 135, 136, 138, 139, 142, 143, 146, 149, 152, 155, 156, 157,
1615   158, 161, 162, 163, 164, 167, 168, 169, 170, 173, 174, 175, 178, 181, 184,
1616   185, 188, 189, 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316,
1617   317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333,
1618   334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 28866, 29018,
1619 };
1620
1621 static const unsigned short dep23[] = {
1622   1, 38, 40, 41, 50, 51, 55, 58, 73, 97, 137, 138, 158, 162, 175, 185, 190,
1623   191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319,
1624   320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333, 334, 335, 336,
1625   337, 338, 339, 340, 341, 342, 343, 344, 4135, 28866, 29018,
1626 };
1627
1628 static const unsigned short dep24[] = {
1629   97, 136, 282, 311,
1630 };
1631
1632 static const unsigned short dep25[] = {
1633   97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 311,
1634 };
1635
1636 static const unsigned short dep26[] = {
1637   97, 137, 282, 312,
1638 };
1639
1640 static const unsigned short dep27[] = {
1641   25, 26, 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 312,
1642
1643 };
1644
1645 static const unsigned short dep28[] = {
1646   97, 190, 282, 344,
1647 };
1648
1649 static const unsigned short dep29[] = {
1650   97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 344,
1651 };
1652
1653 static const unsigned short dep30[] = {
1654   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175,
1655   4135,
1656 };
1657
1658 static const unsigned short dep31[] = {
1659   1, 25, 40, 97, 196, 228, 229, 241, 282, 2082, 2285, 2288, 2395, 28866, 29018,
1660
1661 };
1662
1663 static const unsigned short dep32[] = {
1664   1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228,
1665   230, 241, 282, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286,
1666   2288, 4135, 28866, 29018,
1667 };
1668
1669 static const unsigned short dep33[] = {
1670   97, 282,
1671 };
1672
1673 static const unsigned short dep34[] = {
1674   97, 158, 162, 175, 185, 282, 2082, 2084,
1675 };
1676
1677 static const unsigned short dep35[] = {
1678   40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2168, 2169, 2171,
1679   2172, 2174, 2175, 4135,
1680 };
1681
1682 static const unsigned short dep36[] = {
1683   6, 37, 38, 39, 97, 125, 126, 201, 241, 282, 307, 308, 2395,
1684 };
1685
1686 static const unsigned short dep37[] = {
1687   6, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 241, 282, 307,
1688   308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135,
1689 };
1690
1691 static const unsigned short dep38[] = {
1692   24, 97, 227, 282, 2395,
1693 };
1694
1695 static const unsigned short dep39[] = {
1696   24, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 227, 282, 2166, 2168, 2169,
1697   2171, 2172, 2174, 2175, 4135,
1698 };
1699
1700 static const unsigned short dep40[] = {
1701   6, 24, 37, 38, 39, 97, 125, 126, 201, 227, 241, 282, 307, 308, 2395,
1702 };
1703
1704 static const unsigned short dep41[] = {
1705   6, 24, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 227, 241, 282,
1706   307, 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135,
1707 };
1708
1709 static const unsigned short dep42[] = {
1710   1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228,
1711   230, 241, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286, 2288, 4135,
1712   28866, 29018,
1713 };
1714
1715 static const unsigned short dep43[] = {
1716   97, 158, 162, 175, 185, 282,
1717 };
1718
1719 static const unsigned short dep44[] = {
1720   15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1721   22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1722   22832, 22835, 22836,
1723 };
1724
1725 static const unsigned short dep45[] = {
1726   11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
1727   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1728   18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1729 };
1730
1731 static const unsigned short dep46[] = {
1732   15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325,
1733   18601, 18602, 18761, 18762, 18764, 18765, 22646, 22647, 22648, 22650, 22651,
1734   22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1735 };
1736
1737 static const unsigned short dep47[] = {
1738   11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
1739   216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135,
1740   16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 22824, 22827, 22828,
1741   22831, 22832, 22835, 22836,
1742 };
1743
1744 static const unsigned short dep48[] = {
1745   16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1746   22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1747   22832, 22835, 22836,
1748 };
1749
1750 static const unsigned short dep49[] = {
1751   12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
1752   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1753   18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1754 };
1755
1756 static const unsigned short dep50[] = {
1757   17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1758   22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1759   22832, 22835, 22836,
1760 };
1761
1762 static const unsigned short dep51[] = {
1763   13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
1764   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1765   18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1766 };
1767
1768 static const unsigned short dep52[] = {
1769   18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1770   22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831,
1771   22832, 22835, 22836,
1772 };
1773
1774 static const unsigned short dep53[] = {
1775   14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
1776   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1777   18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
1778 };
1779
1780 static const unsigned short dep54[] = {
1781   15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1782
1783 };
1784
1785 static const unsigned short dep55[] = {
1786   11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
1787   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1788   18764, 18766,
1789 };
1790
1791 static const unsigned short dep56[] = {
1792   15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325,
1793   18601, 18602, 18761, 18762, 18764, 18765,
1794 };
1795
1796 static const unsigned short dep57[] = {
1797   11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
1798   216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135,
1799   16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766,
1800 };
1801
1802 static const unsigned short dep58[] = {
1803   16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1804
1805 };
1806
1807 static const unsigned short dep59[] = {
1808   12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
1809   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1810   18764, 18766,
1811 };
1812
1813 static const unsigned short dep60[] = {
1814   17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1815
1816 };
1817
1818 static const unsigned short dep61[] = {
1819   13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
1820   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1821   18764, 18766,
1822 };
1823
1824 static const unsigned short dep62[] = {
1825   18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1826
1827 };
1828
1829 static const unsigned short dep63[] = {
1830   14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
1831   2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763,
1832   18764, 18766,
1833 };
1834
1835 static const unsigned short dep64[] = {
1836   97, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765,
1837 };
1838
1839 static const unsigned short dep65[] = {
1840   40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173,
1841   2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766,
1842 };
1843
1844 static const unsigned short dep66[] = {
1845   11, 97, 206, 282,
1846 };
1847
1848 static const unsigned short dep67[] = {
1849   11, 40, 41, 97, 158, 162, 175, 185, 206, 282, 2166, 2167, 2170, 2173, 4135,
1850
1851 };
1852
1853 static const unsigned short dep68[] = {
1854   11, 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135,
1855 };
1856
1857 static const unsigned short dep69[] = {
1858   12, 97, 207, 282,
1859 };
1860
1861 static const unsigned short dep70[] = {
1862   11, 40, 41, 97, 158, 162, 175, 185, 207, 282, 2166, 2167, 2170, 2173, 4135,
1863
1864 };
1865
1866 static const unsigned short dep71[] = {
1867   13, 97, 208, 282,
1868 };
1869
1870 static const unsigned short dep72[] = {
1871   11, 40, 41, 97, 158, 162, 175, 185, 208, 282, 2166, 2167, 2170, 2173, 4135,
1872
1873 };
1874
1875 static const unsigned short dep73[] = {
1876   14, 97, 209, 282,
1877 };
1878
1879 static const unsigned short dep74[] = {
1880   11, 40, 41, 97, 158, 162, 175, 185, 209, 282, 2166, 2167, 2170, 2173, 4135,
1881
1882 };
1883
1884 static const unsigned short dep75[] = {
1885   15, 97, 211, 212, 282,
1886 };
1887
1888 static const unsigned short dep76[] = {
1889   40, 41, 97, 158, 162, 175, 185, 211, 212, 282, 2166, 2167, 2170, 2173, 4135,
1890
1891 };
1892
1893 static const unsigned short dep77[] = {
1894   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135,
1895 };
1896
1897 static const unsigned short dep78[] = {
1898   16, 97, 214, 215, 282,
1899 };
1900
1901 static const unsigned short dep79[] = {
1902   40, 41, 97, 158, 162, 175, 185, 214, 215, 282, 2166, 2167, 2170, 2173, 4135,
1903
1904 };
1905
1906 static const unsigned short dep80[] = {
1907   17, 97, 217, 218, 282,
1908 };
1909
1910 static const unsigned short dep81[] = {
1911   40, 41, 97, 158, 162, 175, 185, 217, 218, 282, 2166, 2167, 2170, 2173, 4135,
1912
1913 };
1914
1915 static const unsigned short dep82[] = {
1916   18, 97, 220, 221, 282,
1917 };
1918
1919 static const unsigned short dep83[] = {
1920   40, 41, 97, 158, 162, 175, 185, 220, 221, 282, 2166, 2167, 2170, 2173, 4135,
1921
1922 };
1923
1924 static const unsigned short dep84[] = {
1925   15, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167,
1926   2170, 2173, 4135,
1927 };
1928
1929 static const unsigned short dep85[] = {
1930   15, 16, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166,
1931   2167, 2170, 2173, 4135,
1932 };
1933
1934 static const unsigned short dep86[] = {
1935   15, 17, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166,
1936   2167, 2170, 2173, 4135,
1937 };
1938
1939 static const unsigned short dep87[] = {
1940   15, 18, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166,
1941   2167, 2170, 2173, 4135,
1942 };
1943
1944 static const unsigned short dep88[] = {
1945   15, 97, 210, 211, 282,
1946 };
1947
1948 static const unsigned short dep89[] = {
1949   11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2166, 2167, 2170,
1950   2173, 4135,
1951 };
1952
1953 static const unsigned short dep90[] = {
1954   15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282,
1955 };
1956
1957 static const unsigned short dep91[] = {
1958   11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
1959   216, 218, 219, 221, 282, 2166, 2167, 2170, 2173, 4135,
1960 };
1961
1962 static const unsigned short dep92[] = {
1963   16, 97, 213, 214, 282,
1964 };
1965
1966 static const unsigned short dep93[] = {
1967   12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2166, 2167, 2170,
1968   2173, 4135,
1969 };
1970
1971 static const unsigned short dep94[] = {
1972   17, 97, 216, 217, 282,
1973 };
1974
1975 static const unsigned short dep95[] = {
1976   13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2166, 2167, 2170,
1977   2173, 4135,
1978 };
1979
1980 static const unsigned short dep96[] = {
1981   18, 97, 219, 220, 282,
1982 };
1983
1984 static const unsigned short dep97[] = {
1985   14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2166, 2167, 2170,
1986   2173, 4135,
1987 };
1988
1989 static const unsigned short dep98[] = {
1990   15, 97, 210, 211, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
1991   2348, 2351, 2352, 2355, 2356,
1992 };
1993
1994 static const unsigned short dep99[] = {
1995   11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
1996   2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
1997   16530, 16531, 16533,
1998 };
1999
2000 static const unsigned short dep100[] = {
2001   15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2166, 2167,
2002   2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351, 2352, 2355, 2356,
2003 };
2004
2005 static const unsigned short dep101[] = {
2006   11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
2007   216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2344, 2347,
2008   2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533,
2009 };
2010
2011 static const unsigned short dep102[] = {
2012   16, 97, 213, 214, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
2013   2348, 2351, 2352, 2355, 2356,
2014 };
2015
2016 static const unsigned short dep103[] = {
2017   12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
2018   2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
2019   16530, 16531, 16533,
2020 };
2021
2022 static const unsigned short dep104[] = {
2023   17, 97, 216, 217, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
2024   2348, 2351, 2352, 2355, 2356,
2025 };
2026
2027 static const unsigned short dep105[] = {
2028   13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
2029   2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
2030   16530, 16531, 16533,
2031 };
2032
2033 static const unsigned short dep106[] = {
2034   18, 97, 219, 220, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347,
2035   2348, 2351, 2352, 2355, 2356,
2036 };
2037
2038 static const unsigned short dep107[] = {
2039   14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
2040   2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528,
2041   16530, 16531, 16533,
2042 };
2043
2044 static const unsigned short dep108[] = {
2045   15, 97, 210, 211, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2046   22827, 22828, 22831, 22832, 22835, 22836,
2047 };
2048
2049 static const unsigned short dep109[] = {
2050   11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137,
2051   2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2052   22831, 22832, 22835, 22836,
2053 };
2054
2055 static const unsigned short dep110[] = {
2056   15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 22646, 22647,
2057   22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835,
2058   22836,
2059 };
2060
2061 static const unsigned short dep111[] = {
2062   11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215,
2063   216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 4135, 16528,
2064   16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835, 22836,
2065 };
2066
2067 static const unsigned short dep112[] = {
2068   16, 97, 213, 214, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2069   22827, 22828, 22831, 22832, 22835, 22836,
2070 };
2071
2072 static const unsigned short dep113[] = {
2073   12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137,
2074   2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2075   22831, 22832, 22835, 22836,
2076 };
2077
2078 static const unsigned short dep114[] = {
2079   17, 97, 216, 217, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2080   22827, 22828, 22831, 22832, 22835, 22836,
2081 };
2082
2083 static const unsigned short dep115[] = {
2084   13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137,
2085   2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2086   22831, 22832, 22835, 22836,
2087 };
2088
2089 static const unsigned short dep116[] = {
2090   18, 97, 219, 220, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824,
2091   22827, 22828, 22831, 22832, 22835, 22836,
2092 };
2093
2094 static const unsigned short dep117[] = {
2095   14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137,
2096   2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828,
2097   22831, 22832, 22835, 22836,
2098 };
2099
2100 static const unsigned short dep118[] = {
2101   97, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351,
2102   2352, 2355, 2356,
2103 };
2104
2105 static const unsigned short dep119[] = {
2106   40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173,
2107   2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533,
2108
2109 };
2110
2111 static const unsigned short dep120[] = {
2112   97, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828,
2113   22831, 22832, 22835, 22836,
2114 };
2115
2116 static const unsigned short dep121[] = {
2117   40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173,
2118   4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835,
2119   22836,
2120 };
2121
2122 static const unsigned short dep122[] = {
2123   19, 20, 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167,
2124   2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766,
2125
2126 };
2127
2128 static const unsigned short dep123[] = {
2129   40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2138, 2139, 2140, 2166,
2130   2167, 2170, 2173, 4135, 20616,
2131 };
2132
2133 static const unsigned short dep124[] = {
2134   97, 282, 2083, 2084, 2286, 2287,
2135 };
2136
2137 static const unsigned short dep125[] = {
2138   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173,
2139   2285, 2287, 4135, 20616,
2140 };
2141
2142 static const unsigned short dep126[] = {
2143   40, 41, 97, 158, 162, 175, 185, 282, 2082, 2084, 2166, 2167, 2170, 2173, 2327,
2144   4135, 20616,
2145 };
2146
2147 static const unsigned short dep127[] = {
2148   97, 282, 14455, 14457, 14458, 14460, 14461, 14463, 14635, 14636, 14639, 14640,
2149   14643, 14644,
2150 };
2151
2152 static const unsigned short dep128[] = {
2153   40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 4135, 14635, 14636,
2154   14639, 14640, 14643, 14644, 20616, 24694, 24695, 24698, 24701,
2155 };
2156
2157 static const unsigned short dep129[] = {
2158   97, 122, 124, 125, 127, 282, 303, 304, 307, 308,
2159 };
2160
2161 static const unsigned short dep130[] = {
2162   40, 41, 97, 158, 162, 175, 185, 282, 303, 304, 307, 308, 4135, 24694, 24695,
2163   24698, 24701,
2164 };
2165
2166 static const unsigned short dep131[] = {
2167   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616,
2168
2169 };
2170
2171 static const unsigned short dep132[] = {
2172   40, 41, 97, 119, 122, 125, 158, 162, 175, 185, 282, 2327, 4135, 20616, 24694,
2173
2174 };
2175
2176 static const unsigned short dep133[] = {
2177   6, 24, 26, 27, 97, 201, 227, 230, 282, 2081, 2284,
2178 };
2179
2180 static const unsigned short dep134[] = {
2181   40, 41, 97, 158, 162, 175, 185, 201, 227, 229, 282, 2138, 2139, 2140, 2166,
2182   2167, 2170, 2173, 2284, 4135, 20616,
2183 };
2184
2185 static const unsigned short dep135[] = {
2186   6, 24, 25, 26, 40, 41, 97, 158, 162, 175, 185, 282, 2081, 2166, 2167, 2170,
2187   2173, 2327, 4135, 20616,
2188 };
2189
2190 static const unsigned short dep136[] = {
2191   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2347, 2348,
2192   2351, 2352, 2355, 2356, 4135,
2193 };
2194
2195 static const unsigned short dep137[] = {
2196   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, 22824,
2197   22827, 22828, 22831, 22832, 22835, 22836,
2198 };
2199
2200 static const unsigned short dep138[] = {
2201   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2348,
2202   2349, 2352, 2353, 2356, 4135,
2203 };
2204
2205 static const unsigned short dep139[] = {
2206   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2346, 2347,
2207   2350, 2351, 2354, 2355, 4135,
2208 };
2209
2210 static const unsigned short dep140[] = {
2211   40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2346,
2212   2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 4135,
2213 };
2214
2215 static const unsigned short dep141[] = {
2216   0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167, 2170, 2173,
2217   4135,
2218 };
2219
2220 static const unsigned short dep142[] = {
2221   0, 97, 195, 282,
2222 };
2223
2224 static const unsigned short dep143[] = {
2225   0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 195, 282, 2166, 2167, 2170,
2226   2173, 4135,
2227 };
2228
2229 static const unsigned short dep144[] = {
2230   40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135,
2231 };
2232
2233 static const unsigned short dep145[] = {
2234   2, 28, 97, 197, 231, 282, 28866, 29018,
2235 };
2236
2237 static const unsigned short dep146[] = {
2238   1, 2, 28, 29, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 28866, 29018,
2239
2240 };
2241
2242 static const unsigned short dep147[] = {
2243   1, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 4135,
2244   28866, 29018,
2245 };
2246
2247 static const unsigned short dep148[] = {
2248   0, 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135,
2249
2250 };
2251
2252 static const unsigned short dep149[] = {
2253   1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
2254   28, 29, 30, 31, 97, 196, 197, 198, 199, 200, 202, 203, 204, 205, 206, 207,
2255   208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, 223, 224, 225, 231,
2256   232, 233, 234, 282, 2071, 2081, 2274, 2284, 28866, 29018,
2257 };
2258
2259 static const unsigned short dep150[] = {
2260   29, 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 196, 197, 198, 199,
2261   200, 202, 203, 204, 205, 206, 207, 208, 209, 211, 212, 214, 215, 217, 218,
2262   220, 221, 222, 223, 224, 225, 231, 232, 233, 234, 282, 2138, 2139, 2140, 2166,
2263   2167, 2170, 2173, 2274, 2284, 4135, 20616, 28866, 29018,
2264 };
2265
2266 static const unsigned short dep151[] = {
2267   97, 282, 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666,
2268   14667, 14669, 14670, 14679,
2269 };
2270
2271 static const unsigned short dep152[] = {
2272   40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 2166, 2167, 2170, 2173, 4135,
2273   14645, 14646, 14666, 14667, 14669, 14670, 14679,
2274 };
2275
2276 static const unsigned short dep153[] = {
2277   14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666, 14667,
2278   14669, 14670, 14679,
2279 };
2280
2281 static const unsigned short dep154[] = {
2282   183, 184, 14645, 14646, 14666, 14667, 14669, 14670, 14679,
2283 };
2284
2285 static const unsigned short dep155[] = {
2286   97, 282, 14465, 14466, 14469, 14470, 14480, 14481, 14483, 14484, 14486, 14487,
2287   14489, 14490, 14493, 14495, 14496, 14505, 14506, 14507, 14508, 14510, 14515,
2288   14516, 14518, 14519, 14525, 14645, 14646, 14652, 14653, 14654, 14655, 14657,
2289   14659, 14666, 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679,
2290 };
2291
2292 static const unsigned short dep156[] = {
2293   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170,
2294   2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666,
2295   14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, 34888,
2296 };
2297
2298 static const unsigned short dep157[] = {
2299   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170,
2300   2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666,
2301   14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679,
2302 };
2303
2304 static const unsigned short dep158[] = {
2305   1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
2306   28, 29, 30, 31, 40, 41, 97, 137, 138, 158, 162, 175, 180, 181, 185, 190, 191,
2307   282, 2071, 2081, 2166, 2167, 2170, 2173, 2327, 4135, 20616, 28866,
2308 };
2309
2310 static const unsigned short dep159[] = {
2311   43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63,
2312   64, 65, 67, 69, 70, 71, 72, 73, 94, 96, 97, 243, 244, 245, 246, 247, 248,
2313   249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261, 263, 264, 265, 281,
2314   282, 2116, 2310,
2315 };
2316
2317 static const unsigned short dep160[] = {
2318   40, 41, 96, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191, 243, 244,
2319   245, 246, 247, 248, 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261,
2320   263, 264, 265, 281, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2310, 4135,
2321   20616,
2322 };
2323
2324 static const unsigned short dep161[] = {
2325   59, 95, 97, 254, 281, 282, 2140, 2327,
2326 };
2327
2328 static const unsigned short dep162[] = {
2329   40, 41, 43, 44, 46, 48, 49, 51, 52, 53, 54, 56, 57, 60, 61, 63, 64, 65, 66,
2330   67, 69, 70, 71, 94, 95, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191,
2331   254, 281, 282, 2107, 2116, 2166, 2167, 2170, 2173, 2327, 4135, 20616,
2332 };
2333
2334 static const unsigned short dep163[] = {
2335   2, 28, 41, 97, 197, 231, 241, 282, 2140, 2327, 28866, 29018,
2336 };
2337
2338 static const unsigned short dep164[] = {
2339   2, 25, 26, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231,
2340   241, 282, 2327, 4135, 20616, 28866, 29018,
2341 };
2342
2343 static const unsigned short dep165[] = {
2344   97, 129, 130, 133, 134, 140, 141, 144, 145, 147, 148, 150, 151, 153, 154,
2345   157, 159, 160, 165, 166, 169, 170, 171, 172, 174, 176, 177, 179, 180, 182,
2346   183, 186, 187, 189, 282, 309, 310, 314, 316, 317, 318, 319, 321, 323, 327,
2347   330, 331, 333, 334, 335, 336, 338, 339, 340, 342, 343,
2348 };
2349
2350 static const unsigned short dep166[] = {
2351   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 309, 310, 314, 316,
2352   317, 318, 319, 321, 323, 327, 330, 331, 333, 334, 335, 336, 338, 339, 340,
2353   342, 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, 34888,
2354 };
2355
2356 static const unsigned short dep167[] = {
2357   97, 128, 130, 132, 134, 169, 170, 189, 282, 309, 310, 330, 331, 333, 334,
2358   343,
2359 };
2360
2361 static const unsigned short dep168[] = {
2362   40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 309, 310, 330, 331, 333, 334,
2363   343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616,
2364 };
2365
2366 static const unsigned short dep169[] = {
2367   40, 41, 97, 130, 131, 134, 135, 137, 138, 141, 142, 145, 146, 148, 149, 151,
2368   152, 154, 155, 157, 158, 159, 161, 162, 164, 165, 167, 168, 169, 170, 172,
2369   173, 174, 175, 176, 178, 179, 181, 182, 184, 185, 187, 188, 189, 190, 191,
2370   282, 2166, 2167, 2170, 2173, 2327, 4135, 20616,
2371 };
2372
2373 static const unsigned short dep170[] = {
2374   40, 41, 97, 130, 131, 134, 135, 158, 162, 169, 170, 175, 185, 189, 282, 2166,
2375   2167, 2170, 2173, 2327, 4135, 20616,
2376 };
2377
2378 static const unsigned short dep171[] = {
2379   40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 153, 155, 158, 162, 171, 173,
2380   175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135,
2381   20616,
2382 };
2383
2384 static const unsigned short dep172[] = {
2385   40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 139, 140, 142, 143, 153, 155,
2386   158, 162, 171, 173, 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170,
2387   2173, 4135, 20616,
2388 };
2389
2390 static const unsigned short dep173[] = {
2391   77, 78, 97, 101, 102, 269, 270, 282, 284, 285,
2392 };
2393
2394 static const unsigned short dep174[] = {
2395   40, 41, 47, 62, 78, 80, 86, 97, 99, 102, 137, 138, 158, 160, 161, 162, 175,
2396   185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166, 2167,
2397   2170, 2173, 4135, 20616,
2398 };
2399
2400 static const unsigned short dep175[] = {
2401   40, 41, 47, 62, 78, 80, 97, 99, 102, 104, 106, 137, 138, 158, 160, 161, 162,
2402   175, 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166,
2403   2167, 2170, 2173, 4135, 20616,
2404 };
2405
2406 static const unsigned short dep176[] = {
2407   97, 282, 12480, 12481, 12633,
2408 };
2409
2410 static const unsigned short dep177[] = {
2411   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2412   2166, 2167, 2170, 2173, 4135, 12633, 20616,
2413 };
2414
2415 static const unsigned short dep178[] = {
2416   97, 282, 6219, 6220, 6411,
2417 };
2418
2419 static const unsigned short dep179[] = {
2420   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2421   2166, 2167, 2170, 2173, 4135, 6411, 20616,
2422 };
2423
2424 static const unsigned short dep180[] = {
2425   97, 282, 6237, 6424,
2426 };
2427
2428 static const unsigned short dep181[] = {
2429   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2430   2166, 2167, 2170, 2173, 4135, 6424, 20616,
2431 };
2432
2433 static const unsigned short dep182[] = {
2434   97, 282, 6255, 6256, 6257, 6258, 6435, 6437, 8484,
2435 };
2436
2437 static const unsigned short dep183[] = {
2438   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2439   2166, 2167, 2170, 2173, 4135, 6258, 6436, 6437, 8304, 8483, 20616,
2440 };
2441
2442 static const unsigned short dep184[] = {
2443   97, 282, 6259, 6260, 6438,
2444 };
2445
2446 static const unsigned short dep185[] = {
2447   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2448   2166, 2167, 2170, 2173, 4135, 6438, 20616,
2449 };
2450
2451 static const unsigned short dep186[] = {
2452   97, 282, 6261, 6439,
2453 };
2454
2455 static const unsigned short dep187[] = {
2456   40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140,
2457   2166, 2167, 2170, 2173, 4135, 6439, 20616,
2458 };
2459
2460 static const unsigned short dep188[] = {
2461   97, 282, 10350, 10530,
2462 };
2463