balloon: Don't balloon roms
[qemu.git] / disas / m68k.c
1 /* This file is composed of several different files from the upstream
2 sourceware.org CVS. Original file boundaries marked with **** */
3
4 #include "qemu/osdep.h"
5 #include <math.h>
6
7 #include "disas/bfd.h"
8
9 /* **** floatformat.h from sourceware.org CVS 2005-08-14. */
10 /* IEEE floating point support declarations, for GDB, the GNU Debugger.
11 Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc.
12
13 This file is part of GDB.
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, see <http://www.gnu.org/licenses/>. */
27
28 #if !defined (FLOATFORMAT_H)
29 #define FLOATFORMAT_H 1
30
31 /*#include "ansidecl.h" */
32
33 /* A floatformat consists of a sign bit, an exponent and a mantissa. Once the
34 bytes are concatenated according to the byteorder flag, then each of those
35 fields is contiguous. We number the bits with 0 being the most significant
36 (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
37 contains with the *_start and *_len fields. */
38
39 /* What is the order of the bytes. */
40
41 enum floatformat_byteorders {
42
43 /* Standard little endian byte order.
44 EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
45
46 floatformat_little,
47
48 /* Standard big endian byte order.
49 EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
50
51 floatformat_big,
52
53 /* Little endian byte order but big endian word order.
54 EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
55
56 floatformat_littlebyte_bigword
57
58 };
59
60 enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
61
62 struct floatformat
63 {
64 enum floatformat_byteorders byteorder;
65 unsigned int totalsize; /* Total size of number in bits */
66
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
68 unsigned int sign_start;
69
70 unsigned int exp_start;
71 unsigned int exp_len;
72 /* Bias added to a "true" exponent to form the biased exponent. It
73 is intentionally signed as, otherwize, -exp_bias can turn into a
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
75 bit long, the equation (long)(1 - exp_bias) evaluates to
76 4294950914) instead of -16382). */
77 int exp_bias;
78 /* Exponent value which indicates NaN. This is the actual value stored in
79 the float, not adjusted by the exp_bias. This usually consists of all
80 one bits. */
81 unsigned int exp_nan;
82
83 unsigned int man_start;
84 unsigned int man_len;
85
86 /* Is the integer bit explicit or implicit? */
87 enum floatformat_intbit intbit;
88
89 /* Internal name for debugging. */
90 const char *name;
91
92 /* Validator method. */
93 int (*is_valid) (const struct floatformat *fmt, const char *from);
94 };
95
96 /* floatformats for IEEE single and double, big and little endian. */
97
98 extern const struct floatformat floatformat_ieee_single_big;
99 extern const struct floatformat floatformat_ieee_single_little;
100 extern const struct floatformat floatformat_ieee_double_big;
101 extern const struct floatformat floatformat_ieee_double_little;
102
103 /* floatformat for ARM IEEE double, little endian bytes and big endian words */
104
105 extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
106
107 /* floatformats for various extendeds. */
108
109 extern const struct floatformat floatformat_i387_ext;
110 extern const struct floatformat floatformat_m68881_ext;
111 extern const struct floatformat floatformat_i960_ext;
112 extern const struct floatformat floatformat_m88110_ext;
113 extern const struct floatformat floatformat_m88110_harris_ext;
114 extern const struct floatformat floatformat_arm_ext_big;
115 extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;
116 /* IA-64 Floating Point register spilt into memory. */
117 extern const struct floatformat floatformat_ia64_spill_big;
118 extern const struct floatformat floatformat_ia64_spill_little;
119 extern const struct floatformat floatformat_ia64_quad_big;
120 extern const struct floatformat floatformat_ia64_quad_little;
121
122 /* Convert from FMT to a double.
123 FROM is the address of the extended float.
124 Store the double in *TO. */
125
126 extern void
127 floatformat_to_double (const struct floatformat *, const char *, double *);
128
129 /* The converse: convert the double *FROM to FMT
130 and store where TO points. */
131
132 extern void
133 floatformat_from_double (const struct floatformat *, const double *, char *);
134
135 /* Return non-zero iff the data at FROM is a valid number in format FMT. */
136
137 extern int
138 floatformat_is_valid (const struct floatformat *fmt, const char *from);
139
140 #endif /* defined (FLOATFORMAT_H) */
141 /* **** End of floatformat.h */
142 /* **** m68k-dis.h from sourceware.org CVS 2005-08-14. */
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
144 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
145 2003, 2004 Free Software Foundation, Inc.
146
147 This file is part of GDB, GAS, and the GNU binutils.
148
149 GDB, GAS, and the GNU binutils are free software; you can redistribute
150 them and/or modify them under the terms of the GNU General Public
151 License as published by the Free Software Foundation; either version
152 1, or (at your option) any later version.
153
154 GDB, GAS, and the GNU binutils are distributed in the hope that they
155 will be useful, but WITHOUT ANY WARRANTY; without even the implied
156 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
157 the GNU General Public License for more details.
158
159 You should have received a copy of the GNU General Public License
160 along with this file; see the file COPYING. If not,
161 see <http://www.gnu.org/licenses/>. */
162
163 /* These are used as bit flags for the arch field in the m68k_opcode
164 structure. */
165 #define _m68k_undef 0
166 #define m68000 0x001
167 #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
171 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
172 gas will deal with the few differences. */
173 #define m68040 0x010
174 /* There is no 68050. */
175 #define m68060 0x020
176 #define m68881 0x040
177 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
178 #define m68851 0x080
179 #define cpu32 0x100 /* e.g., 68332 */
180
181 #define mcfmac 0x200 /* ColdFire MAC. */
182 #define mcfemac 0x400 /* ColdFire EMAC. */
183 #define cfloat 0x800 /* ColdFire FPU. */
184 #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
185
186 #define mcfisa_a 0x2000 /* ColdFire ISA_A. */
187 #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
188 #define mcfisa_b 0x8000 /* ColdFire ISA_B. */
189 #define mcfusp 0x10000 /* ColdFire USP instructions. */
190
191 #define mcf5200 0x20000
192 #define mcf5206e 0x40000
193 #define mcf521x 0x80000
194 #define mcf5249 0x100000
195 #define mcf528x 0x200000
196 #define mcf5307 0x400000
197 #define mcf5407 0x800000
198 #define mcf5470 0x1000000
199 #define mcf5480 0x2000000
200
201 /* Handy aliases. */
202 #define m68040up (m68040 | m68060)
203 #define m68030up (m68030 | m68040up)
204 #define m68020up (m68020 | m68030up)
205 #define m68010up (m68010 | cpu32 | m68020up)
206 #define m68000up (m68000 | m68010up)
207
208 #define mfloat (m68881 | m68882 | m68040 | m68060)
209 #define mmmu (m68851 | m68030 | m68040 | m68060)
210
211 /* The structure used to hold information for an opcode. */
212
213 struct m68k_opcode
214 {
215 /* The opcode name. */
216 const char *name;
217 /* The pseudo-size of the instruction(in bytes). Used to determine
218 number of bytes necessary to disassemble the instruction. */
219 unsigned int size;
220 /* The opcode itself. */
221 unsigned long opcode;
222 /* The mask used by the disassembler. */
223 unsigned long match;
224 /* The arguments. */
225 const char *args;
226 /* The architectures which support this opcode. */
227 unsigned int arch;
228 };
229
230 /* The structure used to hold information for an opcode alias. */
231
232 struct m68k_opcode_alias
233 {
234 /* The alias name. */
235 const char *alias;
236 /* The instruction for which this is an alias. */
237 const char *primary;
238 };
239
240 /* We store four bytes of opcode for all opcodes because that is the
241 most any of them need. The actual length of an instruction is
242 always at least 2 bytes, and is as much longer as necessary to hold
243 the operands it has.
244
245 The match field is a mask saying which bits must match particular
246 opcode in order for an instruction to be an instance of that
247 opcode.
248
249 The args field is a string containing two characters for each
250 operand of the instruction. The first specifies the kind of
251 operand; the second, the place it is stored. */
252
253 /* Kinds of operands:
254 Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
255
256 D data register only. Stored as 3 bits.
257 A address register only. Stored as 3 bits.
258 a address register indirect only. Stored as 3 bits.
259 R either kind of register. Stored as 4 bits.
260 r either kind of register indirect only. Stored as 4 bits.
261 At the moment, used only for cas2 instruction.
262 F floating point coprocessor register only. Stored as 3 bits.
263 O an offset (or width): immediate data 0-31 or data register.
264 Stored as 6 bits in special format for BF... insns.
265 + autoincrement only. Stored as 3 bits (number of the address register).
266 - autodecrement only. Stored as 3 bits (number of the address register).
267 Q quick immediate data. Stored as 3 bits.
268 This matches an immediate operand only when value is in range 1 .. 8.
269 M moveq immediate data. Stored as 8 bits.
270 This matches an immediate operand only when value is in range -128..127
271 T trap vector immediate data. Stored as 4 bits.
272
273 k K-factor for fmove.p instruction. Stored as a 7-bit constant or
274 a three bit register offset, depending on the field type.
275
276 # immediate data. Stored in special places (b, w or l)
277 which say how many bits to store.
278 ^ immediate data for floating point instructions. Special places
279 are offset by 2 bytes from '#'...
280 B pc-relative address, converted to an offset
281 that is treated as immediate data.
282 d displacement and register. Stores the register as 3 bits
283 and stores the displacement in the entire second word.
284
285 C the CCR. No need to store it; this is just for filtering validity.
286 S the SR. No need to store, just as with CCR.
287 U the USP. No need to store, just as with CCR.
288 E the MAC ACC. No need to store, just as with CCR.
289 e the EMAC ACC[0123].
290 G the MAC/EMAC MACSR. No need to store, just as with CCR.
291 g the EMAC ACCEXT{01,23}.
292 H the MASK. No need to store, just as with CCR.
293 i the MAC/EMAC scale factor.
294
295 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
296 extracted from the 'd' field of word one, which means that an extended
297 coprocessor opcode can be skipped using the 'i' place, if needed.
298
299 s System Control register for the floating point coprocessor.
300
301 J Misc register for movec instruction, stored in 'j' format.
302 Possible values:
303 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
304 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
305 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
306 0x003 TC MMU Translation Control [60, 40]
307 0x004 ITT0 Instruction Transparent
308 Translation reg 0 [60, 40]
309 0x005 ITT1 Instruction Transparent
310 Translation reg 1 [60, 40]
311 0x006 DTT0 Data Transparent
312 Translation reg 0 [60, 40]
313 0x007 DTT1 Data Transparent
314 Translation reg 1 [60, 40]
315 0x008 BUSCR Bus Control Register [60]
316 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
317 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
318 0x802 CAAR Cache Address Register [ 30, 20]
319 0x803 MSP Master Stack Pointer [ 40, 30, 20]
320 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
321 0x805 MMUSR MMU Status reg [ 40]
322 0x806 URP User Root Pointer [60, 40]
323 0x807 SRP Supervisor Root Pointer [60, 40]
324 0x808 PCR Processor Configuration reg [60]
325 0xC00 ROMBAR ROM Base Address Register [520X]
326 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
327 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
328 0xC0F MBAR0 RAM Base Address Register 0 [520X]
329 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
330 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
331
332 L Register list of the type d0-d7/a0-a7 etc.
333 (New! Improved! Can also hold fp0-fp7, as well!)
334 The assembler tries to see if the registers match the insn by
335 looking at where the insn wants them stored.
336
337 l Register list like L, but with all the bits reversed.
338 Used for going the other way. . .
339
340 c cache identifier which may be "nc" for no cache, "ic"
341 for instruction cache, "dc" for data cache, or "bc"
342 for both caches. Used in cinv and cpush. Always
343 stored in position "d".
344
345 u Any register, with ``upper'' or ``lower'' specification. Used
346 in the mac instructions with size word.
347
348 The remainder are all stored as 6 bits using an address mode and a
349 register number; they differ in which addressing modes they match.
350
351 * all (modes 0-6,7.0-4)
352 ~ alterable memory (modes 2-6,7.0,7.1)
353 (not 0,1,7.2-4)
354 % alterable (modes 0-6,7.0,7.1)
355 (not 7.2-4)
356 ; data (modes 0,2-6,7.0-4)
357 (not 1)
358 @ data, but not immediate (modes 0,2-6,7.0-3)
359 (not 1,7.4)
360 ! control (modes 2,5,6,7.0-3)
361 (not 0,1,3,4,7.4)
362 & alterable control (modes 2,5,6,7.0,7.1)
363 (not 0,1,3,4,7.2-4)
364 $ alterable data (modes 0,2-6,7.0,7.1)
365 (not 1,7.2-4)
366 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
367 (not 1,3,4,7.2-4)
368 / control, or data register (modes 0,2,5,6,7.0-3)
369 (not 1,3,4,7.4)
370 > *save operands (modes 2,4,5,6,7.0,7.1)
371 (not 0,1,3,7.2-4)
372 < *restore operands (modes 2,3,5,6,7.0-3)
373 (not 0,1,4,7.4)
374
375 coldfire move operands:
376 m (modes 0-4)
377 n (modes 5,7.2)
378 o (modes 6,7.0,7.1,7.3,7.4)
379 p (modes 0-5)
380
381 coldfire bset/bclr/btst/mulsl/mulul operands:
382 q (modes 0,2-5)
383 v (modes 0,2-5,7.0,7.1)
384 b (modes 0,2-5,7.2)
385 w (modes 2-5,7.2)
386 y (modes 2,5)
387 z (modes 2,5,7.2)
388 x mov3q immediate operand.
389 4 (modes 2,3,4,5)
390 */
391
392 /* For the 68851: */
393 /* I didn't use much imagination in choosing the
394 following codes, so many of them aren't very
395 mnemonic. -rab
396
397 0 32 bit pmmu register
398 Possible values:
399 000 TC Translation Control Register (68030, 68851)
400
401 1 16 bit pmmu register
402 111 AC Access Control (68851)
403
404 2 8 bit pmmu register
405 100 CAL Current Access Level (68851)
406 101 VAL Validate Access Level (68851)
407 110 SCC Stack Change Control (68851)
408
409 3 68030-only pmmu registers (32 bit)
410 010 TT0 Transparent Translation reg 0
411 (aka Access Control reg 0 -- AC0 -- on 68ec030)
412 011 TT1 Transparent Translation reg 1
413 (aka Access Control reg 1 -- AC1 -- on 68ec030)
414
415 W wide pmmu registers
416 Possible values:
417 001 DRP Dma Root Pointer (68851)
418 010 SRP Supervisor Root Pointer (68030, 68851)
419 011 CRP Cpu Root Pointer (68030, 68851)
420
421 f function code register (68030, 68851)
422 0 SFC
423 1 DFC
424
425 V VAL register only (68851)
426
427 X BADx, BACx (16 bit)
428 100 BAD Breakpoint Acknowledge Data (68851)
429 101 BAC Breakpoint Acknowledge Control (68851)
430
431 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
432 Z PCSR (68851)
433
434 | memory (modes 2-6, 7.*)
435
436 t address test level (68030 only)
437 Stored as 3 bits, range 0-7.
438 Also used for breakpoint instruction now.
439
440 */
441
442 /* Places to put an operand, for non-general operands:
443 Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
444
445 s source, low bits of first word.
446 d dest, shifted 9 in first word
447 1 second word, shifted 12
448 2 second word, shifted 6
449 3 second word, shifted 0
450 4 third word, shifted 12
451 5 third word, shifted 6
452 6 third word, shifted 0
453 7 second word, shifted 7
454 8 second word, shifted 10
455 9 second word, shifted 5
456 D store in both place 1 and place 3; for divul and divsl.
457 B first word, low byte, for branch displacements
458 W second word (entire), for branch displacements
459 L second and third words (entire), for branch displacements
460 (also overloaded for move16)
461 b second word, low byte
462 w second word (entire) [variable word/long branch offset for dbra]
463 W second word (entire) (must be signed 16 bit value)
464 l second and third word (entire)
465 g variable branch offset for bra and similar instructions.
466 The place to store depends on the magnitude of offset.
467 t store in both place 7 and place 8; for floating point operations
468 c branch offset for cpBcc operations.
469 The place to store is word two if bit six of word one is zero,
470 and words two and three if bit six of word one is one.
471 i Increment by two, to skip over coprocessor extended operands. Only
472 works with the 'I' format.
473 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
474 Also used for dynamic fmovem instruction.
475 C floating point coprocessor constant - 7 bits. Also used for static
476 K-factors...
477 j Movec register #, stored in 12 low bits of second word.
478 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
479 and remaining 3 bits of register shifted 9 bits in first word.
480 Indicate upper/lower in 1 bit shifted 7 bits in second word.
481 Use with `R' or `u' format.
482 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
483 with MSB shifted 6 bits in first word and remaining 3 bits of
484 register shifted 9 bits in first word. No upper/lower
485 indication is done.) Use with `R' or `u' format.
486 o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
487 Indicate upper/lower in 1 bit shifted 7 bits in second word.
488 Use with `R' or `u' format.
489 M For M[S]ACw; 4 bits in low bits of first word. Indicate
490 upper/lower in 1 bit shifted 6 bits in second word. Use with
491 `R' or `u' format.
492 N For M[S]ACw; 4 bits in low bits of second word. Indicate
493 upper/lower in 1 bit shifted 6 bits in second word. Use with
494 `R' or `u' format.
495 h shift indicator (scale factor), 1 bit shifted 10 in second word
496
497 Places to put operand, for general operands:
498 d destination, shifted 6 bits in first word
499 b source, at low bit of first word, and immediate uses one byte
500 w source, at low bit of first word, and immediate uses two bytes
501 l source, at low bit of first word, and immediate uses four bytes
502 s source, at low bit of first word.
503 Used sometimes in contexts where immediate is not allowed anyway.
504 f single precision float, low bit of 1st word, immediate uses 4 bytes
505 F double precision float, low bit of 1st word, immediate uses 8 bytes
506 x extended precision float, low bit of 1st word, immediate uses 12 bytes
507 p packed float, low bit of 1st word, immediate uses 12 bytes
508 G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
509 H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
510 F EMAC ACCx
511 f EMAC ACCy
512 I MAC/EMAC scale factor
513 / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
514 ] first word, bit 10
515 */
516
517 extern const struct m68k_opcode m68k_opcodes[];
518 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
519
520 extern const int m68k_numopcodes, m68k_numaliases;
521
522 /* **** End of m68k-opcode.h */
523 /* **** m68k-dis.c from sourceware.org CVS 2005-08-14. */
524 /* Print Motorola 68k instructions.
525 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
526 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
527 Free Software Foundation, Inc.
528
529 This file is free software; you can redistribute it and/or modify
530 it under the terms of the GNU General Public License as published by
531 the Free Software Foundation; either version 2 of the License, or
532 (at your option) any later version.
533
534 This program is distributed in the hope that it will be useful,
535 but WITHOUT ANY WARRANTY; without even the implied warranty of
536 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
537 GNU General Public License for more details.
538
539 You should have received a copy of the GNU General Public License
540 along with this program; if not, see <http://www.gnu.org/licenses/>. */
541
542 /* Local function prototypes. */
543
544 static const char * const fpcr_names[] =
545 {
546 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
547 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
548 };
549
550 static const char *const reg_names[] =
551 {
552 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
553 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
554 "%ps", "%pc"
555 };
556
557 /* Name of register halves for MAC/EMAC.
558 Separate from reg_names since 'spu', 'fpl' look weird. */
559 static const char *const reg_half_names[] =
560 {
561 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
562 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
563 "%ps", "%pc"
564 };
565
566 /* Sign-extend an (unsigned char). */
567 #if __STDC__ == 1
568 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
569 #else
570 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
571 #endif
572
573 /* Get a 1 byte signed integer. */
574 #define NEXTBYTE(p) (p += 2, fetch_data(info, p), COERCE_SIGNED_CHAR(p[-1]))
575
576 /* Get a 2 byte signed integer. */
577 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
578 #define NEXTWORD(p) \
579 (p += 2, fetch_data(info, p), \
580 COERCE16 ((p[-2] << 8) + p[-1]))
581
582 /* Get a 4 byte signed integer. */
583 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
584 #define NEXTLONG(p) \
585 (p += 4, fetch_data(info, p), \
586 (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])))
587
588 /* Get a 4 byte unsigned integer. */
589 #define NEXTULONG(p) \
590 (p += 4, fetch_data(info, p), \
591 (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))
592
593 /* Get a single precision float. */
594 #define NEXTSINGLE(val, p) \
595 (p += 4, fetch_data(info, p), \
596 floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val))
597
598 /* Get a double precision float. */
599 #define NEXTDOUBLE(val, p) \
600 (p += 8, fetch_data(info, p), \
601 floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val))
602
603 /* Get an extended precision float. */
604 #define NEXTEXTEND(val, p) \
605 (p += 12, fetch_data(info, p), \
606 floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val))
607
608 /* Need a function to convert from packed to double
609 precision. Actually, it's easier to print a
610 packed number than a double anyway, so maybe
611 there should be a special case to handle this... */
612 #define NEXTPACKED(p) \
613 (p += 12, fetch_data(info, p), 0.0)
614 \f
615 /* Maximum length of an instruction. */
616 #define MAXLEN 22
617
618 struct private
619 {
620 /* Points to first byte not fetched. */
621 bfd_byte *max_fetched;
622 bfd_byte the_buffer[MAXLEN];
623 bfd_vma insn_start;
624 sigjmp_buf bailout;
625 };
626
627 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
628 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
629 on error. */
630 static int
631 fetch_data2(struct disassemble_info *info, bfd_byte *addr)
632 {
633 int status;
634 struct private *priv = (struct private *)info->private_data;
635 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
636
637 status = (*info->read_memory_func) (start,
638 priv->max_fetched,
639 addr - priv->max_fetched,
640 info);
641 if (status != 0)
642 {
643 (*info->memory_error_func) (status, start, info);
644 siglongjmp(priv->bailout, 1);
645 }
646 else
647 priv->max_fetched = addr;
648 return 1;
649 }
650
651 static int
652 fetch_data(struct disassemble_info *info, bfd_byte *addr)
653 {
654 if (addr <= ((struct private *) (info->private_data))->max_fetched) {
655 return 1;
656 } else {
657 return fetch_data2(info, addr);
658 }
659 }
660
661 /* This function is used to print to the bit-bucket. */
662 static int
663 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
664 const char *format ATTRIBUTE_UNUSED,
665 ...)
666 {
667 return 0;
668 }
669
670 static void
671 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
672 struct disassemble_info *info ATTRIBUTE_UNUSED)
673 {
674 }
675
676 /* Fetch BITS bits from a position in the instruction specified by CODE.
677 CODE is a "place to put an argument", or 'x' for a destination
678 that is a general address (mode and register).
679 BUFFER contains the instruction. */
680
681 static int
682 fetch_arg (unsigned char *buffer,
683 int code,
684 int bits,
685 disassemble_info *info)
686 {
687 int val = 0;
688
689 switch (code)
690 {
691 case '/': /* MAC/EMAC mask bit. */
692 val = buffer[3] >> 5;
693 break;
694
695 case 'G': /* EMAC ACC load. */
696 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
697 break;
698
699 case 'H': /* EMAC ACC !load. */
700 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
701 break;
702
703 case ']': /* EMAC ACCEXT bit. */
704 val = buffer[0] >> 2;
705 break;
706
707 case 'I': /* MAC/EMAC scale factor. */
708 val = buffer[2] >> 1;
709 break;
710
711 case 'F': /* EMAC ACCx. */
712 val = buffer[0] >> 1;
713 break;
714
715 case 'f':
716 val = buffer[1];
717 break;
718
719 case 's':
720 val = buffer[1];
721 break;
722
723 case 'd': /* Destination, for register or quick. */
724 val = (buffer[0] << 8) + buffer[1];
725 val >>= 9;
726 break;
727
728 case 'x': /* Destination, for general arg. */
729 val = (buffer[0] << 8) + buffer[1];
730 val >>= 6;
731 break;
732
733 case 'k':
734 fetch_data(info, buffer + 3);
735 val = (buffer[3] >> 4);
736 break;
737
738 case 'C':
739 fetch_data(info, buffer + 3);
740 val = buffer[3];
741 break;
742
743 case '1':
744 fetch_data(info, buffer + 3);
745 val = (buffer[2] << 8) + buffer[3];
746 val >>= 12;
747 break;
748
749 case '2':
750 fetch_data(info, buffer + 3);
751 val = (buffer[2] << 8) + buffer[3];
752 val >>= 6;
753 break;
754
755 case '3':
756 case 'j':
757 fetch_data(info, buffer + 3);
758 val = (buffer[2] << 8) + buffer[3];
759 break;
760
761 case '4':
762 fetch_data(info, buffer + 5);
763 val = (buffer[4] << 8) + buffer[5];
764 val >>= 12;
765 break;
766
767 case '5':
768 fetch_data(info, buffer + 5);
769 val = (buffer[4] << 8) + buffer[5];
770 val >>= 6;
771 break;
772
773 case '6':
774 fetch_data(info, buffer + 5);
775 val = (buffer[4] << 8) + buffer[5];
776 break;
777
778 case '7':
779 fetch_data(info, buffer + 3);
780 val = (buffer[2] << 8) + buffer[3];
781 val >>= 7;
782 break;
783
784 case '8':
785 fetch_data(info, buffer + 3);
786 val = (buffer[2] << 8) + buffer[3];
787 val >>= 10;
788 break;
789
790 case '9':
791 fetch_data(info, buffer + 3);
792 val = (buffer[2] << 8) + buffer[3];
793 val >>= 5;
794 break;
795
796 case 'e':
797 val = (buffer[1] >> 6);
798 break;
799
800 case 'm':
801 val = (buffer[1] & 0x40 ? 0x8 : 0)
802 | ((buffer[0] >> 1) & 0x7)
803 | (buffer[3] & 0x80 ? 0x10 : 0);
804 break;
805
806 case 'n':
807 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
808 break;
809
810 case 'o':
811 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
812 break;
813
814 case 'M':
815 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
816 break;
817
818 case 'N':
819 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
820 break;
821
822 case 'h':
823 val = buffer[2] >> 2;
824 break;
825
826 default:
827 abort ();
828 }
829
830 switch (bits)
831 {
832 case 1:
833 return val & 1;
834 case 2:
835 return val & 3;
836 case 3:
837 return val & 7;
838 case 4:
839 return val & 017;
840 case 5:
841 return val & 037;
842 case 6:
843 return val & 077;
844 case 7:
845 return val & 0177;
846 case 8:
847 return val & 0377;
848 case 12:
849 return val & 07777;
850 default:
851 abort ();
852 }
853 }
854
855 /* Check if an EA is valid for a particular code. This is required
856 for the EMAC instructions since the type of source address determines
857 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
858 is a non-load EMAC instruction and the bits mean register Ry.
859 A similar case exists for the movem instructions where the register
860 mask is interpreted differently for different EAs. */
861
862 static bfd_boolean
863 m68k_valid_ea (char code, int val)
864 {
865 int mode, mask;
866 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
867 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
868 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
869
870 switch (code)
871 {
872 case '*':
873 mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
874 break;
875 case '~':
876 mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
877 break;
878 case '%':
879 mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
880 break;
881 case ';':
882 mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
883 break;
884 case '@':
885 mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
886 break;
887 case '!':
888 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
889 break;
890 case '&':
891 mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
892 break;
893 case '$':
894 mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
895 break;
896 case '?':
897 mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
898 break;
899 case '/':
900 mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
901 break;
902 case '|':
903 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
904 break;
905 case '>':
906 mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
907 break;
908 case '<':
909 mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
910 break;
911 case 'm':
912 mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
913 break;
914 case 'n':
915 mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
916 break;
917 case 'o':
918 mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
919 break;
920 case 'p':
921 mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
922 break;
923 case 'q':
924 mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
925 break;
926 case 'v':
927 mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
928 break;
929 case 'b':
930 mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
931 break;
932 case 'w':
933 mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
934 break;
935 case 'y':
936 mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
937 break;
938 case 'z':
939 mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
940 break;
941 case '4':
942 mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
943 break;
944 default:
945 abort ();
946 }
947 #undef M
948
949 mode = (val >> 3) & 7;
950 if (mode == 7)
951 mode += val & 7;
952 return (mask & (1 << mode)) != 0;
953 }
954
955 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
956 REGNO = -1 for pc, -2 for none (suppressed). */
957
958 static void
959 print_base (int regno, bfd_vma disp, disassemble_info *info)
960 {
961 if (regno == -1)
962 {
963 (*info->fprintf_func) (info->stream, "%%pc@(");
964 (*info->print_address_func) (disp, info);
965 }
966 else
967 {
968 char buf[50];
969
970 if (regno == -2)
971 (*info->fprintf_func) (info->stream, "@(");
972 else if (regno == -3)
973 (*info->fprintf_func) (info->stream, "%%zpc@(");
974 else
975 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
976
977 sprintf_vma (buf, disp);
978 (*info->fprintf_func) (info->stream, "%s", buf);
979 }
980 }
981
982 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
983 P points to extension word, in buffer.
984 ADDR is the nominal core address of that extension word. */
985
986 static unsigned char *
987 print_indexed (int basereg,
988 unsigned char *p,
989 bfd_vma addr,
990 disassemble_info *info)
991 {
992 int word;
993 static const char *const scales[] = { "", ":2", ":4", ":8" };
994 bfd_vma base_disp;
995 bfd_vma outer_disp;
996 char buf[40];
997 char vmabuf[50];
998
999 word = NEXTWORD (p);
1000
1001 /* Generate the text for the index register.
1002 Where this will be output is not yet determined. */
1003 sprintf (buf, "%s:%c%s",
1004 reg_names[(word >> 12) & 0xf],
1005 (word & 0x800) ? 'l' : 'w',
1006 scales[(word >> 9) & 3]);
1007
1008 /* Handle the 68000 style of indexing. */
1009
1010 if ((word & 0x100) == 0)
1011 {
1012 base_disp = word & 0xff;
1013 if ((base_disp & 0x80) != 0)
1014 base_disp -= 0x100;
1015 if (basereg == -1)
1016 base_disp += addr;
1017 print_base (basereg, base_disp, info);
1018 (*info->fprintf_func) (info->stream, ",%s)", buf);
1019 return p;
1020 }
1021
1022 /* Handle the generalized kind. */
1023 /* First, compute the displacement to add to the base register. */
1024 if (word & 0200)
1025 {
1026 if (basereg == -1)
1027 basereg = -3;
1028 else
1029 basereg = -2;
1030 }
1031 if (word & 0100)
1032 buf[0] = '\0';
1033 base_disp = 0;
1034 switch ((word >> 4) & 3)
1035 {
1036 case 2:
1037 base_disp = NEXTWORD (p);
1038 break;
1039 case 3:
1040 base_disp = NEXTLONG (p);
1041 }
1042 if (basereg == -1)
1043 base_disp += addr;
1044
1045 /* Handle single-level case (not indirect). */
1046 if ((word & 7) == 0)
1047 {
1048 print_base (basereg, base_disp, info);
1049 if (buf[0] != '\0')
1050 (*info->fprintf_func) (info->stream, ",%s", buf);
1051 (*info->fprintf_func) (info->stream, ")");
1052 return p;
1053 }
1054
1055 /* Two level. Compute displacement to add after indirection. */
1056 outer_disp = 0;
1057 switch (word & 3)
1058 {
1059 case 2:
1060 outer_disp = NEXTWORD (p);
1061 break;
1062 case 3:
1063 outer_disp = NEXTLONG (p);
1064 }
1065
1066 print_base (basereg, base_disp, info);
1067 if ((word & 4) == 0 && buf[0] != '\0')
1068 {
1069 (*info->fprintf_func) (info->stream, ",%s", buf);
1070 buf[0] = '\0';
1071 }
1072 sprintf_vma (vmabuf, outer_disp);
1073 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
1074 if (buf[0] != '\0')
1075 (*info->fprintf_func) (info->stream, ",%s", buf);
1076 (*info->fprintf_func) (info->stream, ")");
1077
1078 return p;
1079 }
1080
1081 /* Returns number of bytes "eaten" by the operand, or
1082 return -1 if an invalid operand was found, or -2 if
1083 an opcode tabe error was found.
1084 ADDR is the pc for this arg to be relative to. */
1085
1086 static int
1087 print_insn_arg (const char *d,
1088 unsigned char *buffer,
1089 unsigned char *p0,
1090 bfd_vma addr,
1091 disassemble_info *info)
1092 {
1093 int val = 0;
1094 int place = d[1];
1095 unsigned char *p = p0;
1096 int regno;
1097 const char *regname;
1098 unsigned char *p1;
1099 double flval;
1100 int flt_p;
1101 bfd_signed_vma disp;
1102 unsigned int uval;
1103
1104 switch (*d)
1105 {
1106 case 'c': /* Cache identifier. */
1107 {
1108 static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
1109 val = fetch_arg (buffer, place, 2, info);
1110 (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]);
1111 break;
1112 }
1113
1114 case 'a': /* Address register indirect only. Cf. case '+'. */
1115 {
1116 (*info->fprintf_func)
1117 (info->stream,
1118 "%s@",
1119 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1120 break;
1121 }
1122
1123 case '_': /* 32-bit absolute address for move16. */
1124 {
1125 uval = NEXTULONG (p);
1126 (*info->print_address_func) (uval, info);
1127 break;
1128 }
1129
1130 case 'C':
1131 (*info->fprintf_func) (info->stream, "%%ccr");
1132 break;
1133
1134 case 'S':
1135 (*info->fprintf_func) (info->stream, "%%sr");
1136 break;
1137
1138 case 'U':
1139 (*info->fprintf_func) (info->stream, "%%usp");
1140 break;
1141
1142 case 'E':
1143 (*info->fprintf_func) (info->stream, "%%acc");
1144 break;
1145
1146 case 'G':
1147 (*info->fprintf_func) (info->stream, "%%macsr");
1148 break;
1149
1150 case 'H':
1151 (*info->fprintf_func) (info->stream, "%%mask");
1152 break;
1153
1154 case 'J':
1155 {
1156 /* FIXME: There's a problem here, different m68k processors call the
1157 same address different names. This table can't get it right
1158 because it doesn't know which processor it's disassembling for. */
1159 static const struct { const char *name; int value; } names[]
1160 = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
1161 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
1162 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
1163 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
1164 {"%msp", 0x803}, {"%isp", 0x804},
1165 {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
1166
1167 /* Should we be calling this psr like we do in case 'Y'? */
1168 {"%mmusr",0x805},
1169
1170 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
1171
1172 val = fetch_arg (buffer, place, 12, info);
1173 for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
1174 if (names[regno].value == val)
1175 {
1176 (*info->fprintf_func) (info->stream, "%s", names[regno].name);
1177 break;
1178 }
1179 if (regno < 0)
1180 (*info->fprintf_func) (info->stream, "%d", val);
1181 }
1182 break;
1183
1184 case 'Q':
1185 val = fetch_arg (buffer, place, 3, info);
1186 /* 0 means 8, except for the bkpt instruction... */
1187 if (val == 0 && d[1] != 's')
1188 val = 8;
1189 (*info->fprintf_func) (info->stream, "#%d", val);
1190 break;
1191
1192 case 'x':
1193 val = fetch_arg (buffer, place, 3, info);
1194 /* 0 means -1. */
1195 if (val == 0)
1196 val = -1;
1197 (*info->fprintf_func) (info->stream, "#%d", val);
1198 break;
1199
1200 case 'M':
1201 if (place == 'h')
1202 {
1203 static const char *const scalefactor_name[] = { "<<", ">>" };
1204 val = fetch_arg (buffer, place, 1, info);
1205 (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]);
1206 }
1207 else
1208 {
1209 val = fetch_arg (buffer, place, 8, info);
1210 if (val & 0x80)
1211 val = val - 0x100;
1212 (*info->fprintf_func) (info->stream, "#%d", val);
1213 }
1214 break;
1215
1216 case 'T':
1217 val = fetch_arg (buffer, place, 4, info);
1218 (*info->fprintf_func) (info->stream, "#%d", val);
1219 break;
1220
1221 case 'D':
1222 (*info->fprintf_func) (info->stream, "%s",
1223 reg_names[fetch_arg (buffer, place, 3, info)]);
1224 break;
1225
1226 case 'A':
1227 (*info->fprintf_func)
1228 (info->stream, "%s",
1229 reg_names[fetch_arg (buffer, place, 3, info) + 010]);
1230 break;
1231
1232 case 'R':
1233 (*info->fprintf_func)
1234 (info->stream, "%s",
1235 reg_names[fetch_arg (buffer, place, 4, info)]);
1236 break;
1237
1238 case 'r':
1239 regno = fetch_arg (buffer, place, 4, info);
1240 if (regno > 7)
1241 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
1242 else
1243 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
1244 break;
1245
1246 case 'F':
1247 (*info->fprintf_func)
1248 (info->stream, "%%fp%d",
1249 fetch_arg (buffer, place, 3, info));
1250 break;
1251
1252 case 'O':
1253 val = fetch_arg (buffer, place, 6, info);
1254 if (val & 0x20)
1255 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
1256 else
1257 (*info->fprintf_func) (info->stream, "%d", val);
1258 break;
1259
1260 case '+':
1261 (*info->fprintf_func)
1262 (info->stream, "%s@+",
1263 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1264 break;
1265
1266 case '-':
1267 (*info->fprintf_func)
1268 (info->stream, "%s@-",
1269 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1270 break;
1271
1272 case 'k':
1273 if (place == 'k')
1274 (*info->fprintf_func)
1275 (info->stream, "{%s}",
1276 reg_names[fetch_arg (buffer, place, 3, info)]);
1277 else if (place == 'C')
1278 {
1279 val = fetch_arg (buffer, place, 7, info);
1280 if (val > 63) /* This is a signed constant. */
1281 val -= 128;
1282 (*info->fprintf_func) (info->stream, "{#%d}", val);
1283 }
1284 else
1285 return -2;
1286 break;
1287
1288 case '#':
1289 case '^':
1290 p1 = buffer + (*d == '#' ? 2 : 4);
1291 if (place == 's')
1292 val = fetch_arg (buffer, place, 4, info);
1293 else if (place == 'C')
1294 val = fetch_arg (buffer, place, 7, info);
1295 else if (place == '8')
1296 val = fetch_arg (buffer, place, 3, info);
1297 else if (place == '3')
1298 val = fetch_arg (buffer, place, 8, info);
1299 else if (place == 'b')
1300 val = NEXTBYTE (p1);
1301 else if (place == 'w' || place == 'W')
1302 val = NEXTWORD (p1);
1303 else if (place == 'l')
1304 val = NEXTLONG (p1);
1305 else
1306 return -2;
1307 (*info->fprintf_func) (info->stream, "#%d", val);
1308 break;
1309
1310 case 'B':
1311 if (place == 'b')
1312 disp = NEXTBYTE (p);
1313 else if (place == 'B')
1314 disp = COERCE_SIGNED_CHAR (buffer[1]);
1315 else if (place == 'w' || place == 'W')
1316 disp = NEXTWORD (p);
1317 else if (place == 'l' || place == 'L' || place == 'C')
1318 disp = NEXTLONG (p);
1319 else if (place == 'g')
1320 {
1321 disp = NEXTBYTE (buffer);
1322 if (disp == 0)
1323 disp = NEXTWORD (p);
1324 else if (disp == -1)
1325 disp = NEXTLONG (p);
1326 }
1327 else if (place == 'c')
1328 {
1329 if (buffer[1] & 0x40) /* If bit six is one, long offset. */
1330 disp = NEXTLONG (p);
1331 else
1332 disp = NEXTWORD (p);
1333 }
1334 else
1335 return -2;
1336
1337 (*info->print_address_func) (addr + disp, info);
1338 break;
1339
1340 case 'd':
1341 val = NEXTWORD (p);
1342 (*info->fprintf_func)
1343 (info->stream, "%s@(%d)",
1344 reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
1345 break;
1346
1347 case 's':
1348 (*info->fprintf_func) (info->stream, "%s",
1349 fpcr_names[fetch_arg (buffer, place, 3, info)]);
1350 break;
1351
1352 case 'e':
1353 val = fetch_arg(buffer, place, 2, info);
1354 (*info->fprintf_func) (info->stream, "%%acc%d", val);
1355 break;
1356
1357 case 'g':
1358 val = fetch_arg(buffer, place, 1, info);
1359 (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
1360 break;
1361
1362 case 'i':
1363 val = fetch_arg(buffer, place, 2, info);
1364 if (val == 1)
1365 (*info->fprintf_func) (info->stream, "<<");
1366 else if (val == 3)
1367 (*info->fprintf_func) (info->stream, ">>");
1368 else
1369 return -1;
1370 break;
1371
1372 case 'I':
1373 /* Get coprocessor ID... */
1374 val = fetch_arg (buffer, 'd', 3, info);
1375
1376 if (val != 1) /* Unusual coprocessor ID? */
1377 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
1378 break;
1379
1380 case '4':
1381 case '*':
1382 case '~':
1383 case '%':
1384 case ';':
1385 case '@':
1386 case '!':
1387 case '$':
1388 case '?':
1389 case '/':
1390 case '&':
1391 case '|':
1392 case '<':
1393 case '>':
1394 case 'm':
1395 case 'n':
1396 case 'o':
1397 case 'p':
1398 case 'q':
1399 case 'v':
1400 case 'b':
1401 case 'w':
1402 case 'y':
1403 case 'z':
1404 if (place == 'd')
1405 {
1406 val = fetch_arg (buffer, 'x', 6, info);
1407 val = ((val & 7) << 3) + ((val >> 3) & 7);
1408 }
1409 else
1410 val = fetch_arg (buffer, 's', 6, info);
1411
1412 /* If the <ea> is invalid for *d, then reject this match. */
1413 if (!m68k_valid_ea (*d, val))
1414 return -1;
1415
1416 /* Get register number assuming address register. */
1417 regno = (val & 7) + 8;
1418 regname = reg_names[regno];
1419 switch (val >> 3)
1420 {
1421 case 0:
1422 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
1423 break;
1424
1425 case 1:
1426 (*info->fprintf_func) (info->stream, "%s", regname);
1427 break;
1428
1429 case 2:
1430 (*info->fprintf_func) (info->stream, "%s@", regname);
1431 break;
1432
1433 case 3:
1434 (*info->fprintf_func) (info->stream, "%s@+", regname);
1435 break;
1436
1437 case 4:
1438 (*info->fprintf_func) (info->stream, "%s@-", regname);
1439 break;
1440
1441 case 5:
1442 val = NEXTWORD (p);
1443 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
1444 break;
1445
1446 case 6:
1447 p = print_indexed (regno, p, addr, info);
1448 break;
1449
1450 case 7:
1451 switch (val & 7)
1452 {
1453 case 0:
1454 val = NEXTWORD (p);
1455 (*info->print_address_func) (val, info);
1456 break;
1457
1458 case 1:
1459 uval = NEXTULONG (p);
1460 (*info->print_address_func) (uval, info);
1461 break;
1462
1463 case 2:
1464 val = NEXTWORD (p);
1465 (*info->fprintf_func) (info->stream, "%%pc@(");
1466 (*info->print_address_func) (addr + val, info);
1467 (*info->fprintf_func) (info->stream, ")");
1468 break;
1469
1470 case 3:
1471 p = print_indexed (-1, p, addr, info);
1472 break;
1473
1474 case 4:
1475 flt_p = 1; /* Assume it's a float... */
1476 switch (place)
1477 {
1478 case 'b':
1479 val = NEXTBYTE (p);
1480 flt_p = 0;
1481 break;
1482
1483 case 'w':
1484 val = NEXTWORD (p);
1485 flt_p = 0;
1486 break;
1487
1488 case 'l':
1489 val = NEXTLONG (p);
1490 flt_p = 0;
1491 break;
1492
1493 case 'f':
1494 NEXTSINGLE (flval, p);
1495 break;
1496
1497 case 'F':
1498 NEXTDOUBLE (flval, p);
1499 break;
1500
1501 case 'x':
1502 NEXTEXTEND (flval, p);
1503 break;
1504
1505 case 'p':
1506 flval = NEXTPACKED (p);
1507 break;
1508
1509 default:
1510 return -1;
1511 }
1512 if (flt_p) /* Print a float? */
1513 (*info->fprintf_func) (info->stream, "#%g", flval);
1514 else
1515 (*info->fprintf_func) (info->stream, "#%d", val);
1516 break;
1517
1518 default:
1519 return -1;
1520 }
1521 }
1522
1523 /* If place is '/', then this is the case of the mask bit for
1524 mac/emac loads. Now that the arg has been printed, grab the
1525 mask bit and if set, add a '&' to the arg. */
1526 if (place == '/')
1527 {
1528 val = fetch_arg (buffer, place, 1, info);
1529 if (val)
1530 info->fprintf_func (info->stream, "&");
1531 }
1532 break;
1533
1534 case 'L':
1535 case 'l':
1536 if (place == 'w')
1537 {
1538 char doneany;
1539 p1 = buffer + 2;
1540 val = NEXTWORD (p1);
1541 /* Move the pointer ahead if this point is farther ahead
1542 than the last. */
1543 p = p1 > p ? p1 : p;
1544 if (val == 0)
1545 {
1546 (*info->fprintf_func) (info->stream, "#0");
1547 break;
1548 }
1549 if (*d == 'l')
1550 {
1551 int newval = 0;
1552
1553 for (regno = 0; regno < 16; ++regno)
1554 if (val & (0x8000 >> regno))
1555 newval |= 1 << regno;
1556 val = newval;
1557 }
1558 val &= 0xffff;
1559 doneany = 0;
1560 for (regno = 0; regno < 16; ++regno)
1561 if (val & (1 << regno))
1562 {
1563 int first_regno;
1564
1565 if (doneany)
1566 (*info->fprintf_func) (info->stream, "/");
1567 doneany = 1;
1568 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
1569 first_regno = regno;
1570 while (val & (1 << (regno + 1)))
1571 ++regno;
1572 if (regno > first_regno)
1573 (*info->fprintf_func) (info->stream, "-%s",
1574 reg_names[regno]);
1575 }
1576 }
1577 else if (place == '3')
1578 {
1579 /* `fmovem' insn. */
1580 char doneany;
1581 val = fetch_arg (buffer, place, 8, info);
1582 if (val == 0)
1583 {
1584 (*info->fprintf_func) (info->stream, "#0");
1585 break;
1586 }
1587 if (*d == 'l')
1588 {
1589 int newval = 0;
1590
1591 for (regno = 0; regno < 8; ++regno)
1592 if (val & (0x80 >> regno))
1593 newval |= 1 << regno;
1594 val = newval;
1595 }
1596 val &= 0xff;
1597 doneany = 0;
1598 for (regno = 0; regno < 8; ++regno)
1599 if (val & (1 << regno))
1600 {
1601 int first_regno;
1602 if (doneany)
1603 (*info->fprintf_func) (info->stream, "/");
1604 doneany = 1;
1605 (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1606 first_regno = regno;
1607 while (val & (1 << (regno + 1)))
1608 ++regno;
1609 if (regno > first_regno)
1610 (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1611 }
1612 }
1613 else if (place == '8')
1614 {
1615 /* fmoveml for FP status registers. */
1616 (*info->fprintf_func) (info->stream, "%s",
1617 fpcr_names[fetch_arg (buffer, place, 3,
1618 info)]);
1619 }
1620 else
1621 return -2;
1622 break;
1623
1624 case 'X':
1625 place = '8';
1626 case 'Y':
1627 case 'Z':
1628 case 'W':
1629 case '0':
1630 case '1':
1631 case '2':
1632 case '3':
1633 {
1634 int val = fetch_arg (buffer, place, 5, info);
1635 const char *name = 0;
1636
1637 switch (val)
1638 {
1639 case 2: name = "%tt0"; break;
1640 case 3: name = "%tt1"; break;
1641 case 0x10: name = "%tc"; break;
1642 case 0x11: name = "%drp"; break;
1643 case 0x12: name = "%srp"; break;
1644 case 0x13: name = "%crp"; break;
1645 case 0x14: name = "%cal"; break;
1646 case 0x15: name = "%val"; break;
1647 case 0x16: name = "%scc"; break;
1648 case 0x17: name = "%ac"; break;
1649 case 0x18: name = "%psr"; break;
1650 case 0x19: name = "%pcsr"; break;
1651 case 0x1c:
1652 case 0x1d:
1653 {
1654 int break_reg = ((buffer[3] >> 2) & 7);
1655
1656 (*info->fprintf_func)
1657 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1658 break_reg);
1659 }
1660 break;
1661 default:
1662 (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1663 }
1664 if (name)
1665 (*info->fprintf_func) (info->stream, "%s", name);
1666 }
1667 break;
1668
1669 case 'f':
1670 {
1671 int fc = fetch_arg (buffer, place, 5, info);
1672
1673 if (fc == 1)
1674 (*info->fprintf_func) (info->stream, "%%dfc");
1675 else if (fc == 0)
1676 (*info->fprintf_func) (info->stream, "%%sfc");
1677 else
1678 /* xgettext:c-format */
1679 (*info->fprintf_func) (info->stream, "<function code %d>", fc);
1680 }
1681 break;
1682
1683 case 'V':
1684 (*info->fprintf_func) (info->stream, "%%val");
1685 break;
1686
1687 case 't':
1688 {
1689 int level = fetch_arg (buffer, place, 3, info);
1690
1691 (*info->fprintf_func) (info->stream, "%d", level);
1692 }
1693 break;
1694
1695 case 'u':
1696 {
1697 short is_upper = 0;
1698 int reg = fetch_arg (buffer, place, 5, info);
1699
1700 if (reg & 0x10)
1701 {
1702 is_upper = 1;
1703 reg &= 0xf;
1704 }
1705 (*info->fprintf_func) (info->stream, "%s%s",
1706 reg_half_names[reg],
1707 is_upper ? "u" : "l");
1708 }
1709 break;
1710
1711 default:
1712 return -2;
1713 }
1714
1715 return p - p0;
1716 }
1717
1718 /* Try to match the current instruction to best and if so, return the
1719 number of bytes consumed from the instruction stream, else zero. */
1720
1721 static int
1722 match_insn_m68k (bfd_vma memaddr,
1723 disassemble_info * info,
1724 const struct m68k_opcode * best,
1725 struct private * priv)
1726 {
1727 unsigned char *save_p;
1728 unsigned char *p;
1729 const char *d;
1730
1731 bfd_byte *buffer = priv->the_buffer;
1732 fprintf_function save_printer = info->fprintf_func;
1733 void (* save_print_address) (bfd_vma, struct disassemble_info *)
1734 = info->print_address_func;
1735
1736 /* Point at first word of argument data,
1737 and at descriptor for first argument. */
1738 p = buffer + 2;
1739
1740 /* Figure out how long the fixed-size portion of the instruction is.
1741 The only place this is stored in the opcode table is
1742 in the arguments--look for arguments which specify fields in the 2nd
1743 or 3rd words of the instruction. */
1744 for (d = best->args; *d; d += 2)
1745 {
1746 /* I don't think it is necessary to be checking d[0] here;
1747 I suspect all this could be moved to the case statement below. */
1748 if (d[0] == '#')
1749 {
1750 if (d[1] == 'l' && p - buffer < 6)
1751 p = buffer + 6;
1752 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
1753 p = buffer + 4;
1754 }
1755
1756 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
1757 p = buffer + 4;
1758
1759 switch (d[1])
1760 {
1761 case '1':
1762 case '2':
1763 case '3':
1764 case '7':
1765 case '8':
1766 case '9':
1767 case 'i':
1768 if (p - buffer < 4)
1769 p = buffer + 4;
1770 break;
1771 case '4':
1772 case '5':
1773 case '6':
1774 if (p - buffer < 6)
1775 p = buffer + 6;
1776 break;
1777 default:
1778 break;
1779 }
1780 }
1781
1782 /* pflusha is an exceptions. It takes no arguments but is two words
1783 long. Recognize it by looking at the lower 16 bits of the mask. */
1784 if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
1785 p = buffer + 4;
1786
1787 /* lpstop is another exception. It takes a one word argument but is
1788 three words long. */
1789 if (p - buffer < 6
1790 && (best->match & 0xffff) == 0xffff
1791 && best->args[0] == '#'
1792 && best->args[1] == 'w')
1793 {
1794 /* Copy the one word argument into the usual location for a one
1795 word argument, to simplify printing it. We can get away with
1796 this because we know exactly what the second word is, and we
1797 aren't going to print anything based on it. */
1798 p = buffer + 6;
1799 fetch_data(info, p);
1800 buffer[2] = buffer[4];
1801 buffer[3] = buffer[5];
1802 }
1803
1804 fetch_data(info, p);
1805
1806 d = best->args;
1807
1808 save_p = p;
1809 info->print_address_func = dummy_print_address;
1810 info->fprintf_func = dummy_printer;
1811
1812 /* We scan the operands twice. The first time we don't print anything,
1813 but look for errors. */
1814 for (; *d; d += 2)
1815 {
1816 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1817
1818 if (eaten >= 0)
1819 p += eaten;
1820 else if (eaten == -1)
1821 {
1822 info->fprintf_func = save_printer;
1823 info->print_address_func = save_print_address;
1824 return 0;
1825 }
1826 else
1827 {
1828 info->fprintf_func (info->stream,
1829 /* xgettext:c-format */
1830 "<internal error in opcode table: %s %s>\n",
1831 best->name, best->args);
1832 info->fprintf_func = save_printer;
1833 info->print_address_func = save_print_address;
1834 return 2;
1835 }
1836 }
1837
1838 p = save_p;
1839 info->fprintf_func = save_printer;
1840 info->print_address_func = save_print_address;
1841
1842 d = best->args;
1843
1844 info->fprintf_func (info->stream, "%s", best->name);
1845
1846 if (*d)
1847 info->fprintf_func (info->stream, " ");
1848
1849 while (*d)
1850 {
1851 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1852 d += 2;
1853
1854 if (*d && *(d - 2) != 'I' && *d != 'k')
1855 info->fprintf_func (info->stream, ",");
1856 }
1857
1858 return p - buffer;
1859 }
1860
1861 /* Print the m68k instruction at address MEMADDR in debugged memory,
1862 on INFO->STREAM. Returns length of the instruction, in bytes. */
1863
1864 int
1865 print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
1866 {
1867 int i;
1868 const char *d;
1869 unsigned int arch_mask;
1870 struct private priv;
1871 bfd_byte *buffer = priv.the_buffer;
1872 int major_opcode;
1873 static int numopcodes[16];
1874 static const struct m68k_opcode **opcodes[16];
1875 int val;
1876
1877 if (!opcodes[0])
1878 {
1879 /* Speed up the matching by sorting the opcode
1880 table on the upper four bits of the opcode. */
1881 const struct m68k_opcode **opc_pointer[16];
1882
1883 /* First count how many opcodes are in each of the sixteen buckets. */
1884 for (i = 0; i < m68k_numopcodes; i++)
1885 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
1886
1887 /* Then create a sorted table of pointers
1888 that point into the unsorted table. */
1889 opc_pointer[0] = malloc (sizeof (struct m68k_opcode *)
1890 * m68k_numopcodes);
1891 opcodes[0] = opc_pointer[0];
1892
1893 for (i = 1; i < 16; i++)
1894 {
1895 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
1896 opcodes[i] = opc_pointer[i];
1897 }
1898
1899 for (i = 0; i < m68k_numopcodes; i++)
1900 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
1901 }
1902
1903 info->private_data = (PTR) &priv;
1904 /* Tell objdump to use two bytes per chunk
1905 and six bytes per line for displaying raw data. */
1906 info->bytes_per_chunk = 2;
1907 info->bytes_per_line = 6;
1908 info->display_endian = BFD_ENDIAN_BIG;
1909 priv.max_fetched = priv.the_buffer;
1910 priv.insn_start = memaddr;
1911
1912 if (sigsetjmp(priv.bailout, 0) != 0) {
1913 /* Error return. */
1914 return -1;
1915 }
1916
1917 switch (info->mach)
1918 {
1919 default:
1920 case 0:
1921 arch_mask = (unsigned int) -1;
1922 break;
1923 case bfd_mach_m68000:
1924 arch_mask = m68000|m68881|m68851;
1925 break;
1926 case bfd_mach_m68008:
1927 arch_mask = m68008|m68881|m68851;
1928 break;
1929 case bfd_mach_m68010:
1930 arch_mask = m68010|m68881|m68851;
1931 break;
1932 case bfd_mach_m68020:
1933 arch_mask = m68020|m68881|m68851;
1934 break;
1935 case bfd_mach_m68030:
1936 arch_mask = m68030|m68881|m68851;
1937 break;
1938 case bfd_mach_m68040:
1939 arch_mask = m68040|m68881|m68851;
1940 break;
1941 case bfd_mach_m68060:
1942 arch_mask = m68060|m68881|m68851;
1943 break;
1944 case bfd_mach_mcf5200:
1945 arch_mask = mcfisa_a;
1946 break;
1947 case bfd_mach_mcf521x:
1948 case bfd_mach_mcf528x:
1949 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
1950 break;
1951 case bfd_mach_mcf5206e:
1952 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1953 break;
1954 case bfd_mach_mcf5249:
1955 arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
1956 break;
1957 case bfd_mach_mcf5307:
1958 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1959 break;
1960 case bfd_mach_mcf5407:
1961 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
1962 break;
1963 case bfd_mach_mcf547x:
1964 case bfd_mach_mcf548x:
1965 case bfd_mach_mcfv4e:
1966 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
1967 break;
1968 }
1969
1970 fetch_data(info, buffer + 2);
1971 major_opcode = (buffer[0] >> 4) & 15;
1972
1973 for (i = 0; i < numopcodes[major_opcode]; i++)
1974 {
1975 const struct m68k_opcode *opc = opcodes[major_opcode][i];
1976 unsigned long opcode = opc->opcode;
1977 unsigned long match = opc->match;
1978
1979 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
1980 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
1981 /* Only fetch the next two bytes if we need to. */
1982 && (((0xffff & match) == 0)
1983 ||
1984 (fetch_data(info, buffer + 4)
1985 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
1986 && ((0xff & buffer[3] & match) == (0xff & opcode)))
1987 )
1988 && (opc->arch & arch_mask) != 0)
1989 {
1990 /* Don't use for printout the variants of divul and divsl
1991 that have the same register number in two places.
1992 The more general variants will match instead. */
1993 for (d = opc->args; *d; d += 2)
1994 if (d[1] == 'D')
1995 break;
1996
1997 /* Don't use for printout the variants of most floating
1998 point coprocessor instructions which use the same
1999 register number in two places, as above. */
2000 if (*d == '\0')
2001 for (d = opc->args; *d; d += 2)
2002 if (d[1] == 't')
2003 break;
2004
2005 /* Don't match fmovel with more than one register;
2006 wait for fmoveml. */
2007 if (*d == '\0')
2008 {
2009 for (d = opc->args; *d; d += 2)
2010 {
2011 if (d[0] == 's' && d[1] == '8')
2012 {
2013 val = fetch_arg (buffer, d[1], 3, info);
2014 if ((val & (val - 1)) != 0)
2015 break;
2016 }
2017 }
2018 }
2019
2020 if (*d == '\0')
2021 if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
2022 return val;
2023 }
2024 }
2025
2026 /* Handle undefined instructions. */
2027 info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
2028 return 2;
2029 }
2030 /* **** End of m68k-dis.c */
2031 /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */
2032 /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
2033 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2034 2000, 2001, 2003, 2004, 2005
2035 Free Software Foundation, Inc.
2036
2037 This file is part of GDB, GAS, and the GNU binutils.
2038
2039 GDB, GAS, and the GNU binutils are free software; you can redistribute
2040 them and/or modify them under the terms of the GNU General Public
2041 License as published by the Free Software Foundation; either version
2042 1, or (at your option) any later version.
2043
2044 GDB, GAS, and the GNU binutils are distributed in the hope that they
2045 will be useful, but WITHOUT ANY WARRANTY; without even the implied
2046 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
2047 the GNU General Public License for more details.
2048
2049 You should have received a copy of the GNU General Public License
2050 along with this file; see the file COPYING. If not,
2051 see <http://www.gnu.org/licenses/>. */
2052
2053 #define one(x) ((unsigned int) (x) << 16)
2054 #define two(x, y) (((unsigned int) (x) << 16) + (y))
2055
2056 /* The assembler requires that all instances of the same mnemonic must
2057 be consecutive. If they aren't, the assembler will bomb at
2058 runtime. */
2059
2060 const struct m68k_opcode m68k_opcodes[] =
2061 {
2062 {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up },
2063 {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up },
2064
2065 {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2066 {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2067
2068 {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up },
2069 {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2070 {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up },
2071 {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2072
2073 {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2074 {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2075 {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2076
2077 /* The add opcode can generate the adda, addi, and addq instructions. */
2078 {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2079 {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up },
2080 {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up },
2081 {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up },
2082 {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2083 {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2084 {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2085 {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up },
2086 {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up },
2087 {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2088 {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up },
2089 {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2090 {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2091 {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a },
2092 {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2093
2094 {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up },
2095 {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up },
2096 {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up },
2097 {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up },
2098 {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a },
2099 {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up },
2100
2101 {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up },
2102 {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up },
2103 {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2104 {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2105 {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up },
2106 {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2107 {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up },
2108 {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up },
2109 {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up },
2110
2111 /* The and opcode can generate the andi instruction. */
2112 {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up },
2113 {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up },
2114 {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up },
2115 {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up },
2116 {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2117 {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2118 {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up },
2119 {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2120 {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up },
2121 {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2122 {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a },
2123 {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2124 {"and", 4, one(0001100), one(0177700), "#w$w", m68000up },
2125 {"and", 4, one(0001074), one(0177777), "#bCs", m68000up },
2126 {"and", 4, one(0001174), one(0177777), "#wSs", m68000up },
2127 {"and", 2, one(0140100), one(0170700), ";wDd", m68000up },
2128 {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2129
2130 {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up },
2131 {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up },
2132 {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up },
2133 {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up },
2134 {"aslw", 2, one(0160700), one(0177700), "~s", m68000up },
2135 {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a },
2136 {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a },
2137
2138 {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up },
2139 {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up },
2140 {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up },
2141 {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up },
2142 {"asrw", 2, one(0160300), one(0177700), "~s", m68000up },
2143 {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a },
2144 {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a },
2145
2146 {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a },
2147 {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a },
2148 {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a },
2149 {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a },
2150 {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a },
2151 {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a },
2152 {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a },
2153 {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a },
2154 {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a },
2155 {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a },
2156 {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a },
2157 {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a },
2158 {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a },
2159 {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a },
2160
2161 {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2162 {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2163 {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2164 {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2165 {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2166 {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2167 {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2168 {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2169 {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2170 {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2171 {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2172 {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2173 {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2174 {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2175
2176 {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a },
2177 {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a },
2178 {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a },
2179 {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a },
2180 {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a },
2181 {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a },
2182 {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a },
2183 {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a },
2184 {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a },
2185 {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a },
2186 {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a },
2187 {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a },
2188 {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a },
2189 {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a },
2190
2191 {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a },
2192 {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a },
2193 {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a },
2194 {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a },
2195 {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a },
2196 {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a },
2197 {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a },
2198 {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a },
2199 {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a },
2200 {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a },
2201 {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a },
2202 {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a },
2203 {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a },
2204 {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a },
2205
2206 {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a },
2207 {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up },
2208 {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a },
2209
2210 {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2211 {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up },
2212 {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a },
2213
2214 {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2215 {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2216 {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2217 {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2218 {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2219 {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up },
2220 {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2221 {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up },
2222
2223 {"bgnd", 2, one(0045372), one(0177777), "", cpu32 },
2224
2225 {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa},
2226
2227 {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up },
2228
2229 {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a },
2230 {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2231 {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a },
2232
2233 {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a },
2234 {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a },
2235 {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up },
2236 {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
2237
2238 {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a },
2239 {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2240 {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a },
2241
2242 {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a },
2243 {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
2244 {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
2245
2246 {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa},
2247
2248 {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 },
2249
2250 {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2251 {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2252 {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2253 {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2254
2255 {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2256 {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2257 {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2258
2259 {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2260 {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2261 {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2262
2263 {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up },
2264 {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up },
2265
2266 #define SCOPE_LINE (0x1 << 3)
2267 #define SCOPE_PAGE (0x2 << 3)
2268 #define SCOPE_ALL (0x3 << 3)
2269
2270 {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up },
2271 {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up },
2272 {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2273
2274 {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up },
2275 {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a },
2276 {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2277
2278 #undef SCOPE_LINE
2279 #undef SCOPE_PAGE
2280 #undef SCOPE_ALL
2281
2282 {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a },
2283 {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a },
2284 {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a },
2285
2286 {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2287 {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2288 {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2289
2290 {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2291 {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2292
2293 {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
2294 {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2295 {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2296 {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2297 {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
2298 {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2299
2300 {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2301 {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2302 {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up },
2303
2304 /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
2305 {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up },
2306 {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2307 {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2308 {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up },
2309 {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b },
2310 {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2311 {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2312 {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2313 {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2314 {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b },
2315 {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2316 {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up },
2317 {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2318 {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
2319 {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
2320
2321 {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
2322 {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
2323 {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
2324 {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up },
2325 {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up },
2326 {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up },
2327 {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up },
2328 {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up },
2329 {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up },
2330 {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up },
2331 {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up },
2332 {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up },
2333 {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up },
2334 {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up },
2335 {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up },
2336 {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up },
2337
2338 {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv },
2339
2340 {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2341 {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2342 {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv },
2343
2344 {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2345 {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2346
2347 {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv },
2348
2349 {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2350 {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2351 {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv },
2352
2353 {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2354 {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2355
2356 {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up },
2357 {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up },
2358 {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2359 {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2360 {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up },
2361 {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2362 {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up },
2363 {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up },
2364 {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up },
2365
2366 /* The eor opcode can generate the eori instruction. */
2367 {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up },
2368 {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up },
2369 {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up },
2370 {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2371 {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2372 {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up },
2373 {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up },
2374 {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2375 {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2376 {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up },
2377 {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
2378 {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
2379 {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
2380
2381 {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
2382 {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
2383 {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
2384 {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up },
2385
2386 {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a },
2387 {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a },
2388 {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a },
2389
2390 {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa},
2391
2392 /* float stuff starts here */
2393
2394 {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2395 {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2396 {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2397 {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2398 {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2399 {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2400 {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2401 {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2402 {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2403 {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat },
2404 {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2405 {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2406 {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2407 {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2408 {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2409 {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2410
2411 {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2412 {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2413 {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2414 {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2415 {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2416 {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2417 {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2418 {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2419 {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2420 {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2421 {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2422 {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2423 {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2424 {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2425 {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2426 {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up },
2427
2428 {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2429 {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up},
2430 {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2431 {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2432 {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2433 {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up},
2434 {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2435 {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up},
2436 {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up},
2437 {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2438 {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up},
2439 {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2440 {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up},
2441 {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up},
2442 {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up},
2443 {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up},
2444
2445 {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2446 {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2447 {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2448 {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2449 {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2450 {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2451 {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2452 {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2453 {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2454
2455 {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2456 {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2457 {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2458 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2459 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2460 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2461 {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2462 {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2463 {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2464 {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2465 {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2466 {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2467 {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2468 {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2469 {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2470
2471 {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2472 {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2473 {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2474 {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2475 {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2476 {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2477 {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2478 {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2479 {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2480 {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2481 {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2482 {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2483 {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2484 {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2485
2486 {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2487 {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2488 {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2489 {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2490 {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2491 {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2492 {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2493 {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2494 {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2495 {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2496 {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2497 {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2498 {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2499 {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2500
2501 {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2502 {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2503 {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2504 {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2505 {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2506 {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2507 {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2508 {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2509 {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2510
2511 {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2512 {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2513 {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2514 {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2515 {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2516 {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2517 {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2518 {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2519 {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2520
2521 {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2522 {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2523 {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2524 {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2525 {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2526 {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2527 {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2528 {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2529 {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2530
2531 {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat },
2532 {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat },
2533 {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat },
2534 {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat },
2535 {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat },
2536 {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat },
2537 {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat },
2538 {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat },
2539 {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat },
2540 {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat },
2541 {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat },
2542 {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat },
2543 {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat },
2544 {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat },
2545 {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat },
2546 {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat },
2547 {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat },
2548 {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat },
2549 {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat },
2550 {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat },
2551 {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat },
2552 {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat },
2553 {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat },
2554 {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat },
2555 {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat },
2556 {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat },
2557 {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat },
2558 {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat },
2559 {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat },
2560 {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat },
2561 {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat },
2562 {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat },
2563
2564 {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat },
2565 {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat },
2566 {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat },
2567 {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat },
2568 {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat },
2569 {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat },
2570 {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat },
2571 {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat },
2572 {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat },
2573 {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat },
2574 {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat },
2575 {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat },
2576 {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat },
2577 {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat },
2578 {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat },
2579 {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat },
2580 {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat },
2581 {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat },
2582 {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat },
2583 {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat },
2584 {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat },
2585 {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat },
2586 {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat },
2587 {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat },
2588 {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat },
2589 {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat },
2590 {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat },
2591 {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat },
2592 {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat },
2593 {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat },
2594 {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat },
2595 {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat },
2596
2597 {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat },
2598 {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat },
2599 {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat },
2600 {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat },
2601 {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat },
2602 {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat },
2603 {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat },
2604 {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat },
2605 {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat },
2606 {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat },
2607 {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat },
2608 {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat },
2609 {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat },
2610 {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat },
2611 {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat },
2612 {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat },
2613 {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat },
2614 {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat },
2615 {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat },
2616 {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat },
2617 {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat },
2618 {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat },
2619 {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat },
2620 {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat },
2621 {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat },
2622 {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat },
2623 {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat },
2624 {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat },
2625 {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat },
2626 {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat },
2627 {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat },
2628 {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat },
2629
2630 {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2631 {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2632 {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7