sm501: Add missing arbitration control register
[qemu.git] / disas / nios2.c
1 /* Nios II opcode library for QEMU.
2 Copyright (C) 2012-2016 Free Software Foundation, Inc.
3 Contributed by Nigel Gray (ngray@altera.com).
4 Contributed by Mentor Graphics, Inc.
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 Boston, MA 02110-1301, USA. */
20
21 /* This file resembles a concatenation of the following files from
22 binutils:
23
24 include/opcode/nios2.h
25 include/opcode/nios2r1.h
26 include/opcode/nios2r2.h
27 opcodes/nios2-opc.c
28 opcodes/nios2-dis.c
29
30 It has been derived from the original patches which have been
31 relicensed by the contributors as GPL version 2 for inclusion
32 in QEMU. */
33
34 #ifndef _NIOS2_H_
35 #define _NIOS2_H_
36
37 /*#include "bfd.h"*/
38 #include "qemu/osdep.h"
39 #include "disas/bfd.h"
40
41
42 /****************************************************************************
43 * This file contains structures, bit masks and shift counts used
44 * by the GNU toolchain to define the Nios II instruction set and
45 * access various opcode fields.
46 ****************************************************************************/
47
48 /* Instruction encoding formats. */
49 enum iw_format_type {
50 /* R1 formats. */
51 iw_i_type,
52 iw_r_type,
53 iw_j_type,
54 iw_custom_type,
55
56 /* 32-bit R2 formats. */
57 iw_L26_type,
58 iw_F2I16_type,
59 iw_F2X4I12_type,
60 iw_F1X4I12_type,
61 iw_F1X4L17_type,
62 iw_F3X6L5_type,
63 iw_F2X6L10_type,
64 iw_F3X6_type,
65 iw_F3X8_type,
66
67 /* 16-bit R2 formats. */
68 iw_I10_type,
69 iw_T1I7_type,
70 iw_T2I4_type,
71 iw_T1X1I6_type,
72 iw_X1I7_type,
73 iw_L5I4X1_type,
74 iw_T2X1L3_type,
75 iw_T2X1I3_type,
76 iw_T3X1_type,
77 iw_T2X3_type,
78 iw_F1X1_type,
79 iw_X2L5_type,
80 iw_F1I5_type,
81 iw_F2_type
82 };
83
84 /* Identify different overflow situations for error messages. */
85 enum overflow_type
86 {
87 call_target_overflow = 0,
88 branch_target_overflow,
89 address_offset_overflow,
90 signed_immed16_overflow,
91 unsigned_immed16_overflow,
92 unsigned_immed5_overflow,
93 signed_immed12_overflow,
94 custom_opcode_overflow,
95 enumeration_overflow,
96 no_overflow
97 };
98
99 /* This structure holds information for a particular instruction.
100
101 The args field is a string describing the operands. The following
102 letters can appear in the args:
103 c - a 5-bit control register index
104 d - a 5-bit destination register index
105 s - a 5-bit left source register index
106 t - a 5-bit right source register index
107 D - a 3-bit encoded destination register
108 S - a 3-bit encoded left source register
109 T - a 3-bit encoded right source register
110 i - a 16-bit signed immediate
111 j - a 5-bit unsigned immediate
112 k - a (second) 5-bit unsigned immediate
113 l - a 8-bit custom instruction constant
114 m - a 26-bit unsigned immediate
115 o - a 16-bit signed pc-relative offset
116 u - a 16-bit unsigned immediate
117 I - a 12-bit signed immediate
118 M - a 6-bit unsigned immediate
119 N - a 6-bit unsigned immediate with 2-bit shift
120 O - a 10-bit signed pc-relative offset with 1-bit shift
121 P - a 7-bit signed pc-relative offset with 1-bit shift
122 U - a 7-bit unsigned immediate with 2-bit shift
123 V - a 5-bit unsigned immediate with 2-bit shift
124 W - a 4-bit unsigned immediate with 2-bit shift
125 X - a 4-bit unsigned immediate with 1-bit shift
126 Y - a 4-bit unsigned immediate
127 e - an immediate coded as an enumeration for addi.n/subi.n
128 f - an immediate coded as an enumeration for slli.n/srli.n
129 g - an immediate coded as an enumeration for andi.n
130 h - an immediate coded as an enumeration for movi.n
131 R - a reglist for ldwm/stwm or push.n/pop.n
132 B - a base register specifier and option list for ldwm/stwm
133 Literal ',', '(', and ')' characters may also appear in the args as
134 delimiters.
135
136 Note that the args describe the semantics and assembly-language syntax
137 of the operands, not their encoding into the instruction word.
138
139 The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection
140 of bits describing the instruction, notably any relevant hazard
141 information.
142
143 When assembling, the match field contains the opcode template, which
144 is modified by the arguments to produce the actual opcode
145 that is emitted. If pinfo is INSN_MACRO, then this is 0.
146
147 If pinfo is INSN_MACRO, the mask field stores the macro identifier.
148 Otherwise this is a bit mask for the relevant portions of the opcode
149 when disassembling. If the actual opcode anded with the match field
150 equals the opcode field, then we have found the correct instruction. */
151
152 struct nios2_opcode
153 {
154 const char *name; /* The name of the instruction. */
155 const char *args; /* A string describing the arguments for this
156 instruction. */
157 const char *args_test; /* Like args, but with an extra argument for
158 the expected opcode. */
159 unsigned long num_args; /* The number of arguments the instruction
160 takes. */
161 unsigned size; /* Size in bytes of the instruction. */
162 enum iw_format_type format; /* Instruction format. */
163 unsigned long match; /* The basic opcode for the instruction. */
164 unsigned long mask; /* Mask for the opcode field of the
165 instruction. */
166 unsigned long pinfo; /* Is this a real instruction or instruction
167 macro? */
168 enum overflow_type overflow_msg; /* Used to generate informative
169 message when fixup overflows. */
170 };
171
172 /* This value is used in the nios2_opcode.pinfo field to indicate that the
173 instruction is a macro or pseudo-op. This requires special treatment by
174 the assembler, and is used by the disassembler to determine whether to
175 check for a nop. */
176 #define NIOS2_INSN_MACRO 0x80000000
177 #define NIOS2_INSN_MACRO_MOV 0x80000001
178 #define NIOS2_INSN_MACRO_MOVI 0x80000002
179 #define NIOS2_INSN_MACRO_MOVIA 0x80000004
180
181 #define NIOS2_INSN_RELAXABLE 0x40000000
182 #define NIOS2_INSN_UBRANCH 0x00000010
183 #define NIOS2_INSN_CBRANCH 0x00000020
184 #define NIOS2_INSN_CALL 0x00000040
185
186 #define NIOS2_INSN_OPTARG 0x00000080
187
188 /* Register attributes. */
189 #define REG_NORMAL (1<<0) /* Normal registers. */
190 #define REG_CONTROL (1<<1) /* Control registers. */
191 #define REG_COPROCESSOR (1<<2) /* For custom instructions. */
192 #define REG_3BIT (1<<3) /* For R2 CDX instructions. */
193 #define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */
194 #define REG_POP (1<<5) /* For R2 pop.n/push.n. */
195
196 struct nios2_reg
197 {
198 const char *name;
199 const int index;
200 unsigned long regtype;
201 };
202
203 /* Pull in the instruction field accessors, opcodes, and masks. */
204 /*#include "nios2r1.h"*/
205
206 #ifndef _NIOS2R1_H_
207 #define _NIOS2R1_H_
208
209 /* R1 fields. */
210 #define IW_R1_OP_LSB 0
211 #define IW_R1_OP_SIZE 6
212 #define IW_R1_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R1_OP_SIZE))
213 #define IW_R1_OP_SHIFTED_MASK (IW_R1_OP_UNSHIFTED_MASK << IW_R1_OP_LSB)
214 #define GET_IW_R1_OP(W) (((W) >> IW_R1_OP_LSB) & IW_R1_OP_UNSHIFTED_MASK)
215 #define SET_IW_R1_OP(V) (((V) & IW_R1_OP_UNSHIFTED_MASK) << IW_R1_OP_LSB)
216
217 #define IW_I_A_LSB 27
218 #define IW_I_A_SIZE 5
219 #define IW_I_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_A_SIZE))
220 #define IW_I_A_SHIFTED_MASK (IW_I_A_UNSHIFTED_MASK << IW_I_A_LSB)
221 #define GET_IW_I_A(W) (((W) >> IW_I_A_LSB) & IW_I_A_UNSHIFTED_MASK)
222 #define SET_IW_I_A(V) (((V) & IW_I_A_UNSHIFTED_MASK) << IW_I_A_LSB)
223
224 #define IW_I_B_LSB 22
225 #define IW_I_B_SIZE 5
226 #define IW_I_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_B_SIZE))
227 #define IW_I_B_SHIFTED_MASK (IW_I_B_UNSHIFTED_MASK << IW_I_B_LSB)
228 #define GET_IW_I_B(W) (((W) >> IW_I_B_LSB) & IW_I_B_UNSHIFTED_MASK)
229 #define SET_IW_I_B(V) (((V) & IW_I_B_UNSHIFTED_MASK) << IW_I_B_LSB)
230
231 #define IW_I_IMM16_LSB 6
232 #define IW_I_IMM16_SIZE 16
233 #define IW_I_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_IMM16_SIZE))
234 #define IW_I_IMM16_SHIFTED_MASK (IW_I_IMM16_UNSHIFTED_MASK << IW_I_IMM16_LSB)
235 #define GET_IW_I_IMM16(W) (((W) >> IW_I_IMM16_LSB) & IW_I_IMM16_UNSHIFTED_MASK)
236 #define SET_IW_I_IMM16(V) (((V) & IW_I_IMM16_UNSHIFTED_MASK) << IW_I_IMM16_LSB)
237
238 #define IW_R_A_LSB 27
239 #define IW_R_A_SIZE 5
240 #define IW_R_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_A_SIZE))
241 #define IW_R_A_SHIFTED_MASK (IW_R_A_UNSHIFTED_MASK << IW_R_A_LSB)
242 #define GET_IW_R_A(W) (((W) >> IW_R_A_LSB) & IW_R_A_UNSHIFTED_MASK)
243 #define SET_IW_R_A(V) (((V) & IW_R_A_UNSHIFTED_MASK) << IW_R_A_LSB)
244
245 #define IW_R_B_LSB 22
246 #define IW_R_B_SIZE 5
247 #define IW_R_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_B_SIZE))
248 #define IW_R_B_SHIFTED_MASK (IW_R_B_UNSHIFTED_MASK << IW_R_B_LSB)
249 #define GET_IW_R_B(W) (((W) >> IW_R_B_LSB) & IW_R_B_UNSHIFTED_MASK)
250 #define SET_IW_R_B(V) (((V) & IW_R_B_UNSHIFTED_MASK) << IW_R_B_LSB)
251
252 #define IW_R_C_LSB 17
253 #define IW_R_C_SIZE 5
254 #define IW_R_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_C_SIZE))
255 #define IW_R_C_SHIFTED_MASK (IW_R_C_UNSHIFTED_MASK << IW_R_C_LSB)
256 #define GET_IW_R_C(W) (((W) >> IW_R_C_LSB) & IW_R_C_UNSHIFTED_MASK)
257 #define SET_IW_R_C(V) (((V) & IW_R_C_UNSHIFTED_MASK) << IW_R_C_LSB)
258
259 #define IW_R_OPX_LSB 11
260 #define IW_R_OPX_SIZE 6
261 #define IW_R_OPX_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_OPX_SIZE))
262 #define IW_R_OPX_SHIFTED_MASK (IW_R_OPX_UNSHIFTED_MASK << IW_R_OPX_LSB)
263 #define GET_IW_R_OPX(W) (((W) >> IW_R_OPX_LSB) & IW_R_OPX_UNSHIFTED_MASK)
264 #define SET_IW_R_OPX(V) (((V) & IW_R_OPX_UNSHIFTED_MASK) << IW_R_OPX_LSB)
265
266 #define IW_R_IMM5_LSB 6
267 #define IW_R_IMM5_SIZE 5
268 #define IW_R_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_IMM5_SIZE))
269 #define IW_R_IMM5_SHIFTED_MASK (IW_R_IMM5_UNSHIFTED_MASK << IW_R_IMM5_LSB)
270 #define GET_IW_R_IMM5(W) (((W) >> IW_R_IMM5_LSB) & IW_R_IMM5_UNSHIFTED_MASK)
271 #define SET_IW_R_IMM5(V) (((V) & IW_R_IMM5_UNSHIFTED_MASK) << IW_R_IMM5_LSB)
272
273 #define IW_J_IMM26_LSB 6
274 #define IW_J_IMM26_SIZE 26
275 #define IW_J_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_J_IMM26_SIZE))
276 #define IW_J_IMM26_SHIFTED_MASK (IW_J_IMM26_UNSHIFTED_MASK << IW_J_IMM26_LSB)
277 #define GET_IW_J_IMM26(W) (((W) >> IW_J_IMM26_LSB) & IW_J_IMM26_UNSHIFTED_MASK)
278 #define SET_IW_J_IMM26(V) (((V) & IW_J_IMM26_UNSHIFTED_MASK) << IW_J_IMM26_LSB)
279
280 #define IW_CUSTOM_A_LSB 27
281 #define IW_CUSTOM_A_SIZE 5
282 #define IW_CUSTOM_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_A_SIZE))
283 #define IW_CUSTOM_A_SHIFTED_MASK (IW_CUSTOM_A_UNSHIFTED_MASK << IW_CUSTOM_A_LSB)
284 #define GET_IW_CUSTOM_A(W) (((W) >> IW_CUSTOM_A_LSB) & IW_CUSTOM_A_UNSHIFTED_MASK)
285 #define SET_IW_CUSTOM_A(V) (((V) & IW_CUSTOM_A_UNSHIFTED_MASK) << IW_CUSTOM_A_LSB)
286
287 #define IW_CUSTOM_B_LSB 22
288 #define IW_CUSTOM_B_SIZE 5
289 #define IW_CUSTOM_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_B_SIZE))
290 #define IW_CUSTOM_B_SHIFTED_MASK (IW_CUSTOM_B_UNSHIFTED_MASK << IW_CUSTOM_B_LSB)
291 #define GET_IW_CUSTOM_B(W) (((W) >> IW_CUSTOM_B_LSB) & IW_CUSTOM_B_UNSHIFTED_MASK)
292 #define SET_IW_CUSTOM_B(V) (((V) & IW_CUSTOM_B_UNSHIFTED_MASK) << IW_CUSTOM_B_LSB)
293
294 #define IW_CUSTOM_C_LSB 17
295 #define IW_CUSTOM_C_SIZE 5
296 #define IW_CUSTOM_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_C_SIZE))
297 #define IW_CUSTOM_C_SHIFTED_MASK (IW_CUSTOM_C_UNSHIFTED_MASK << IW_CUSTOM_C_LSB)
298 #define GET_IW_CUSTOM_C(W) (((W) >> IW_CUSTOM_C_LSB) & IW_CUSTOM_C_UNSHIFTED_MASK)
299 #define SET_IW_CUSTOM_C(V) (((V) & IW_CUSTOM_C_UNSHIFTED_MASK) << IW_CUSTOM_C_LSB)
300
301 #define IW_CUSTOM_READA_LSB 16
302 #define IW_CUSTOM_READA_SIZE 1
303 #define IW_CUSTOM_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READA_SIZE))
304 #define IW_CUSTOM_READA_SHIFTED_MASK (IW_CUSTOM_READA_UNSHIFTED_MASK << IW_CUSTOM_READA_LSB)
305 #define GET_IW_CUSTOM_READA(W) (((W) >> IW_CUSTOM_READA_LSB) & IW_CUSTOM_READA_UNSHIFTED_MASK)
306 #define SET_IW_CUSTOM_READA(V) (((V) & IW_CUSTOM_READA_UNSHIFTED_MASK) << IW_CUSTOM_READA_LSB)
307
308 #define IW_CUSTOM_READB_LSB 15
309 #define IW_CUSTOM_READB_SIZE 1
310 #define IW_CUSTOM_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READB_SIZE))
311 #define IW_CUSTOM_READB_SHIFTED_MASK (IW_CUSTOM_READB_UNSHIFTED_MASK << IW_CUSTOM_READB_LSB)
312 #define GET_IW_CUSTOM_READB(W) (((W) >> IW_CUSTOM_READB_LSB) & IW_CUSTOM_READB_UNSHIFTED_MASK)
313 #define SET_IW_CUSTOM_READB(V) (((V) & IW_CUSTOM_READB_UNSHIFTED_MASK) << IW_CUSTOM_READB_LSB)
314
315 #define IW_CUSTOM_READC_LSB 14
316 #define IW_CUSTOM_READC_SIZE 1
317 #define IW_CUSTOM_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READC_SIZE))
318 #define IW_CUSTOM_READC_SHIFTED_MASK (IW_CUSTOM_READC_UNSHIFTED_MASK << IW_CUSTOM_READC_LSB)
319 #define GET_IW_CUSTOM_READC(W) (((W) >> IW_CUSTOM_READC_LSB) & IW_CUSTOM_READC_UNSHIFTED_MASK)
320 #define SET_IW_CUSTOM_READC(V) (((V) & IW_CUSTOM_READC_UNSHIFTED_MASK) << IW_CUSTOM_READC_LSB)
321
322 #define IW_CUSTOM_N_LSB 6
323 #define IW_CUSTOM_N_SIZE 8
324 #define IW_CUSTOM_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_N_SIZE))
325 #define IW_CUSTOM_N_SHIFTED_MASK (IW_CUSTOM_N_UNSHIFTED_MASK << IW_CUSTOM_N_LSB)
326 #define GET_IW_CUSTOM_N(W) (((W) >> IW_CUSTOM_N_LSB) & IW_CUSTOM_N_UNSHIFTED_MASK)
327 #define SET_IW_CUSTOM_N(V) (((V) & IW_CUSTOM_N_UNSHIFTED_MASK) << IW_CUSTOM_N_LSB)
328
329 /* R1 opcodes. */
330 #define R1_OP_CALL 0
331 #define R1_OP_JMPI 1
332 #define R1_OP_LDBU 3
333 #define R1_OP_ADDI 4
334 #define R1_OP_STB 5
335 #define R1_OP_BR 6
336 #define R1_OP_LDB 7
337 #define R1_OP_CMPGEI 8
338 #define R1_OP_LDHU 11
339 #define R1_OP_ANDI 12
340 #define R1_OP_STH 13
341 #define R1_OP_BGE 14
342 #define R1_OP_LDH 15
343 #define R1_OP_CMPLTI 16
344 #define R1_OP_INITDA 19
345 #define R1_OP_ORI 20
346 #define R1_OP_STW 21
347 #define R1_OP_BLT 22
348 #define R1_OP_LDW 23
349 #define R1_OP_CMPNEI 24
350 #define R1_OP_FLUSHDA 27
351 #define R1_OP_XORI 28
352 #define R1_OP_BNE 30
353 #define R1_OP_CMPEQI 32
354 #define R1_OP_LDBUIO 35
355 #define R1_OP_MULI 36
356 #define R1_OP_STBIO 37
357 #define R1_OP_BEQ 38
358 #define R1_OP_LDBIO 39
359 #define R1_OP_CMPGEUI 40
360 #define R1_OP_LDHUIO 43
361 #define R1_OP_ANDHI 44
362 #define R1_OP_STHIO 45
363 #define R1_OP_BGEU 46
364 #define R1_OP_LDHIO 47
365 #define R1_OP_CMPLTUI 48
366 #define R1_OP_CUSTOM 50
367 #define R1_OP_INITD 51
368 #define R1_OP_ORHI 52
369 #define R1_OP_STWIO 53
370 #define R1_OP_BLTU 54
371 #define R1_OP_LDWIO 55
372 #define R1_OP_RDPRS 56
373 #define R1_OP_OPX 58
374 #define R1_OP_FLUSHD 59
375 #define R1_OP_XORHI 60
376
377 #define R1_OPX_ERET 1
378 #define R1_OPX_ROLI 2
379 #define R1_OPX_ROL 3
380 #define R1_OPX_FLUSHP 4
381 #define R1_OPX_RET 5
382 #define R1_OPX_NOR 6
383 #define R1_OPX_MULXUU 7
384 #define R1_OPX_CMPGE 8
385 #define R1_OPX_BRET 9
386 #define R1_OPX_ROR 11
387 #define R1_OPX_FLUSHI 12
388 #define R1_OPX_JMP 13
389 #define R1_OPX_AND 14
390 #define R1_OPX_CMPLT 16
391 #define R1_OPX_SLLI 18
392 #define R1_OPX_SLL 19
393 #define R1_OPX_WRPRS 20
394 #define R1_OPX_OR 22
395 #define R1_OPX_MULXSU 23
396 #define R1_OPX_CMPNE 24
397 #define R1_OPX_SRLI 26
398 #define R1_OPX_SRL 27
399 #define R1_OPX_NEXTPC 28
400 #define R1_OPX_CALLR 29
401 #define R1_OPX_XOR 30
402 #define R1_OPX_MULXSS 31
403 #define R1_OPX_CMPEQ 32
404 #define R1_OPX_DIVU 36
405 #define R1_OPX_DIV 37
406 #define R1_OPX_RDCTL 38
407 #define R1_OPX_MUL 39
408 #define R1_OPX_CMPGEU 40
409 #define R1_OPX_INITI 41
410 #define R1_OPX_TRAP 45
411 #define R1_OPX_WRCTL 46
412 #define R1_OPX_CMPLTU 48
413 #define R1_OPX_ADD 49
414 #define R1_OPX_BREAK 52
415 #define R1_OPX_SYNC 54
416 #define R1_OPX_SUB 57
417 #define R1_OPX_SRAI 58
418 #define R1_OPX_SRA 59
419
420 /* Some convenience macros for R1 encodings, for use in instruction tables.
421 MATCH_R1_OPX0(NAME) and MASK_R1_OPX0 are used for R-type instructions
422 with 3 register operands and constant 0 in the immediate field.
423 The general forms are MATCH_R1_OPX(NAME, A, B, C) where the arguments specify
424 constant values and MASK_R1_OPX(A, B, C, N) where the arguments are booleans
425 that are true if the field should be included in the mask.
426 */
427 #define MATCH_R1_OP(NAME) \
428 (SET_IW_R1_OP (R1_OP_##NAME))
429 #define MASK_R1_OP \
430 IW_R1_OP_SHIFTED_MASK
431
432 #define MATCH_R1_OPX0(NAME) \
433 (SET_IW_R1_OP (R1_OP_OPX) | SET_IW_R_OPX (R1_OPX_##NAME))
434 #define MASK_R1_OPX0 \
435 (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK | IW_R_IMM5_SHIFTED_MASK)
436
437 #define MATCH_R1_OPX(NAME, A, B, C) \
438 (MATCH_R1_OPX0 (NAME) | SET_IW_R_A (A) | SET_IW_R_B (B) | SET_IW_R_C (C))
439 #define MASK_R1_OPX(A, B, C, N) \
440 (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK \
441 | (A ? IW_R_A_SHIFTED_MASK : 0) \
442 | (B ? IW_R_B_SHIFTED_MASK : 0) \
443 | (C ? IW_R_C_SHIFTED_MASK : 0) \
444 | (N ? IW_R_IMM5_SHIFTED_MASK : 0))
445
446 /* And here's the match/mask macros for the R1 instruction set. */
447 #define MATCH_R1_ADD MATCH_R1_OPX0 (ADD)
448 #define MASK_R1_ADD MASK_R1_OPX0
449 #define MATCH_R1_ADDI MATCH_R1_OP (ADDI)
450 #define MASK_R1_ADDI MASK_R1_OP
451 #define MATCH_R1_AND MATCH_R1_OPX0 (AND)
452 #define MASK_R1_AND MASK_R1_OPX0
453 #define MATCH_R1_ANDHI MATCH_R1_OP (ANDHI)
454 #define MASK_R1_ANDHI MASK_R1_OP
455 #define MATCH_R1_ANDI MATCH_R1_OP (ANDI)
456 #define MASK_R1_ANDI MASK_R1_OP
457 #define MATCH_R1_BEQ MATCH_R1_OP (BEQ)
458 #define MASK_R1_BEQ MASK_R1_OP
459 #define MATCH_R1_BGE MATCH_R1_OP (BGE)
460 #define MASK_R1_BGE MASK_R1_OP
461 #define MATCH_R1_BGEU MATCH_R1_OP (BGEU)
462 #define MASK_R1_BGEU MASK_R1_OP
463 #define MATCH_R1_BGT MATCH_R1_OP (BLT)
464 #define MASK_R1_BGT MASK_R1_OP
465 #define MATCH_R1_BGTU MATCH_R1_OP (BLTU)
466 #define MASK_R1_BGTU MASK_R1_OP
467 #define MATCH_R1_BLE MATCH_R1_OP (BGE)
468 #define MASK_R1_BLE MASK_R1_OP
469 #define MATCH_R1_BLEU MATCH_R1_OP (BGEU)
470 #define MASK_R1_BLEU MASK_R1_OP
471 #define MATCH_R1_BLT MATCH_R1_OP (BLT)
472 #define MASK_R1_BLT MASK_R1_OP
473 #define MATCH_R1_BLTU MATCH_R1_OP (BLTU)
474 #define MASK_R1_BLTU MASK_R1_OP
475 #define MATCH_R1_BNE MATCH_R1_OP (BNE)
476 #define MASK_R1_BNE MASK_R1_OP
477 #define MATCH_R1_BR MATCH_R1_OP (BR)
478 #define MASK_R1_BR MASK_R1_OP | IW_I_A_SHIFTED_MASK | IW_I_B_SHIFTED_MASK
479 #define MATCH_R1_BREAK MATCH_R1_OPX (BREAK, 0, 0, 0x1e)
480 #define MASK_R1_BREAK MASK_R1_OPX (1, 1, 1, 0)
481 #define MATCH_R1_BRET MATCH_R1_OPX (BRET, 0x1e, 0, 0)
482 #define MASK_R1_BRET MASK_R1_OPX (1, 1, 1, 1)
483 #define MATCH_R1_CALL MATCH_R1_OP (CALL)
484 #define MASK_R1_CALL MASK_R1_OP
485 #define MATCH_R1_CALLR MATCH_R1_OPX (CALLR, 0, 0, 0x1f)
486 #define MASK_R1_CALLR MASK_R1_OPX (0, 1, 1, 1)
487 #define MATCH_R1_CMPEQ MATCH_R1_OPX0 (CMPEQ)
488 #define MASK_R1_CMPEQ MASK_R1_OPX0
489 #define MATCH_R1_CMPEQI MATCH_R1_OP (CMPEQI)
490 #define MASK_R1_CMPEQI MASK_R1_OP
491 #define MATCH_R1_CMPGE MATCH_R1_OPX0 (CMPGE)
492 #define MASK_R1_CMPGE MASK_R1_OPX0
493 #define MATCH_R1_CMPGEI MATCH_R1_OP (CMPGEI)
494 #define MASK_R1_CMPGEI MASK_R1_OP
495 #define MATCH_R1_CMPGEU MATCH_R1_OPX0 (CMPGEU)
496 #define MASK_R1_CMPGEU MASK_R1_OPX0
497 #define MATCH_R1_CMPGEUI MATCH_R1_OP (CMPGEUI)
498 #define MASK_R1_CMPGEUI MASK_R1_OP
499 #define MATCH_R1_CMPGT MATCH_R1_OPX0 (CMPLT)
500 #define MASK_R1_CMPGT MASK_R1_OPX0
501 #define MATCH_R1_CMPGTI MATCH_R1_OP (CMPGEI)
502 #define MASK_R1_CMPGTI MASK_R1_OP
503 #define MATCH_R1_CMPGTU MATCH_R1_OPX0 (CMPLTU)
504 #define MASK_R1_CMPGTU MASK_R1_OPX0
505 #define MATCH_R1_CMPGTUI MATCH_R1_OP (CMPGEUI)
506 #define MASK_R1_CMPGTUI MASK_R1_OP
507 #define MATCH_R1_CMPLE MATCH_R1_OPX0 (CMPGE)
508 #define MASK_R1_CMPLE MASK_R1_OPX0
509 #define MATCH_R1_CMPLEI MATCH_R1_OP (CMPLTI)
510 #define MASK_R1_CMPLEI MASK_R1_OP
511 #define MATCH_R1_CMPLEU MATCH_R1_OPX0 (CMPGEU)
512 #define MASK_R1_CMPLEU MASK_R1_OPX0
513 #define MATCH_R1_CMPLEUI MATCH_R1_OP (CMPLTUI)
514 #define MASK_R1_CMPLEUI MASK_R1_OP
515 #define MATCH_R1_CMPLT MATCH_R1_OPX0 (CMPLT)
516 #define MASK_R1_CMPLT MASK_R1_OPX0
517 #define MATCH_R1_CMPLTI MATCH_R1_OP (CMPLTI)
518 #define MASK_R1_CMPLTI MASK_R1_OP
519 #define MATCH_R1_CMPLTU MATCH_R1_OPX0 (CMPLTU)
520 #define MASK_R1_CMPLTU MASK_R1_OPX0
521 #define MATCH_R1_CMPLTUI MATCH_R1_OP (CMPLTUI)
522 #define MASK_R1_CMPLTUI MASK_R1_OP
523 #define MATCH_R1_CMPNE MATCH_R1_OPX0 (CMPNE)
524 #define MASK_R1_CMPNE MASK_R1_OPX0
525 #define MATCH_R1_CMPNEI MATCH_R1_OP (CMPNEI)
526 #define MASK_R1_CMPNEI MASK_R1_OP
527 #define MATCH_R1_CUSTOM MATCH_R1_OP (CUSTOM)
528 #define MASK_R1_CUSTOM MASK_R1_OP
529 #define MATCH_R1_DIV MATCH_R1_OPX0 (DIV)
530 #define MASK_R1_DIV MASK_R1_OPX0
531 #define MATCH_R1_DIVU MATCH_R1_OPX0 (DIVU)
532 #define MASK_R1_DIVU MASK_R1_OPX0
533 #define MATCH_R1_ERET MATCH_R1_OPX (ERET, 0x1d, 0x1e, 0)
534 #define MASK_R1_ERET MASK_R1_OPX (1, 1, 1, 1)
535 #define MATCH_R1_FLUSHD MATCH_R1_OP (FLUSHD) | SET_IW_I_B (0)
536 #define MASK_R1_FLUSHD MASK_R1_OP | IW_I_B_SHIFTED_MASK
537 #define MATCH_R1_FLUSHDA MATCH_R1_OP (FLUSHDA) | SET_IW_I_B (0)
538 #define MASK_R1_FLUSHDA MASK_R1_OP | IW_I_B_SHIFTED_MASK
539 #define MATCH_R1_FLUSHI MATCH_R1_OPX (FLUSHI, 0, 0, 0)
540 #define MASK_R1_FLUSHI MASK_R1_OPX (0, 1, 1, 1)
541 #define MATCH_R1_FLUSHP MATCH_R1_OPX (FLUSHP, 0, 0, 0)
542 #define MASK_R1_FLUSHP MASK_R1_OPX (1, 1, 1, 1)
543 #define MATCH_R1_INITD MATCH_R1_OP (INITD) | SET_IW_I_B (0)
544 #define MASK_R1_INITD MASK_R1_OP | IW_I_B_SHIFTED_MASK
545 #define MATCH_R1_INITDA MATCH_R1_OP (INITDA) | SET_IW_I_B (0)
546 #define MASK_R1_INITDA MASK_R1_OP | IW_I_B_SHIFTED_MASK
547 #define MATCH_R1_INITI MATCH_R1_OPX (INITI, 0, 0, 0)
548 #define MASK_R1_INITI MASK_R1_OPX (0, 1, 1, 1)
549 #define MATCH_R1_JMP MATCH_R1_OPX (JMP, 0, 0, 0)
550 #define MASK_R1_JMP MASK_R1_OPX (0, 1, 1, 1)
551 #define MATCH_R1_JMPI MATCH_R1_OP (JMPI)
552 #define MASK_R1_JMPI MASK_R1_OP
553 #define MATCH_R1_LDB MATCH_R1_OP (LDB)
554 #define MASK_R1_LDB MASK_R1_OP
555 #define MATCH_R1_LDBIO MATCH_R1_OP (LDBIO)
556 #define MASK_R1_LDBIO MASK_R1_OP
557 #define MATCH_R1_LDBU MATCH_R1_OP (LDBU)
558 #define MASK_R1_LDBU MASK_R1_OP
559 #define MATCH_R1_LDBUIO MATCH_R1_OP (LDBUIO)
560 #define MASK_R1_LDBUIO MASK_R1_OP
561 #define MATCH_R1_LDH MATCH_R1_OP (LDH)
562 #define MASK_R1_LDH MASK_R1_OP
563 #define MATCH_R1_LDHIO MATCH_R1_OP (LDHIO)
564 #define MASK_R1_LDHIO MASK_R1_OP
565 #define MATCH_R1_LDHU MATCH_R1_OP (LDHU)
566 #define MASK_R1_LDHU MASK_R1_OP
567 #define MATCH_R1_LDHUIO MATCH_R1_OP (LDHUIO)
568 #define MASK_R1_LDHUIO MASK_R1_OP
569 #define MATCH_R1_LDW MATCH_R1_OP (LDW)
570 #define MASK_R1_LDW MASK_R1_OP
571 #define MATCH_R1_LDWIO MATCH_R1_OP (LDWIO)
572 #define MASK_R1_LDWIO MASK_R1_OP
573 #define MATCH_R1_MOV MATCH_R1_OPX (ADD, 0, 0, 0)
574 #define MASK_R1_MOV MASK_R1_OPX (0, 1, 0, 1)
575 #define MATCH_R1_MOVHI MATCH_R1_OP (ORHI) | SET_IW_I_A (0)
576 #define MASK_R1_MOVHI MASK_R1_OP | IW_I_A_SHIFTED_MASK
577 #define MATCH_R1_MOVI MATCH_R1_OP (ADDI) | SET_IW_I_A (0)
578 #define MASK_R1_MOVI MASK_R1_OP | IW_I_A_SHIFTED_MASK
579 #define MATCH_R1_MOVUI MATCH_R1_OP (ORI) | SET_IW_I_A (0)
580 #define MASK_R1_MOVUI MASK_R1_OP | IW_I_A_SHIFTED_MASK
581 #define MATCH_R1_MUL MATCH_R1_OPX0 (MUL)
582 #define MASK_R1_MUL MASK_R1_OPX0
583 #define MATCH_R1_MULI MATCH_R1_OP (MULI)
584 #define MASK_R1_MULI MASK_R1_OP
585 #define MATCH_R1_MULXSS MATCH_R1_OPX0 (MULXSS)
586 #define MASK_R1_MULXSS MASK_R1_OPX0
587 #define MATCH_R1_MULXSU MATCH_R1_OPX0 (MULXSU)
588 #define MASK_R1_MULXSU MASK_R1_OPX0
589 #define MATCH_R1_MULXUU MATCH_R1_OPX0 (MULXUU)
590 #define MASK_R1_MULXUU MASK_R1_OPX0
591 #define MATCH_R1_NEXTPC MATCH_R1_OPX (NEXTPC, 0, 0, 0)
592 #define MASK_R1_NEXTPC MASK_R1_OPX (1, 1, 0, 1)
593 #define MATCH_R1_NOP MATCH_R1_OPX (ADD, 0, 0, 0)
594 #define MASK_R1_NOP MASK_R1_OPX (1, 1, 1, 1)
595 #define MATCH_R1_NOR MATCH_R1_OPX0 (NOR)
596 #define MASK_R1_NOR MASK_R1_OPX0
597 #define MATCH_R1_OR MATCH_R1_OPX0 (OR)
598 #define MASK_R1_OR MASK_R1_OPX0
599 #define MATCH_R1_ORHI MATCH_R1_OP (ORHI)
600 #define MASK_R1_ORHI MASK_R1_OP
601 #define MATCH_R1_ORI MATCH_R1_OP (ORI)
602 #define MASK_R1_ORI MASK_R1_OP
603 #define MATCH_R1_RDCTL MATCH_R1_OPX (RDCTL, 0, 0, 0)
604 #define MASK_R1_RDCTL MASK_R1_OPX (1, 1, 0, 0)
605 #define MATCH_R1_RDPRS MATCH_R1_OP (RDPRS)
606 #define MASK_R1_RDPRS MASK_R1_OP
607 #define MATCH_R1_RET MATCH_R1_OPX (RET, 0x1f, 0, 0)
608 #define MASK_R1_RET MASK_R1_OPX (1, 1, 1, 1)
609 #define MATCH_R1_ROL MATCH_R1_OPX0 (ROL)
610 #define MASK_R1_ROL MASK_R1_OPX0
611 #define MATCH_R1_ROLI MATCH_R1_OPX (ROLI, 0, 0, 0)
612 #define MASK_R1_ROLI MASK_R1_OPX (0, 1, 0, 0)
613 #define MATCH_R1_ROR MATCH_R1_OPX0 (ROR)
614 #define MASK_R1_ROR MASK_R1_OPX0
615 #define MATCH_R1_SLL MATCH_R1_OPX0 (SLL)
616 #define MASK_R1_SLL MASK_R1_OPX0
617 #define MATCH_R1_SLLI MATCH_R1_OPX (SLLI, 0, 0, 0)
618 #define MASK_R1_SLLI MASK_R1_OPX (0, 1, 0, 0)
619 #define MATCH_R1_SRA MATCH_R1_OPX0 (SRA)
620 #define MASK_R1_SRA MASK_R1_OPX0
621 #define MATCH_R1_SRAI MATCH_R1_OPX (SRAI, 0, 0, 0)
622 #define MASK_R1_SRAI MASK_R1_OPX (0, 1, 0, 0)
623 #define MATCH_R1_SRL MATCH_R1_OPX0 (SRL)
624 #define MASK_R1_SRL MASK_R1_OPX0
625 #define MATCH_R1_SRLI MATCH_R1_OPX (SRLI, 0, 0, 0)
626 #define MASK_R1_SRLI MASK_R1_OPX (0, 1, 0, 0)
627 #define MATCH_R1_STB MATCH_R1_OP (STB)
628 #define MASK_R1_STB MASK_R1_OP
629 #define MATCH_R1_STBIO MATCH_R1_OP (STBIO)
630 #define MASK_R1_STBIO MASK_R1_OP
631 #define MATCH_R1_STH MATCH_R1_OP (STH)
632 #define MASK_R1_STH MASK_R1_OP
633 #define MATCH_R1_STHIO MATCH_R1_OP (STHIO)
634 #define MASK_R1_STHIO MASK_R1_OP
635 #define MATCH_R1_STW MATCH_R1_OP (STW)
636 #define MASK_R1_STW MASK_R1_OP
637 #define MATCH_R1_STWIO MATCH_R1_OP (STWIO)
638 #define MASK_R1_STWIO MASK_R1_OP
639 #define MATCH_R1_SUB MATCH_R1_OPX0 (SUB)
640 #define MASK_R1_SUB MASK_R1_OPX0
641 #define MATCH_R1_SUBI MATCH_R1_OP (ADDI)
642 #define MASK_R1_SUBI MASK_R1_OP
643 #define MATCH_R1_SYNC MATCH_R1_OPX (SYNC, 0, 0, 0)
644 #define MASK_R1_SYNC MASK_R1_OPX (1, 1, 1, 1)
645 #define MATCH_R1_TRAP MATCH_R1_OPX (TRAP, 0, 0, 0x1d)
646 #define MASK_R1_TRAP MASK_R1_OPX (1, 1, 1, 0)
647 #define MATCH_R1_WRCTL MATCH_R1_OPX (WRCTL, 0, 0, 0)
648 #define MASK_R1_WRCTL MASK_R1_OPX (0, 1, 1, 0)
649 #define MATCH_R1_WRPRS MATCH_R1_OPX (WRPRS, 0, 0, 0)
650 #define MASK_R1_WRPRS MASK_R1_OPX (0, 1, 0, 1)
651 #define MATCH_R1_XOR MATCH_R1_OPX0 (XOR)
652 #define MASK_R1_XOR MASK_R1_OPX0
653 #define MATCH_R1_XORHI MATCH_R1_OP (XORHI)
654 #define MASK_R1_XORHI MASK_R1_OP
655 #define MATCH_R1_XORI MATCH_R1_OP (XORI)
656 #define MASK_R1_XORI MASK_R1_OP
657
658 #endif /* _NIOS2R1_H */
659
660 /*#include "nios2r2.h"*/
661
662 #ifndef _NIOS2R2_H_
663 #define _NIOS2R2_H_
664
665 /* Fields for 32-bit R2 instructions. */
666
667 #define IW_R2_OP_LSB 0
668 #define IW_R2_OP_SIZE 6
669 #define IW_R2_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R2_OP_SIZE))
670 #define IW_R2_OP_SHIFTED_MASK (IW_R2_OP_UNSHIFTED_MASK << IW_R2_OP_LSB)
671 #define GET_IW_R2_OP(W) (((W) >> IW_R2_OP_LSB) & IW_R2_OP_UNSHIFTED_MASK)
672 #define SET_IW_R2_OP(V) (((V) & IW_R2_OP_UNSHIFTED_MASK) << IW_R2_OP_LSB)
673
674 #define IW_L26_IMM26_LSB 6
675 #define IW_L26_IMM26_SIZE 26
676 #define IW_L26_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L26_IMM26_SIZE))
677 #define IW_L26_IMM26_SHIFTED_MASK (IW_L26_IMM26_UNSHIFTED_MASK << IW_L26_IMM26_LSB)
678 #define GET_IW_L26_IMM26(W) (((W) >> IW_L26_IMM26_LSB) & IW_L26_IMM26_UNSHIFTED_MASK)
679 #define SET_IW_L26_IMM26(V) (((V) & IW_L26_IMM26_UNSHIFTED_MASK) << IW_L26_IMM26_LSB)
680
681 #define IW_F2I16_A_LSB 6
682 #define IW_F2I16_A_SIZE 5
683 #define IW_F2I16_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_A_SIZE))
684 #define IW_F2I16_A_SHIFTED_MASK (IW_F2I16_A_UNSHIFTED_MASK << IW_F2I16_A_LSB)
685 #define GET_IW_F2I16_A(W) (((W) >> IW_F2I16_A_LSB) & IW_F2I16_A_UNSHIFTED_MASK)
686 #define SET_IW_F2I16_A(V) (((V) & IW_F2I16_A_UNSHIFTED_MASK) << IW_F2I16_A_LSB)
687
688 #define IW_F2I16_B_LSB 11
689 #define IW_F2I16_B_SIZE 5
690 #define IW_F2I16_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_B_SIZE))
691 #define IW_F2I16_B_SHIFTED_MASK (IW_F2I16_B_UNSHIFTED_MASK << IW_F2I16_B_LSB)
692 #define GET_IW_F2I16_B(W) (((W) >> IW_F2I16_B_LSB) & IW_F2I16_B_UNSHIFTED_MASK)
693 #define SET_IW_F2I16_B(V) (((V) & IW_F2I16_B_UNSHIFTED_MASK) << IW_F2I16_B_LSB)
694
695 #define IW_F2I16_IMM16_LSB 16
696 #define IW_F2I16_IMM16_SIZE 16
697 #define IW_F2I16_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_IMM16_SIZE))
698 #define IW_F2I16_IMM16_SHIFTED_MASK (IW_F2I16_IMM16_UNSHIFTED_MASK << IW_F2I16_IMM16_LSB)
699 #define GET_IW_F2I16_IMM16(W) (((W) >> IW_F2I16_IMM16_LSB) & IW_F2I16_IMM16_UNSHIFTED_MASK)
700 #define SET_IW_F2I16_IMM16(V) (((V) & IW_F2I16_IMM16_UNSHIFTED_MASK) << IW_F2I16_IMM16_LSB)
701
702 /* Common to all three I12-group formats F2X4I12, F1X4I12, F1X4L17. */
703 #define IW_I12_X_LSB 28
704 #define IW_I12_X_SIZE 4
705 #define IW_I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I12_X_SIZE))
706 #define IW_I12_X_SHIFTED_MASK (IW_I12_X_UNSHIFTED_MASK << IW_I12_X_LSB)
707 #define GET_IW_I12_X(W) (((W) >> IW_I12_X_LSB) & IW_I12_X_UNSHIFTED_MASK)
708 #define SET_IW_I12_X(V) (((V) & IW_I12_X_UNSHIFTED_MASK) << IW_I12_X_LSB)
709
710 #define IW_F2X4I12_A_LSB 6
711 #define IW_F2X4I12_A_SIZE 5
712 #define IW_F2X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_A_SIZE))
713 #define IW_F2X4I12_A_SHIFTED_MASK (IW_F2X4I12_A_UNSHIFTED_MASK << IW_F2X4I12_A_LSB)
714 #define GET_IW_F2X4I12_A(W) (((W) >> IW_F2X4I12_A_LSB) & IW_F2X4I12_A_UNSHIFTED_MASK)
715 #define SET_IW_F2X4I12_A(V) (((V) & IW_F2X4I12_A_UNSHIFTED_MASK) << IW_F2X4I12_A_LSB)
716
717 #define IW_F2X4I12_B_LSB 11
718 #define IW_F2X4I12_B_SIZE 5
719 #define IW_F2X4I12_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_B_SIZE))
720 #define IW_F2X4I12_B_SHIFTED_MASK (IW_F2X4I12_B_UNSHIFTED_MASK << IW_F2X4I12_B_LSB)
721 #define GET_IW_F2X4I12_B(W) (((W) >> IW_F2X4I12_B_LSB) & IW_F2X4I12_B_UNSHIFTED_MASK)
722 #define SET_IW_F2X4I12_B(V) (((V) & IW_F2X4I12_B_UNSHIFTED_MASK) << IW_F2X4I12_B_LSB)
723
724 #define IW_F2X4I12_IMM12_LSB 16
725 #define IW_F2X4I12_IMM12_SIZE 12
726 #define IW_F2X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_IMM12_SIZE))
727 #define IW_F2X4I12_IMM12_SHIFTED_MASK (IW_F2X4I12_IMM12_UNSHIFTED_MASK << IW_F2X4I12_IMM12_LSB)
728 #define GET_IW_F2X4I12_IMM12(W) (((W) >> IW_F2X4I12_IMM12_LSB) & IW_F2X4I12_IMM12_UNSHIFTED_MASK)
729 #define SET_IW_F2X4I12_IMM12(V) (((V) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) << IW_F2X4I12_IMM12_LSB)
730
731 #define IW_F1X4I12_A_LSB 6
732 #define IW_F1X4I12_A_SIZE 5
733 #define IW_F1X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_A_SIZE))
734 #define IW_F1X4I12_A_SHIFTED_MASK (IW_F1X4I12_A_UNSHIFTED_MASK << IW_F1X4I12_A_LSB)
735 #define GET_IW_F1X4I12_A(W) (((W) >> IW_F1X4I12_A_LSB) & IW_F1X4I12_A_UNSHIFTED_MASK)
736 #define SET_IW_F1X4I12_A(V) (((V) & IW_F1X4I12_A_UNSHIFTED_MASK) << IW_F1X4I12_A_LSB)
737
738 #define IW_F1X4I12_X_LSB 11
739 #define IW_F1X4I12_X_SIZE 5
740 #define IW_F1X4I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_X_SIZE))
741 #define IW_F1X4I12_X_SHIFTED_MASK (IW_F1X4I12_X_UNSHIFTED_MASK << IW_F1X4I12_X_LSB)
742 #define GET_IW_F1X4I12_X(W) (((W) >> IW_F1X4I12_X_LSB) & IW_F1X4I12_X_UNSHIFTED_MASK)
743 #define SET_IW_F1X4I12_X(V) (((V) & IW_F1X4I12_X_UNSHIFTED_MASK) << IW_F1X4I12_X_LSB)
744
745 #define IW_F1X4I12_IMM12_LSB 16
746 #define IW_F1X4I12_IMM12_SIZE 12
747 #define IW_F1X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_IMM12_SIZE))
748 #define IW_F1X4I12_IMM12_SHIFTED_MASK (IW_F1X4I12_IMM12_UNSHIFTED_MASK << IW_F1X4I12_IMM12_LSB)
749 #define GET_IW_F1X4I12_IMM12(W) (((W) >> IW_F1X4I12_IMM12_LSB) & IW_F1X4I12_IMM12_UNSHIFTED_MASK)
750 #define SET_IW_F1X4I12_IMM12(V) (((V) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) << IW_F1X4I12_IMM12_LSB)
751
752 #define IW_F1X4L17_A_LSB 6
753 #define IW_F1X4L17_A_SIZE 5
754 #define IW_F1X4L17_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_A_SIZE))
755 #define IW_F1X4L17_A_SHIFTED_MASK (IW_F1X4L17_A_UNSHIFTED_MASK << IW_F1X4L17_A_LSB)
756 #define GET_IW_F1X4L17_A(W) (((W) >> IW_F1X4L17_A_LSB) & IW_F1X4L17_A_UNSHIFTED_MASK)
757 #define SET_IW_F1X4L17_A(V) (((V) & IW_F1X4L17_A_UNSHIFTED_MASK) << IW_F1X4L17_A_LSB)
758
759 #define IW_F1X4L17_ID_LSB 11
760 #define IW_F1X4L17_ID_SIZE 1
761 #define IW_F1X4L17_ID_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_ID_SIZE))
762 #define IW_F1X4L17_ID_SHIFTED_MASK (IW_F1X4L17_ID_UNSHIFTED_MASK << IW_F1X4L17_ID_LSB)
763 #define GET_IW_F1X4L17_ID(W) (((W) >> IW_F1X4L17_ID_LSB) & IW_F1X4L17_ID_UNSHIFTED_MASK)
764 #define SET_IW_F1X4L17_ID(V) (((V) & IW_F1X4L17_ID_UNSHIFTED_MASK) << IW_F1X4L17_ID_LSB)
765
766 #define IW_F1X4L17_WB_LSB 12
767 #define IW_F1X4L17_WB_SIZE 1
768 #define IW_F1X4L17_WB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_WB_SIZE))
769 #define IW_F1X4L17_WB_SHIFTED_MASK (IW_F1X4L17_WB_UNSHIFTED_MASK << IW_F1X4L17_WB_LSB)
770 #define GET_IW_F1X4L17_WB(W) (((W) >> IW_F1X4L17_WB_LSB) & IW_F1X4L17_WB_UNSHIFTED_MASK)
771 #define SET_IW_F1X4L17_WB(V) (((V) & IW_F1X4L17_WB_UNSHIFTED_MASK) << IW_F1X4L17_WB_LSB)
772
773 #define IW_F1X4L17_RS_LSB 13
774 #define IW_F1X4L17_RS_SIZE 1
775 #define IW_F1X4L17_RS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RS_SIZE))
776 #define IW_F1X4L17_RS_SHIFTED_MASK (IW_F1X4L17_RS_UNSHIFTED_MASK << IW_F1X4L17_RS_LSB)
777 #define GET_IW_F1X4L17_RS(W) (((W) >> IW_F1X4L17_RS_LSB) & IW_F1X4L17_RS_UNSHIFTED_MASK)
778 #define SET_IW_F1X4L17_RS(V) (((V) & IW_F1X4L17_RS_UNSHIFTED_MASK) << IW_F1X4L17_RS_LSB)
779
780 #define IW_F1X4L17_PC_LSB 14
781 #define IW_F1X4L17_PC_SIZE 1
782 #define IW_F1X4L17_PC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_PC_SIZE))
783 #define IW_F1X4L17_PC_SHIFTED_MASK (IW_F1X4L17_PC_UNSHIFTED_MASK << IW_F1X4L17_PC_LSB)
784 #define GET_IW_F1X4L17_PC(W) (((W) >> IW_F1X4L17_PC_LSB) & IW_F1X4L17_PC_UNSHIFTED_MASK)
785 #define SET_IW_F1X4L17_PC(V) (((V) & IW_F1X4L17_PC_UNSHIFTED_MASK) << IW_F1X4L17_PC_LSB)
786
787 #define IW_F1X4L17_RSV_LSB 15
788 #define IW_F1X4L17_RSV_SIZE 1
789 #define IW_F1X4L17_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RSV_SIZE))
790 #define IW_F1X4L17_RSV_SHIFTED_MASK (IW_F1X4L17_RSV_UNSHIFTED_MASK << IW_F1X4L17_RSV_LSB)
791 #define GET_IW_F1X4L17_RSV(W) (((W) >> IW_F1X4L17_RSV_LSB) & IW_F1X4L17_RSV_UNSHIFTED_MASK)
792 #define SET_IW_F1X4L17_RSV(V) (((V) & IW_F1X4L17_RSV_UNSHIFTED_MASK) << IW_F1X4L17_RSV_LSB)
793
794 #define IW_F1X4L17_REGMASK_LSB 16
795 #define IW_F1X4L17_REGMASK_SIZE 12
796 #define IW_F1X4L17_REGMASK_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_REGMASK_SIZE))
797 #define IW_F1X4L17_REGMASK_SHIFTED_MASK (IW_F1X4L17_REGMASK_UNSHIFTED_MASK << IW_F1X4L17_REGMASK_LSB)
798 #define GET_IW_F1X4L17_REGMASK(W) (((W) >> IW_F1X4L17_REGMASK_LSB) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK)
799 #define SET_IW_F1X4L17_REGMASK(V) (((V) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) << IW_F1X4L17_REGMASK_LSB)
800
801 /* Shared by OPX-group formats F3X6L5, F2X6L10, F3X6. */
802 #define IW_OPX_X_LSB 26
803 #define IW_OPX_X_SIZE 6
804 #define IW_OPX_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_OPX_X_SIZE))
805 #define IW_OPX_X_SHIFTED_MASK (IW_OPX_X_UNSHIFTED_MASK << IW_OPX_X_LSB)
806 #define GET_IW_OPX_X(W) (((W) >> IW_OPX_X_LSB) & IW_OPX_X_UNSHIFTED_MASK)
807 #define SET_IW_OPX_X(V) (((V) & IW_OPX_X_UNSHIFTED_MASK) << IW_OPX_X_LSB)
808
809 /* F3X6L5 accessors are also used for F3X6 formats. */
810 #define IW_F3X6L5_A_LSB 6
811 #define IW_F3X6L5_A_SIZE 5
812 #define IW_F3X6L5_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_A_SIZE))
813 #define IW_F3X6L5_A_SHIFTED_MASK (IW_F3X6L5_A_UNSHIFTED_MASK << IW_F3X6L5_A_LSB)
814 #define GET_IW_F3X6L5_A(W) (((W) >> IW_F3X6L5_A_LSB) & IW_F3X6L5_A_UNSHIFTED_MASK)
815 #define SET_IW_F3X6L5_A(V) (((V) & IW_F3X6L5_A_UNSHIFTED_MASK) << IW_F3X6L5_A_LSB)
816
817 #define IW_F3X6L5_B_LSB 11
818 #define IW_F3X6L5_B_SIZE 5
819 #define IW_F3X6L5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_B_SIZE))
820 #define IW_F3X6L5_B_SHIFTED_MASK (IW_F3X6L5_B_UNSHIFTED_MASK << IW_F3X6L5_B_LSB)
821 #define GET_IW_F3X6L5_B(W) (((W) >> IW_F3X6L5_B_LSB) & IW_F3X6L5_B_UNSHIFTED_MASK)
822 #define SET_IW_F3X6L5_B(V) (((V) & IW_F3X6L5_B_UNSHIFTED_MASK) << IW_F3X6L5_B_LSB)
823
824 #define IW_F3X6L5_C_LSB 16
825 #define IW_F3X6L5_C_SIZE 5
826 #define IW_F3X6L5_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_C_SIZE))
827 #define IW_F3X6L5_C_SHIFTED_MASK (IW_F3X6L5_C_UNSHIFTED_MASK << IW_F3X6L5_C_LSB)
828 #define GET_IW_F3X6L5_C(W) (((W) >> IW_F3X6L5_C_LSB) & IW_F3X6L5_C_UNSHIFTED_MASK)
829 #define SET_IW_F3X6L5_C(V) (((V) & IW_F3X6L5_C_UNSHIFTED_MASK) << IW_F3X6L5_C_LSB)
830
831 #define IW_F3X6L5_IMM5_LSB 21
832 #define IW_F3X6L5_IMM5_SIZE 5
833 #define IW_F3X6L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_IMM5_SIZE))
834 #define IW_F3X6L5_IMM5_SHIFTED_MASK (IW_F3X6L5_IMM5_UNSHIFTED_MASK << IW_F3X6L5_IMM5_LSB)
835 #define GET_IW_F3X6L5_IMM5(W) (((W) >> IW_F3X6L5_IMM5_LSB) & IW_F3X6L5_IMM5_UNSHIFTED_MASK)
836 #define SET_IW_F3X6L5_IMM5(V) (((V) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) << IW_F3X6L5_IMM5_LSB)
837
838 #define IW_F2X6L10_A_LSB 6
839 #define IW_F2X6L10_A_SIZE 5
840 #define IW_F2X6L10_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_A_SIZE))
841 #define IW_F2X6L10_A_SHIFTED_MASK (IW_F2X6L10_A_UNSHIFTED_MASK << IW_F2X6L10_A_LSB)
842 #define GET_IW_F2X6L10_A(W) (((W) >> IW_F2X6L10_A_LSB) & IW_F2X6L10_A_UNSHIFTED_MASK)
843 #define SET_IW_F2X6L10_A(V) (((V) & IW_F2X6L10_A_UNSHIFTED_MASK) << IW_F2X6L10_A_LSB)
844
845 #define IW_F2X6L10_B_LSB 11
846 #define IW_F2X6L10_B_SIZE 5
847 #define IW_F2X6L10_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_B_SIZE))
848 #define IW_F2X6L10_B_SHIFTED_MASK (IW_F2X6L10_B_UNSHIFTED_MASK << IW_F2X6L10_B_LSB)
849 #define GET_IW_F2X6L10_B(W) (((W) >> IW_F2X6L10_B_LSB) & IW_F2X6L10_B_UNSHIFTED_MASK)
850 #define SET_IW_F2X6L10_B(V) (((V) & IW_F2X6L10_B_UNSHIFTED_MASK) << IW_F2X6L10_B_LSB)
851
852 #define IW_F2X6L10_LSB_LSB 16
853 #define IW_F2X6L10_LSB_SIZE 5
854 #define IW_F2X6L10_LSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_LSB_SIZE))
855 #define IW_F2X6L10_LSB_SHIFTED_MASK (IW_F2X6L10_LSB_UNSHIFTED_MASK << IW_F2X6L10_LSB_LSB)
856 #define GET_IW_F2X6L10_LSB(W) (((W) >> IW_F2X6L10_LSB_LSB) & IW_F2X6L10_LSB_UNSHIFTED_MASK)
857 #define SET_IW_F2X6L10_LSB(V) (((V) & IW_F2X6L10_LSB_UNSHIFTED_MASK) << IW_F2X6L10_LSB_LSB)
858
859 #define IW_F2X6L10_MSB_LSB 21
860 #define IW_F2X6L10_MSB_SIZE 5
861 #define IW_F2X6L10_MSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_MSB_SIZE))
862 #define IW_F2X6L10_MSB_SHIFTED_MASK (IW_F2X6L10_MSB_UNSHIFTED_MASK << IW_F2X6L10_MSB_LSB)
863 #define GET_IW_F2X6L10_MSB(W) (((W) >> IW_F2X6L10_MSB_LSB) & IW_F2X6L10_MSB_UNSHIFTED_MASK)
864 #define SET_IW_F2X6L10_MSB(V) (((V) & IW_F2X6L10_MSB_UNSHIFTED_MASK) << IW_F2X6L10_MSB_LSB)
865
866 #define IW_F3X8_A_LSB 6
867 #define IW_F3X8_A_SIZE 5
868 #define IW_F3X8_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_A_SIZE))
869 #define IW_F3X8_A_SHIFTED_MASK (IW_F3X8_A_UNSHIFTED_MASK << IW_F3X8_A_LSB)
870 #define GET_IW_F3X8_A(W) (((W) >> IW_F3X8_A_LSB) & IW_F3X8_A_UNSHIFTED_MASK)
871 #define SET_IW_F3X8_A(V) (((V) & IW_F3X8_A_UNSHIFTED_MASK) << IW_F3X8_A_LSB)
872
873 #define IW_F3X8_B_LSB 11
874 #define IW_F3X8_B_SIZE 5
875 #define IW_F3X8_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_B_SIZE))
876 #define IW_F3X8_B_SHIFTED_MASK (IW_F3X8_B_UNSHIFTED_MASK << IW_F3X8_B_LSB)
877 #define GET_IW_F3X8_B(W) (((W) >> IW_F3X8_B_LSB) & IW_F3X8_B_UNSHIFTED_MASK)
878 #define SET_IW_F3X8_B(V) (((V) & IW_F3X8_B_UNSHIFTED_MASK) << IW_F3X8_B_LSB)
879
880 #define IW_F3X8_C_LSB 16
881 #define IW_F3X8_C_SIZE 5
882 #define IW_F3X8_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_C_SIZE))
883 #define IW_F3X8_C_SHIFTED_MASK (IW_F3X8_C_UNSHIFTED_MASK << IW_F3X8_C_LSB)
884 #define GET_IW_F3X8_C(W) (((W) >> IW_F3X8_C_LSB) & IW_F3X8_C_UNSHIFTED_MASK)
885 #define SET_IW_F3X8_C(V) (((V) & IW_F3X8_C_UNSHIFTED_MASK) << IW_F3X8_C_LSB)
886
887 #define IW_F3X8_READA_LSB 21
888 #define IW_F3X8_READA_SIZE 1
889 #define IW_F3X8_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READA_SIZE))
890 #define IW_F3X8_READA_SHIFTED_MASK (IW_F3X8_READA_UNSHIFTED_MASK << IW_F3X8_READA_LSB)
891 #define GET_IW_F3X8_READA(W) (((W) >> IW_F3X8_READA_LSB) & IW_F3X8_READA_UNSHIFTED_MASK)
892 #define SET_IW_F3X8_READA(V) (((V) & IW_F3X8_READA_UNSHIFTED_MASK) << IW_F3X8_READA_LSB)
893
894 #define IW_F3X8_READB_LSB 22
895 #define IW_F3X8_READB_SIZE 1
896 #define IW_F3X8_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READB_SIZE))
897 #define IW_F3X8_READB_SHIFTED_MASK (IW_F3X8_READB_UNSHIFTED_MASK << IW_F3X8_READB_LSB)
898 #define GET_IW_F3X8_READB(W) (((W) >> IW_F3X8_READB_LSB) & IW_F3X8_READB_UNSHIFTED_MASK)
899 #define SET_IW_F3X8_READB(V) (((V) & IW_F3X8_READB_UNSHIFTED_MASK) << IW_F3X8_READB_LSB)
900
901 #define IW_F3X8_READC_LSB 23
902 #define IW_F3X8_READC_SIZE 1
903 #define IW_F3X8_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READC_SIZE))
904 #define IW_F3X8_READC_SHIFTED_MASK (IW_F3X8_READC_UNSHIFTED_MASK << IW_F3X8_READC_LSB)
905 #define GET_IW_F3X8_READC(W) (((W) >> IW_F3X8_READC_LSB) & IW_F3X8_READC_UNSHIFTED_MASK)
906 #define SET_IW_F3X8_READC(V) (((V) & IW_F3X8_READC_UNSHIFTED_MASK) << IW_F3X8_READC_LSB)
907
908 #define IW_F3X8_N_LSB 24
909 #define IW_F3X8_N_SIZE 8
910 #define IW_F3X8_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_N_SIZE))
911 #define IW_F3X8_N_SHIFTED_MASK (IW_F3X8_N_UNSHIFTED_MASK << IW_F3X8_N_LSB)
912 #define GET_IW_F3X8_N(W) (((W) >> IW_F3X8_N_LSB) & IW_F3X8_N_UNSHIFTED_MASK)
913 #define SET_IW_F3X8_N(V) (((V) & IW_F3X8_N_UNSHIFTED_MASK) << IW_F3X8_N_LSB)
914
915 /* 16-bit R2 fields. */
916
917 #define IW_I10_IMM10_LSB 6
918 #define IW_I10_IMM10_SIZE 10
919 #define IW_I10_IMM10_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I10_IMM10_SIZE))
920 #define IW_I10_IMM10_SHIFTED_MASK (IW_I10_IMM10_UNSHIFTED_MASK << IW_I10_IMM10_LSB)
921 #define GET_IW_I10_IMM10(W) (((W) >> IW_I10_IMM10_LSB) & IW_I10_IMM10_UNSHIFTED_MASK)
922 #define SET_IW_I10_IMM10(V) (((V) & IW_I10_IMM10_UNSHIFTED_MASK) << IW_I10_IMM10_LSB)
923
924 #define IW_T1I7_A3_LSB 6
925 #define IW_T1I7_A3_SIZE 3
926 #define IW_T1I7_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_A3_SIZE))
927 #define IW_T1I7_A3_SHIFTED_MASK (IW_T1I7_A3_UNSHIFTED_MASK << IW_T1I7_A3_LSB)
928 #define GET_IW_T1I7_A3(W) (((W) >> IW_T1I7_A3_LSB) & IW_T1I7_A3_UNSHIFTED_MASK)
929 #define SET_IW_T1I7_A3(V) (((V) & IW_T1I7_A3_UNSHIFTED_MASK) << IW_T1I7_A3_LSB)
930
931 #define IW_T1I7_IMM7_LSB 9
932 #define IW_T1I7_IMM7_SIZE 7
933 #define IW_T1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_IMM7_SIZE))
934 #define IW_T1I7_IMM7_SHIFTED_MASK (IW_T1I7_IMM7_UNSHIFTED_MASK << IW_T1I7_IMM7_LSB)
935 #define GET_IW_T1I7_IMM7(W) (((W) >> IW_T1I7_IMM7_LSB) & IW_T1I7_IMM7_UNSHIFTED_MASK)
936 #define SET_IW_T1I7_IMM7(V) (((V) & IW_T1I7_IMM7_UNSHIFTED_MASK) << IW_T1I7_IMM7_LSB)
937
938 #define IW_T2I4_A3_LSB 6
939 #define IW_T2I4_A3_SIZE 3
940 #define IW_T2I4_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_A3_SIZE))
941 #define IW_T2I4_A3_SHIFTED_MASK (IW_T2I4_A3_UNSHIFTED_MASK << IW_T2I4_A3_LSB)
942 #define GET_IW_T2I4_A3(W) (((W) >> IW_T2I4_A3_LSB) & IW_T2I4_A3_UNSHIFTED_MASK)
943 #define SET_IW_T2I4_A3(V) (((V) & IW_T2I4_A3_UNSHIFTED_MASK) << IW_T2I4_A3_LSB)
944
945 #define IW_T2I4_B3_LSB 9
946 #define IW_T2I4_B3_SIZE 3
947 #define IW_T2I4_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_B3_SIZE))
948 #define IW_T2I4_B3_SHIFTED_MASK (IW_T2I4_B3_UNSHIFTED_MASK << IW_T2I4_B3_LSB)
949 #define GET_IW_T2I4_B3(W) (((W) >> IW_T2I4_B3_LSB) & IW_T2I4_B3_UNSHIFTED_MASK)
950 #define SET_IW_T2I4_B3(V) (((V) & IW_T2I4_B3_UNSHIFTED_MASK) << IW_T2I4_B3_LSB)
951
952 #define IW_T2I4_IMM4_LSB 12
953 #define IW_T2I4_IMM4_SIZE 4
954 #define IW_T2I4_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_IMM4_SIZE))
955 #define IW_T2I4_IMM4_SHIFTED_MASK (IW_T2I4_IMM4_UNSHIFTED_MASK << IW_T2I4_IMM4_LSB)
956 #define GET_IW_T2I4_IMM4(W) (((W) >> IW_T2I4_IMM4_LSB) & IW_T2I4_IMM4_UNSHIFTED_MASK)
957 #define SET_IW_T2I4_IMM4(V) (((V) & IW_T2I4_IMM4_UNSHIFTED_MASK) << IW_T2I4_IMM4_LSB)
958
959 #define IW_T1X1I6_A3_LSB 6
960 #define IW_T1X1I6_A3_SIZE 3
961 #define IW_T1X1I6_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_A3_SIZE))
962 #define IW_T1X1I6_A3_SHIFTED_MASK (IW_T1X1I6_A3_UNSHIFTED_MASK << IW_T1X1I6_A3_LSB)
963 #define GET_IW_T1X1I6_A3(W) (((W) >> IW_T1X1I6_A3_LSB) & IW_T1X1I6_A3_UNSHIFTED_MASK)
964 #define SET_IW_T1X1I6_A3(V) (((V) & IW_T1X1I6_A3_UNSHIFTED_MASK) << IW_T1X1I6_A3_LSB)
965
966 #define IW_T1X1I6_IMM6_LSB 9
967 #define IW_T1X1I6_IMM6_SIZE 6
968 #define IW_T1X1I6_IMM6_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_IMM6_SIZE))
969 #define IW_T1X1I6_IMM6_SHIFTED_MASK (IW_T1X1I6_IMM6_UNSHIFTED_MASK << IW_T1X1I6_IMM6_LSB)
970 #define GET_IW_T1X1I6_IMM6(W) (((W) >> IW_T1X1I6_IMM6_LSB) & IW_T1X1I6_IMM6_UNSHIFTED_MASK)
971 #define SET_IW_T1X1I6_IMM6(V) (((V) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) << IW_T1X1I6_IMM6_LSB)
972
973 #define IW_T1X1I6_X_LSB 15
974 #define IW_T1X1I6_X_SIZE 1
975 #define IW_T1X1I6_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_X_SIZE))
976 #define IW_T1X1I6_X_SHIFTED_MASK (IW_T1X1I6_X_UNSHIFTED_MASK << IW_T1X1I6_X_LSB)
977 #define GET_IW_T1X1I6_X(W) (((W) >> IW_T1X1I6_X_LSB) & IW_T1X1I6_X_UNSHIFTED_MASK)
978 #define SET_IW_T1X1I6_X(V) (((V) & IW_T1X1I6_X_UNSHIFTED_MASK) << IW_T1X1I6_X_LSB)
979
980 #define IW_X1I7_IMM7_LSB 6
981 #define IW_X1I7_IMM7_SIZE 7
982 #define IW_X1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_IMM7_SIZE))
983 #define IW_X1I7_IMM7_SHIFTED_MASK (IW_X1I7_IMM7_UNSHIFTED_MASK << IW_X1I7_IMM7_LSB)
984 #define GET_IW_X1I7_IMM7(W) (((W) >> IW_X1I7_IMM7_LSB) & IW_X1I7_IMM7_UNSHIFTED_MASK)
985 #define SET_IW_X1I7_IMM7(V) (((V) & IW_X1I7_IMM7_UNSHIFTED_MASK) << IW_X1I7_IMM7_LSB)
986
987 #define IW_X1I7_RSV_LSB 13
988 #define IW_X1I7_RSV_SIZE 2
989 #define IW_X1I7_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_RSV_SIZE))
990 #define IW_X1I7_RSV_SHIFTED_MASK (IW_X1I7_RSV_UNSHIFTED_MASK << IW_X1I7_RSV_LSB)
991 #define GET_IW_X1I7_RSV(W) (((W) >> IW_X1I7_RSV_LSB) & IW_X1I7_RSV_UNSHIFTED_MASK)
992 #define SET_IW_X1I7_RSV(V) (((V) & IW_X1I7_RSV_UNSHIFTED_MASK) << IW_X1I7_RSV_LSB)
993
994 #define IW_X1I7_X_LSB 15
995 #define IW_X1I7_X_SIZE 1
996 #define IW_X1I7_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_X_SIZE))
997 #define IW_X1I7_X_SHIFTED_MASK (IW_X1I7_X_UNSHIFTED_MASK << IW_X1I7_X_LSB)
998 #define GET_IW_X1I7_X(W) (((W) >> IW_X1I7_X_LSB) & IW_X1I7_X_UNSHIFTED_MASK)
999 #define SET_IW_X1I7_X(V) (((V) & IW_X1I7_X_UNSHIFTED_MASK) << IW_X1I7_X_LSB)
1000
1001 #define IW_L5I4X1_IMM4_LSB 6
1002 #define IW_L5I4X1_IMM4_SIZE 4
1003 #define IW_L5I4X1_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_IMM4_SIZE))
1004 #define IW_L5I4X1_IMM4_SHIFTED_MASK (IW_L5I4X1_IMM4_UNSHIFTED_MASK << IW_L5I4X1_IMM4_LSB)
1005 #define GET_IW_L5I4X1_IMM4(W) (((W) >> IW_L5I4X1_IMM4_LSB) & IW_L5I4X1_IMM4_UNSHIFTED_MASK)
1006 #define SET_IW_L5I4X1_IMM4(V) (((V) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) << IW_L5I4X1_IMM4_LSB)
1007
1008 #define IW_L5I4X1_REGRANGE_LSB 10
1009 #define IW_L5I4X1_REGRANGE_SIZE 3
1010 #define IW_L5I4X1_REGRANGE_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_REGRANGE_SIZE))
1011 #define IW_L5I4X1_REGRANGE_SHIFTED_MASK (IW_L5I4X1_REGRANGE_UNSHIFTED_MASK << IW_L5I4X1_REGRANGE_LSB)
1012 #define GET_IW_L5I4X1_REGRANGE(W) (((W) >> IW_L5I4X1_REGRANGE_LSB) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK)
1013 #define SET_IW_L5I4X1_REGRANGE(V) (((V) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) << IW_L5I4X1_REGRANGE_LSB)
1014
1015 #define IW_L5I4X1_FP_LSB 13
1016 #define IW_L5I4X1_FP_SIZE 1
1017 #define IW_L5I4X1_FP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_FP_SIZE))
1018 #define IW_L5I4X1_FP_SHIFTED_MASK (IW_L5I4X1_FP_UNSHIFTED_MASK << IW_L5I4X1_FP_LSB)
1019 #define GET_IW_L5I4X1_FP(W) (((W) >> IW_L5I4X1_FP_LSB) & IW_L5I4X1_FP_UNSHIFTED_MASK)
1020 #define SET_IW_L5I4X1_FP(V) (((V) & IW_L5I4X1_FP_UNSHIFTED_MASK) << IW_L5I4X1_FP_LSB)
1021
1022 #define IW_L5I4X1_CS_LSB 14
1023 #define IW_L5I4X1_CS_SIZE 1
1024 #define IW_L5I4X1_CS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_CS_SIZE))
1025 #define IW_L5I4X1_CS_SHIFTED_MASK (IW_L5I4X1_CS_UNSHIFTED_MASK << IW_L5I4X1_CS_LSB)
1026 #define GET_IW_L5I4X1_CS(W) (((W) >> IW_L5I4X1_CS_LSB) & IW_L5I4X1_CS_UNSHIFTED_MASK)
1027 #define SET_IW_L5I4X1_CS(V) (((V) & IW_L5I4X1_CS_UNSHIFTED_MASK) << IW_L5I4X1_CS_LSB)
1028
1029 #define IW_L5I4X1_X_LSB 15
1030 #define IW_L5I4X1_X_SIZE 1
1031 #define IW_L5I4X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_X_SIZE))
1032 #define IW_L5I4X1_X_SHIFTED_MASK (IW_L5I4X1_X_UNSHIFTED_MASK << IW_L5I4X1_X_LSB)
1033 #define GET_IW_L5I4X1_X(W) (((W) >> IW_L5I4X1_X_LSB) & IW_L5I4X1_X_UNSHIFTED_MASK)
1034 #define SET_IW_L5I4X1_X(V) (((V) & IW_L5I4X1_X_UNSHIFTED_MASK) << IW_L5I4X1_X_LSB)
1035
1036 #define IW_T2X1L3_A3_LSB 6
1037 #define IW_T2X1L3_A3_SIZE 3
1038 #define IW_T2X1L3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_A3_SIZE))
1039 #define IW_T2X1L3_A3_SHIFTED_MASK (IW_T2X1L3_A3_UNSHIFTED_MASK << IW_T2X1L3_A3_LSB)
1040 #define GET_IW_T2X1L3_A3(W) (((W) >> IW_T2X1L3_A3_LSB) & IW_T2X1L3_A3_UNSHIFTED_MASK)
1041 #define SET_IW_T2X1L3_A3(V) (((V) & IW_T2X1L3_A3_UNSHIFTED_MASK) << IW_T2X1L3_A3_LSB)
1042
1043 #define IW_T2X1L3_B3_LSB 9
1044 #define IW_T2X1L3_B3_SIZE 3
1045 #define IW_T2X1L3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_B3_SIZE))
1046 #define IW_T2X1L3_B3_SHIFTED_MASK (IW_T2X1L3_B3_UNSHIFTED_MASK << IW_T2X1L3_B3_LSB)
1047 #define GET_IW_T2X1L3_B3(W) (((W) >> IW_T2X1L3_B3_LSB) & IW_T2X1L3_B3_UNSHIFTED_MASK)
1048 #define SET_IW_T2X1L3_B3(V) (((V) & IW_T2X1L3_B3_UNSHIFTED_MASK) << IW_T2X1L3_B3_LSB)
1049
1050 #define IW_T2X1L3_SHAMT_LSB 12
1051 #define IW_T2X1L3_SHAMT_SIZE 3
1052 #define IW_T2X1L3_SHAMT_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_SHAMT_SIZE))
1053 #define IW_T2X1L3_SHAMT_SHIFTED_MASK (IW_T2X1L3_SHAMT_UNSHIFTED_MASK << IW_T2X1L3_SHAMT_LSB)
1054 #define GET_IW_T2X1L3_SHAMT(W) (((W) >> IW_T2X1L3_SHAMT_LSB) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK)
1055 #define SET_IW_T2X1L3_SHAMT(V) (((V) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) << IW_T2X1L3_SHAMT_LSB)
1056
1057 #define IW_T2X1L3_X_LSB 15
1058 #define IW_T2X1L3_X_SIZE 1
1059 #define IW_T2X1L3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_X_SIZE))
1060 #define IW_T2X1L3_X_SHIFTED_MASK (IW_T2X1L3_X_UNSHIFTED_MASK << IW_T2X1L3_X_LSB)
1061 #define GET_IW_T2X1L3_X(W) (((W) >> IW_T2X1L3_X_LSB) & IW_T2X1L3_X_UNSHIFTED_MASK)
1062 #define SET_IW_T2X1L3_X(V) (((V) & IW_T2X1L3_X_UNSHIFTED_MASK) << IW_T2X1L3_X_LSB)
1063
1064 #define IW_T2X1I3_A3_LSB 6
1065 #define IW_T2X1I3_A3_SIZE 3
1066 #define IW_T2X1I3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_A3_SIZE))
1067 #define IW_T2X1I3_A3_SHIFTED_MASK (IW_T2X1I3_A3_UNSHIFTED_MASK << IW_T2X1I3_A3_LSB)
1068 #define GET_IW_T2X1I3_A3(W) (((W) >> IW_T2X1I3_A3_LSB) & IW_T2X1I3_A3_UNSHIFTED_MASK)
1069 #define SET_IW_T2X1I3_A3(V) (((V) & IW_T2X1I3_A3_UNSHIFTED_MASK) << IW_T2X1I3_A3_LSB)
1070
1071 #define IW_T2X1I3_B3_LSB 9
1072 #define IW_T2X1I3_B3_SIZE 3
1073 #define IW_T2X1I3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_B3_SIZE))
1074 #define IW_T2X1I3_B3_SHIFTED_MASK (IW_T2X1I3_B3_UNSHIFTED_MASK << IW_T2X1I3_B3_LSB)
1075 #define GET_IW_T2X1I3_B3(W) (((W) >> IW_T2X1I3_B3_LSB) & IW_T2X1I3_B3_UNSHIFTED_MASK)
1076 #define SET_IW_T2X1I3_B3(V) (((V) & IW_T2X1I3_B3_UNSHIFTED_MASK) << IW_T2X1I3_B3_LSB)
1077
1078 #define IW_T2X1I3_IMM3_LSB 12
1079 #define IW_T2X1I3_IMM3_SIZE 3
1080 #define IW_T2X1I3_IMM3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_IMM3_SIZE))
1081 #define IW_T2X1I3_IMM3_SHIFTED_MASK (IW_T2X1I3_IMM3_UNSHIFTED_MASK << IW_T2X1I3_IMM3_LSB)
1082 #define GET_IW_T2X1I3_IMM3(W) (((W) >> IW_T2X1I3_IMM3_LSB) & IW_T2X1I3_IMM3_UNSHIFTED_MASK)
1083 #define SET_IW_T2X1I3_IMM3(V) (((V) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) << IW_T2X1I3_IMM3_LSB)
1084
1085 #define IW_T2X1I3_X_LSB 15
1086 #define IW_T2X1I3_X_SIZE 1
1087 #define IW_T2X1I3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_X_SIZE))
1088 #define IW_T2X1I3_X_SHIFTED_MASK (IW_T2X1I3_X_UNSHIFTED_MASK << IW_T2X1I3_X_LSB)
1089 #define GET_IW_T2X1I3_X(W) (((W) >> IW_T2X1I3_X_LSB) & IW_T2X1I3_X_UNSHIFTED_MASK)
1090 #define SET_IW_T2X1I3_X(V) (((V) & IW_T2X1I3_X_UNSHIFTED_MASK) << IW_T2X1I3_X_LSB)
1091
1092 #define IW_T3X1_A3_LSB 6
1093 #define IW_T3X1_A3_SIZE 3
1094 #define IW_T3X1_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_A3_SIZE))
1095 #define IW_T3X1_A3_SHIFTED_MASK (IW_T3X1_A3_UNSHIFTED_MASK << IW_T3X1_A3_LSB)
1096 #define GET_IW_T3X1_A3(W) (((W) >> IW_T3X1_A3_LSB) & IW_T3X1_A3_UNSHIFTED_MASK)
1097 #define SET_IW_T3X1_A3(V) (((V) & IW_T3X1_A3_UNSHIFTED_MASK) << IW_T3X1_A3_LSB)
1098
1099 #define IW_T3X1_B3_LSB 9
1100 #define IW_T3X1_B3_SIZE 3
1101 #define IW_T3X1_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_B3_SIZE))
1102 #define IW_T3X1_B3_SHIFTED_MASK (IW_T3X1_B3_UNSHIFTED_MASK << IW_T3X1_B3_LSB)
1103 #define GET_IW_T3X1_B3(W) (((W) >> IW_T3X1_B3_LSB) & IW_T3X1_B3_UNSHIFTED_MASK)
1104 #define SET_IW_T3X1_B3(V) (((V) & IW_T3X1_B3_UNSHIFTED_MASK) << IW_T3X1_B3_LSB)
1105
1106 #define IW_T3X1_C3_LSB 12
1107 #define IW_T3X1_C3_SIZE 3
1108 #define IW_T3X1_C3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_C3_SIZE))
1109 #define IW_T3X1_C3_SHIFTED_MASK (IW_T3X1_C3_UNSHIFTED_MASK << IW_T3X1_C3_LSB)
1110 #define GET_IW_T3X1_C3(W) (((W) >> IW_T3X1_C3_LSB) & IW_T3X1_C3_UNSHIFTED_MASK)
1111 #define SET_IW_T3X1_C3(V) (((V) & IW_T3X1_C3_UNSHIFTED_MASK) << IW_T3X1_C3_LSB)
1112
1113 #define IW_T3X1_X_LSB 15
1114 #define IW_T3X1_X_SIZE 1
1115 #define IW_T3X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_X_SIZE))
1116 #define IW_T3X1_X_SHIFTED_MASK (IW_T3X1_X_UNSHIFTED_MASK << IW_T3X1_X_LSB)
1117 #define GET_IW_T3X1_X(W) (((W) >> IW_T3X1_X_LSB) & IW_T3X1_X_UNSHIFTED_MASK)
1118 #define SET_IW_T3X1_X(V) (((V) & IW_T3X1_X_UNSHIFTED_MASK) << IW_T3X1_X_LSB)
1119
1120 /* The X field for all three R.N-class instruction formats is represented
1121 here as 4 bits, including the bits defined as constant 0 or 1 that
1122 determine which of the formats T2X3, F1X1, or X2L5 it is. */
1123 #define IW_R_N_X_LSB 12
1124 #define IW_R_N_X_SIZE 4
1125 #define IW_R_N_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_N_X_SIZE))
1126 #define IW_R_N_X_SHIFTED_MASK (IW_R_N_X_UNSHIFTED_MASK << IW_R_N_X_LSB)
1127 #define GET_IW_R_N_X(W) (((W) >> IW_R_N_X_LSB) & IW_R_N_X_UNSHIFTED_MASK)
1128 #define SET_IW_R_N_X(V) (((V) & IW_R_N_X_UNSHIFTED_MASK) << IW_R_N_X_LSB)
1129
1130 #define IW_T2X3_A3_LSB 6
1131 #define IW_T2X3_A3_SIZE 3
1132 #define IW_T2X3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_A3_SIZE))
1133 #define IW_T2X3_A3_SHIFTED_MASK (IW_T2X3_A3_UNSHIFTED_MASK << IW_T2X3_A3_LSB)
1134 #define GET_IW_T2X3_A3(W) (((W) >> IW_T2X3_A3_LSB) & IW_T2X3_A3_UNSHIFTED_MASK)
1135 #define SET_IW_T2X3_A3(V) (((V) & IW_T2X3_A3_UNSHIFTED_MASK) << IW_T2X3_A3_LSB)
1136
1137 #define IW_T2X3_B3_LSB 9
1138 #define IW_T2X3_B3_SIZE 3
1139 #define IW_T2X3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_B3_SIZE))
1140 #define IW_T2X3_B3_SHIFTED_MASK (IW_T2X3_B3_UNSHIFTED_MASK << IW_T2X3_B3_LSB)
1141 #define GET_IW_T2X3_B3(W) (((W) >> IW_T2X3_B3_LSB) & IW_T2X3_B3_UNSHIFTED_MASK)
1142 #define SET_IW_T2X3_B3(V) (((V) & IW_T2X3_B3_UNSHIFTED_MASK) << IW_T2X3_B3_LSB)
1143
1144 #define IW_F1X1_A_LSB 6
1145 #define IW_F1X1_A_SIZE 5
1146 #define IW_F1X1_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_A_SIZE))
1147 #define IW_F1X1_A_SHIFTED_MASK (IW_F1X1_A_UNSHIFTED_MASK << IW_F1X1_A_LSB)
1148 #define GET_IW_F1X1_A(W) (((W) >> IW_F1X1_A_LSB) & IW_F1X1_A_UNSHIFTED_MASK)
1149 #define SET_IW_F1X1_A(V) (((V) & IW_F1X1_A_UNSHIFTED_MASK) << IW_F1X1_A_LSB)
1150
1151 #define IW_F1X1_RSV_LSB 11
1152 #define IW_F1X1_RSV_SIZE 1
1153 #define IW_F1X1_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_RSV_SIZE))
1154 #define IW_F1X1_RSV_SHIFTED_MASK (IW_F1X1_RSV_UNSHIFTED_MASK << IW_F1X1_RSV_LSB)
1155 #define GET_IW_F1X1_RSV(W) (((W) >> IW_F1X1_RSV_LSB) & IW_F1X1_RSV_UNSHIFTED_MASK)
1156 #define SET_IW_F1X1_RSV(V) (((V) & IW_F1X1_RSV_UNSHIFTED_MASK) << IW_F1X1_RSV_LSB)
1157
1158 #define IW_X2L5_IMM5_LSB 6
1159 #define IW_X2L5_IMM5_SIZE 5
1160 #define IW_X2L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_IMM5_SIZE))
1161 #define IW_X2L5_IMM5_SHIFTED_MASK (IW_X2L5_IMM5_UNSHIFTED_MASK << IW_X2L5_IMM5_LSB)
1162 #define GET_IW_X2L5_IMM5(W) (((W) >> IW_X2L5_IMM5_LSB) & IW_X2L5_IMM5_UNSHIFTED_MASK)
1163 #define SET_IW_X2L5_IMM5(V) (((V) & IW_X2L5_IMM5_UNSHIFTED_MASK) << IW_X2L5_IMM5_LSB)
1164
1165 #define IW_X2L5_RSV_LSB 11
1166 #define IW_X2L5_RSV_SIZE 1
1167 #define IW_X2L5_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_RSV_SIZE))
1168 #define IW_X2L5_RSV_SHIFTED_MASK (IW_X2L5_RSV_UNSHIFTED_MASK << IW_X2L5_RSV_LSB)
1169 #define GET_IW_X2L5_RSV(W) (((W) >> IW_X2L5_RSV_LSB) & IW_X2L5_RSV_UNSHIFTED_MASK)
1170 #define SET_IW_X2L5_RSV(V) (((V) & IW_X2L5_RSV_UNSHIFTED_MASK) << IW_X2L5_RSV_LSB)
1171
1172 #define IW_F1I5_IMM5_LSB 6
1173 #define IW_F1I5_IMM5_SIZE 5
1174 #define IW_F1I5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_IMM5_SIZE))
1175 #define IW_F1I5_IMM5_SHIFTED_MASK (IW_F1I5_IMM5_UNSHIFTED_MASK << IW_F1I5_IMM5_LSB)
1176 #define GET_IW_F1I5_IMM5(W) (((W) >> IW_F1I5_IMM5_LSB) & IW_F1I5_IMM5_UNSHIFTED_MASK)
1177 #define SET_IW_F1I5_IMM5(V) (((V) & IW_F1I5_IMM5_UNSHIFTED_MASK) << IW_F1I5_IMM5_LSB)
1178
1179 #define IW_F1I5_B_LSB 11
1180 #define IW_F1I5_B_SIZE 5
1181 #define IW_F1I5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_B_SIZE))
1182 #define IW_F1I5_B_SHIFTED_MASK (IW_F1I5_B_UNSHIFTED_MASK << IW_F1I5_B_LSB)
1183 #define GET_IW_F1I5_B(W) (((W) >> IW_F1I5_B_LSB) & IW_F1I5_B_UNSHIFTED_MASK)
1184 #define SET_IW_F1I5_B(V) (((V) & IW_F1I5_B_UNSHIFTED_MASK) << IW_F1I5_B_LSB)
1185
1186 #define IW_F2_A_LSB 6
1187 #define IW_F2_A_SIZE 5
1188 #define IW_F2_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_A_SIZE))
1189 #define IW_F2_A_SHIFTED_MASK (IW_F2_A_UNSHIFTED_MASK << IW_F2_A_LSB)
1190 #define GET_IW_F2_A(W) (((W) >> IW_F2_A_LSB) & IW_F2_A_UNSHIFTED_MASK)
1191 #define SET_IW_F2_A(V) (((V) & IW_F2_A_UNSHIFTED_MASK) << IW_F2_A_LSB)
1192
1193 #define IW_F2_B_LSB 11
1194 #define IW_F2_B_SIZE 5
1195 #define IW_F2_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_B_SIZE))
1196 #define IW_F2_B_SHIFTED_MASK (IW_F2_B_UNSHIFTED_MASK << IW_F2_B_LSB)
1197 #define GET_IW_F2_B(W) (((W) >> IW_F2_B_LSB) & IW_F2_B_UNSHIFTED_MASK)
1198 #define SET_IW_F2_B(V) (((V) & IW_F2_B_UNSHIFTED_MASK) << IW_F2_B_LSB)
1199
1200 /* R2 opcodes. */
1201 #define R2_OP_CALL 0
1202 #define R2_OP_AS_N 1
1203 #define R2_OP_BR 2
1204 #define R2_OP_BR_N 3
1205 #define R2_OP_ADDI 4
1206 #define R2_OP_LDBU_N 5
1207 #define R2_OP_LDBU 6
1208 #define R2_OP_LDB 7
1209 #define R2_OP_JMPI 8
1210 #define R2_OP_R_N 9
1211 #define R2_OP_ANDI_N 11
1212 #define R2_OP_ANDI 12
1213 #define R2_OP_LDHU_N 13
1214 #define R2_OP_LDHU 14
1215 #define R2_OP_LDH 15
1216 #define R2_OP_ASI_N 17
1217 #define R2_OP_BGE 18
1218 #define R2_OP_LDWSP_N 19
1219 #define R2_OP_ORI 20
1220 #define R2_OP_LDW_N 21
1221 #define R2_OP_CMPGEI 22
1222 #define R2_OP_LDW 23
1223 #define R2_OP_SHI_N 25
1224 #define R2_OP_BLT 26
1225 #define R2_OP_MOVI_N 27
1226 #define R2_OP_XORI 28
1227 #define R2_OP_STZ_N 29
1228 #define R2_OP_CMPLTI 30
1229 #define R2_OP_ANDCI 31
1230 #define R2_OP_OPX 32
1231 #define R2_OP_PP_N 33
1232 #define R2_OP_BNE 34
1233 #define R2_OP_BNEZ_N 35
1234 #define R2_OP_MULI 36
1235 #define R2_OP_STB_N 37
1236 #define R2_OP_CMPNEI 38
1237 #define R2_OP_STB 39
1238 #define R2_OP_I12 40
1239 #define R2_OP_SPI_N 41
1240 #define R2_OP_BEQ 42
1241 #define R2_OP_BEQZ_N 43
1242 #define R2_OP_ANDHI 44
1243 #define R2_OP_STH_N 45
1244 #define R2_OP_CMPEQI 46
1245 #define R2_OP_STH 47
1246 #define R2_OP_CUSTOM 48
1247 #define R2_OP_BGEU 50
1248 #define R2_OP_STWSP_N 51
1249 #define R2_OP_ORHI 52
1250 #define R2_OP_STW_N 53
1251 #define R2_OP_CMPGEUI 54
1252 #define R2_OP_STW 55
1253 #define R2_OP_BLTU 58
1254 #define R2_OP_MOV_N 59
1255 #define R2_OP_XORHI 60
1256 #define R2_OP_SPADDI_N 61
1257 #define R2_OP_CMPLTUI 62
1258 #define R2_OP_ANDCHI 63
1259
1260 #define R2_OPX_WRPIE 0
1261 #define R2_OPX_ERET 1
1262 #define R2_OPX_ROLI 2
1263 #define R2_OPX_ROL 3
1264 #define R2_OPX_FLUSHP 4
1265 #define R2_OPX_RET 5
1266 #define R2_OPX_NOR 6
1267 #define R2_OPX_MULXUU 7
1268 #define R2_OPX_ENI 8
1269 #define R2_OPX_BRET 9
1270 #define R2_OPX_ROR 11
1271 #define R2_OPX_FLUSHI 12
1272 #define R2_OPX_JMP 13
1273 #define R2_OPX_AND 14
1274 #define R2_OPX_CMPGE 16
1275 #define R2_OPX_SLLI 18
1276 #define R2_OPX_SLL 19
1277 #define R2_OPX_WRPRS 20
1278 #define R2_OPX_OR 22
1279 #define R2_OPX_MULXSU 23
1280 #define R2_OPX_CMPLT 24
1281 #define R2_OPX_SRLI 26
1282 #define R2_OPX_SRL 27
1283 #define R2_OPX_NEXTPC 28
1284 #define R2_OPX_CALLR 29
1285 #define R2_OPX_XOR 30
1286 #define R2_OPX_MULXSS 31
1287 #define R2_OPX_CMPNE 32
1288 #define R2_OPX_INSERT 35
1289 #define R2_OPX_DIVU 36
1290 #define R2_OPX_DIV 37
1291 #define R2_OPX_RDCTL 38
1292 #define R2_OPX_MUL 39
1293 #define R2_OPX_CMPEQ 40
1294 #define R2_OPX_INITI 41
1295 #define R2_OPX_MERGE 43
1296 #define R2_OPX_HBREAK 44
1297 #define R2_OPX_TRAP 45
1298 #define R2_OPX_WRCTL 46
1299 #define R2_OPX_CMPGEU 48
1300 #define R2_OPX_ADD 49
1301 #define R2_OPX_EXTRACT 51
1302 #define R2_OPX_BREAK 52
1303 #define R2_OPX_LDEX 53
1304 #define R2_OPX_SYNC 54
1305 #define R2_OPX_LDSEX 55
1306 #define R2_OPX_CMPLTU 56
1307 #define R2_OPX_SUB 57
1308 #define R2_OPX_SRAI 58
1309 #define R2_OPX_SRA 59
1310 #define R2_OPX_STEX 61
1311 #define R2_OPX_STSEX 63
1312
1313 #define R2_I12_LDBIO 0
1314 #define R2_I12_STBIO 1
1315 #define R2_I12_LDBUIO 2
1316 #define R2_I12_DCACHE 3
1317 #define R2_I12_LDHIO 4
1318 #define R2_I12_STHIO 5
1319 #define R2_I12_LDHUIO 6
1320 #define R2_I12_RDPRS 7
1321 #define R2_I12_LDWIO 8
1322 #define R2_I12_STWIO 9
1323 #define R2_I12_LDWM 12
1324 #define R2_I12_STWM 13
1325
1326 #define R2_DCACHE_INITD 0
1327 #define R2_DCACHE_INITDA 1
1328 #define R2_DCACHE_FLUSHD 2
1329 #define R2_DCACHE_FLUSHDA 3
1330
1331 #define R2_AS_N_ADD_N 0
1332 #define R2_AS_N_SUB_N 1
1333
1334 #define R2_R_N_AND_N 0
1335 #define R2_R_N_OR_N 2
1336 #define R2_R_N_XOR_N 3
1337 #define R2_R_N_SLL_N 4
1338 #define R2_R_N_SRL_N 5
1339 #define R2_R_N_NOT_N 6
1340 #define R2_R_N_NEG_N 7
1341 #define R2_R_N_CALLR_N 8
1342 #define R2_R_N_JMPR_N 10
1343 #define R2_R_N_BREAK_N 12
1344 #define R2_R_N_TRAP_N 13
1345 #define R2_R_N_RET_N 14
1346
1347 #define R2_SPI_N_SPINCI_N 0
1348 #define R2_SPI_N_SPDECI_N 1
1349
1350 #define R2_ASI_N_ADDI_N 0
1351 #define R2_ASI_N_SUBI_N 1
1352
1353 #define R2_SHI_N_SLLI_N 0
1354 #define R2_SHI_N_SRLI_N 1
1355
1356 #define R2_PP_N_POP_N 0
1357 #define R2_PP_N_PUSH_N 1
1358
1359 #define R2_STZ_N_STWZ_N 0
1360 #define R2_STZ_N_STBZ_N 1
1361
1362 /* Convenience macros for R2 encodings. */
1363
1364 #define MATCH_R2_OP(NAME) \
1365 (SET_IW_R2_OP (R2_OP_##NAME))
1366 #define MASK_R2_OP \
1367 IW_R2_OP_SHIFTED_MASK
1368
1369 #define MATCH_R2_OPX0(NAME) \
1370 (SET_IW_R2_OP (R2_OP_OPX) | SET_IW_OPX_X (R2_OPX_##NAME))
1371 #define MASK_R2_OPX0 \
1372 (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \
1373 | IW_F3X6L5_IMM5_SHIFTED_MASK)
1374
1375 #define MATCH_R2_OPX(NAME, A, B, C) \
1376 (MATCH_R2_OPX0 (NAME) | SET_IW_F3X6L5_A (A) | SET_IW_F3X6L5_B (B) \
1377 | SET_IW_F3X6L5_C (C))
1378 #define MASK_R2_OPX(A, B, C, N) \
1379 (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \
1380 | (A ? IW_F3X6L5_A_SHIFTED_MASK : 0) \
1381 | (B ? IW_F3X6L5_B_SHIFTED_MASK : 0) \
1382 | (C ? IW_F3X6L5_C_SHIFTED_MASK : 0) \
1383 | (N ? IW_F3X6L5_IMM5_SHIFTED_MASK : 0))
1384
1385 #define MATCH_R2_I12(NAME) \
1386 (SET_IW_R2_OP (R2_OP_I12) | SET_IW_I12_X (R2_I12_##NAME))
1387 #define MASK_R2_I12 \
1388 (IW_R2_OP_SHIFTED_MASK | IW_I12_X_SHIFTED_MASK )
1389
1390 #define MATCH_R2_DCACHE(NAME) \
1391 (MATCH_R2_I12(DCACHE) | SET_IW_F1X4I12_X (R2_DCACHE_##NAME))
1392 #define MASK_R2_DCACHE \
1393 (MASK_R2_I12 | IW_F1X4I12_X_SHIFTED_MASK)
1394
1395 #define MATCH_R2_R_N(NAME) \
1396 (SET_IW_R2_OP (R2_OP_R_N) | SET_IW_R_N_X (R2_R_N_##NAME))
1397 #define MASK_R2_R_N \
1398 (IW_R2_OP_SHIFTED_MASK | IW_R_N_X_SHIFTED_MASK )
1399
1400 /* Match/mask macros for R2 instructions. */
1401
1402 #define MATCH_R2_ADD MATCH_R2_OPX0 (ADD)
1403 #define MASK_R2_ADD MASK_R2_OPX0
1404 #define MATCH_R2_ADDI MATCH_R2_OP (ADDI)
1405 #define MASK_R2_ADDI MASK_R2_OP
1406 #define MATCH_R2_ADD_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_ADD_N))
1407 #define MASK_R2_ADD_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK)
1408 #define MATCH_R2_ADDI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_ADDI_N))
1409 #define MASK_R2_ADDI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK)
1410 #define MATCH_R2_AND MATCH_R2_OPX0 (AND)
1411 #define MASK_R2_AND MASK_R2_OPX0
1412 #define MATCH_R2_ANDCHI MATCH_R2_OP (ANDCHI)
1413 #define MASK_R2_ANDCHI MASK_R2_OP
1414 #define MATCH_R2_ANDCI MATCH_R2_OP (ANDCI)
1415 #define MASK_R2_ANDCI MASK_R2_OP
1416 #define MATCH_R2_ANDHI MATCH_R2_OP (ANDHI)
1417 #define MASK_R2_ANDHI MASK_R2_OP
1418 #define MATCH_R2_ANDI MATCH_R2_OP (ANDI)
1419 #define MASK_R2_ANDI MASK_R2_OP
1420 #define MATCH_R2_ANDI_N MATCH_R2_OP (ANDI_N)
1421 #define MASK_R2_ANDI_N MASK_R2_OP
1422 #define MATCH_R2_AND_N MATCH_R2_R_N (AND_N)
1423 #define MASK_R2_AND_N MASK_R2_R_N
1424 #define MATCH_R2_BEQ MATCH_R2_OP (BEQ)
1425 #define MASK_R2_BEQ MASK_R2_OP
1426 #define MATCH_R2_BEQZ_N MATCH_R2_OP (BEQZ_N)
1427 #define MASK_R2_BEQZ_N MASK_R2_OP
1428 #define MATCH_R2_BGE MATCH_R2_OP (BGE)
1429 #define MASK_R2_BGE MASK_R2_OP
1430 #define MATCH_R2_BGEU MATCH_R2_OP (BGEU)
1431 #define MASK_R2_BGEU MASK_R2_OP
1432 #define MATCH_R2_BGT MATCH_R2_OP (BLT)
1433 #define MASK_R2_BGT MASK_R2_OP
1434 #define MATCH_R2_BGTU MATCH_R2_OP (BLTU)
1435 #define MASK_R2_BGTU MASK_R2_OP
1436 #define MATCH_R2_BLE MATCH_R2_OP (BGE)
1437 #define MASK_R2_BLE MASK_R2_OP
1438 #define MATCH_R2_BLEU MATCH_R2_OP (BGEU)
1439 #define MASK_R2_BLEU MASK_R2_OP
1440 #define MATCH_R2_BLT MATCH_R2_OP (BLT)
1441 #define MASK_R2_BLT MASK_R2_OP
1442 #define MATCH_R2_BLTU MATCH_R2_OP (BLTU)
1443 #define MASK_R2_BLTU MASK_R2_OP
1444 #define MATCH_R2_BNE MATCH_R2_OP (BNE)
1445 #define MASK_R2_BNE MASK_R2_OP
1446 #define MATCH_R2_BNEZ_N MATCH_R2_OP (BNEZ_N)
1447 #define MASK_R2_BNEZ_N MASK_R2_OP
1448 #define MATCH_R2_BR MATCH_R2_OP (BR)
1449 #define MASK_R2_BR MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK | IW_F2I16_B_SHIFTED_MASK
1450 #define MATCH_R2_BREAK MATCH_R2_OPX (BREAK, 0, 0, 0x1e)
1451 #define MASK_R2_BREAK MASK_R2_OPX (1, 1, 1, 0)
1452 #define MATCH_R2_BREAK_N MATCH_R2_R_N (BREAK_N)
1453 #define MASK_R2_BREAK_N MASK_R2_R_N
1454 #define MATCH_R2_BRET MATCH_R2_OPX (BRET, 0x1e, 0, 0)
1455 #define MASK_R2_BRET MASK_R2_OPX (1, 1, 1, 1)
1456 #define MATCH_R2_BR_N MATCH_R2_OP (BR_N)
1457 #define MASK_R2_BR_N MASK_R2_OP
1458 #define MATCH_R2_CALL MATCH_R2_OP (CALL)
1459 #define MASK_R2_CALL MASK_R2_OP
1460 #define MATCH_R2_CALLR MATCH_R2_OPX (CALLR, 0, 0, 0x1f)
1461 #define MASK_R2_CALLR MASK_R2_OPX (0, 1, 1, 1)
1462 #define MATCH_R2_CALLR_N MATCH_R2_R_N (CALLR_N)
1463 #define MASK_R2_CALLR_N MASK_R2_R_N
1464 #define MATCH_R2_CMPEQ MATCH_R2_OPX0 (CMPEQ)
1465 #define MASK_R2_CMPEQ MASK_R2_OPX0
1466 #define MATCH_R2_CMPEQI MATCH_R2_OP (CMPEQI)
1467 #define MASK_R2_CMPEQI MASK_R2_OP
1468 #define MATCH_R2_CMPGE MATCH_R2_OPX0 (CMPGE)
1469 #define MASK_R2_CMPGE MASK_R2_OPX0
1470 #define MATCH_R2_CMPGEI MATCH_R2_OP (CMPGEI)
1471 #define MASK_R2_CMPGEI MASK_R2_OP
1472 #define MATCH_R2_CMPGEU MATCH_R2_OPX0 (CMPGEU)
1473 #define MASK_R2_CMPGEU MASK_R2_OPX0
1474 #define MATCH_R2_CMPGEUI MATCH_R2_OP (CMPGEUI)
1475 #define MASK_R2_CMPGEUI MASK_R2_OP
1476 #define MATCH_R2_CMPGT MATCH_R2_OPX0 (CMPLT)
1477 #define MASK_R2_CMPGT MASK_R2_OPX0
1478 #define MATCH_R2_CMPGTI MATCH_R2_OP (CMPGEI)
1479 #define MASK_R2_CMPGTI MASK_R2_OP
1480 #define MATCH_R2_CMPGTU MATCH_R2_OPX0 (CMPLTU)
1481 #define MASK_R2_CMPGTU MASK_R2_OPX0
1482 #define MATCH_R2_CMPGTUI MATCH_R2_OP (CMPGEUI)
1483 #define MASK_R2_CMPGTUI MASK_R2_OP
1484 #define MATCH_R2_CMPLE MATCH_R2_OPX0 (CMPGE)
1485 #define MASK_R2_CMPLE MASK_R2_OPX0
1486 #define MATCH_R2_CMPLEI MATCH_R2_OP (CMPLTI)
1487 #define MASK_R2_CMPLEI MASK_R2_OP
1488 #define MATCH_R2_CMPLEU MATCH_R2_OPX0 (CMPGEU)
1489 #define MASK_R2_CMPLEU MASK_R2_OPX0
1490 #define MATCH_R2_CMPLEUI MATCH_R2_OP (CMPLTUI)
1491 #define MASK_R2_CMPLEUI MASK_R2_OP
1492 #define MATCH_R2_CMPLT MATCH_R2_OPX0 (CMPLT)
1493 #define MASK_R2_CMPLT MASK_R2_OPX0
1494 #define MATCH_R2_CMPLTI MATCH_R2_OP (CMPLTI)
1495 #define MASK_R2_CMPLTI MASK_R2_OP
1496 #define MATCH_R2_CMPLTU MATCH_R2_OPX0 (CMPLTU)
1497 #define MASK_R2_CMPLTU MASK_R2_OPX0
1498 #define MATCH_R2_CMPLTUI MATCH_R2_OP (CMPLTUI)
1499 #define MASK_R2_CMPLTUI MASK_R2_OP
1500 #define MATCH_R2_CMPNE MATCH_R2_OPX0 (CMPNE)
1501 #define MASK_R2_CMPNE MASK_R2_OPX0
1502 #define MATCH_R2_CMPNEI MATCH_R2_OP (CMPNEI)
1503 #define MASK_R2_CMPNEI MASK_R2_OP
1504 #define MATCH_R2_CUSTOM MATCH_R2_OP (CUSTOM)
1505 #define MASK_R2_CUSTOM MASK_R2_OP
1506 #define MATCH_R2_DIV MATCH_R2_OPX0 (DIV)
1507 #define MASK_R2_DIV MASK_R2_OPX0
1508 #define MATCH_R2_DIVU MATCH_R2_OPX0 (DIVU)
1509 #define MASK_R2_DIVU MASK_R2_OPX0
1510 #define MATCH_R2_ENI MATCH_R2_OPX (ENI, 0, 0, 0)
1511 #define MASK_R2_ENI MASK_R2_OPX (1, 1, 1, 0)
1512 #define MATCH_R2_ERET MATCH_R2_OPX (ERET, 0x1d, 0x1e, 0)
1513 #define MASK_R2_ERET MASK_R2_OPX (1, 1, 1, 1)
1514 #define MATCH_R2_EXTRACT MATCH_R2_OPX (EXTRACT, 0, 0, 0)
1515 #define MASK_R2_EXTRACT MASK_R2_OPX (0, 0, 0, 0)
1516 #define MATCH_R2_FLUSHD MATCH_R2_DCACHE (FLUSHD)
1517 #define MASK_R2_FLUSHD MASK_R2_DCACHE
1518 #define MATCH_R2_FLUSHDA MATCH_R2_DCACHE (FLUSHDA)
1519 #define MASK_R2_FLUSHDA MASK_R2_DCACHE
1520 #define MATCH_R2_FLUSHI MATCH_R2_OPX (FLUSHI, 0, 0, 0)
1521 #define MASK_R2_FLUSHI MASK_R2_OPX (0, 1, 1, 1)
1522 #define MATCH_R2_FLUSHP MATCH_R2_OPX (FLUSHP, 0, 0, 0)
1523 #define MASK_R2_FLUSHP MASK_R2_OPX (1, 1, 1, 1)
1524 #define MATCH_R2_INITD MATCH_R2_DCACHE (INITD)
1525 #define MASK_R2_INITD MASK_R2_DCACHE
1526 #define MATCH_R2_INITDA MATCH_R2_DCACHE (INITDA)
1527 #define MASK_R2_INITDA MASK_R2_DCACHE
1528 #define MATCH_R2_INITI MATCH_R2_OPX (INITI, 0, 0, 0)
1529 #define MASK_R2_INITI MASK_R2_OPX (0, 1, 1, 1)
1530 #define MATCH_R2_INSERT MATCH_R2_OPX (INSERT, 0, 0, 0)
1531 #define MASK_R2_INSERT MASK_R2_OPX (0, 0, 0, 0)
1532 #define MATCH_R2_JMP MATCH_R2_OPX (JMP, 0, 0, 0)
1533 #define MASK_R2_JMP MASK_R2_OPX (0, 1, 1, 1)
1534 #define MATCH_R2_JMPI MATCH_R2_OP (JMPI)
1535 #define MASK_R2_JMPI MASK_R2_OP
1536 #define MATCH_R2_JMPR_N MATCH_R2_R_N (JMPR_N)
1537 #define MASK_R2_JMPR_N MASK_R2_R_N
1538 #define MATCH_R2_LDB MATCH_R2_OP (LDB)
1539 #define MASK_R2_LDB MASK_R2_OP
1540 #define MATCH_R2_LDBIO MATCH_R2_I12 (LDBIO)
1541 #define MASK_R2_LDBIO MASK_R2_I12
1542 #define MATCH_R2_LDBU MATCH_R2_OP (LDBU)
1543 #define MASK_R2_LDBU MASK_R2_OP
1544 #define MATCH_R2_LDBUIO MATCH_R2_I12 (LDBUIO)
1545 #define MASK_R2_LDBUIO MASK_R2_I12
1546 #define MATCH_R2_LDBU_N MATCH_R2_OP (LDBU_N)
1547 #define MASK_R2_LDBU_N MASK_R2_OP
1548 #define MATCH_R2_LDEX MATCH_R2_OPX (LDEX, 0, 0, 0)
1549 #define MASK_R2_LDEX MASK_R2_OPX (0, 1, 0, 1)
1550 #define MATCH_R2_LDH MATCH_R2_OP (LDH)
1551 #define MASK_R2_LDH MASK_R2_OP
1552 #define MATCH_R2_LDHIO MATCH_R2_I12 (LDHIO)
1553 #define MASK_R2_LDHIO MASK_R2_I12
1554 #define MATCH_R2_LDHU MATCH_R2_OP (LDHU)
1555 #define MASK_R2_LDHU MASK_R2_OP
1556 #define MATCH_R2_LDHUIO MATCH_R2_I12 (LDHUIO)
1557 #define MASK_R2_LDHUIO MASK_R2_I12
1558 #define MATCH_R2_LDHU_N MATCH_R2_OP (LDHU_N)
1559 #define MASK_R2_LDHU_N MASK_R2_OP
1560 #define MATCH_R2_LDSEX MATCH_R2_OPX (LDSEX, 0, 0, 0)
1561 #define MASK_R2_LDSEX MASK_R2_OPX (0, 1, 0, 1)
1562 #define MATCH_R2_LDW MATCH_R2_OP (LDW)
1563 #define MASK_R2_LDW MASK_R2_OP
1564 #define MATCH_R2_LDWIO MATCH_R2_I12 (LDWIO)
1565 #define MASK_R2_LDWIO MASK_R2_I12
1566 #define MATCH_R2_LDWM MATCH_R2_I12 (LDWM)
1567 #define MASK_R2_LDWM MASK_R2_I12
1568 #define MATCH_R2_LDWSP_N MATCH_R2_OP (LDWSP_N)
1569 #define MASK_R2_LDWSP_N MASK_R2_OP
1570 #define MATCH_R2_LDW_N MATCH_R2_OP (LDW_N)
1571 #define MASK_R2_LDW_N MASK_R2_OP
1572 #define MATCH_R2_MERGE MATCH_R2_OPX (MERGE, 0, 0, 0)
1573 #define MASK_R2_MERGE MASK_R2_OPX (0, 0, 0, 0)
1574 #define MATCH_R2_MOV MATCH_R2_OPX (ADD, 0, 0, 0)
1575 #define MASK_R2_MOV MASK_R2_OPX (0, 1, 0, 1)
1576 #define MATCH_R2_MOVHI MATCH_R2_OP (ORHI) | SET_IW_F2I16_A (0)
1577 #define MASK_R2_MOVHI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK
1578 #define MATCH_R2_MOVI MATCH_R2_OP (ADDI) | SET_IW_F2I16_A (0)
1579 #define MASK_R2_MOVI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK
1580 #define MATCH_R2_MOVUI MATCH_R2_OP (ORI) | SET_IW_F2I16_A (0)
1581 #define MASK_R2_MOVUI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK
1582 #define MATCH_R2_MOV_N MATCH_R2_OP (MOV_N)
1583 #define MASK_R2_MOV_N MASK_R2_OP
1584 #define MATCH_R2_MOVI_N MATCH_R2_OP (MOVI_N)
1585 #define MASK_R2_MOVI_N MASK_R2_OP
1586 #define MATCH_R2_MUL MATCH_R2_OPX0 (MUL)
1587 #define MASK_R2_MUL MASK_R2_OPX0
1588 #define MATCH_R2_MULI MATCH_R2_OP (MULI)
1589 #define MASK_R2_MULI MASK_R2_OP
1590 #define MATCH_R2_MULXSS MATCH_R2_OPX0 (MULXSS)
1591 #define MASK_R2_MULXSS MASK_R2_OPX0
1592 #define MATCH_R2_MULXSU MATCH_R2_OPX0 (MULXSU)
1593 #define MASK_R2_MULXSU MASK_R2_OPX0
1594 #define MATCH_R2_MULXUU MATCH_R2_OPX0 (MULXUU)
1595 #define MASK_R2_MULXUU MASK_R2_OPX0
1596 #define MATCH_R2_NEG_N MATCH_R2_R_N (NEG_N)
1597 #define MASK_R2_NEG_N MASK_R2_R_N
1598 #define MATCH_R2_NEXTPC MATCH_R2_OPX (NEXTPC, 0, 0, 0)
1599 #define MASK_R2_NEXTPC MASK_R2_OPX (1, 1, 0, 1)
1600 #define MATCH_R2_NOP MATCH_R2_OPX (ADD, 0, 0, 0)
1601 #define MASK_R2_NOP MASK_R2_OPX (1, 1, 1, 1)
1602 #define MATCH_R2_NOP_N (MATCH_R2_OP (MOV_N) | SET_IW_F2_A (0) | SET_IW_F2_B (0))
1603 #define MASK_R2_NOP_N (MASK_R2_OP | IW_F2_A_SHIFTED_MASK | IW_F2_B_SHIFTED_MASK)
1604 #define MATCH_R2_NOR MATCH_R2_OPX0 (NOR)
1605 #define MASK_R2_NOR MASK_R2_OPX0
1606 #define MATCH_R2_NOT_N MATCH_R2_R_N (NOT_N)
1607 #define MASK_R2_NOT_N MASK_R2_R_N
1608 #define MATCH_R2_OR MATCH_R2_OPX0 (OR)
1609 #define MASK_R2_OR MASK_R2_OPX0
1610 #define MATCH_R2_OR_N MATCH_R2_R_N (OR_N)
1611 #define MASK_R2_OR_N MASK_R2_R_N
1612 #define MATCH_R2_ORHI MATCH_R2_OP (ORHI)
1613 #define MASK_R2_ORHI MASK_R2_OP
1614 #define MATCH_R2_ORI MATCH_R2_OP (ORI)
1615 #define MASK_R2_ORI MASK_R2_OP
1616 #define MATCH_R2_POP_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_POP_N))
1617 #define MASK_R2_POP_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK)
1618 #define MATCH_R2_PUSH_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_PUSH_N))
1619 #define MASK_R2_PUSH_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK)
1620 #define MATCH_R2_RDCTL MATCH_R2_OPX (RDCTL, 0, 0, 0)
1621 #define MASK_R2_RDCTL MASK_R2_OPX (1, 1, 0, 0)
1622 #define MATCH_R2_RDPRS MATCH_R2_I12 (RDPRS)
1623 #define MASK_R2_RDPRS MASK_R2_I12
1624 #define MATCH_R2_RET MATCH_R2_OPX (RET, 0x1f, 0, 0)
1625 #define MASK_R2_RET MASK_R2_OPX (1, 1, 1, 1)
1626 #define MATCH_R2_RET_N (MATCH_R2_R_N (RET_N) | SET_IW_X2L5_IMM5 (0))
1627 #define MASK_R2_RET_N (MASK_R2_R_N | IW_X2L5_IMM5_SHIFTED_MASK)
1628 #define MATCH_R2_ROL MATCH_R2_OPX0 (ROL)
1629 #define MASK_R2_ROL MASK_R2_OPX0
1630 #define MATCH_R2_ROLI MATCH_R2_OPX (ROLI, 0, 0, 0)
1631 #define MASK_R2_ROLI MASK_R2_OPX (0, 1, 0, 0)
1632 #define MATCH_R2_ROR MATCH_R2_OPX0 (ROR)
1633 #define MASK_R2_ROR MASK_R2_OPX0
1634 #define MATCH_R2_SLL MATCH_R2_OPX0 (SLL)
1635 #define MASK_R2_SLL MASK_R2_OPX0
1636 #define MATCH_R2_SLLI MATCH_R2_OPX (SLLI, 0, 0, 0)
1637 #define MASK_R2_SLLI MASK_R2_OPX (0, 1, 0, 0)
1638 #define MATCH_R2_SLL_N MATCH_R2_R_N (SLL_N)
1639 #define MASK_R2_SLL_N MASK_R2_R_N
1640 #define MATCH_R2_SLLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SLLI_N))
1641 #define MASK_R2_SLLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK)
1642 #define MATCH_R2_SPADDI_N MATCH_R2_OP (SPADDI_N)
1643 #define MASK_R2_SPADDI_N MASK_R2_OP
1644 #define MATCH_R2_SPDECI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPDECI_N))
1645 #define MASK_R2_SPDECI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK)
1646 #define MATCH_R2_SPINCI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPINCI_N))
1647 #define MASK_R2_SPINCI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK)
1648 #define MATCH_R2_SRA MATCH_R2_OPX0 (SRA)
1649 #define MASK_R2_SRA MASK_R2_OPX0
1650 #define MATCH_R2_SRAI MATCH_R2_OPX (SRAI, 0, 0, 0)
1651 #define MASK_R2_SRAI MASK_R2_OPX (0, 1, 0, 0)
1652 #define MATCH_R2_SRL MATCH_R2_OPX0 (SRL)
1653 #define MASK_R2_SRL MASK_R2_OPX0
1654 #define MATCH_R2_SRLI MATCH_R2_OPX (SRLI, 0, 0, 0)
1655 #define MASK_R2_SRLI MASK_R2_OPX (0, 1, 0, 0)
1656 #define MATCH_R2_SRL_N MATCH_R2_R_N (SRL_N)
1657 #define MASK_R2_SRL_N MASK_R2_R_N
1658 #define MATCH_R2_SRLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SRLI_N))
1659 #define MASK_R2_SRLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK)
1660 #define MATCH_R2_STB MATCH_R2_OP (STB)
1661 #define MASK_R2_STB MASK_R2_OP
1662 #define MATCH_R2_STBIO MATCH_R2_I12 (STBIO)
1663 #define MASK_R2_STBIO MASK_R2_I12
1664 #define MATCH_R2_STB_N MATCH_R2_OP (STB_N)
1665 #define MASK_R2_STB_N MASK_R2_OP
1666 #define MATCH_R2_STBZ_N (MATCH_R2_OP (STZ_N) | SET_IW_T1X1I6_X (R2_STZ_N_STBZ_N))
1667 #define MASK_R2_STBZ_N (MASK_R2_OP | IW_T1X1I6_X_SHIFTED_MASK)
1668 #define MATCH_R2_STEX MATCH_R2_OPX0 (STEX)
1669 #define MASK_R2_STEX MASK_R2_OPX0
1670 #define MATCH_R2_STH MATCH_R2_OP (STH)
1671 #define MASK_R2_STH MASK_R2_OP
1672 #define MATCH_R2_STHIO MATCH_R2_I12 (STHIO)
1673 #define MASK_R2_STHIO MASK_R2_I12
1674 #define MATCH_R2_STH_N MATCH_R2_OP (STH_N)
1675 #define MASK_R2_STH_N MASK_R2_OP
1676 #define MATCH_R2_STSEX MATCH_R2_OPX0 (STSEX)
1677 #define MASK_R2_STSEX MASK_R2_OPX0
1678 #define MATCH_R2_STW MATCH_R2_OP (STW)
1679 #define MASK_R2_STW MASK_R2_OP
1680 #define MATCH_R2_STWIO MATCH_R2_I12 (STWIO)
1681 #define MASK_R2_STWIO MASK_R2_I12
1682 #define MATCH_R2_STWM MATCH_R2_I12 (STWM)
1683 #define MASK_R2_STWM MASK_R2_I12
1684 #define MATCH_R2_STWSP_N MATCH_R2_OP (STWSP_N)
1685 #define MASK_R2_STWSP_N MASK_R2_OP
1686 #define MATCH_R2_STW_N MATCH_R2_OP (STW_N)
1687 #define MASK_R2_STW_N MASK_R2_OP
1688 #define MATCH_R2_STWZ_N MATCH_R2_OP (STZ_N)
1689 #define MASK_R2_STWZ_N MASK_R2_OP
1690 #define MATCH_R2_SUB MATCH_R2_OPX0 (SUB)
1691 #define MASK_R2_SUB MASK_R2_OPX0
1692 #define MATCH_R2_SUBI MATCH_R2_OP (ADDI)
1693 #define MASK_R2_SUBI MASK_R2_OP
1694 #define MATCH_R2_SUB_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_SUB_N))
1695 #define MASK_R2_SUB_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK)
1696 #define MATCH_R2_SUBI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_SUBI_N))
1697 #define MASK_R2_SUBI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK)
1698 #define MATCH_R2_SYNC MATCH_R2_OPX (SYNC, 0, 0, 0)
1699 #define MASK_R2_SYNC MASK_R2_OPX (1, 1, 1, 1)
1700 #define MATCH_R2_TRAP MATCH_R2_OPX (TRAP, 0, 0, 0x1d)
1701 #define MASK_R2_TRAP MASK_R2_OPX (1, 1, 1, 0)
1702 #define MATCH_R2_TRAP_N MATCH_R2_R_N (TRAP_N)
1703 #define MASK_R2_TRAP_N MASK_R2_R_N
1704 #define MATCH_R2_WRCTL MATCH_R2_OPX (WRCTL, 0, 0, 0)
1705 #define MASK_R2_WRCTL MASK_R2_OPX (0, 1, 1, 0)
1706 #define MATCH_R2_WRPIE MATCH_R2_OPX (WRPIE, 0, 0, 0)
1707 #define MASK_R2_WRPIE MASK_R2_OPX (0, 1, 0, 1)
1708 #define MATCH_R2_WRPRS MATCH_R2_OPX (WRPRS, 0, 0, 0)
1709 #define MASK_R2_WRPRS MASK_R2_OPX (0, 1, 0, 1)
1710 #define MATCH_R2_XOR MATCH_R2_OPX0 (XOR)
1711 #define MASK_R2_XOR MASK_R2_OPX0
1712 #define MATCH_R2_XORHI MATCH_R2_OP (XORHI)
1713 #define MASK_R2_XORHI MASK_R2_OP
1714 #define MATCH_R2_XORI MATCH_R2_OP (XORI)
1715 #define MASK_R2_XORI MASK_R2_OP
1716 #define MATCH_R2_XOR_N MATCH_R2_R_N (XOR_N)
1717 #define MASK_R2_XOR_N MASK_R2_R_N
1718
1719 #endif /* _NIOS2R2_H */
1720
1721
1722 /* These are the data structures used to hold the instruction information. */
1723 extern const struct nios2_opcode nios2_r1_opcodes[];
1724 extern const int nios2_num_r1_opcodes;
1725 extern const struct nios2_opcode nios2_r2_opcodes[];
1726 extern const int nios2_num_r2_opcodes;
1727 extern struct nios2_opcode *nios2_opcodes;
1728 extern int nios2_num_opcodes;
1729
1730 /* These are the data structures used to hold the register information. */
1731 extern const struct nios2_reg nios2_builtin_regs[];
1732 extern struct nios2_reg *nios2_regs;
1733 extern const int nios2_num_builtin_regs;
1734 extern int nios2_num_regs;
1735
1736 /* Return the opcode descriptor for a single instruction. */
1737 extern const struct nios2_opcode *
1738 nios2_find_opcode_hash (unsigned long, unsigned long);
1739
1740 /* Lookup tables for R2 immediate decodings. */
1741 extern unsigned int nios2_r2_asi_n_mappings[];
1742 extern const int nios2_num_r2_asi_n_mappings;
1743 extern unsigned int nios2_r2_shi_n_mappings[];
1744 extern const int nios2_num_r2_shi_n_mappings;
1745 extern unsigned int nios2_r2_andi_n_mappings[];
1746 extern const int nios2_num_r2_andi_n_mappings;
1747
1748 /* Lookup table for 3-bit register decodings. */
1749 extern int nios2_r2_reg3_mappings[];
1750 extern const int nios2_num_r2_reg3_mappings;
1751
1752 /* Lookup table for REG_RANGE value list decodings. */
1753 extern unsigned long nios2_r2_reg_range_mappings[];
1754 extern const int nios2_num_r2_reg_range_mappings;
1755
1756 #endif /* _NIOS2_H */
1757
1758 /*#include "sysdep.h"
1759 #include <stdio.h>
1760 #include "opcode/nios2.h"
1761 */
1762 /* Register string table */
1763
1764 const struct nios2_reg nios2_builtin_regs[] = {
1765 /* Standard register names. */
1766 {"zero", 0, REG_NORMAL},
1767 {"at", 1, REG_NORMAL}, /* assembler temporary */
1768 {"r2", 2, REG_NORMAL | REG_3BIT | REG_LDWM},
1769 {"r3", 3, REG_NORMAL | REG_3BIT | REG_LDWM},
1770 {"r4", 4, REG_NORMAL | REG_3BIT | REG_LDWM},
1771 {"r5", 5, REG_NORMAL | REG_3BIT | REG_LDWM},
1772 {"r6", 6, REG_NORMAL | REG_3BIT | REG_LDWM},
1773 {"r7", 7, REG_NORMAL | REG_3BIT | REG_LDWM},
1774 {"r8", 8, REG_NORMAL | REG_LDWM},
1775 {"r9", 9, REG_NORMAL | REG_LDWM},
1776 {"r10", 10, REG_NORMAL | REG_LDWM},
1777 {"r11", 11, REG_NORMAL | REG_LDWM},
1778 {"r12", 12, REG_NORMAL | REG_LDWM},
1779 {"r13", 13, REG_NORMAL | REG_LDWM},
1780 {"r14", 14, REG_NORMAL | REG_LDWM},
1781 {"r15", 15, REG_NORMAL | REG_LDWM},
1782 {"r16", 16, REG_NORMAL | REG_3BIT | REG_LDWM | REG_POP},
1783 {"r17", 17, REG_NORMAL | REG_3BIT | REG_LDWM | REG_POP},
1784 {"r18", 18, REG_NORMAL | REG_LDWM | REG_POP},
1785 {"r19", 19, REG_NORMAL | REG_LDWM | REG_POP},
1786 {"r20", 20, REG_NORMAL | REG_LDWM | REG_POP},
1787 {"r21", 21, REG_NORMAL | REG_LDWM | REG_POP},
1788 {"r22", 22, REG_NORMAL | REG_LDWM | REG_POP},
1789 {"r23", 23, REG_NORMAL | REG_LDWM | REG_POP},
1790 {"et", 24, REG_NORMAL},
1791 {"bt", 25, REG_NORMAL},
1792 {"gp", 26, REG_NORMAL}, /* global pointer */
1793 {"sp", 27, REG_NORMAL}, /* stack pointer */
1794 {"fp", 28, REG_NORMAL | REG_LDWM | REG_POP}, /* frame pointer */
1795 {"ea", 29, REG_NORMAL}, /* exception return address */
1796 {"sstatus", 30, REG_NORMAL}, /* saved processor status */
1797 {"ra", 31, REG_NORMAL | REG_LDWM | REG_POP}, /* return address */
1798
1799 /* Alternative names for special registers. */
1800 {"r0", 0, REG_NORMAL},
1801 {"r1", 1, REG_NORMAL},
1802 {"r24", 24, REG_NORMAL},
1803 {"r25", 25, REG_NORMAL},
1804 {"r26", 26, REG_NORMAL},
1805 {"r27", 27, REG_NORMAL},
1806 {"r28", 28, REG_NORMAL | REG_LDWM | REG_POP},
1807 {"r29", 29, REG_NORMAL},
1808 {"r30", 30, REG_NORMAL},
1809 {"ba", 30, REG_NORMAL}, /* breakpoint return address */
1810 {"r31", 31, REG_NORMAL | REG_LDWM | REG_POP},
1811
1812 /* Control register names. */
1813 {"status", 0, REG_CONTROL},
1814 {"estatus", 1, REG_CONTROL},
1815 {"bstatus", 2, REG_CONTROL},
1816 {"ienable", 3, REG_CONTROL},
1817 {"ipending", 4, REG_CONTROL},
1818 {"cpuid", 5, REG_CONTROL},
1819 {"ctl6", 6, REG_CONTROL},
1820 {"exception", 7, REG_CONTROL},
1821 {"pteaddr", 8, REG_CONTROL},
1822 {"tlbacc", 9, REG_CONTROL},
1823 {"tlbmisc", 10, REG_CONTROL},
1824 {"eccinj", 11, REG_CONTROL},
1825 {"badaddr", 12, REG_CONTROL},
1826 {"config", 13, REG_CONTROL},
1827 {"mpubase", 14, REG_CONTROL},
1828 {"mpuacc", 15, REG_CONTROL},
1829 {"ctl16", 16, REG_CONTROL},
1830 {"ctl17", 17, REG_CONTROL},
1831 {"ctl18", 18, REG_CONTROL},
1832 {"ctl19", 19, REG_CONTROL},
1833 {"ctl20", 20, REG_CONTROL},
1834 {"ctl21", 21, REG_CONTROL},
1835 {"ctl22", 22, REG_CONTROL},
1836 {"ctl23", 23, REG_CONTROL},
1837 {"ctl24", 24, REG_CONTROL},
1838 {"ctl25", 25, REG_CONTROL},
1839 {"ctl26", 26, REG_CONTROL},
1840 {"ctl27", 27, REG_CONTROL},
1841 {"ctl28", 28, REG_CONTROL},
1842 {"ctl29", 29, REG_CONTROL},
1843 {"ctl30", 30, REG_CONTROL},
1844 {"ctl31", 31, REG_CONTROL},
1845
1846 /* Alternative names for special control registers. */
1847 {"ctl0", 0, REG_CONTROL},
1848 {"ctl1", 1, REG_CONTROL},
1849 {"ctl2", 2, REG_CONTROL},
1850 {"ctl3", 3, REG_CONTROL},
1851 {"ctl4", 4, REG_CONTROL},
1852 {"ctl5", 5, REG_CONTROL},
1853 {"ctl7", 7, REG_CONTROL},
1854 {"ctl8", 8, REG_CONTROL},
1855 {"ctl9", 9, REG_CONTROL},
1856 {"ctl10", 10, REG_CONTROL},
1857 {"ctl11", 11, REG_CONTROL},
1858 {"ctl12", 12, REG_CONTROL},
1859 {"ctl13", 13, REG_CONTROL},
1860 {"ctl14", 14, REG_CONTROL},
1861 {"ctl15", 15, REG_CONTROL},
1862
1863 /* Coprocessor register names. */
1864 {"c0", 0, REG_COPROCESSOR},
1865 {"c1", 1, REG_COPROCESSOR},
1866 {"c2", 2, REG_COPROCESSOR},
1867 {"c3", 3, REG_COPROCESSOR},
1868 {"c4", 4, REG_COPROCESSOR},
1869 {"c5", 5, REG_COPROCESSOR},
1870 {"c6", 6, REG_COPROCESSOR},
1871 {"c7", 7, REG_COPROCESSOR},
1872 {"c8", 8, REG_COPROCESSOR},
1873 {"c9", 9, REG_COPROCESSOR},
1874 {"c10", 10, REG_COPROCESSOR},
1875 {"c11", 11, REG_COPROCESSOR},
1876 {"c12", 12, REG_COPROCESSOR},
1877 {"c13", 13, REG_COPROCESSOR},
1878 {"c14", 14, REG_COPROCESSOR},
1879 {"c15", 15, REG_COPROCESSOR},
1880 {"c16", 16, REG_COPROCESSOR},
1881 {"c17", 17, REG_COPROCESSOR},
1882 {"c18", 18, REG_COPROCESSOR},
1883 {"c19", 19, REG_COPROCESSOR},
1884 {"c20", 20, REG_COPROCESSOR},
1885 {"c21", 21, REG_COPROCESSOR},
1886 {"c22", 22, REG_COPROCESSOR},
1887 {"c23", 23, REG_COPROCESSOR},
1888 {"c24", 24, REG_COPROCESSOR},
1889 {"c25", 25, REG_COPROCESSOR},
1890 {"c26", 26, REG_COPROCESSOR},
1891 {"c27", 27, REG_COPROCESSOR},
1892 {"c28", 28, REG_COPROCESSOR},
1893 {"c29", 29, REG_COPROCESSOR},
1894 {"c30", 30, REG_COPROCESSOR},
1895 {"c31", 31, REG_COPROCESSOR},
1896 };
1897
1898 #define NIOS2_NUM_REGS \
1899 ((sizeof nios2_builtin_regs) / (sizeof (nios2_builtin_regs[0])))
1900 const int nios2_num_builtin_regs = NIOS2_NUM_REGS;
1901
1902 /* This is not const in order to allow for dynamic extensions to the
1903 built-in instruction set. */
1904 struct nios2_reg *nios2_regs = (struct nios2_reg *) nios2_builtin_regs;
1905 int nios2_num_regs = NIOS2_NUM_REGS;
1906 #undef NIOS2_NUM_REGS
1907
1908 /* This is the opcode table used by the Nios II GNU as, disassembler
1909 and GDB. */
1910 const struct nios2_opcode nios2_r1_opcodes[] =
1911 {
1912 /* { name, args, args_test, num_args, size, format,
1913 match, mask, pinfo, overflow } */
1914 {"add", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1915 MATCH_R1_ADD, MASK_R1_ADD, 0, no_overflow},
1916 {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1917 MATCH_R1_ADDI, MASK_R1_ADDI, 0, signed_immed16_overflow},
1918 {"and", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1919 MATCH_R1_AND, MASK_R1_AND, 0, no_overflow},
1920 {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
1921 MATCH_R1_ANDHI, MASK_R1_ANDHI, 0, unsigned_immed16_overflow},
1922 {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
1923 MATCH_R1_ANDI, MASK_R1_ANDI, 0, unsigned_immed16_overflow},
1924 {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1925 MATCH_R1_BEQ, MASK_R1_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow},
1926 {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1927 MATCH_R1_BGE, MASK_R1_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow},
1928 {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1929 MATCH_R1_BGEU, MASK_R1_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow},
1930 {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1931 MATCH_R1_BGT, MASK_R1_BGT,
1932 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
1933 {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1934 MATCH_R1_BGTU, MASK_R1_BGTU,
1935 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
1936 {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1937 MATCH_R1_BLE, MASK_R1_BLE,
1938 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
1939 {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1940 MATCH_R1_BLEU, MASK_R1_BLEU,
1941 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
1942 {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1943 MATCH_R1_BLT, MASK_R1_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow},
1944 {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1945 MATCH_R1_BLTU, MASK_R1_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow},
1946 {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
1947 MATCH_R1_BNE, MASK_R1_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow},
1948 {"br", "o", "o,E", 1, 4, iw_i_type,
1949 MATCH_R1_BR, MASK_R1_BR, NIOS2_INSN_UBRANCH, branch_target_overflow},
1950 {"break", "j", "j,E", 1, 4, iw_r_type,
1951 MATCH_R1_BREAK, MASK_R1_BREAK, NIOS2_INSN_OPTARG, no_overflow},
1952 {"bret", "", "E", 0, 4, iw_r_type,
1953 MATCH_R1_BRET, MASK_R1_BRET, 0, no_overflow},
1954 {"call", "m", "m,E", 1, 4, iw_j_type,
1955 MATCH_R1_CALL, MASK_R1_CALL, NIOS2_INSN_CALL, call_target_overflow},
1956 {"callr", "s", "s,E", 1, 4, iw_r_type,
1957 MATCH_R1_CALLR, MASK_R1_CALLR, 0, no_overflow},
1958 {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1959 MATCH_R1_CMPEQ, MASK_R1_CMPEQ, 0, no_overflow},
1960 {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1961 MATCH_R1_CMPEQI, MASK_R1_CMPEQI, 0, signed_immed16_overflow},
1962 {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1963 MATCH_R1_CMPGE, MASK_R1_CMPGE, 0, no_overflow},
1964 {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1965 MATCH_R1_CMPGEI, MASK_R1_CMPGEI, 0, signed_immed16_overflow},
1966 {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1967 MATCH_R1_CMPGEU, MASK_R1_CMPGEU, 0, no_overflow},
1968 {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
1969 MATCH_R1_CMPGEUI, MASK_R1_CMPGEUI, 0, unsigned_immed16_overflow},
1970 {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1971 MATCH_R1_CMPGT, MASK_R1_CMPGT, NIOS2_INSN_MACRO, no_overflow},
1972 {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1973 MATCH_R1_CMPGTI, MASK_R1_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow},
1974 {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1975 MATCH_R1_CMPGTU, MASK_R1_CMPGTU, NIOS2_INSN_MACRO, no_overflow},
1976 {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
1977 MATCH_R1_CMPGTUI, MASK_R1_CMPGTUI,
1978 NIOS2_INSN_MACRO, unsigned_immed16_overflow},
1979 {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1980 MATCH_R1_CMPLE, MASK_R1_CMPLE, NIOS2_INSN_MACRO, no_overflow},
1981 {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1982 MATCH_R1_CMPLEI, MASK_R1_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow},
1983 {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1984 MATCH_R1_CMPLEU, MASK_R1_CMPLEU, NIOS2_INSN_MACRO, no_overflow},
1985 {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
1986 MATCH_R1_CMPLEUI, MASK_R1_CMPLEUI,
1987 NIOS2_INSN_MACRO, unsigned_immed16_overflow},
1988 {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1989 MATCH_R1_CMPLT, MASK_R1_CMPLT, 0, no_overflow},
1990 {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1991 MATCH_R1_CMPLTI, MASK_R1_CMPLTI, 0, signed_immed16_overflow},
1992 {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1993 MATCH_R1_CMPLTU, MASK_R1_CMPLTU, 0, no_overflow},
1994 {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
1995 MATCH_R1_CMPLTUI, MASK_R1_CMPLTUI, 0, unsigned_immed16_overflow},
1996 {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
1997 MATCH_R1_CMPNE, MASK_R1_CMPNE, 0, no_overflow},
1998 {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
1999 MATCH_R1_CMPNEI, MASK_R1_CMPNEI, 0, signed_immed16_overflow},
2000 {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_custom_type,
2001 MATCH_R1_CUSTOM, MASK_R1_CUSTOM, 0, custom_opcode_overflow},
2002 {"div", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2003 MATCH_R1_DIV, MASK_R1_DIV, 0, no_overflow},
2004 {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2005 MATCH_R1_DIVU, MASK_R1_DIVU, 0, no_overflow},
2006 {"eret", "", "E", 0, 4, iw_r_type,
2007 MATCH_R1_ERET, MASK_R1_ERET, 0, no_overflow},
2008 {"flushd", "i(s)", "i(s),E", 2, 4, iw_i_type,
2009 MATCH_R1_FLUSHD, MASK_R1_FLUSHD, 0, address_offset_overflow},
2010 {"flushda", "i(s)", "i(s),E", 2, 4, iw_i_type,
2011 MATCH_R1_FLUSHDA, MASK_R1_FLUSHDA, 0, address_offset_overflow},
2012 {"flushi", "s", "s,E", 1, 4, iw_r_type,
2013 MATCH_R1_FLUSHI, MASK_R1_FLUSHI, 0, no_overflow},
2014 {"flushp", "", "E", 0, 4, iw_r_type,
2015 MATCH_R1_FLUSHP, MASK_R1_FLUSHP, 0, no_overflow},
2016 {"initd", "i(s)", "i(s),E", 2, 4, iw_i_type,
2017 MATCH_R1_INITD, MASK_R1_INITD, 0, address_offset_overflow},
2018 {"initda", "i(s)", "i(s),E", 2, 4, iw_i_type,
2019 MATCH_R1_INITDA, MASK_R1_INITDA, 0, address_offset_overflow},
2020 {"initi", "s", "s,E", 1, 4, iw_r_type,
2021 MATCH_R1_INITI, MASK_R1_INITI, 0, no_overflow},
2022 {"jmp", "s", "s,E", 1, 4, iw_r_type,
2023 MATCH_R1_JMP, MASK_R1_JMP, 0, no_overflow},
2024 {"jmpi", "m", "m,E", 1, 4, iw_j_type,
2025 MATCH_R1_JMPI, MASK_R1_JMPI, 0, call_target_overflow},
2026 {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2027 MATCH_R1_LDB, MASK_R1_LDB, 0, address_offset_overflow},
2028 {"ldbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2029 MATCH_R1_LDBIO, MASK_R1_LDBIO, 0, address_offset_overflow},
2030 {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2031 MATCH_R1_LDBU, MASK_R1_LDBU, 0, address_offset_overflow},
2032 {"ldbuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2033 MATCH_R1_LDBUIO, MASK_R1_LDBUIO, 0, address_offset_overflow},
2034 {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2035 MATCH_R1_LDH, MASK_R1_LDH, 0, address_offset_overflow},
2036 {"ldhio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2037 MATCH_R1_LDHIO, MASK_R1_LDHIO, 0, address_offset_overflow},
2038 {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2039 MATCH_R1_LDHU, MASK_R1_LDHU, 0, address_offset_overflow},
2040 {"ldhuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2041 MATCH_R1_LDHUIO, MASK_R1_LDHUIO, 0, address_offset_overflow},
2042 {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2043 MATCH_R1_LDW, MASK_R1_LDW, 0, address_offset_overflow},
2044 {"ldwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2045 MATCH_R1_LDWIO, MASK_R1_LDWIO, 0, address_offset_overflow},
2046 {"mov", "d,s", "d,s,E", 2, 4, iw_r_type,
2047 MATCH_R1_MOV, MASK_R1_MOV, NIOS2_INSN_MACRO_MOV, no_overflow},
2048 {"movhi", "t,u", "t,u,E", 2, 4, iw_i_type,
2049 MATCH_R1_MOVHI, MASK_R1_MOVHI,
2050 NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
2051 {"movi", "t,i", "t,i,E", 2, 4, iw_i_type,
2052 MATCH_R1_MOVI, MASK_R1_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow},
2053 {"movia", "t,o", "t,o,E", 2, 4, iw_i_type,
2054 MATCH_R1_ORHI, MASK_R1_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow},
2055 {"movui", "t,u", "t,u,E", 2, 4, iw_i_type,
2056 MATCH_R1_MOVUI, MASK_R1_MOVUI,
2057 NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
2058 {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2059 MATCH_R1_MUL, MASK_R1_MUL, 0, no_overflow},
2060 {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
2061 MATCH_R1_MULI, MASK_R1_MULI, 0, signed_immed16_overflow},
2062 {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2063 MATCH_R1_MULXSS, MASK_R1_MULXSS, 0, no_overflow},
2064 {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2065 MATCH_R1_MULXSU, MASK_R1_MULXSU, 0, no_overflow},
2066 {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2067 MATCH_R1_MULXUU, MASK_R1_MULXUU, 0, no_overflow},
2068 {"nextpc", "d", "d,E", 1, 4, iw_r_type,
2069 MATCH_R1_NEXTPC, MASK_R1_NEXTPC, 0, no_overflow},
2070 {"nop", "", "E", 0, 4, iw_r_type,
2071 MATCH_R1_NOP, MASK_R1_NOP, NIOS2_INSN_MACRO_MOV, no_overflow},
2072 {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2073 MATCH_R1_NOR, MASK_R1_NOR, 0, no_overflow},
2074 {"or", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2075 MATCH_R1_OR, MASK_R1_OR, 0, no_overflow},
2076 {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
2077 MATCH_R1_ORHI, MASK_R1_ORHI, 0, unsigned_immed16_overflow},
2078 {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
2079 MATCH_R1_ORI, MASK_R1_ORI, 0, unsigned_immed16_overflow},
2080 {"rdctl", "d,c", "d,c,E", 2, 4, iw_r_type,
2081 MATCH_R1_RDCTL, MASK_R1_RDCTL, 0, no_overflow},
2082 {"rdprs", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
2083 MATCH_R1_RDPRS, MASK_R1_RDPRS, 0, signed_immed16_overflow},
2084 {"ret", "", "E", 0, 4, iw_r_type,
2085 MATCH_R1_RET, MASK_R1_RET, 0, no_overflow},
2086 {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2087 MATCH_R1_ROL, MASK_R1_ROL, 0, no_overflow},
2088 {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
2089 MATCH_R1_ROLI, MASK_R1_ROLI, 0, unsigned_immed5_overflow},
2090 {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2091 MATCH_R1_ROR, MASK_R1_ROR, 0, no_overflow},
2092 {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2093 MATCH_R1_SLL, MASK_R1_SLL, 0, no_overflow},
2094 {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
2095 MATCH_R1_SLLI, MASK_R1_SLLI, 0, unsigned_immed5_overflow},
2096 {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2097 MATCH_R1_SRA, MASK_R1_SRA, 0, no_overflow},
2098 {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
2099 MATCH_R1_SRAI, MASK_R1_SRAI, 0, unsigned_immed5_overflow},
2100 {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2101 MATCH_R1_SRL, MASK_R1_SRL, 0, no_overflow},
2102 {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
2103 MATCH_R1_SRLI, MASK_R1_SRLI, 0, unsigned_immed5_overflow},
2104 {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2105 MATCH_R1_STB, MASK_R1_STB, 0, address_offset_overflow},
2106 {"stbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2107 MATCH_R1_STBIO, MASK_R1_STBIO, 0, address_offset_overflow},
2108 {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2109 MATCH_R1_STH, MASK_R1_STH, 0, address_offset_overflow},
2110 {"sthio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2111 MATCH_R1_STHIO, MASK_R1_STHIO, 0, address_offset_overflow},
2112 {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2113 MATCH_R1_STW, MASK_R1_STW, 0, address_offset_overflow},
2114 {"stwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
2115 MATCH_R1_STWIO, MASK_R1_STWIO, 0, address_offset_overflow},
2116 {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2117 MATCH_R1_SUB, MASK_R1_SUB, 0, no_overflow},
2118 {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
2119 MATCH_R1_SUBI, MASK_R1_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow},
2120 {"sync", "", "E", 0, 4, iw_r_type,
2121 MATCH_R1_SYNC, MASK_R1_SYNC, 0, no_overflow},
2122 {"trap", "j", "j,E", 1, 4, iw_r_type,
2123 MATCH_R1_TRAP, MASK_R1_TRAP, NIOS2_INSN_OPTARG, no_overflow},
2124 {"wrctl", "c,s", "c,s,E", 2, 4, iw_r_type,
2125 MATCH_R1_WRCTL, MASK_R1_WRCTL, 0, no_overflow},
2126 {"wrprs", "d,s", "d,s,E", 2, 4, iw_r_type,
2127 MATCH_R1_WRPRS, MASK_R1_WRPRS, 0, no_overflow},
2128 {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
2129 MATCH_R1_XOR, MASK_R1_XOR, 0, no_overflow},
2130 {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
2131 MATCH_R1_XORHI, MASK_R1_XORHI, 0, unsigned_immed16_overflow},
2132 {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
2133 MATCH_R1_XORI, MASK_R1_XORI, 0, unsigned_immed16_overflow}
2134 };
2135
2136 #define NIOS2_NUM_R1_OPCODES \
2137 ((sizeof nios2_r1_opcodes) / (sizeof (nios2_r1_opcodes[0])))
2138 const int nios2_num_r1_opcodes = NIOS2_NUM_R1_OPCODES;
2139
2140
2141 const struct nios2_opcode nios2_r2_opcodes[] =
2142 {
2143 /* { name, args, args_test, num_args, size, format,
2144 match, mask, pinfo, overflow } */
2145 {"add", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2146 MATCH_R2_ADD, MASK_R2_ADD, 0, no_overflow},
2147 {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2148 MATCH_R2_ADDI, MASK_R2_ADDI, 0, signed_immed16_overflow},
2149 {"add.n", "D,S,T", "D,S,T,E", 3, 2, iw_T3X1_type,
2150 MATCH_R2_ADD_N, MASK_R2_ADD_N, 0, no_overflow},
2151 {"addi.n", "D,S,e", "D,S,e,E", 3, 2, iw_T2X1I3_type,
2152 MATCH_R2_ADDI_N, MASK_R2_ADDI_N, 0, enumeration_overflow},
2153 {"and", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2154 MATCH_R2_AND, MASK_R2_AND, 0, no_overflow},
2155 {"andchi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2156 MATCH_R2_ANDCHI, MASK_R2_ANDCHI, 0, unsigned_immed16_overflow},
2157 {"andci", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2158 MATCH_R2_ANDCI, MASK_R2_ANDCI, 0, unsigned_immed16_overflow},
2159 {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2160 MATCH_R2_ANDHI, MASK_R2_ANDHI, 0, unsigned_immed16_overflow},
2161 {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2162 MATCH_R2_ANDI, MASK_R2_ANDI, 0, unsigned_immed16_overflow},
2163 {"andi.n", "T,S,g", "T,S,g,E", 3, 2, iw_T2I4_type,
2164 MATCH_R2_ANDI_N, MASK_R2_ANDI_N, 0, enumeration_overflow},
2165 {"and.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type,
2166 MATCH_R2_AND_N, MASK_R2_AND_N, 0, no_overflow},
2167 {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2168 MATCH_R2_BEQ, MASK_R2_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow},
2169 {"beqz.n", "S,P", "S,P,E", 2, 2, iw_T1I7_type,
2170 MATCH_R2_BEQZ_N, MASK_R2_BEQZ_N, NIOS2_INSN_CBRANCH, branch_target_overflow},
2171 {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2172 MATCH_R2_BGE, MASK_R2_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow},
2173 {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2174 MATCH_R2_BGEU, MASK_R2_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow},
2175 {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2176 MATCH_R2_BGT, MASK_R2_BGT,
2177 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
2178 {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2179 MATCH_R2_BGTU, MASK_R2_BGTU,
2180 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
2181 {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2182 MATCH_R2_BLE, MASK_R2_BLE,
2183 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
2184 {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2185 MATCH_R2_BLEU, MASK_R2_BLEU,
2186 NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
2187 {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2188 MATCH_R2_BLT, MASK_R2_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow},
2189 {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2190 MATCH_R2_BLTU, MASK_R2_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow},
2191 {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type,
2192 MATCH_R2_BNE, MASK_R2_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow},
2193 {"bnez.n", "S,P", "S,P,E", 2, 2, iw_T1I7_type,
2194 MATCH_R2_BNEZ_N, MASK_R2_BNEZ_N, NIOS2_INSN_CBRANCH, branch_target_overflow},
2195 {"br", "o", "o,E", 1, 4, iw_F2I16_type,
2196 MATCH_R2_BR, MASK_R2_BR, NIOS2_INSN_UBRANCH, branch_target_overflow},
2197 {"break", "j", "j,E", 1, 4, iw_F3X6L5_type,
2198 MATCH_R2_BREAK, MASK_R2_BREAK, NIOS2_INSN_OPTARG, no_overflow},
2199 {"break.n", "j", "j,E", 1, 2, iw_X2L5_type,
2200 MATCH_R2_BREAK_N, MASK_R2_BREAK_N, NIOS2_INSN_OPTARG, no_overflow},
2201 {"bret", "", "E", 0, 4, iw_F3X6_type,
2202 MATCH_R2_BRET, MASK_R2_BRET, 0, no_overflow},
2203 {"br.n", "O", "O,E", 1, 2, iw_I10_type,
2204 MATCH_R2_BR_N, MASK_R2_BR_N, NIOS2_INSN_UBRANCH, branch_target_overflow},
2205 {"call", "m", "m,E", 1, 4, iw_L26_type,
2206 MATCH_R2_CALL, MASK_R2_CALL, NIOS2_INSN_CALL, call_target_overflow},
2207 {"callr", "s", "s,E", 1, 4, iw_F3X6_type,
2208 MATCH_R2_CALLR, MASK_R2_CALLR, 0, no_overflow},
2209 {"callr.n", "s", "s,E", 1, 2, iw_F1X1_type,
2210 MATCH_R2_CALLR_N, MASK_R2_CALLR_N, 0, no_overflow},
2211 {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2212 MATCH_R2_CMPEQ, MASK_R2_CMPEQ, 0, no_overflow},
2213 {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2214 MATCH_R2_CMPEQI, MASK_R2_CMPEQI, 0, signed_immed16_overflow},
2215 {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2216 MATCH_R2_CMPGE, MASK_R2_CMPGE, 0, no_overflow},
2217 {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2218 MATCH_R2_CMPGEI, MASK_R2_CMPGEI, 0, signed_immed16_overflow},
2219 {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2220 MATCH_R2_CMPGEU, MASK_R2_CMPGEU, 0, no_overflow},
2221 {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2222 MATCH_R2_CMPGEUI, MASK_R2_CMPGEUI, 0, unsigned_immed16_overflow},
2223 {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2224 MATCH_R2_CMPGT, MASK_R2_CMPGT, NIOS2_INSN_MACRO, no_overflow},
2225 {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2226 MATCH_R2_CMPGTI, MASK_R2_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow},
2227 {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2228 MATCH_R2_CMPGTU, MASK_R2_CMPGTU, NIOS2_INSN_MACRO, no_overflow},
2229 {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2230 MATCH_R2_CMPGTUI, MASK_R2_CMPGTUI,
2231 NIOS2_INSN_MACRO, unsigned_immed16_overflow},
2232 {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2233 MATCH_R2_CMPLE, MASK_R2_CMPLE, NIOS2_INSN_MACRO, no_overflow},
2234 {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2235 MATCH_R2_CMPLEI, MASK_R2_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow},
2236 {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2237 MATCH_R2_CMPLEU, MASK_R2_CMPLEU, NIOS2_INSN_MACRO, no_overflow},
2238 {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2239 MATCH_R2_CMPLEUI, MASK_R2_CMPLEUI,
2240 NIOS2_INSN_MACRO, unsigned_immed16_overflow},
2241 {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2242 MATCH_R2_CMPLT, MASK_R2_CMPLT, 0, no_overflow},
2243 {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2244 MATCH_R2_CMPLTI, MASK_R2_CMPLTI, 0, signed_immed16_overflow},
2245 {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2246 MATCH_R2_CMPLTU, MASK_R2_CMPLTU, 0, no_overflow},
2247 {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2248 MATCH_R2_CMPLTUI, MASK_R2_CMPLTUI, 0, unsigned_immed16_overflow},
2249 {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2250 MATCH_R2_CMPNE, MASK_R2_CMPNE, 0, no_overflow},
2251 {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2252 MATCH_R2_CMPNEI, MASK_R2_CMPNEI, 0, signed_immed16_overflow},
2253 {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_F3X8_type,
2254 MATCH_R2_CUSTOM, MASK_R2_CUSTOM, 0, custom_opcode_overflow},
2255 {"div", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2256 MATCH_R2_DIV, MASK_R2_DIV, 0, no_overflow},
2257 {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2258 MATCH_R2_DIVU, MASK_R2_DIVU, 0, no_overflow},
2259 {"eni", "j", "j,E", 1, 4, iw_F3X6L5_type,
2260 MATCH_R2_ENI, MASK_R2_ENI, NIOS2_INSN_OPTARG, no_overflow},
2261 {"eret", "", "E", 0, 4, iw_F3X6_type,
2262 MATCH_R2_ERET, MASK_R2_ERET, 0, no_overflow},
2263 {"extract", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type,
2264 MATCH_R2_EXTRACT, MASK_R2_EXTRACT, 0, no_overflow},
2265 {"flushd", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type,
2266 MATCH_R2_FLUSHD, MASK_R2_FLUSHD, 0, address_offset_overflow},
2267 {"flushda", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type,
2268 MATCH_R2_FLUSHDA, MASK_R2_FLUSHDA, 0, address_offset_overflow},
2269 {"flushi", "s", "s,E", 1, 4, iw_F3X6_type,
2270 MATCH_R2_FLUSHI, MASK_R2_FLUSHI, 0, no_overflow},
2271 {"flushp", "", "E", 0, 4, iw_F3X6_type,
2272 MATCH_R2_FLUSHP, MASK_R2_FLUSHP, 0, no_overflow},
2273 {"initd", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type,
2274 MATCH_R2_INITD, MASK_R2_INITD, 0, address_offset_overflow},
2275 {"initda", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type,
2276 MATCH_R2_INITDA, MASK_R2_INITDA, 0, address_offset_overflow},
2277 {"initi", "s", "s,E", 1, 4, iw_F3X6_type,
2278 MATCH_R2_INITI, MASK_R2_INITI, 0, no_overflow},
2279 {"insert", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type,
2280 MATCH_R2_INSERT, MASK_R2_INSERT, 0, no_overflow},
2281 {"jmp", "s", "s,E", 1, 4, iw_F3X6_type,
2282 MATCH_R2_JMP, MASK_R2_JMP, 0, no_overflow},
2283 {"jmpi", "m", "m,E", 1, 4, iw_L26_type,
2284 MATCH_R2_JMPI, MASK_R2_JMPI, 0, call_target_overflow},
2285 {"jmpr.n", "s", "s,E", 1, 2, iw_F1X1_type,
2286 MATCH_R2_JMPR_N, MASK_R2_JMPR_N, 0, no_overflow},
2287 {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2288 MATCH_R2_LDB, MASK_R2_LDB, 0, address_offset_overflow},
2289 {"ldbio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2290 MATCH_R2_LDBIO, MASK_R2_LDBIO, 0, signed_immed12_overflow},
2291 {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2292 MATCH_R2_LDBU, MASK_R2_LDBU, 0, address_offset_overflow},
2293 {"ldbuio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2294 MATCH_R2_LDBUIO, MASK_R2_LDBUIO, 0, signed_immed12_overflow},
2295 {"ldbu.n", "T,Y(S)", "T,Y(S),E", 3, 2, iw_T2I4_type,
2296 MATCH_R2_LDBU_N, MASK_R2_LDBU_N, 0, address_offset_overflow},
2297 {"ldex", "d,(s)", "d,(s),E", 2, 4, iw_F3X6_type,
2298 MATCH_R2_LDEX, MASK_R2_LDEX, 0, no_overflow},
2299 {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2300 MATCH_R2_LDH, MASK_R2_LDH, 0, address_offset_overflow},
2301 {"ldhio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2302 MATCH_R2_LDHIO, MASK_R2_LDHIO, 0, signed_immed12_overflow},
2303 {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2304 MATCH_R2_LDHU, MASK_R2_LDHU, 0, address_offset_overflow},
2305 {"ldhuio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2306 MATCH_R2_LDHUIO, MASK_R2_LDHUIO, 0, signed_immed12_overflow},
2307 {"ldhu.n", "T,X(S)", "T,X(S),E", 3, 2, iw_T2I4_type,
2308 MATCH_R2_LDHU_N, MASK_R2_LDHU_N, 0, address_offset_overflow},
2309 {"ldsex", "d,(s)", "d,(s),E", 2, 4, iw_F3X6_type,
2310 MATCH_R2_LDSEX, MASK_R2_LDSEX, 0, no_overflow},
2311 {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2312 MATCH_R2_LDW, MASK_R2_LDW, 0, address_offset_overflow},
2313 {"ldwio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2314 MATCH_R2_LDWIO, MASK_R2_LDWIO, 0, signed_immed12_overflow},
2315 {"ldwm", "R,B", "R,B,E", 2, 4, iw_F1X4L17_type,
2316 MATCH_R2_LDWM, MASK_R2_LDWM, 0, no_overflow},
2317 {"ldw.n", "T,W(S)", "T,W(S),E", 3, 2, iw_T2I4_type,
2318 MATCH_R2_LDW_N, MASK_R2_LDW_N, 0, address_offset_overflow},
2319 {"ldwsp.n", "t,V(s)", "t,V(s),E", 3, 2, iw_F1I5_type,
2320 MATCH_R2_LDWSP_N, MASK_R2_LDWSP_N, 0, address_offset_overflow},
2321 {"merge", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type,
2322 MATCH_R2_MERGE, MASK_R2_MERGE, 0, no_overflow},
2323 {"mov", "d,s", "d,s,E", 2, 4, iw_F3X6_type,
2324 MATCH_R2_MOV, MASK_R2_MOV, NIOS2_INSN_MACRO_MOV, no_overflow},
2325 {"mov.n", "d,s", "d,s,E", 2, 2, iw_F2_type,
2326 MATCH_R2_MOV_N, MASK_R2_MOV_N, 0, no_overflow},
2327 {"movi.n", "D,h", "D,h,E", 2, 2, iw_T1I7_type,
2328 MATCH_R2_MOVI_N, MASK_R2_MOVI_N, 0, enumeration_overflow},
2329 {"movhi", "t,u", "t,u,E", 2, 4, iw_F2I16_type,
2330 MATCH_R2_MOVHI, MASK_R2_MOVHI,
2331 NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
2332 {"movi", "t,i", "t,i,E", 2, 4, iw_F2I16_type,
2333 MATCH_R2_MOVI, MASK_R2_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow},
2334 {"movia", "t,o", "t,o,E", 2, 4, iw_F2I16_type,
2335 MATCH_R2_ORHI, MASK_R2_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow},
2336 {"movui", "t,u", "t,u,E", 2, 4, iw_F2I16_type,
2337 MATCH_R2_MOVUI, MASK_R2_MOVUI,
2338 NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
2339 {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2340 MATCH_R2_MUL, MASK_R2_MUL, 0, no_overflow},
2341 {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2342 MATCH_R2_MULI, MASK_R2_MULI, 0, signed_immed16_overflow},
2343 {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2344 MATCH_R2_MULXSS, MASK_R2_MULXSS, 0, no_overflow},
2345 {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2346 MATCH_R2_MULXSU, MASK_R2_MULXSU, 0, no_overflow},
2347 {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2348 MATCH_R2_MULXUU, MASK_R2_MULXUU, 0, no_overflow},
2349 /* The encoding of the neg.n operands is backwards, not
2350 the interpretation -- the first operand is still the
2351 destination and the second the source. */
2352 {"neg.n", "S,D", "S,D,E", 2, 2, iw_T2X3_type,
2353 MATCH_R2_NEG_N, MASK_R2_NEG_N, 0, no_overflow},
2354 {"nextpc", "d", "d,E", 1, 4, iw_F3X6_type,
2355 MATCH_R2_NEXTPC, MASK_R2_NEXTPC, 0, no_overflow},
2356 {"nop", "", "E", 0, 4, iw_F3X6_type,
2357 MATCH_R2_NOP, MASK_R2_NOP, NIOS2_INSN_MACRO_MOV, no_overflow},
2358 {"nop.n", "", "E", 0, 2, iw_F2_type,
2359 MATCH_R2_NOP_N, MASK_R2_NOP_N, NIOS2_INSN_MACRO_MOV, no_overflow},
2360 {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2361 MATCH_R2_NOR, MASK_R2_NOR, 0, no_overflow},
2362 {"not.n", "D,S", "D,S,E", 2, 2, iw_T2X3_type,
2363 MATCH_R2_NOT_N, MASK_R2_NOT_N, 0, no_overflow},
2364 {"or", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2365 MATCH_R2_OR, MASK_R2_OR, 0, no_overflow},
2366 {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2367 MATCH_R2_ORHI, MASK_R2_ORHI, 0, unsigned_immed16_overflow},
2368 {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2369 MATCH_R2_ORI, MASK_R2_ORI, 0, unsigned_immed16_overflow},
2370 {"or.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type,
2371 MATCH_R2_OR_N, MASK_R2_OR_N, 0, no_overflow},
2372 {"pop.n", "R,W", "R,W,E", 2, 2, iw_L5I4X1_type,
2373 MATCH_R2_POP_N, MASK_R2_POP_N, NIOS2_INSN_OPTARG, no_overflow},
2374 {"push.n", "R,W", "R,W,E", 2, 2, iw_L5I4X1_type,
2375 MATCH_R2_PUSH_N, MASK_R2_PUSH_N, NIOS2_INSN_OPTARG, no_overflow},
2376 {"rdctl", "d,c", "d,c,E", 2, 4, iw_F3X6L5_type,
2377 MATCH_R2_RDCTL, MASK_R2_RDCTL, 0, no_overflow},
2378 {"rdprs", "t,s,I", "t,s,I,E", 3, 4, iw_F2X4I12_type,
2379 MATCH_R2_RDPRS, MASK_R2_RDPRS, 0, signed_immed12_overflow},
2380 {"ret", "", "E", 0, 4, iw_F3X6_type,
2381 MATCH_R2_RET, MASK_R2_RET, 0, no_overflow},
2382 {"ret.n", "", "E", 0, 2, iw_X2L5_type,
2383 MATCH_R2_RET_N, MASK_R2_RET_N, 0, no_overflow},
2384 {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2385 MATCH_R2_ROL, MASK_R2_ROL, 0, no_overflow},
2386 {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type,
2387 MATCH_R2_ROLI, MASK_R2_ROLI, 0, unsigned_immed5_overflow},
2388 {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2389 MATCH_R2_ROR, MASK_R2_ROR, 0, no_overflow},
2390 {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2391 MATCH_R2_SLL, MASK_R2_SLL, 0, no_overflow},
2392 {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type,
2393 MATCH_R2_SLLI, MASK_R2_SLLI, 0, unsigned_immed5_overflow},
2394 {"sll.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type,
2395 MATCH_R2_SLL_N, MASK_R2_SLL_N, 0, no_overflow},
2396 {"slli.n", "D,S,f", "D,S,f,E", 3, 2, iw_T2X1L3_type,
2397 MATCH_R2_SLLI_N, MASK_R2_SLLI_N, 0, enumeration_overflow},
2398 {"spaddi.n", "D,U", "D,U,E", 2, 2, iw_T1I7_type,
2399 MATCH_R2_SPADDI_N, MASK_R2_SPADDI_N, 0, address_offset_overflow},
2400 {"spdeci.n", "U", "U,E", 1, 2, iw_X1I7_type,
2401 MATCH_R2_SPDECI_N, MASK_R2_SPDECI_N, 0, address_offset_overflow},
2402 {"spinci.n", "U", "U,E", 1, 2, iw_X1I7_type,
2403 MATCH_R2_SPINCI_N, MASK_R2_SPINCI_N, 0, address_offset_overflow},
2404 {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2405 MATCH_R2_SRA, MASK_R2_SRA, 0, no_overflow},
2406 {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type,
2407 MATCH_R2_SRAI, MASK_R2_SRAI, 0, unsigned_immed5_overflow},
2408 {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2409 MATCH_R2_SRL, MASK_R2_SRL, 0, no_overflow},
2410 {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type,
2411 MATCH_R2_SRLI, MASK_R2_SRLI, 0, unsigned_immed5_overflow},
2412 {"srl.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type,
2413 MATCH_R2_SRL_N, MASK_R2_SRL_N, 0, no_overflow},
2414 {"srli.n", "D,S,f", "D,S,f,E", 3, 2, iw_T2X1L3_type,
2415 MATCH_R2_SRLI_N, MASK_R2_SRLI_N, 0, enumeration_overflow},
2416 {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2417 MATCH_R2_STB, MASK_R2_STB, 0, address_offset_overflow},
2418 {"stbio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2419 MATCH_R2_STBIO, MASK_R2_STBIO, 0, signed_immed12_overflow},
2420 {"stb.n", "T,Y(S)", "T,Y(S),E", 3, 2, iw_T2I4_type,
2421 MATCH_R2_STB_N, MASK_R2_STB_N, 0, address_offset_overflow},
2422 {"stbz.n", "t,M(S)", "t,M(S),E", 3, 2, iw_T1X1I6_type,
2423 MATCH_R2_STBZ_N, MASK_R2_STBZ_N, 0, address_offset_overflow},
2424 {"stex", "d,t,(s)", "d,t,(s),E", 3, 4, iw_F3X6_type,
2425 MATCH_R2_STEX, MASK_R2_STEX, 0, no_overflow},
2426 {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2427 MATCH_R2_STH, MASK_R2_STH, 0, address_offset_overflow},
2428 {"sthio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2429 MATCH_R2_STHIO, MASK_R2_STHIO, 0, signed_immed12_overflow},
2430 {"sth.n", "T,X(S)", "T,X(S),E", 3, 2, iw_T2I4_type,
2431 MATCH_R2_STH_N, MASK_R2_STH_N, 0, address_offset_overflow},
2432 {"stsex", "d,t,(s)", "d,t,(s),E", 3, 4, iw_F3X6_type,
2433 MATCH_R2_STSEX, MASK_R2_STSEX, 0, no_overflow},
2434 {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type,
2435 MATCH_R2_STW, MASK_R2_STW, 0, address_offset_overflow},
2436 {"stwio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type,
2437 MATCH_R2_STWIO, MASK_R2_STWIO, 0, signed_immed12_overflow},
2438 {"stwm", "R,B", "R,B,E", 2, 4, iw_F1X4L17_type,
2439 MATCH_R2_STWM, MASK_R2_STWM, 0, no_overflow},
2440 {"stwsp.n", "t,V(s)", "t,V(s),E", 3, 2, iw_F1I5_type,
2441 MATCH_R2_STWSP_N, MASK_R2_STWSP_N, 0, address_offset_overflow},
2442 {"stw.n", "T,W(S)", "T,W(S),E", 3, 2, iw_T2I4_type,
2443 MATCH_R2_STW_N, MASK_R2_STW_N, 0, address_offset_overflow},
2444 {"stwz.n", "t,N(S)", "t,N(S),E", 3, 2, iw_T1X1I6_type,
2445 MATCH_R2_STWZ_N, MASK_R2_STWZ_N, 0, address_offset_overflow},
2446 {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2447 MATCH_R2_SUB, MASK_R2_SUB, 0, no_overflow},
2448 {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type,
2449 MATCH_R2_SUBI, MASK_R2_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow},
2450 {"sub.n", "D,S,T", "D,S,T,E", 3, 2, iw_T3X1_type,
2451 MATCH_R2_SUB_N, MASK_R2_SUB_N, 0, no_overflow},
2452 {"subi.n", "D,S,e", "D,S,e,E", 3, 2, iw_T2X1I3_type,
2453 MATCH_R2_SUBI_N, MASK_R2_SUBI_N, 0, enumeration_overflow},
2454 {"sync", "", "E", 0, 4, iw_F3X6_type,
2455 MATCH_R2_SYNC, MASK_R2_SYNC, 0, no_overflow},
2456 {"trap", "j", "j,E", 1, 4, iw_F3X6L5_type,
2457 MATCH_R2_TRAP, MASK_R2_TRAP, NIOS2_INSN_OPTARG, no_overflow},
2458 {"trap.n", "j", "j,E", 1, 2, iw_X2L5_type,
2459 MATCH_R2_TRAP_N, MASK_R2_TRAP_N, NIOS2_INSN_OPTARG, no_overflow},
2460 {"wrctl", "c,s", "c,s,E", 2, 4, iw_F3X6L5_type,
2461 MATCH_R2_WRCTL, MASK_R2_WRCTL, 0, no_overflow},
2462 {"wrpie", "d,s", "d,s,E", 2, 4, iw_F3X6L5_type,
2463 MATCH_R2_WRPIE, MASK_R2_WRPIE, 0, no_overflow},
2464 {"wrprs", "d,s", "d,s,E", 2, 4, iw_F3X6_type,
2465 MATCH_R2_WRPRS, MASK_R2_WRPRS, 0, no_overflow},
2466 {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type,
2467 MATCH_R2_XOR, MASK_R2_XOR, 0, no_overflow},
2468 {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2469 MATCH_R2_XORHI, MASK_R2_XORHI, 0, unsigned_immed16_overflow},
2470 {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type,
2471 MATCH_R2_XORI, MASK_R2_XORI, 0, unsigned_immed16_overflow},
2472 {"xor.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type,
2473 MATCH_R2_XOR_N, MASK_R2_XOR_N, 0, no_overflow},
2474 };
2475
2476 #define NIOS2_NUM_R2_OPCODES \
2477 ((sizeof nios2_r2_opcodes) / (sizeof (nios2_r2_opcodes[0])))
2478 const int nios2_num_r2_opcodes = NIOS2_NUM_R2_OPCODES;
2479
2480 /* Default to using the R1 instruction tables. */
2481 struct nios2_opcode *nios2_opcodes = (struct nios2_opcode *) nios2_r1_opcodes;
2482 int nios2_num_opcodes = NIOS2_NUM_R1_OPCODES;
2483 #undef NIOS2_NUM_R1_OPCODES
2484 #undef NIOS2_NUM_R2_OPCODES
2485
2486 /* Decodings for R2 asi.n (addi.n/subi.n) immediate values. */
2487 unsigned int nios2_r2_asi_n_mappings[] =
2488 {1, 2, 4, 8, 16, 32, 64, 128};
2489 const int nios2_num_r2_asi_n_mappings = 8;
2490
2491 /* Decodings for R2 shi.n (slli.n/srli.n) immediate values. */
2492 unsigned int nios2_r2_shi_n_mappings[] =
2493 {1, 2, 3, 8, 12, 16, 24, 31};
2494 const int nios2_num_r2_shi_n_mappings = 8;
2495
2496 /* Decodings for R2 andi.n immediate values. */
2497 unsigned int nios2_r2_andi_n_mappings[] =
2498 {1, 2, 3, 4, 8, 0xf, 0x10, 0x1f,
2499 0x20, 0x3f, 0x7f, 0x80, 0xff, 0x7ff, 0xff00, 0xffff};
2500 const int nios2_num_r2_andi_n_mappings = 16;
2501
2502 /* Decodings for R2 3-bit register fields. */
2503 int nios2_r2_reg3_mappings[] =
2504 {16, 17, 2, 3, 4, 5, 6, 7};
2505 const int nios2_num_r2_reg3_mappings = 8;
2506
2507 /* Decodings for R2 push.n/pop.n REG_RANGE value list. */
2508 unsigned long nios2_r2_reg_range_mappings[] = {
2509 0x00010000,
2510 0x00030000,
2511 0x00070000,
2512 0x000f0000,
2513 0x001f0000,
2514 0x003f0000,
2515 0x007f0000,
2516 0x00ff0000
2517 };
2518 const int nios2_num_r2_reg_range_mappings = 8;
2519
2520 /*#include "sysdep.h"
2521 #include "dis-asm.h"
2522 #include "opcode/nios2.h"
2523 #include "libiberty.h"
2524 #include <string.h>
2525 #include <assert.h>
2526 */
2527 /* No symbol table is available when this code runs out in an embedded
2528 system as when it is used for disassembler support in a monitor. */
2529 #if !defined(EMBEDDED_ENV)
2530 #define SYMTAB_AVAILABLE 1
2531 /*
2532 #include "elf-bfd.h"
2533 #include "elf/nios2.h"
2534 */
2535 #endif
2536
2537 /* Default length of Nios II instruction in bytes. */
2538 #define INSNLEN 4
2539
2540 /* Data structures used by the opcode hash table. */
2541 typedef struct _nios2_opcode_hash
2542 {
2543 const struct nios2_opcode *opcode;
2544 struct _nios2_opcode_hash *next;
2545 } nios2_opcode_hash;
2546
2547 /* Hash table size. */
2548 #define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
2549
2550 /* Extract the opcode from an instruction word. */
2551 static unsigned int
2552 nios2_r1_extract_opcode (unsigned int x)
2553 {
2554 return GET_IW_R1_OP (x);
2555 }
2556
2557 static unsigned int
2558 nios2_r2_extract_opcode (unsigned int x)
2559 {
2560 return GET_IW_R2_OP (x);
2561 }
2562
2563 /* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops
2564 are stored in a different table than regular instructions. */
2565
2566 typedef struct _nios2_disassembler_state
2567 {
2568 const struct nios2_opcode *opcodes;
2569 const int *num_opcodes;
2570 unsigned int (*extract_opcode) (unsigned int);
2571 nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
2572 nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
2573 const struct nios2_opcode *nop;
2574 bfd_boolean init;
2575 } nios2_disassembler_state;
2576
2577 static nios2_disassembler_state
2578 nios2_r1_disassembler_state = {
2579 nios2_r1_opcodes,
2580 &nios2_num_r1_opcodes,
2581 nios2_r1_extract_opcode,
2582 {},
2583 {},
2584 NULL,
2585 0
2586 };
2587
2588 static nios2_disassembler_state
2589 nios2_r2_disassembler_state = {
2590 nios2_r2_opcodes,
2591 &nios2_num_r2_opcodes,
2592 nios2_r2_extract_opcode,
2593 {},
2594 {},
2595 NULL,
2596 0
2597 };
2598
2599 /* Function to initialize the opcode hash table. */
2600 static void
2601 nios2_init_opcode_hash (nios2_disassembler_state *state)
2602 {
2603 unsigned int i;
2604 register const struct nios2_opcode *op;
2605
2606 for (i = 0; i < OPCODE_HASH_SIZE; i++)
2607 for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
2608 {
2609 nios2_opcode_hash *new_hash;
2610 nios2_opcode_hash **bucket = NULL;
2611
2612 if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
2613 {
2614 if (i == state->extract_opcode (op->match)
2615 && (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
2616 & 0x7fffffff))
2617 {
2618 bucket = &(state->ps_hash[i]);
2619 if (strcmp (op->name, "nop") == 0)
2620 state->nop = op;
2621 }
2622 }
2623 else if (i == state->extract_opcode (op->match))
2624 bucket = &(state->hash[i]);
2625
2626 if (bucket)
2627 {
2628 new_hash =
2629 (nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
2630 if (new_hash == NULL)
2631 {
2632 fprintf (stderr,
2633 "error allocating memory...broken disassembler\n");
2634 abort ();
2635 }
2636 new_hash->opcode = op;
2637 new_hash->next = NULL;
2638 while (*bucket)
2639 bucket = &((*bucket)->next);
2640 *bucket = new_hash;
2641 }
2642 }
2643 state->init = 1;
2644
2645 #ifdef DEBUG_HASHTABLE
2646 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
2647 {
2648 nios2_opcode_hash *tmp_hash = state->hash[i];
2649 printf ("index: 0x%02X ops: ", i);
2650 while (tmp_hash != NULL)
2651 {
2652 printf ("%s ", tmp_hash->opcode->name);
2653 tmp_hash = tmp_hash->next;
2654 }
2655 printf ("\n");
2656 }
2657
2658 for (i = 0; i < OPCODE_HASH_SIZE; ++i)
2659 {
2660 nios2_opcode_hash *tmp_hash = state->ps_hash[i];
2661 printf ("index: 0x%02X ops: ", i);
2662 while (tmp_hash != NULL)
2663 {
2664 printf ("%s ", tmp_hash->opcode->name);
2665 tmp_hash = tmp_hash->next;
2666 }
2667 printf ("\n");
2668 }
2669 #endif /* DEBUG_HASHTABLE */
2670 }
2671
2672 /* Return a pointer to an nios2_opcode struct for a given instruction
2673 word OPCODE for bfd machine MACH, or NULL if there is an error. */
2674 const struct nios2_opcode *
2675 nios2_find_opcode_hash (unsigned long opcode, unsigned long mach)
2676 {
2677 nios2_opcode_hash *entry;
2678 nios2_disassembler_state *state;
2679
2680 /* Select the right instruction set, hash tables, and opcode accessor
2681 for the mach variant. */
2682 if (mach == bfd_mach_nios2r2)
2683 state = &nios2_r2_disassembler_state;
2684 else
2685 state = &nios2_r1_disassembler_state;
2686
2687 /* Build a hash table to shorten the search time. */
2688 if (!state->init)
2689 nios2_init_opcode_hash (state);
2690
2691 /* Check for NOP first. Both NOP and MOV are macros that expand into
2692 an ADD instruction, and we always want to give priority to NOP. */
2693 if (state->nop->match == (opcode & state->nop->mask))
2694 return state->nop;
2695
2696 /* First look in the pseudo-op hashtable. */
2697 for (entry = state->ps_hash[state->extract_opcode (opcode)];
2698 entry; entry = entry->next)
2699 if (entry->opcode->match == (opcode & entry->opcode->mask))
2700 return entry->opcode;
2701
2702 /* Otherwise look in the main hashtable. */
2703 for (entry = state->hash[state->extract_opcode (opcode)];
2704 entry; entry = entry->next)
2705 if (entry->opcode->match == (opcode & entry->opcode->mask))
2706 return entry->opcode;
2707
2708 return NULL;
2709 }
2710
2711 /* There are 32 regular registers, 32 coprocessor registers,
2712 and 32 control registers. */
2713 #define NUMREGNAMES 32
2714
2715 /* Return a pointer to the base of the coprocessor register name array. */
2716 static struct nios2_reg *
2717 nios2_coprocessor_regs (void)
2718 {
2719 static struct nios2_reg *cached = NULL;
2720
2721 if (!cached)
2722 {
2723 int i;
2724 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
2725 if (!strcmp (nios2_regs[i].name, "c0"))
2726 {
2727 cached = nios2_regs + i;
2728 break;
2729 }
2730 assert (cached);
2731 }
2732 return cached;
2733 }
2734
2735 /* Return a pointer to the base of the control register name array. */
2736 static struct nios2_reg *
2737 nios2_control_regs (void)
2738 {
2739 static struct nios2_reg *cached = NULL;
2740
2741 if (!cached)
2742 {
2743 int i;
2744 for (i = NUMREGNAMES; i < nios2_num_regs; i++)
2745 if (!strcmp (nios2_regs[i].name, "status"))
2746 {
2747 cached = nios2_regs + i;
2748 break;
2749 }
2750 assert (cached);
2751 }
2752 return cached;
2753 }
2754
2755 /* Helper routine to report internal errors. */
2756 static void
2757 bad_opcode (const struct nios2_opcode *op)
2758 {
2759 fprintf (stderr, "Internal error: broken opcode descriptor for `%s %s'\n",
2760 op->name, op->args);
2761 abort ();
2762 }
2763
2764 /* The function nios2_print_insn_arg uses the character pointed
2765 to by ARGPTR to determine how it print the next token or separator
2766 character in the arguments to an instruction. */
2767 static int
2768 nios2_print_insn_arg (const char *argptr,
2769 unsigned long opcode, bfd_vma address,
2770 disassemble_info *info,
2771 const struct nios2_opcode *op)
2772 {
2773 unsigned long i = 0;
2774 struct nios2_reg *reg_base;
2775
2776 switch (*argptr)
2777 {
2778 case ',':
2779 case '(':
2780 case ')':
2781 (*info->fprintf_func) (info->stream, "%c", *argptr);
2782 break;
2783
2784 case 'c':
2785 /* Control register index. */
2786 switch (op->format)
2787 {
2788 case iw_r_type:
2789 i = GET_IW_R_IMM5 (opcode);
2790 break;
2791 case iw_F3X6L5_type:
2792 i = GET_IW_F3X6L5_IMM5 (opcode);
2793 break;
2794 default:
2795 bad_opcode (op);
2796 }
2797 reg_base = nios2_control_regs ();
2798 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
2799 break;
2800
2801 case 'd':
2802 reg_base = nios2_regs;
2803 switch (op->format)
2804 {
2805 case iw_r_type:
2806 i = GET_IW_R_C (opcode);
2807 break;
2808 case iw_custom_type:
2809 i = GET_IW_CUSTOM_C (opcode);
2810 if (GET_IW_CUSTOM_READC (opcode) == 0)
2811 reg_base = nios2_coprocessor_regs ();
2812 break;
2813 case iw_F3X6L5_type:
2814 case iw_F3X6_type:
2815 i = GET_IW_F3X6L5_C (opcode);
2816 break;
2817 case iw_F3X8_type:
2818 i = GET_IW_F3X8_C (opcode);
2819 if (GET_IW_F3X8_READC (opcode) == 0)
2820 reg_base = nios2_coprocessor_regs ();
2821 break;
2822 case iw_F2_type:
2823 i = GET_IW_F2_B (opcode);
2824 break;
2825 default:
2826 bad_opcode (op);
2827 }
2828 if (i < NUMREGNAMES)
2829 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
2830 else
2831 (*info->fprintf_func) (info->stream, "unknown");
2832 break;
2833
2834 case 's':
2835 reg_base = nios2_regs;
2836 switch (op->format)
2837 {
2838 case iw_r_type:
2839 i = GET_IW_R_A (opcode);
2840 break;
2841 case iw_i_type:
2842 i = GET_IW_I_A (opcode);
2843 break;
2844 case iw_custom_type:
2845 i = GET_IW_CUSTOM_A (opcode);
2846 if (GET_IW_CUSTOM_READA (opcode) == 0)
2847 reg_base = nios2_coprocessor_regs ();
2848 break;
2849 case iw_F2I16_type:
2850 i = GET_IW_F2I16_A (opcode);
2851 break;
2852 case iw_F2X4I12_type:
2853 i = GET_IW_F2X4I12_A (opcode);
2854 break;
2855 case iw_F1X4I12_type:
2856 i = GET_IW_F1X4I12_A (opcode);
2857 break;
2858 case iw_F1X4L17_type:
2859 i = GET_IW_F1X4L17_A (opcode);
2860 break;
2861 case iw_F3X6L5_type:
2862 case iw_F3X6_type:
2863 i = GET_IW_F3X6L5_A (opcode);
2864 break;
2865 case iw_F2X6L10_type:
2866 i = GET_IW_F2X6L10_A (opcode);
2867 break;
2868 case iw_F3X8_type:
2869 i = GET_IW_F3X8_A (opcode);
2870 if (GET_IW_F3X8_READA (opcode) == 0)
2871 reg_base = nios2_coprocessor_regs ();
2872 break;
2873 case iw_F1X1_type:
2874 i = GET_IW_F1X1_A (opcode);
2875 break;
2876 case iw_F1I5_type:
2877 i = 27; /* Implicit stack pointer reference. */
2878 break;
2879 case iw_F2_type:
2880 i = GET_IW_F2_A (opcode);
2881 break;
2882 default:
2883 bad_opcode (op);
2884 }
2885 if (i < NUMREGNAMES)
2886 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
2887 else
2888 (*info->fprintf_func) (info->stream, "unknown");
2889 break;
2890
2891 case 't':
2892 reg_base = nios2_regs;
2893 switch (op->format)
2894 {
2895 case iw_r_type:
2896 i = GET_IW_R_B (opcode);
2897 break;
2898 case iw_i_type:
2899 i = GET_IW_I_B (opcode);
2900 break;
2901 case iw_custom_type:
2902 i = GET_IW_CUSTOM_B (opcode);
2903 if (GET_IW_CUSTOM_READB (opcode) == 0)
2904 reg_base = nios2_coprocessor_regs ();
2905 break;
2906 case iw_F2I16_type:
2907 i = GET_IW_F2I16_B (opcode);
2908 break;
2909 case iw_F2X4I12_type:
2910 i = GET_IW_F2X4I12_B (opcode);
2911 break;
2912 case iw_F3X6L5_type:
2913 case iw_F3X6_type:
2914 i = GET_IW_F3X6L5_B (opcode);
2915 break;
2916 case iw_F2X6L10_type:
2917 i = GET_IW_F2X6L10_B (opcode);
2918 break;
2919 case iw_F3X8_type:
2920 i = GET_IW_F3X8_B (opcode);
2921 if (GET_IW_F3X8_READB (opcode) == 0)
2922 reg_base = nios2_coprocessor_regs ();
2923 break;
2924 case iw_F1I5_type:
2925 i = GET_IW_F1I5_B (opcode);
2926 break;
2927 case iw_F2_type:
2928 i = GET_IW_F2_B (opcode);
2929 break;
2930 case iw_T1X1I6_type:
2931 i = 0;
2932 break;
2933 default:
2934 bad_opcode (op);
2935 }
2936 if (i < NUMREGNAMES)
2937 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
2938 else
2939 (*info->fprintf_func) (info->stream, "unknown");
2940 break;
2941
2942 case 'D':
2943 switch (op->format)
2944 {
2945 case iw_T1I7_type:
2946 i = GET_IW_T1I7_A3 (opcode);
2947 break;
2948 case iw_T2X1L3_type:
2949 i = GET_IW_T2X1L3_B3 (opcode);
2950 break;
2951 case iw_T2X1I3_type:
2952 i = GET_IW_T2X1I3_B3 (opcode);
2953 break;
2954 case iw_T3X1_type:
2955 i = GET_IW_T3X1_C3 (opcode);
2956 break;
2957 case iw_T2X3_type:
2958 if (op->num_args == 3)
2959 i = GET_IW_T2X3_A3 (opcode);
2960 else
2961 i = GET_IW_T2X3_B3 (opcode);
2962 break;
2963 default:
2964 bad_opcode (op);
2965 }
2966 i = nios2_r2_reg3_mappings[i];
2967 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
2968 break;
2969
2970 case 'M':
2971 /* 6-bit unsigned immediate with no shift. */
2972 switch (op->format)
2973 {
2974 case iw_T1X1I6_type:
2975 i = GET_IW_T1X1I6_IMM6 (opcode);
2976 break;
2977 default:
2978 bad_opcode (op);
2979 }
2980 (*info->fprintf_func) (info->stream, "%ld", i);
2981 break;
2982
2983 case 'N':
2984 /* 6-bit unsigned immediate with 2-bit shift. */
2985 switch (op->format)
2986 {
2987 case iw_T1X1I6_type:
2988 i = GET_IW_T1X1I6_IMM6 (opcode) << 2;
2989 break;
2990 default:
2991 bad_opcode (op);
2992 }
2993 (*info->fprintf_func) (info->stream, "%ld", i);
2994 break;
2995
2996 case 'S':
2997 switch (op->format)
2998 {
2999 case iw_T1I7_type:
3000 i = GET_IW_T1I7_A3 (opcode);
3001 break;
3002 case iw_T2I4_type:
3003 i = GET_IW_T2I4_A3 (opcode);
3004 break;
3005 case iw_T2X1L3_type:
3006 i = GET_IW_T2X1L3_A3 (opcode);
3007 break;
3008 case iw_T2X1I3_type:
3009 i = GET_IW_T2X1I3_A3 (opcode);
3010 break;
3011 case iw_T3X1_type:
3012 i = GET_IW_T3X1_A3 (opcode);
3013 break;
3014 case iw_T2X3_type:
3015 i = GET_IW_T2X3_A3 (opcode);
3016 break;
3017 case iw_T1X1I6_type:
3018 i = GET_IW_T1X1I6_A3 (opcode);
3019 break;
3020 default:
3021 bad_opcode (op);
3022 }
3023 i = nios2_r2_reg3_mappings[i];
3024 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
3025 break;
3026
3027 case 'T':
3028 switch (op->format)
3029 {
3030 case iw_T2I4_type:
3031 i = GET_IW_T2I4_B3 (opcode);
3032 break;
3033 case iw_T3X1_type:
3034 i = GET_IW_T3X1_B3 (opcode);
3035 break;
3036 case iw_T2X3_type:
3037 i = GET_IW_T2X3_B3 (opcode);
3038 break;
3039 default:
3040 bad_opcode (op);
3041 }
3042 i = nios2_r2_reg3_mappings[i];
3043 (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name);
3044 break;
3045
3046 case 'i':
3047 /* 16-bit signed immediate. */
3048 switch (op->format)
3049 {
3050 case iw_i_type:
3051 i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
3052 break;
3053 case iw_F2I16_type:
3054 i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
3055 break;
3056 default:
3057 bad_opcode (op);
3058 }
3059 (*info->fprintf_func) (info->stream, "%ld", i);
3060 break;
3061
3062 case 'I':
3063 /* 12-bit signed immediate. */
3064 switch (op->format)
3065 {
3066 case iw_F2X4I12_type:
3067 i = (signed) (GET_IW_F2X4I12_IMM12 (opcode) << 20) >> 20;
3068 break;
3069 case iw_F1X4I12_type:
3070 i = (signed) (GET_IW_F1X4I12_IMM12 (opcode) << 20) >> 20;
3071 break;
3072 default:
3073 bad_opcode (op);
3074 }
3075 (*info->fprintf_func) (info->stream, "%ld", i);
3076 break;
3077
3078 case 'u':
3079 /* 16-bit unsigned immediate. */
3080 switch (op->format)
3081 {
3082 case iw_i_type:
3083 i = GET_IW_I_IMM16 (opcode);
3084 break;
3085 case iw_F2I16_type:
3086 i = GET_IW_F2I16_IMM16 (opcode);
3087 break;
3088 default:
3089 bad_opcode (op);
3090 }
3091 (*info->fprintf_func) (info->stream, "%ld", i);
3092 break;
3093
3094 case 'U':
3095 /* 7-bit unsigned immediate with 2-bit shift. */
3096 switch (op->format)
3097 {
3098 case iw_T1I7_type:
3099 i = GET_IW_T1I7_IMM7 (opcode) << 2;
3100 break;
3101 case iw_X1I7_type:
3102 i = GET_IW_X1I7_IMM7 (opcode) << 2;
3103 break;
3104 default:
3105 bad_opcode (op);
3106 }
3107 (*info->fprintf_func) (info->stream, "%ld", i);
3108 break;
3109
3110 case 'V':
3111 /* 5-bit unsigned immediate with 2-bit shift. */
3112 switch (op->format)
3113 {
3114 case iw_F1I5_type:
3115 i = GET_IW_F1I5_IMM5 (opcode) << 2;
3116 break;
3117 default:
3118 bad_opcode (op);
3119 }
3120 (*info->fprintf_func) (info->stream, "%ld", i);
3121 break;
3122
3123 case 'W':
3124 /* 4-bit unsigned immediate with 2-bit shift. */
3125 switch (op->format)
3126 {
3127 case iw_T2I4_type:
3128 i = GET_IW_T2I4_IMM4 (opcode) << 2;
3129 break;
3130 case iw_L5I4X1_type:
3131 i = GET_IW_L5I4X1_IMM4 (opcode) << 2;
3132 break;
3133 default:
3134 bad_opcode (op);
3135 }
3136 (*info->fprintf_func) (info->stream, "%ld", i);
3137 break;
3138
3139 case 'X':
3140 /* 4-bit unsigned immediate with 1-bit shift. */
3141 switch (op->format)
3142 {
3143 case iw_T2I4_type:
3144 i = GET_IW_T2I4_IMM4 (opcode) << 1;
3145 break;
3146 default:
3147 bad_opcode (op);
3148 }
3149 (*info->fprintf_func) (info->stream, "%ld", i);
3150 break;
3151
3152 case 'Y':
3153 /* 4-bit unsigned immediate without shift. */
3154 switch (op->format)
3155 {
3156 case iw_T2I4_type:
3157 i = GET_IW_T2I4_IMM4 (opcode);
3158 break;
3159 default:
3160 bad_opcode (op);
3161 }
3162 (*info->fprintf_func) (info->stream, "%ld", i);
3163 break;
3164
3165 case 'o':
3166 /* 16-bit signed immediate address offset. */
3167 switch (op->format)
3168 {
3169 case iw_i_type:
3170 i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
3171 break;
3172 case iw_F2I16_type:
3173 i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16;
3174 break;
3175 default:
3176 bad_opcode (op);
3177 }
3178 address = address + 4 + i;
3179 (*info->print_address_func) (address, info);
3180 break;
3181
3182 case 'O':
3183 /* 10-bit signed address offset with 1-bit shift. */
3184 switch (op->format)
3185 {
3186 case iw_I10_type:
3187 i = (signed) (GET_IW_I10_IMM10 (opcode) << 22) >> 21;
3188 break;
3189 default:
3190 bad_opcode (op);
3191 }
3192 address = address + 2 + i;
3193 (*info->print_address_func) (address, info);
3194 break;
3195
3196 case 'P':
3197 /* 7-bit signed address offset with 1-bit shift. */
3198 switch (op->format)
3199 {
3200 case iw_T1I7_type:
3201 i = (signed) (GET_IW_T1I7_IMM7 (opcode) << 25) >> 24;
3202 break;
3203 default:
3204 bad_opcode (op);
3205 }
3206 address = address + 2 + i;
3207 (*info->print_address_func) (address, info);
3208 break;
3209
3210 case 'j':
3211 /* 5-bit unsigned immediate. */
3212 switch (op->format)
3213 {
3214 case iw_r_type:
3215 i = GET_IW_R_IMM5 (opcode);
3216 break;
3217 case iw_F3X6L5_type:
3218 i = GET_IW_F3X6L5_IMM5 (opcode);
3219 break;
3220 case iw_F2X6L10_type:
3221 i = GET_IW_F2X6L10_MSB (opcode);
3222 break;
3223 case iw_X2L5_type:
3224 i = GET_IW_X2L5_IMM5 (opcode);
3225 break;
3226 default:
3227 bad_opcode (op);
3228 }
3229 (*info->fprintf_func) (info->stream, "%ld", i);
3230 break;
3231
3232 case 'k':
3233 /* Second 5-bit unsigned immediate field. */
3234 switch (op->format)
3235 {
3236 case iw_F2X6L10_type:
3237 i = GET_IW_F2X6L10_LSB (opcode);
3238 break;
3239 default:
3240 bad_opcode (op);
3241 }
3242 (*info->fprintf_func) (info->stream, "%ld", i);
3243 break;
3244
3245 case 'l':
3246 /* 8-bit unsigned immediate. */
3247 switch (op->format)
3248 {
3249 case iw_custom_type:
3250 i = GET_IW_CUSTOM_N (opcode);
3251 break;
3252 case iw_F3X8_type:
3253 i = GET_IW_F3X8_N (opcode);
3254 break;
3255 default:
3256 bad_opcode (op);
3257 }
3258 (*info->fprintf_func) (info->stream, "%lu", i);
3259 break;
3260
3261 case 'm':
3262 /* 26-bit unsigned immediate. */
3263 switch (op->format)
3264 {
3265 case iw_j_type:
3266 i = GET_IW_J_IMM26 (opcode);
3267 break;
3268 case iw_L26_type:
3269 i = GET_IW_L26_IMM26 (opcode);
3270 break;
3271 default:
3272 bad_opcode (op);