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[qemu.git] / disas / ppc.c
1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not,
20 see <http://www.gnu.org/licenses/>. */
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #define BFD_DEFAULT_TARGET_SIZE 64
24
25 /* ppc.h -- Header file for PowerPC opcode table
26 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
27 2007 Free Software Foundation, Inc.
28 Written by Ian Lance Taylor, Cygnus Support
29
30 This file is part of GDB, GAS, and the GNU binutils.
31
32 GDB, GAS, and the GNU binutils are free software; you can redistribute
33 them and/or modify them under the terms of the GNU General Public
34 License as published by the Free Software Foundation; either version
35 1, or (at your option) any later version.
36
37 GDB, GAS, and the GNU binutils are distributed in the hope that they
38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
40 the GNU General Public License for more details.
41
42 You should have received a copy of the GNU General Public License
43 along with this file; see the file COPYING. If not,
44 see <http://www.gnu.org/licenses/>. */
45
46 /* The opcode table is an array of struct powerpc_opcode. */
47
48 struct powerpc_opcode
49 {
50 /* The opcode name. */
51 const char *name;
52
53 /* The opcode itself. Those bits which will be filled in with
54 operands are zeroes. */
55 unsigned long opcode;
56
57 /* The opcode mask. This is used by the disassembler. This is a
58 mask containing ones indicating those bits which must match the
59 opcode field, and zeroes indicating those bits which need not
60 match (and are presumably filled in by operands). */
61 unsigned long mask;
62
63 /* One bit flags for the opcode. These are used to indicate which
64 specific processors support the instructions. The defined values
65 are listed below. */
66 unsigned long flags;
67
68 /* An array of operand codes. Each code is an index into the
69 operand table. They appear in the order which the operands must
70 appear in assembly code, and are terminated by a zero. */
71 unsigned char operands[8];
72 };
73
74 /* The table itself is sorted by major opcode number, and is otherwise
75 in the order in which the disassembler should consider
76 instructions. */
77 extern const struct powerpc_opcode powerpc_opcodes[];
78 extern const int powerpc_num_opcodes;
79
80 /* Values defined for the flags field of a struct powerpc_opcode. */
81
82 /* Opcode is defined for the PowerPC architecture. */
83 #define PPC_OPCODE_PPC 1
84
85 /* Opcode is defined for the POWER (RS/6000) architecture. */
86 #define PPC_OPCODE_POWER 2
87
88 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
89 #define PPC_OPCODE_POWER2 4
90
91 /* Opcode is only defined on 32 bit architectures. */
92 #define PPC_OPCODE_32 8
93
94 /* Opcode is only defined on 64 bit architectures. */
95 #define PPC_OPCODE_64 0x10
96
97 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
98 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
99 but it also supports many additional POWER instructions. */
100 #define PPC_OPCODE_601 0x20
101
102 /* Opcode is supported in both the Power and PowerPC architectures
103 (ie, compiler's -mcpu=common or assembler's -mcom). */
104 #define PPC_OPCODE_COMMON 0x40
105
106 /* Opcode is supported for any Power or PowerPC platform (this is
107 for the assembler's -many option, and it eliminates duplicates). */
108 #define PPC_OPCODE_ANY 0x80
109
110 /* Opcode is supported as part of the 64-bit bridge. */
111 #define PPC_OPCODE_64_BRIDGE 0x100
112
113 /* Opcode is supported by Altivec Vector Unit */
114 #define PPC_OPCODE_ALTIVEC 0x200
115
116 /* Opcode is supported by PowerPC 403 processor. */
117 #define PPC_OPCODE_403 0x400
118
119 /* Opcode is supported by PowerPC BookE processor. */
120 #define PPC_OPCODE_BOOKE 0x800
121
122 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
123 #define PPC_OPCODE_BOOKE64 0x1000
124
125 /* Opcode is supported by PowerPC 440 processor. */
126 #define PPC_OPCODE_440 0x2000
127
128 /* Opcode is only supported by Power4 architecture. */
129 #define PPC_OPCODE_POWER4 0x4000
130
131 /* Opcode isn't supported by Power4 architecture. */
132 #define PPC_OPCODE_NOPOWER4 0x8000
133
134 /* Opcode is only supported by POWERPC Classic architecture. */
135 #define PPC_OPCODE_CLASSIC 0x10000
136
137 /* Opcode is only supported by e500x2 Core. */
138 #define PPC_OPCODE_SPE 0x20000
139
140 /* Opcode is supported by e500x2 Integer select APU. */
141 #define PPC_OPCODE_ISEL 0x40000
142
143 /* Opcode is an e500 SPE floating point instruction. */
144 #define PPC_OPCODE_EFS 0x80000
145
146 /* Opcode is supported by branch locking APU. */
147 #define PPC_OPCODE_BRLOCK 0x100000
148
149 /* Opcode is supported by performance monitor APU. */
150 #define PPC_OPCODE_PMR 0x200000
151
152 /* Opcode is supported by cache locking APU. */
153 #define PPC_OPCODE_CACHELCK 0x400000
154
155 /* Opcode is supported by machine check APU. */
156 #define PPC_OPCODE_RFMCI 0x800000
157
158 /* Opcode is only supported by Power5 architecture. */
159 #define PPC_OPCODE_POWER5 0x1000000
160
161 /* Opcode is supported by PowerPC e300 family. */
162 #define PPC_OPCODE_E300 0x2000000
163
164 /* Opcode is only supported by Power6 architecture. */
165 #define PPC_OPCODE_POWER6 0x4000000
166
167 /* Opcode is only supported by PowerPC Cell family. */
168 #define PPC_OPCODE_CELL 0x8000000
169
170 /* A macro to extract the major opcode from an instruction. */
171 #define PPC_OP(i) (((i) >> 26) & 0x3f)
172 \f
173 /* The operands table is an array of struct powerpc_operand. */
174
175 struct powerpc_operand
176 {
177 /* A bitmask of bits in the operand. */
178 unsigned int bitm;
179
180 /* How far the operand is left shifted in the instruction.
181 -1 to indicate that BITM and SHIFT cannot be used to determine
182 where the operand goes in the insn. */
183 int shift;
184
185 /* Insertion function. This is used by the assembler. To insert an
186 operand value into an instruction, check this field.
187
188 If it is NULL, execute
189 i |= (op & o->bitm) << o->shift;
190 (i is the instruction which we are filling in, o is a pointer to
191 this structure, and op is the operand value).
192
193 If this field is not NULL, then simply call it with the
194 instruction and the operand value. It will return the new value
195 of the instruction. If the ERRMSG argument is not NULL, then if
196 the operand value is illegal, *ERRMSG will be set to a warning
197 string (the operand will be inserted in any case). If the
198 operand value is legal, *ERRMSG will be unchanged (most operands
199 can accept any value). */
200 unsigned long (*insert)
201 (unsigned long instruction, long op, int dialect, const char **errmsg);
202
203 /* Extraction function. This is used by the disassembler. To
204 extract this operand type from an instruction, check this field.
205
206 If it is NULL, compute
207 op = (i >> o->shift) & o->bitm;
208 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
209 sign_extend (op);
210 (i is the instruction, o is a pointer to this structure, and op
211 is the result).
212
213 If this field is not NULL, then simply call it with the
214 instruction value. It will return the value of the operand. If
215 the INVALID argument is not NULL, *INVALID will be set to
216 non-zero if this operand type can not actually be extracted from
217 this operand (i.e., the instruction does not match). If the
218 operand is valid, *INVALID will not be changed. */
219 long (*extract) (unsigned long instruction, int dialect, int *invalid);
220
221 /* One bit syntax flags. */
222 unsigned long flags;
223 };
224
225 /* Elements in the table are retrieved by indexing with values from
226 the operands field of the powerpc_opcodes table. */
227
228 extern const struct powerpc_operand powerpc_operands[];
229 extern const unsigned int num_powerpc_operands;
230
231 /* Values defined for the flags field of a struct powerpc_operand. */
232
233 /* This operand takes signed values. */
234 #define PPC_OPERAND_SIGNED (0x1)
235
236 /* This operand takes signed values, but also accepts a full positive
237 range of values when running in 32 bit mode. That is, if bits is
238 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
239 this flag is ignored. */
240 #define PPC_OPERAND_SIGNOPT (0x2)
241
242 /* This operand does not actually exist in the assembler input. This
243 is used to support extended mnemonics such as mr, for which two
244 operands fields are identical. The assembler should call the
245 insert function with any op value. The disassembler should call
246 the extract function, ignore the return value, and check the value
247 placed in the valid argument. */
248 #define PPC_OPERAND_FAKE (0x4)
249
250 /* The next operand should be wrapped in parentheses rather than
251 separated from this one by a comma. This is used for the load and
252 store instructions which want their operands to look like
253 reg,displacement(reg)
254 */
255 #define PPC_OPERAND_PARENS (0x8)
256
257 /* This operand may use the symbolic names for the CR fields, which
258 are
259 lt 0 gt 1 eq 2 so 3 un 3
260 cr0 0 cr1 1 cr2 2 cr3 3
261 cr4 4 cr5 5 cr6 6 cr7 7
262 These may be combined arithmetically, as in cr2*4+gt. These are
263 only supported on the PowerPC, not the POWER. */
264 #define PPC_OPERAND_CR (0x10)
265
266 /* This operand names a register. The disassembler uses this to print
267 register names with a leading 'r'. */
268 #define PPC_OPERAND_GPR (0x20)
269
270 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
271 #define PPC_OPERAND_GPR_0 (0x40)
272
273 /* This operand names a floating point register. The disassembler
274 prints these with a leading 'f'. */
275 #define PPC_OPERAND_FPR (0x80)
276
277 /* This operand is a relative branch displacement. The disassembler
278 prints these symbolically if possible. */
279 #define PPC_OPERAND_RELATIVE (0x100)
280
281 /* This operand is an absolute branch address. The disassembler
282 prints these symbolically if possible. */
283 #define PPC_OPERAND_ABSOLUTE (0x200)
284
285 /* This operand is optional, and is zero if omitted. This is used for
286 example, in the optional BF field in the comparison instructions. The
287 assembler must count the number of operands remaining on the line,
288 and the number of operands remaining for the opcode, and decide
289 whether this operand is present or not. The disassembler should
290 print this operand out only if it is not zero. */
291 #define PPC_OPERAND_OPTIONAL (0x400)
292
293 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
294 is omitted, then for the next operand use this operand value plus
295 1, ignoring the next operand field for the opcode. This wretched
296 hack is needed because the Power rotate instructions can take
297 either 4 or 5 operands. The disassembler should print this operand
298 out regardless of the PPC_OPERAND_OPTIONAL field. */
299 #define PPC_OPERAND_NEXT (0x800)
300
301 /* This operand should be regarded as a negative number for the
302 purposes of overflow checking (i.e., the normal most negative
303 number is disallowed and one more than the normal most positive
304 number is allowed). This flag will only be set for a signed
305 operand. */
306 #define PPC_OPERAND_NEGATIVE (0x1000)
307
308 /* This operand names a vector unit register. The disassembler
309 prints these with a leading 'v'. */
310 #define PPC_OPERAND_VR (0x2000)
311
312 /* This operand is for the DS field in a DS form instruction. */
313 #define PPC_OPERAND_DS (0x4000)
314
315 /* This operand is for the DQ field in a DQ form instruction. */
316 #define PPC_OPERAND_DQ (0x8000)
317
318 /* Valid range of operand is 0..n rather than 0..n-1. */
319 #define PPC_OPERAND_PLUS1 (0x10000)
320 \f
321 /* The POWER and PowerPC assemblers use a few macros. We keep them
322 with the operands table for simplicity. The macro table is an
323 array of struct powerpc_macro. */
324
325 struct powerpc_macro
326 {
327 /* The macro name. */
328 const char *name;
329
330 /* The number of operands the macro takes. */
331 unsigned int operands;
332
333 /* One bit flags for the opcode. These are used to indicate which
334 specific processors support the instructions. The values are the
335 same as those for the struct powerpc_opcode flags field. */
336 unsigned long flags;
337
338 /* A format string to turn the macro into a normal instruction.
339 Each %N in the string is replaced with operand number N (zero
340 based). */
341 const char *format;
342 };
343
344 extern const struct powerpc_macro powerpc_macros[];
345 extern const int powerpc_num_macros;
346
347 /* ppc-opc.c -- PowerPC opcode list
348 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
349 2005, 2006, 2007 Free Software Foundation, Inc.
350 Written by Ian Lance Taylor, Cygnus Support
351
352 This file is part of GDB, GAS, and the GNU binutils.
353
354 GDB, GAS, and the GNU binutils are free software; you can redistribute
355 them and/or modify them under the terms of the GNU General Public
356 License as published by the Free Software Foundation; either version
357 2, or (at your option) any later version.
358
359 GDB, GAS, and the GNU binutils are distributed in the hope that they
360 will be useful, but WITHOUT ANY WARRANTY; without even the implied
361 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
362 the GNU General Public License for more details.
363
364 You should have received a copy of the GNU General Public License
365 along with this file; see the file COPYING.
366 If not, see <http://www.gnu.org/licenses/>. */
367
368 /* This file holds the PowerPC opcode table. The opcode table
369 includes almost all of the extended instruction mnemonics. This
370 permits the disassembler to use them, and simplifies the assembler
371 logic, at the cost of increasing the table size. The table is
372 strictly constant data, so the compiler should be able to put it in
373 the .text section.
374
375 This file also holds the operand table. All knowledge about
376 inserting operands into instructions and vice-versa is kept in this
377 file. */
378 \f
379 /* Local insertion and extraction functions. */
380
381 static unsigned long insert_bat (unsigned long, long, int, const char **);
382 static long extract_bat (unsigned long, int, int *);
383 static unsigned long insert_bba (unsigned long, long, int, const char **);
384 static long extract_bba (unsigned long, int, int *);
385 static unsigned long insert_bdm (unsigned long, long, int, const char **);
386 static long extract_bdm (unsigned long, int, int *);
387 static unsigned long insert_bdp (unsigned long, long, int, const char **);
388 static long extract_bdp (unsigned long, int, int *);
389 static unsigned long insert_bo (unsigned long, long, int, const char **);
390 static long extract_bo (unsigned long, int, int *);
391 static unsigned long insert_boe (unsigned long, long, int, const char **);
392 static long extract_boe (unsigned long, int, int *);
393 static unsigned long insert_fxm (unsigned long, long, int, const char **);
394 static long extract_fxm (unsigned long, int, int *);
395 static unsigned long insert_mbe (unsigned long, long, int, const char **);
396 static long extract_mbe (unsigned long, int, int *);
397 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
398 static long extract_mb6 (unsigned long, int, int *);
399 static long extract_nb (unsigned long, int, int *);
400 static unsigned long insert_nsi (unsigned long, long, int, const char **);
401 static long extract_nsi (unsigned long, int, int *);
402 static unsigned long insert_ral (unsigned long, long, int, const char **);
403 static unsigned long insert_ram (unsigned long, long, int, const char **);
404 static unsigned long insert_raq (unsigned long, long, int, const char **);
405 static unsigned long insert_ras (unsigned long, long, int, const char **);
406 static unsigned long insert_rbs (unsigned long, long, int, const char **);
407 static long extract_rbs (unsigned long, int, int *);
408 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
409 static long extract_sh6 (unsigned long, int, int *);
410 static unsigned long insert_spr (unsigned long, long, int, const char **);
411 static long extract_spr (unsigned long, int, int *);
412 static unsigned long insert_sprg (unsigned long, long, int, const char **);
413 static long extract_sprg (unsigned long, int, int *);
414 static unsigned long insert_tbr (unsigned long, long, int, const char **);
415 static long extract_tbr (unsigned long, int, int *);
416 \f
417 /* The operands table.
418
419 The fields are bitm, shift, insert, extract, flags.
420
421 We used to put parens around the various additions, like the one
422 for BA just below. However, that caused trouble with feeble
423 compilers with a limit on depth of a parenthesized expression, like
424 (reportedly) the compiler in Microsoft Developer Studio 5. So we
425 omit the parens, since the macros are never used in a context where
426 the addition will be ambiguous. */
427
428 const struct powerpc_operand powerpc_operands[] =
429 {
430 /* The zero index is used to indicate the end of the list of
431 operands. */
432 #define UNUSED 0
433 { 0, 0, NULL, NULL, 0 },
434
435 /* The BA field in an XL form instruction. */
436 #define BA UNUSED + 1
437 /* The BI field in a B form or XL form instruction. */
438 #define BI BA
439 #define BI_MASK (0x1f << 16)
440 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
441
442 /* The BA field in an XL form instruction when it must be the same
443 as the BT field in the same instruction. */
444 #define BAT BA + 1
445 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
446
447 /* The BB field in an XL form instruction. */
448 #define BB BAT + 1
449 #define BB_MASK (0x1f << 11)
450 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
451
452 /* The BB field in an XL form instruction when it must be the same
453 as the BA field in the same instruction. */
454 #define BBA BB + 1
455 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
456
457 /* The BD field in a B form instruction. The lower two bits are
458 forced to zero. */
459 #define BD BBA + 1
460 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
461
462 /* The BD field in a B form instruction when absolute addressing is
463 used. */
464 #define BDA BD + 1
465 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
466
467 /* The BD field in a B form instruction when the - modifier is used.
468 This sets the y bit of the BO field appropriately. */
469 #define BDM BDA + 1
470 { 0xfffc, 0, insert_bdm, extract_bdm,
471 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
472
473 /* The BD field in a B form instruction when the - modifier is used
474 and absolute address is used. */
475 #define BDMA BDM + 1
476 { 0xfffc, 0, insert_bdm, extract_bdm,
477 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
478
479 /* The BD field in a B form instruction when the + modifier is used.
480 This sets the y bit of the BO field appropriately. */
481 #define BDP BDMA + 1
482 { 0xfffc, 0, insert_bdp, extract_bdp,
483 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
484
485 /* The BD field in a B form instruction when the + modifier is used
486 and absolute addressing is used. */
487 #define BDPA BDP + 1
488 { 0xfffc, 0, insert_bdp, extract_bdp,
489 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
490
491 /* The BF field in an X or XL form instruction. */
492 #define BF BDPA + 1
493 /* The CRFD field in an X form instruction. */
494 #define CRFD BF
495 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
496
497 /* The BF field in an X or XL form instruction. */
498 #define BFF BF + 1
499 { 0x7, 23, NULL, NULL, 0 },
500
501 /* An optional BF field. This is used for comparison instructions,
502 in which an omitted BF field is taken as zero. */
503 #define OBF BFF + 1
504 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
505
506 /* The BFA field in an X or XL form instruction. */
507 #define BFA OBF + 1
508 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
509
510 /* The BO field in a B form instruction. Certain values are
511 illegal. */
512 #define BO BFA + 1
513 #define BO_MASK (0x1f << 21)
514 { 0x1f, 21, insert_bo, extract_bo, 0 },
515
516 /* The BO field in a B form instruction when the + or - modifier is
517 used. This is like the BO field, but it must be even. */
518 #define BOE BO + 1
519 { 0x1e, 21, insert_boe, extract_boe, 0 },
520
521 #define BH BOE + 1
522 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
523
524 /* The BT field in an X or XL form instruction. */
525 #define BT BH + 1
526 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
527
528 /* The condition register number portion of the BI field in a B form
529 or XL form instruction. This is used for the extended
530 conditional branch mnemonics, which set the lower two bits of the
531 BI field. This field is optional. */
532 #define CR BT + 1
533 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
534
535 /* The CRB field in an X form instruction. */
536 #define CRB CR + 1
537 /* The MB field in an M form instruction. */
538 #define MB CRB
539 #define MB_MASK (0x1f << 6)
540 { 0x1f, 6, NULL, NULL, 0 },
541
542 /* The CRFS field in an X form instruction. */
543 #define CRFS CRB + 1
544 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
545
546 /* The CT field in an X form instruction. */
547 #define CT CRFS + 1
548 /* The MO field in an mbar instruction. */
549 #define MO CT
550 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
551
552 /* The D field in a D form instruction. This is a displacement off
553 a register, and implies that the next operand is a register in
554 parentheses. */
555 #define D CT + 1
556 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
557
558 /* The DE field in a DE form instruction. This is like D, but is 12
559 bits only. */
560 #define DE D + 1
561 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
562
563 /* The DES field in a DES form instruction. This is like DS, but is 14
564 bits only (12 stored.) */
565 #define DES DE + 1
566 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
567
568 /* The DQ field in a DQ form instruction. This is like D, but the
569 lower four bits are forced to zero. */
570 #define DQ DES + 1
571 { 0xfff0, 0, NULL, NULL,
572 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
573
574 /* The DS field in a DS form instruction. This is like D, but the
575 lower two bits are forced to zero. */
576 #undef DS
577 #define DS DQ + 1
578 { 0xfffc, 0, NULL, NULL,
579 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
580
581 /* The E field in a wrteei instruction. */
582 #define E DS + 1
583 { 0x1, 15, NULL, NULL, 0 },
584
585 /* The FL1 field in a POWER SC form instruction. */
586 #define FL1 E + 1
587 /* The U field in an X form instruction. */
588 #define U FL1
589 { 0xf, 12, NULL, NULL, 0 },
590
591 /* The FL2 field in a POWER SC form instruction. */
592 #define FL2 FL1 + 1
593 { 0x7, 2, NULL, NULL, 0 },
594
595 /* The FLM field in an XFL form instruction. */
596 #define FLM FL2 + 1
597 { 0xff, 17, NULL, NULL, 0 },
598
599 /* The FRA field in an X or A form instruction. */
600 #define FRA FLM + 1
601 #define FRA_MASK (0x1f << 16)
602 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
603
604 /* The FRB field in an X or A form instruction. */
605 #define FRB FRA + 1
606 #define FRB_MASK (0x1f << 11)
607 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
608
609 /* The FRC field in an A form instruction. */
610 #define FRC FRB + 1
611 #define FRC_MASK (0x1f << 6)
612 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
613
614 /* The FRS field in an X form instruction or the FRT field in a D, X
615 or A form instruction. */
616 #define FRS FRC + 1
617 #define FRT FRS
618 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
619
620 /* The FXM field in an XFX instruction. */
621 #define FXM FRS + 1
622 { 0xff, 12, insert_fxm, extract_fxm, 0 },
623
624 /* Power4 version for mfcr. */
625 #define FXM4 FXM + 1
626 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
627
628 /* The L field in a D or X form instruction. */
629 #define L FXM4 + 1
630 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
631
632 /* The LEV field in a POWER SVC form instruction. */
633 #define SVC_LEV L + 1
634 { 0x7f, 5, NULL, NULL, 0 },
635
636 /* The LEV field in an SC form instruction. */
637 #define LEV SVC_LEV + 1
638 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
639
640 /* The LI field in an I form instruction. The lower two bits are
641 forced to zero. */
642 #define LI LEV + 1
643 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
644
645 /* The LI field in an I form instruction when used as an absolute
646 address. */
647 #define LIA LI + 1
648 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
649
650 /* The LS field in an X (sync) form instruction. */
651 #define LS LIA + 1
652 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
653
654 /* The ME field in an M form instruction. */
655 #define ME LS + 1
656 #define ME_MASK (0x1f << 1)
657 { 0x1f, 1, NULL, NULL, 0 },
658
659 /* The MB and ME fields in an M form instruction expressed a single
660 operand which is a bitmask indicating which bits to select. This
661 is a two operand form using PPC_OPERAND_NEXT. See the
662 description in opcode/ppc.h for what this means. */
663 #define MBE ME + 1
664 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
665 { -1, 0, insert_mbe, extract_mbe, 0 },
666
667 /* The MB or ME field in an MD or MDS form instruction. The high
668 bit is wrapped to the low end. */
669 #define MB6 MBE + 2
670 #define ME6 MB6
671 #define MB6_MASK (0x3f << 5)
672 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
673
674 /* The NB field in an X form instruction. The value 32 is stored as
675 0. */
676 #define NB MB6 + 1
677 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
678
679 /* The NSI field in a D form instruction. This is the same as the
680 SI field, only negated. */
681 #define NSI NB + 1
682 { 0xffff, 0, insert_nsi, extract_nsi,
683 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
684
685 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
686 #define RA NSI + 1
687 #define RA_MASK (0x1f << 16)
688 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
689
690 /* As above, but 0 in the RA field means zero, not r0. */
691 #define RA0 RA + 1
692 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
693
694 /* The RA field in the DQ form lq instruction, which has special
695 value restrictions. */
696 #define RAQ RA0 + 1
697 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
698
699 /* The RA field in a D or X form instruction which is an updating
700 load, which means that the RA field may not be zero and may not
701 equal the RT field. */
702 #define RAL RAQ + 1
703 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
704
705 /* The RA field in an lmw instruction, which has special value
706 restrictions. */
707 #define RAM RAL + 1
708 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
709
710 /* The RA field in a D or X form instruction which is an updating
711 store or an updating floating point load, which means that the RA
712 field may not be zero. */
713 #define RAS RAM + 1
714 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
715
716 /* The RA field of the tlbwe instruction, which is optional. */
717 #define RAOPT RAS + 1
718 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
719
720 /* The RB field in an X, XO, M, or MDS form instruction. */
721 #define RB RAOPT + 1
722 #define RB_MASK (0x1f << 11)
723 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
724
725 /* The RB field in an X form instruction when it must be the same as
726 the RS field in the instruction. This is used for extended
727 mnemonics like mr. */
728 #define RBS RB + 1
729 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
730
731 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
732 instruction or the RT field in a D, DS, X, XFX or XO form
733 instruction. */
734 #define RS RBS + 1
735 #define RT RS
736 #define RT_MASK (0x1f << 21)
737 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
738
739 /* The RS and RT fields of the DS form stq instruction, which have
740 special value restrictions. */
741 #define RSQ RS + 1
742 #define RTQ RSQ
743 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
744
745 /* The RS field of the tlbwe instruction, which is optional. */
746 #define RSO RSQ + 1
747 #define RTO RSO
748 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
749
750 /* The SH field in an X or M form instruction. */
751 #define SH RSO + 1
752 #define SH_MASK (0x1f << 11)
753 /* The other UIMM field in a EVX form instruction. */
754 #define EVUIMM SH
755 { 0x1f, 11, NULL, NULL, 0 },
756
757 /* The SH field in an MD form instruction. This is split. */
758 #define SH6 SH + 1
759 #define SH6_MASK ((0x1f << 11) | (1 << 1))
760 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
761
762 /* The SH field of the tlbwe instruction, which is optional. */
763 #define SHO SH6 + 1
764 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
765
766 /* The SI field in a D form instruction. */
767 #define SI SHO + 1
768 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
769
770 /* The SI field in a D form instruction when we accept a wide range
771 of positive values. */
772 #define SISIGNOPT SI + 1
773 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
774
775 /* The SPR field in an XFX form instruction. This is flipped--the
776 lower 5 bits are stored in the upper 5 and vice- versa. */
777 #define SPR SISIGNOPT + 1
778 #define PMR SPR
779 #define SPR_MASK (0x3ff << 11)
780 { 0x3ff, 11, insert_spr, extract_spr, 0 },
781
782 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
783 #define SPRBAT SPR + 1
784 #define SPRBAT_MASK (0x3 << 17)
785 { 0x3, 17, NULL, NULL, 0 },
786
787 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
788 #define SPRG SPRBAT + 1
789 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
790
791 /* The SR field in an X form instruction. */
792 #define SR SPRG + 1
793 { 0xf, 16, NULL, NULL, 0 },
794
795 /* The STRM field in an X AltiVec form instruction. */
796 #define STRM SR + 1
797 { 0x3, 21, NULL, NULL, 0 },
798
799 /* The SV field in a POWER SC form instruction. */
800 #define SV STRM + 1
801 { 0x3fff, 2, NULL, NULL, 0 },
802
803 /* The TBR field in an XFX form instruction. This is like the SPR
804 field, but it is optional. */
805 #define TBR SV + 1
806 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
807
808 /* The TO field in a D or X form instruction. */
809 #define TO TBR + 1
810 #define TO_MASK (0x1f << 21)
811 { 0x1f, 21, NULL, NULL, 0 },
812
813 /* The UI field in a D form instruction. */
814 #define UI TO + 1
815 { 0xffff, 0, NULL, NULL, 0 },
816
817 /* The VA field in a VA, VX or VXR form instruction. */
818 #define VA UI + 1
819 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
820
821 /* The VB field in a VA, VX or VXR form instruction. */
822 #define VB VA + 1
823 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
824
825 /* The VC field in a VA form instruction. */
826 #define VC VB + 1
827 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
828
829 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
830 #define VD VC + 1
831 #define VS VD
832 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
833
834 /* The SIMM field in a VX form instruction. */
835 #define SIMM VD + 1
836 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
837
838 /* The UIMM field in a VX form instruction, and TE in Z form. */
839 #define UIMM SIMM + 1
840 #define TE UIMM
841 { 0x1f, 16, NULL, NULL, 0 },
842
843 /* The SHB field in a VA form instruction. */
844 #define SHB UIMM + 1
845 { 0xf, 6, NULL, NULL, 0 },
846
847 /* The other UIMM field in a half word EVX form instruction. */
848 #define EVUIMM_2 SHB + 1
849 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
850
851 /* The other UIMM field in a word EVX form instruction. */
852 #define EVUIMM_4 EVUIMM_2 + 1
853 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
854
855 /* The other UIMM field in a double EVX form instruction. */
856 #define EVUIMM_8 EVUIMM_4 + 1
857 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
858
859 /* The WS field. */
860 #define WS EVUIMM_8 + 1
861 { 0x7, 11, NULL, NULL, 0 },
862
863 /* The L field in an mtmsrd or A form instruction or W in an X form. */
864 #define A_L WS + 1
865 #define W A_L
866 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
867
868 #define RMC A_L + 1
869 { 0x3, 9, NULL, NULL, 0 },
870
871 #define R RMC + 1
872 { 0x1, 16, NULL, NULL, 0 },
873
874 #define SP R + 1
875 { 0x3, 19, NULL, NULL, 0 },
876
877 #define S SP + 1
878 { 0x1, 20, NULL, NULL, 0 },
879
880 /* SH field starting at bit position 16. */
881 #define SH16 S + 1
882 /* The DCM and DGM fields in a Z form instruction. */
883 #define DCM SH16
884 #define DGM DCM
885 { 0x3f, 10, NULL, NULL, 0 },
886
887 /* The EH field in larx instruction. */
888 #define EH SH16 + 1
889 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
890
891 /* The L field in an mtfsf or XFL form instruction. */
892 #define XFL_L EH + 1
893 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
894 };
895
896 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
897 / sizeof (powerpc_operands[0]));
898
899 /* The functions used to insert and extract complicated operands. */
900
901 /* The BA field in an XL form instruction when it must be the same as
902 the BT field in the same instruction. This operand is marked FAKE.
903 The insertion function just copies the BT field into the BA field,
904 and the extraction function just checks that the fields are the
905 same. */
906
907 static unsigned long
908 insert_bat (unsigned long insn,
909 long value ATTRIBUTE_UNUSED,
910 int dialect ATTRIBUTE_UNUSED,
911 const char **errmsg ATTRIBUTE_UNUSED)
912 {
913 return insn | (((insn >> 21) & 0x1f) << 16);
914 }
915
916 static long
917 extract_bat (unsigned long insn,
918 int dialect ATTRIBUTE_UNUSED,
919 int *invalid)
920 {
921 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
922 *invalid = 1;
923 return 0;
924 }
925
926 /* The BB field in an XL form instruction when it must be the same as
927 the BA field in the same instruction. This operand is marked FAKE.
928 The insertion function just copies the BA field into the BB field,
929 and the extraction function just checks that the fields are the
930 same. */
931
932 static unsigned long
933 insert_bba (unsigned long insn,
934 long value ATTRIBUTE_UNUSED,
935 int dialect ATTRIBUTE_UNUSED,
936 const char **errmsg ATTRIBUTE_UNUSED)
937 {
938 return insn | (((insn >> 16) & 0x1f) << 11);
939 }
940
941 static long
942 extract_bba (unsigned long insn,
943 int dialect ATTRIBUTE_UNUSED,
944 int *invalid)
945 {
946 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
947 *invalid = 1;
948 return 0;
949 }
950
951 /* The BD field in a B form instruction when the - modifier is used.
952 This modifier means that the branch is not expected to be taken.
953 For chips built to versions of the architecture prior to version 2
954 (ie. not Power4 compatible), we set the y bit of the BO field to 1
955 if the offset is negative. When extracting, we require that the y
956 bit be 1 and that the offset be positive, since if the y bit is 0
957 we just want to print the normal form of the instruction.
958 Power4 compatible targets use two bits, "a", and "t", instead of
959 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
960 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
961 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
962 for branch on CTR. We only handle the taken/not-taken hint here.
963 Note that we don't relax the conditions tested here when
964 disassembling with -Many because insns using extract_bdm and
965 extract_bdp always occur in pairs. One or the other will always
966 be valid. */
967
968 static unsigned long
969 insert_bdm (unsigned long insn,
970 long value,
971 int dialect,
972 const char **errmsg ATTRIBUTE_UNUSED)
973 {
974 if ((dialect & PPC_OPCODE_POWER4) == 0)
975 {
976 if ((value & 0x8000) != 0)
977 insn |= 1 << 21;
978 }
979 else
980 {
981 if ((insn & (0x14 << 21)) == (0x04 << 21))
982 insn |= 0x02 << 21;
983 else if ((insn & (0x14 << 21)) == (0x10 << 21))
984 insn |= 0x08 << 21;
985 }
986 return insn | (value & 0xfffc);
987 }
988
989 static long
990 extract_bdm (unsigned long insn,
991 int dialect,
992 int *invalid)
993 {
994 if ((dialect & PPC_OPCODE_POWER4) == 0)
995 {
996 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
997 *invalid = 1;
998 }
999 else
1000 {
1001 if ((insn & (0x17 << 21)) != (0x06 << 21)
1002 && (insn & (0x1d << 21)) != (0x18 << 21))
1003 *invalid = 1;
1004 }
1005
1006 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1007 }
1008
1009 /* The BD field in a B form instruction when the + modifier is used.
1010 This is like BDM, above, except that the branch is expected to be
1011 taken. */
1012
1013 static unsigned long
1014 insert_bdp (unsigned long insn,
1015 long value,
1016 int dialect,
1017 const char **errmsg ATTRIBUTE_UNUSED)
1018 {
1019 if ((dialect & PPC_OPCODE_POWER4) == 0)
1020 {
1021 if ((value & 0x8000) == 0)
1022 insn |= 1 << 21;
1023 }
1024 else
1025 {
1026 if ((insn & (0x14 << 21)) == (0x04 << 21))
1027 insn |= 0x03 << 21;
1028 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1029 insn |= 0x09 << 21;
1030 }
1031 return insn | (value & 0xfffc);
1032 }
1033
1034 static long
1035 extract_bdp (unsigned long insn,
1036 int dialect,
1037 int *invalid)
1038 {
1039 if ((dialect & PPC_OPCODE_POWER4) == 0)
1040 {
1041 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1042 *invalid = 1;
1043 }
1044 else
1045 {
1046 if ((insn & (0x17 << 21)) != (0x07 << 21)
1047 && (insn & (0x1d << 21)) != (0x19 << 21))
1048 *invalid = 1;
1049 }
1050
1051 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1052 }
1053
1054 /* Check for legal values of a BO field. */
1055
1056 static int
1057 valid_bo (long value, int dialect, int extract)
1058 {
1059 if ((dialect & PPC_OPCODE_POWER4) == 0)
1060 {
1061 int valid;
1062 /* Certain encodings have bits that are required to be zero.
1063 These are (z must be zero, y may be anything):
1064 001zy
1065 011zy
1066 1z00y
1067 1z01y
1068 1z1zz
1069 */
1070 switch (value & 0x14)
1071 {
1072 default:
1073 case 0:
1074 valid = 1;
1075 break;
1076 case 0x4:
1077 valid = (value & 0x2) == 0;
1078 break;
1079 case 0x10:
1080 valid = (value & 0x8) == 0;
1081 break;
1082 case 0x14:
1083 valid = value == 0x14;
1084 break;
1085 }
1086 /* When disassembling with -Many, accept power4 encodings too. */
1087 if (valid
1088 || (dialect & PPC_OPCODE_ANY) == 0
1089 || !extract)
1090 return valid;
1091 }
1092
1093 /* Certain encodings have bits that are required to be zero.
1094 These are (z must be zero, a & t may be anything):
1095 0000z
1096 0001z
1097 0100z
1098 0101z
1099 001at
1100 011at
1101 1a00t
1102 1a01t
1103 1z1zz
1104 */
1105 if ((value & 0x14) == 0)
1106 return (value & 0x1) == 0;
1107 else if ((value & 0x14) == 0x14)
1108 return value == 0x14;
1109 else
1110 return 1;
1111 }
1112
1113 /* The BO field in a B form instruction. Warn about attempts to set
1114 the field to an illegal value. */
1115
1116 static unsigned long
1117 insert_bo (unsigned long insn,
1118 long value,
1119 int dialect,
1120 const char **errmsg)
1121 {
1122 if (!valid_bo (value, dialect, 0))
1123 *errmsg = "invalid conditional option";
1124 return insn | ((value & 0x1f) << 21);
1125 }
1126
1127 static long
1128 extract_bo (unsigned long insn,
1129 int dialect,
1130 int *invalid)
1131 {
1132 long value;
1133
1134 value = (insn >> 21) & 0x1f;
1135 if (!valid_bo (value, dialect, 1))
1136 *invalid = 1;
1137 return value;
1138 }
1139
1140 /* The BO field in a B form instruction when the + or - modifier is
1141 used. This is like the BO field, but it must be even. When
1142 extracting it, we force it to be even. */
1143
1144 static unsigned long
1145 insert_boe (unsigned long insn,
1146 long value,
1147 int dialect,
1148 const char **errmsg)
1149 {
1150 if (!valid_bo (value, dialect, 0))
1151 *errmsg = "invalid conditional option";
1152 else if ((value & 1) != 0)
1153 *errmsg = "attempt to set y bit when using + or - modifier";
1154
1155 return insn | ((value & 0x1f) << 21);
1156 }
1157
1158 static long
1159 extract_boe (unsigned long insn,
1160 int dialect,
1161 int *invalid)
1162 {
1163 long value;
1164
1165 value = (insn >> 21) & 0x1f;
1166 if (!valid_bo (value, dialect, 1))
1167 *invalid = 1;
1168 return value & 0x1e;
1169 }
1170
1171 /* FXM mask in mfcr and mtcrf instructions. */
1172
1173 static unsigned long
1174 insert_fxm (unsigned long insn,
1175 long value,
1176 int dialect,
1177 const char **errmsg)
1178 {
1179 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1180 one bit of the mask field is set. */
1181 if ((insn & (1 << 20)) != 0)
1182 {
1183 if (value == 0 || (value & -value) != value)
1184 {
1185 *errmsg = "invalid mask field";
1186 value = 0;
1187 }
1188 }
1189
1190 /* If the optional field on mfcr is missing that means we want to use
1191 the old form of the instruction that moves the whole cr. In that
1192 case we'll have VALUE zero. There doesn't seem to be a way to
1193 distinguish this from the case where someone writes mfcr %r3,0. */
1194 else if (value == 0)
1195 ;
1196
1197 /* If only one bit of the FXM field is set, we can use the new form
1198 of the instruction, which is faster. Unlike the Power4 branch hint
1199 encoding, this is not backward compatible. Do not generate the
1200 new form unless -mpower4 has been given, or -many and the two
1201 operand form of mfcr was used. */
1202 else if ((value & -value) == value
1203 && ((dialect & PPC_OPCODE_POWER4) != 0
1204 || ((dialect & PPC_OPCODE_ANY) != 0
1205 && (insn & (0x3ff << 1)) == 19 << 1)))
1206 insn |= 1 << 20;
1207
1208 /* Any other value on mfcr is an error. */
1209 else if ((insn & (0x3ff << 1)) == 19 << 1)
1210 {
1211 *errmsg = "ignoring invalid mfcr mask";
1212 value = 0;
1213 }
1214
1215 return insn | ((value & 0xff) << 12);
1216 }
1217
1218 static long
1219 extract_fxm (unsigned long insn,
1220 int dialect ATTRIBUTE_UNUSED,
1221 int *invalid)
1222 {
1223 long mask = (insn >> 12) & 0xff;
1224
1225 /* Is this a Power4 insn? */
1226 if ((insn & (1 << 20)) != 0)
1227 {
1228 /* Exactly one bit of MASK should be set. */
1229 if (mask == 0 || (mask & -mask) != mask)
1230 *invalid = 1;
1231 }
1232
1233 /* Check that non-power4 form of mfcr has a zero MASK. */
1234 else if ((insn & (0x3ff << 1)) == 19 << 1)
1235 {
1236 if (mask != 0)
1237 *invalid = 1;
1238 }
1239
1240 return mask;
1241 }
1242
1243 /* The MB and ME fields in an M form instruction expressed as a single
1244 operand which is itself a bitmask. The extraction function always
1245 marks it as invalid, since we never want to recognize an
1246 instruction which uses a field of this type. */
1247
1248 static unsigned long
1249 insert_mbe (unsigned long insn,
1250 long value,
1251 int dialect ATTRIBUTE_UNUSED,
1252 const char **errmsg)
1253 {
1254 unsigned long uval, mask;
1255 int mb, me, mx, count, last;
1256
1257 uval = value;
1258
1259 if (uval == 0)
1260 {
1261 *errmsg = "illegal bitmask";
1262 return insn;
1263 }
1264
1265 mb = 0;
1266 me = 32;
1267 if ((uval & 1) != 0)
1268 last = 1;
1269 else
1270 last = 0;
1271 count = 0;
1272
1273 /* mb: location of last 0->1 transition */
1274 /* me: location of last 1->0 transition */
1275 /* count: # transitions */
1276
1277 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1278 {
1279 if ((uval & mask) && !last)
1280 {
1281 ++count;
1282 mb = mx;
1283 last = 1;
1284 }
1285 else if (!(uval & mask) && last)
1286 {
1287 ++count;
1288 me = mx;
1289 last = 0;
1290 }
1291 }
1292 if (me == 0)
1293 me = 32;
1294
1295 if (count != 2 && (count != 0 || ! last))
1296 *errmsg = "illegal bitmask";
1297
1298 return insn | (mb << 6) | ((me - 1) << 1);
1299 }
1300
1301 static long
1302 extract_mbe (unsigned long insn,
1303 int dialect ATTRIBUTE_UNUSED,
1304 int *invalid)
1305 {
1306 long ret;
1307 int mb, me;
1308 int i;
1309
1310 *invalid = 1;
1311
1312 mb = (insn >> 6) & 0x1f;
1313 me = (insn >> 1) & 0x1f;
1314 if (mb < me + 1)
1315 {
1316 ret = 0;
1317 for (i = mb; i <= me; i++)
1318 ret |= 1L << (31 - i);
1319 }
1320 else if (mb == me + 1)
1321 ret = ~0;
1322 else /* (mb > me + 1) */
1323 {
1324 ret = ~0;
1325 for (i = me + 1; i < mb; i++)
1326 ret &= ~(1L << (31 - i));
1327 }
1328 return ret;
1329 }
1330
1331 /* The MB or ME field in an MD or MDS form instruction. The high bit
1332 is wrapped to the low end. */
1333
1334 static unsigned long
1335 insert_mb6 (unsigned long insn,
1336 long value,
1337 int dialect ATTRIBUTE_UNUSED,
1338 const char **errmsg ATTRIBUTE_UNUSED)
1339 {
1340 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1341 }
1342
1343 static long
1344 extract_mb6 (unsigned long insn,
1345 int dialect ATTRIBUTE_UNUSED,
1346 int *invalid ATTRIBUTE_UNUSED)
1347 {
1348 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1349 }
1350
1351 /* The NB field in an X form instruction. The value 32 is stored as
1352 0. */
1353
1354 static long
1355 extract_nb (unsigned long insn,
1356 int dialect ATTRIBUTE_UNUSED,
1357 int *invalid ATTRIBUTE_UNUSED)
1358 {
1359 long ret;
1360
1361 ret = (insn >> 11) & 0x1f;
1362 if (ret == 0)
1363 ret = 32;
1364 return ret;
1365 }
1366
1367 /* The NSI field in a D form instruction. This is the same as the SI
1368 field, only negated. The extraction function always marks it as
1369 invalid, since we never want to recognize an instruction which uses
1370 a field of this type. */
1371
1372 static unsigned long
1373 insert_nsi (unsigned long insn,
1374 long value,
1375 int dialect ATTRIBUTE_UNUSED,
1376 const char **errmsg ATTRIBUTE_UNUSED)
1377 {
1378 return insn | (-value & 0xffff);
1379 }
1380
1381 static long
1382 extract_nsi (unsigned long insn,
1383 int dialect ATTRIBUTE_UNUSED,
1384 int *invalid)
1385 {
1386 *invalid = 1;
1387 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1388 }
1389
1390 /* The RA field in a D or X form instruction which is an updating
1391 load, which means that the RA field may not be zero and may not
1392 equal the RT field. */
1393
1394 static unsigned long
1395 insert_ral (unsigned long insn,
1396 long value,
1397 int dialect ATTRIBUTE_UNUSED,
1398 const char **errmsg)
1399 {
1400 if (value == 0
1401 || (unsigned long) value == ((insn >> 21) & 0x1f))
1402 *errmsg = "invalid register operand when updating";
1403 return insn | ((value & 0x1f) << 16);
1404 }
1405
1406 /* The RA field in an lmw instruction, which has special value
1407 restrictions. */
1408
1409 static unsigned long
1410 insert_ram (unsigned long insn,
1411 long value,
1412 int dialect ATTRIBUTE_UNUSED,
1413 const char **errmsg)
1414 {
1415 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1416 *errmsg = "index register in load range";
1417 return insn | ((value & 0x1f) << 16);
1418 }
1419
1420 /* The RA field in the DQ form lq instruction, which has special
1421 value restrictions. */
1422
1423 static unsigned long
1424 insert_raq (unsigned long insn,
1425 long value,
1426 int dialect ATTRIBUTE_UNUSED,
1427 const char **errmsg)
1428 {
1429 long rtvalue = (insn & RT_MASK) >> 21;
1430
1431 if (value == rtvalue)
1432 *errmsg = "source and target register operands must be different";
1433 return insn | ((value & 0x1f) << 16);
1434 }
1435
1436 /* The RA field in a D or X form instruction which is an updating
1437 store or an updating floating point load, which means that the RA
1438 field may not be zero. */
1439
1440 static unsigned long
1441 insert_ras (unsigned long insn,
1442 long value,
1443 int dialect ATTRIBUTE_UNUSED,
1444 const char **errmsg)
1445 {
1446 if (value == 0)
1447 *errmsg = "invalid register operand when updating";
1448 return insn | ((value & 0x1f) << 16);
1449 }
1450
1451 /* The RB field in an X form instruction when it must be the same as
1452 the RS field in the instruction. This is used for extended
1453 mnemonics like mr. This operand is marked FAKE. The insertion
1454 function just copies the BT field into the BA field, and the
1455 extraction function just checks that the fields are the same. */
1456
1457 static unsigned long
1458 insert_rbs (unsigned long insn,
1459 long value ATTRIBUTE_UNUSED,
1460 int dialect ATTRIBUTE_UNUSED,
1461 const char **errmsg ATTRIBUTE_UNUSED)
1462 {
1463 return insn | (((insn >> 21) & 0x1f) << 11);
1464 }
1465
1466 static long
1467 extract_rbs (unsigned long insn,
1468 int dialect ATTRIBUTE_UNUSED,
1469 int *invalid)
1470 {
1471 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1472 *invalid = 1;
1473 return 0;
1474 }
1475
1476 /* The SH field in an MD form instruction. This is split. */
1477
1478 static unsigned long
1479 insert_sh6 (unsigned long insn,
1480 long value,
1481 int dialect ATTRIBUTE_UNUSED,
1482 const char **errmsg ATTRIBUTE_UNUSED)
1483 {
1484 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1485 }
1486
1487 static long
1488 extract_sh6 (unsigned long insn,
1489 int dialect ATTRIBUTE_UNUSED,
1490 int *invalid ATTRIBUTE_UNUSED)
1491 {
1492 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1493 }
1494
1495 /* The SPR field in an XFX form instruction. This is flipped--the
1496 lower 5 bits are stored in the upper 5 and vice- versa. */
1497
1498 static unsigned long
1499 insert_spr (unsigned long insn,
1500 long value,
1501 int dialect ATTRIBUTE_UNUSED,
1502 const char **errmsg ATTRIBUTE_UNUSED)
1503 {
1504 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1505 }
1506
1507 static long
1508 extract_spr (unsigned long insn,
1509 int dialect ATTRIBUTE_UNUSED,
1510 int *invalid ATTRIBUTE_UNUSED)
1511 {
1512 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1513 }
1514
1515 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1516
1517 static unsigned long
1518 insert_sprg (unsigned long insn,
1519 long value,
1520 int dialect,
1521 const char **errmsg)
1522 {
1523 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1524 as a synonym. If ever a 405 specific dialect is added this
1525 check should use that instead. */
1526 if (value > 7
1527 || (value > 3
1528 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1529 *errmsg = "invalid sprg number";
1530
1531 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1532 user mode. Anything else must use spr 272..279. */
1533 if (value <= 3 || (insn & 0x100) != 0)
1534 value |= 0x10;
1535
1536 return insn | ((value & 0x17) << 16);
1537 }
1538
1539 static long
1540 extract_sprg (unsigned long insn,
1541 int dialect,
1542 int *invalid)
1543 {
1544 unsigned long val = (insn >> 16) & 0x1f;
1545
1546 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1547 If not BOOKE or 405, then both use only 272..275. */
1548 if (val <= 3
1549 || (val < 0x10 && (insn & 0x100) != 0)
1550 || (val - 0x10 > 3
1551 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1552 *invalid = 1;
1553 return val & 7;
1554 }
1555
1556 /* The TBR field in an XFX instruction. This is just like SPR, but it
1557 is optional. When TBR is omitted, it must be inserted as 268 (the
1558 magic number of the TB register). These functions treat 0
1559 (indicating an omitted optional operand) as 268. This means that
1560 ``mftb 4,0'' is not handled correctly. This does not matter very
1561 much, since the architecture manual does not define mftb as
1562 accepting any values other than 268 or 269. */
1563
1564 #define TB (268)
1565
1566 static unsigned long
1567 insert_tbr (unsigned long insn,
1568 long value,
1569 int dialect ATTRIBUTE_UNUSED,
1570 const char **errmsg ATTRIBUTE_UNUSED)
1571 {
1572 if (value == 0)
1573 value = TB;
1574 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1575 }
1576
1577 static long
1578 extract_tbr (unsigned long insn,
1579 int dialect ATTRIBUTE_UNUSED,
1580 int *invalid ATTRIBUTE_UNUSED)
1581 {
1582 long ret;
1583
1584 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1585 if (ret == TB)
1586 ret = 0;
1587 return ret;
1588 }
1589 \f
1590 /* Macros used to form opcodes. */
1591
1592 /* The main opcode. */
1593 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1594 #define OP_MASK OP (0x3f)
1595
1596 /* The main opcode combined with a trap code in the TO field of a D
1597 form instruction. Used for extended mnemonics for the trap
1598 instructions. */
1599 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1600 #define OPTO_MASK (OP_MASK | TO_MASK)
1601
1602 /* The main opcode combined with a comparison size bit in the L field
1603 of a D form or X form instruction. Used for extended mnemonics for
1604 the comparison instructions. */
1605 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1606 #define OPL_MASK OPL (0x3f,1)
1607
1608 /* An A form instruction. */
1609 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1610 #define A_MASK A (0x3f, 0x1f, 1)
1611
1612 /* An A_MASK with the FRB field fixed. */
1613 #define AFRB_MASK (A_MASK | FRB_MASK)
1614
1615 /* An A_MASK with the FRC field fixed. */
1616 #define AFRC_MASK (A_MASK | FRC_MASK)
1617
1618 /* An A_MASK with the FRA and FRC fields fixed. */
1619 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1620
1621 /* An AFRAFRC_MASK, but with L bit clear. */
1622 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1623
1624 /* A B form instruction. */
1625 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1626 #define B_MASK B (0x3f, 1, 1)
1627
1628 /* A B form instruction setting the BO field. */
1629 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1630 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1631
1632 /* A BBO_MASK with the y bit of the BO field removed. This permits
1633 matching a conditional branch regardless of the setting of the y
1634 bit. Similarly for the 'at' bits used for power4 branch hints. */
1635 #define Y_MASK (((unsigned long) 1) << 21)
1636 #define AT1_MASK (((unsigned long) 3) << 21)
1637 #define AT2_MASK (((unsigned long) 9) << 21)
1638 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1639 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1640
1641 /* A B form instruction setting the BO field and the condition bits of
1642 the BI field. */
1643 #define BBOCB(op, bo, cb, aa, lk) \
1644 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1645 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1646
1647 /* A BBOCB_MASK with the y bit of the BO field removed. */
1648 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1649 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1650 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1651
1652 /* A BBOYCB_MASK in which the BI field is fixed. */
1653 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1654 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1655
1656 /* An Context form instruction. */
1657 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1658 #define CTX_MASK CTX(0x3f, 0x7)
1659
1660 /* An User Context form instruction. */
1661 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1662 #define UCTX_MASK UCTX(0x3f, 0x1f)
1663
1664 /* The main opcode mask with the RA field clear. */
1665 #define DRA_MASK (OP_MASK | RA_MASK)
1666
1667 /* A DS form instruction. */
1668 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1669 #define DS_MASK DSO (0x3f, 3)
1670
1671 /* A DE form instruction. */
1672 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1673 #define DE_MASK DEO (0x3e, 0xf)
1674
1675 /* An EVSEL form instruction. */
1676 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1677 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1678
1679 /* An M form instruction. */
1680 #define M(op, rc) (OP (op) | ((rc) & 1))
1681 #define M_MASK M (0x3f, 1)
1682
1683 /* An M form instruction with the ME field specified. */
1684 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1685
1686 /* An M_MASK with the MB and ME fields fixed. */
1687 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1688
1689 /* An M_MASK with the SH and ME fields fixed. */
1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1691
1692 /* An MD form instruction. */
1693 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1694 #define MD_MASK MD (0x3f, 0x7, 1)
1695
1696 /* An MD_MASK with the MB field fixed. */
1697 #define MDMB_MASK (MD_MASK | MB6_MASK)
1698
1699 /* An MD_MASK with the SH field fixed. */
1700 #define MDSH_MASK (MD_MASK | SH6_MASK)
1701
1702 /* An MDS form instruction. */
1703 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1704 #define MDS_MASK MDS (0x3f, 0xf, 1)
1705
1706 /* An MDS_MASK with the MB field fixed. */
1707 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1708
1709 /* An SC form instruction. */
1710 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1711 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1712
1713 /* An VX form instruction. */
1714 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1715
1716 /* The mask for an VX form instruction. */
1717 #define VX_MASK VX(0x3f, 0x7ff)
1718
1719 /* An VA form instruction. */
1720 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1721
1722 /* The mask for an VA form instruction. */
1723 #define VXA_MASK VXA(0x3f, 0x3f)
1724
1725 /* An VXR form instruction. */
1726 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1727
1728 /* The mask for a VXR form instruction. */
1729 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1730
1731 /* An X form instruction. */
1732 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1733
1734 /* A Z form instruction. */
1735 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1736
1737 /* An X form instruction with the RC bit specified. */
1738 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1739
1740 /* A Z form instruction with the RC bit specified. */
1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1742
1743 /* The mask for an X form instruction. */
1744 #define X_MASK XRC (0x3f, 0x3ff, 1)
1745
1746 /* The mask for a Z form instruction. */
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1749
1750 /* An X_MASK with the RA field fixed. */
1751 #define XRA_MASK (X_MASK | RA_MASK)
1752
1753 /* An XRA_MASK with the W field clear. */
1754 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1755
1756 /* An X_MASK with the RB field fixed. */
1757 #define XRB_MASK (X_MASK | RB_MASK)
1758
1759 /* An X_MASK with the RT field fixed. */
1760 #define XRT_MASK (X_MASK | RT_MASK)
1761
1762 /* An XRT_MASK mask with the L bits clear. */
1763 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1764
1765 /* An X_MASK with the RA and RB fields fixed. */
1766 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1767
1768 /* An XRARB_MASK, but with the L bit clear. */
1769 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1770
1771 /* An X_MASK with the RT and RA fields fixed. */
1772 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1773
1774 /* An XRTRA_MASK, but with L bit clear. */
1775 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1776
1777 /* An X form instruction with the L bit specified. */
1778 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1779
1780 /* The mask for an X form comparison instruction. */
1781 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1782
1783 /* The mask for an X form comparison instruction with the L field
1784 fixed. */
1785 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1786
1787 /* An X form trap instruction with the TO field specified. */
1788 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1789 #define XTO_MASK (X_MASK | TO_MASK)
1790
1791 /* An X form tlb instruction with the SH field specified. */
1792 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1793 #define XTLB_MASK (X_MASK | SH_MASK)
1794
1795 /* An X form sync instruction. */
1796 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1797
1798 /* An X form sync instruction with everything filled in except the LS field. */
1799 #define XSYNC_MASK (0xff9fffff)
1800
1801 /* An X_MASK, but with the EH bit clear. */
1802 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1803
1804 /* An X form AltiVec dss instruction. */
1805 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1806 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1807
1808 /* An XFL form instruction. */
1809 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1810 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1811
1812 /* An X form isel instruction. */
1813 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1814 #define XISEL_MASK XISEL(0x3f, 0x1f)
1815
1816 /* An XL form instruction with the LK field set to 0. */
1817 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1818
1819 /* An XL form instruction which uses the LK field. */
1820 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1821
1822 /* The mask for an XL form instruction. */
1823 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1824
1825 /* An XL form instruction which explicitly sets the BO field. */
1826 #define XLO(op, bo, xop, lk) \
1827 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1828 #define XLO_MASK (XL_MASK | BO_MASK)
1829
1830 /* An XL form instruction which explicitly sets the y bit of the BO
1831 field. */
1832 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1833 #define XLYLK_MASK (XL_MASK | Y_MASK)
1834
1835 /* An XL form instruction which sets the BO field and the condition
1836 bits of the BI field. */
1837 #define XLOCB(op, bo, cb, xop, lk) \
1838 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1839 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1840
1841 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1842 #define XLBB_MASK (XL_MASK | BB_MASK)
1843 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1844 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1845
1846 /* A mask for branch instructions using the BH field. */
1847 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1848
1849 /* An XL_MASK with the BO and BB fields fixed. */
1850 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1851
1852 /* An XL_MASK with the BO, BI and BB fields fixed. */
1853 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1854
1855 /* An XO form instruction. */
1856 #define XO(op, xop, oe, rc) \
1857 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1858 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1859
1860 /* An XO_MASK with the RB field fixed. */
1861 #define XORB_MASK (XO_MASK | RB_MASK)
1862
1863 /* An XS form instruction. */
1864 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1865 #define XS_MASK XS (0x3f, 0x1ff, 1)
1866
1867 /* A mask for the FXM version of an XFX form instruction. */
1868 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1869
1870 /* An XFX form instruction with the FXM field filled in. */
1871 #define XFXM(op, xop, fxm, p4) \
1872 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1873 | ((unsigned long)(p4) << 20))
1874
1875 /* An XFX form instruction with the SPR field filled in. */
1876 #define XSPR(op, xop, spr) \
1877 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1878 #define XSPR_MASK (X_MASK | SPR_MASK)
1879
1880 /* An XFX form instruction with the SPR field filled in except for the
1881 SPRBAT field. */
1882 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1883
1884 /* An XFX form instruction with the SPR field filled in except for the
1885 SPRG field. */
1886 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1887
1888 /* An X form instruction with everything filled in except the E field. */
1889 #define XE_MASK (0xffff7fff)
1890
1891 /* An X form user context instruction. */
1892 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1893 #define XUC_MASK XUC(0x3f, 0x1f)
1894
1895 /* The BO encodings used in extended conditional branch mnemonics. */
1896 #define BODNZF (0x0)
1897 #define BODNZFP (0x1)
1898 #define BODZF (0x2)
1899 #define BODZFP (0x3)
1900 #define BODNZT (0x8)
1901 #define BODNZTP (0x9)
1902 #define BODZT (0xa)
1903 #define BODZTP (0xb)
1904
1905 #define BOF (0x4)
1906 #define BOFP (0x5)
1907 #define BOFM4 (0x6)
1908 #define BOFP4 (0x7)
1909 #define BOT (0xc)
1910 #define BOTP (0xd)
1911 #define BOTM4 (0xe)
1912 #define BOTP4 (0xf)
1913
1914 #define BODNZ (0x10)
1915 #define BODNZP (0x11)
1916 #define BODZ (0x12)
1917 #define BODZP (0x13)
1918 #define BODNZM4 (0x18)
1919 #define BODNZP4 (0x19)
1920 #define BODZM4 (0x1a)
1921 #define BODZP4 (0x1b)
1922
1923 #define BOU (0x14)
1924
1925 /* The BI condition bit encodings used in extended conditional branch
1926 mnemonics. */
1927 #define CBLT (0)
1928 #define CBGT (1)
1929 #define CBEQ (2)
1930 #define CBSO (3)
1931
1932 /* The TO encodings used in extended trap mnemonics. */
1933 #define TOLGT (0x1)
1934 #define TOLLT (0x2)
1935 #define TOEQ (0x4)
1936 #define TOLGE (0x5)
1937 #define TOLNL (0x5)
1938 #define TOLLE (0x6)
1939 #define TOLNG (0x6)
1940 #define TOGT (0x8)
1941 #define TOGE (0xc)
1942 #define TONL (0xc)
1943 #define TOLT (0x10)
1944 #define TOLE (0x14)
1945 #define TONG (0x14)
1946 #define TONE (0x18)
1947 #define TOU (0x1f)
1948 \f
1949 /* Smaller names for the flags so each entry in the opcodes table will
1950 fit on a single line. */
1951 #undef PPC
1952 #define PPC PPC_OPCODE_PPC
1953 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1954 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1955 #define POWER4 PPC_OPCODE_POWER4
1956 #define POWER5 PPC_OPCODE_POWER5
1957 #define POWER6 PPC_OPCODE_POWER6
1958 #define CELL PPC_OPCODE_CELL
1959 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1960 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1961 #define PPC403 PPC_OPCODE_403
1962 #define PPC405 PPC403
1963 #define PPC440 PPC_OPCODE_440
1964 #define PPC750 PPC
1965 #define PPC860 PPC
1966 #define PPCVEC PPC_OPCODE_ALTIVEC
1967 #define POWER PPC_OPCODE_POWER
1968 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1969 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1970 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1971 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1972 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1973 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1974 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1975 #define MFDEC1 PPC_OPCODE_POWER
1976 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1977 #define BOOKE PPC_OPCODE_BOOKE
1978 #define BOOKE64 PPC_OPCODE_BOOKE64
1979 #define CLASSIC PPC_OPCODE_CLASSIC
1980 #define PPCE300 PPC_OPCODE_E300
1981 #define PPCSPE PPC_OPCODE_SPE
1982 #define PPCISEL PPC_OPCODE_ISEL
1983 #define PPCEFS PPC_OPCODE_EFS
1984 #define PPCBRLK PPC_OPCODE_BRLOCK
1985 #define PPCPMR PPC_OPCODE_PMR
1986 #define PPCCHLK PPC_OPCODE_CACHELCK
1987 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1988 #define PPCRFMCI PPC_OPCODE_RFMCI
1989 \f
1990 /* The opcode table.
1991
1992 The format of the opcode table is:
1993
1994 NAME OPCODE MASK FLAGS { OPERANDS }
1995
1996 NAME is the name of the instruction.
1997 OPCODE is the instruction opcode.
1998 MASK is the opcode mask; this is used to tell the disassembler
1999 which bits in the actual opcode must match OPCODE.
2000 FLAGS are flags indicated what processors support the instruction.
2001 OPERANDS is the list of operands.
2002
2003 The disassembler reads the table in order and prints the first
2004 instruction which matches, so this table is sorted to put more
2005 specific instructions before more general instructions. It is also
2006 sorted by major opcode. */
2007
2008 const struct powerpc_opcode powerpc_opcodes[] = {
2009 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2010 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
2011 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
2012 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
2013 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
2014 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
2015 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2016 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
2017 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
2018 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
2019 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
2020 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
2021 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
2022 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
2023 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
2024 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2025
2026 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
2027 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
2028 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
2029 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
2030 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
2031 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
2032 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
2033 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
2034 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
2035 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
2036 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2037 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
2038 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
2039 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
2040 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
2041 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
2042 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
2044 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
2045 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
2046 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
2047 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
2048 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
2049 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
2050 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
2051 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
2052 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
2053 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
2054 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2055 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2056
2057 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2072 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2073 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2075 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2076 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2078 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2079 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2080 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2081 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2082 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2083 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2084 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2085 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2086 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2087 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2088 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2089 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2090 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2091 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2092 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2093 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2094 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2095 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2096 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2097 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2098 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2099 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2100 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2101 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2103 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2104 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2105 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2106 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2107 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2108 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2109 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2110 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2111 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2112 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2113 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2114 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2115 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2116 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2117 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2118 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2119 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2120 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2121 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2122 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2123 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2124 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2125 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2126 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2127 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2128 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2129 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2130 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2131 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2132 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2133 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2134 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2135 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2136 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2137 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2138 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2139 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2140 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2141 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2142 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2143
2144 /* Double-precision opcodes. */
2145 /* Some of these conflict with AltiVec, so move them before, since
2146 PPCVEC includes the PPC_OPCODE_PPC set. */
2147 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2148 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2149 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2150 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2151 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2152 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2153 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2154 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2155 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2156 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2157 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2158 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2159 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2160 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2161 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2162 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2163 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2164 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2165 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2166 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2167 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2168 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2169 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2170 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2171 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2172 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2173 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2174 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2175 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2176 /* End of double-precision opcodes. */
2177
2178 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2179 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2180 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2181 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2182 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2183 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2184 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2185 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2186 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2187 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2188 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2189 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2190 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2191 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2192 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2193 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2194 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2195 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2196 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2197 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2198 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2199 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2200 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2201 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2202 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2203 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2204 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2205 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2206 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2207 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2208 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2209 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2210 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2211 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2212 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2213 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2214 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2215 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2216 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2217 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2218 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2219 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2220 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2221 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2222 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2223 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2224 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2225 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2226 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2227 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2228 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2229 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2230 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2231 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2232 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2233 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2234 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2235 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2236 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2237 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2238 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2239 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2240 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2241 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2242 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2243 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2244 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2245 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2246 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2247 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2248 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2249 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2250 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2251 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2252 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2253 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2254 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2255 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2256 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2257 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2258 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2259 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2260 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2261 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2262 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2263 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2264 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2265 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2266 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2267 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2268 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2269 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2270 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2271 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2272 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2273 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2274 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2275 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2276 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2277 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2278 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2279 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2280 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2281 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2282 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2283 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2284 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2285 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2286 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2287 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2288 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2289 { "vrldmi", VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } },
2290 { "vrldnm", VX(4, 453), VX_MASK, PPCVEC, { VD, VA, VB } },
2291 { "vrlwmi", VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} },
2292 { "vrlwnm", VX(4, 389), VX_MASK, PPCVEC, { VD, VA, VB } },
2293 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2294 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2295 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2296 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2297 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2298 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2299 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2300 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2301 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2302 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2303 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2304 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2305 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2306 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2307 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2308 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2309 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2310 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2311 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2312 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2313 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2314 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2315 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2316 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2317 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2318 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2319 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2320 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2321 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2322 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2323 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2324 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2325 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2326 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2327 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2328 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2329 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2330 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2331 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2332 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2333 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2334 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2335 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2336 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2337
2338 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2340 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2342 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2343 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2344 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2345 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2346 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2347 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2348 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2349 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2350 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2351
2352 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2353
2354 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2357 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2359 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2362 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2363 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2364
2365 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2366 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2367 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2368 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2369 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2370 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2371 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2372 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2373 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2374 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2375 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2376 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2377 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2378 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2379
2380 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2381 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2382 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2383 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2384 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2385 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2386
2387 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2388 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2389 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2390 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2391 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2392 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2393 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2394 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2395 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2396 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2398 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2400 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2402 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2403 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2404 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2406 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2408 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2409
2410 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2411 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2413 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2415 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2417 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2419 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2421 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2422 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2423 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2424
2425 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2426 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2427 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2428 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2429 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2433 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2434 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2435 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2436 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2437 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2438 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2439 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2440 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2441 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2442 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2443 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2444 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2445 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2446 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2447 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2448
2449 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2450 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2451 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2452 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2453 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2454 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2455 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2456 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2457 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2458 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2459 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2460 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2461 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2462 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2463 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2464 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2465 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2466 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2467 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2468 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2469 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2470 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2471 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2472
2473 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2474 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2489
2490 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2491 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2496 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2497 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2498 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2499 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2500 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2501 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2502
2503 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2504 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2505 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2507 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2508 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2509 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2510 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2511 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2512 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2513 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2514 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2515
2516 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2517 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2518 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2519 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2520 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2521 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2522
2523 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2524 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2525 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2526 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2527 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2528 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2529
2530 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2531 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2532 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2533 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2534 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2535 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2536 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2537 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2538
2539 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2540 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2541
2542 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2543 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2544 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2545 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2546
2547 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2548 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2549 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2550 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2551
2552 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2553 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2554 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2555 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2556 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2557 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2558 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2559 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2560
2561 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2562 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2563 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2564 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2565
2566 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2567 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2568 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2569 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2570
2571 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2572 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2573 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2574 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2575
2576 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2577 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2578 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2579 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2580
2581 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2582
2583 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2584 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2585
2586 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2587 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2588
2589 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2590 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2591
2592 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2593
2594 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2595 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2596 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2597 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2598
2599 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2600 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2601 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2602 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2603
2604 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2605 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2606 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2607 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2608
2609 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2610 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2611 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2612
2613 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2614 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2615 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2616
2617 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2618 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2619 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2620 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2621 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2622 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2623
2624 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2625 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2626 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2627 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2628 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2629
2630 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2631 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2632 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2633 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2634 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2635 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2636 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2637 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2638 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2639 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2640 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2641 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2642 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2643 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2644 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2645 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2646 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2647 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2648 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2649 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2650 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2651 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2652 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2653 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2654 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2655 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2656 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2657 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2658 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2659 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2660 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2661 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2662 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2663 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2664 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2665 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2666 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2667 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2668 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2669 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2670 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2671 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2672 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2673 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2674 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2675 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2676 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2677 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2678 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2679 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2680 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2681 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2682 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2683 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2684 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2685 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2686 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2687 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2688 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2689 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2690 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2691 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2692 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2693 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2694 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2695 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2696 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2697 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2698 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2699 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2700 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2701 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2702 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2703 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2704 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2705 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2706 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2707 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2708 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2709 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2710 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2711 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2712 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2713 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2714 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2715 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2716 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2717 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2718 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2719 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2720 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2721 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2722 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2723 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2724 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2725 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2726 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2727 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2728 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2729 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2730 { "bnl-", BBOCB(16,BOF,CBLT,0,0