nbd: Remove unused nbd_export_get_blockdev()
[qemu.git] / disas / s390.c
1 /* opcodes/s390-dis.c revision 1.12 */
2 /* s390-dis.c -- Disassemble S390 instructions
3 Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
4 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
5
6 This file is part of GDB, GAS and the GNU binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "qemu/osdep.h"
24 #include "disas/dis-asm.h"
25
26 /* include/opcode/s390.h revision 1.9 */
27 /* s390.h -- Header file for S390 opcode table
28 Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
29 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
30
31 This file is part of BFD, the Binary File Descriptor library.
32
33 This program is free software; you can redistribute it and/or modify
34 it under the terms of the GNU General Public License as published by
35 the Free Software Foundation; either version 2 of the License, or
36 (at your option) any later version.
37
38 This program is distributed in the hope that it will be useful,
39 but WITHOUT ANY WARRANTY; without even the implied warranty of
40 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41 GNU General Public License for more details.
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
46 02110-1301, USA. */
47
48 #ifndef S390_H
49 #define S390_H
50
51 /* List of instruction sets variations. */
52
53 enum s390_opcode_mode_val
54 {
55 S390_OPCODE_ESA = 0,
56 S390_OPCODE_ZARCH
57 };
58
59 enum s390_opcode_cpu_val
60 {
61 S390_OPCODE_G5 = 0,
62 S390_OPCODE_G6,
63 S390_OPCODE_Z900,
64 S390_OPCODE_Z990,
65 S390_OPCODE_Z9_109,
66 S390_OPCODE_Z9_EC,
67 S390_OPCODE_Z10
68 };
69
70 /* The opcode table is an array of struct s390_opcode. */
71
72 struct s390_opcode
73 {
74 /* The opcode name. */
75 const char * name;
76
77 /* The opcode itself. Those bits which will be filled in with
78 operands are zeroes. */
79 unsigned char opcode[6];
80
81 /* The opcode mask. This is used by the disassembler. This is a
82 mask containing ones indicating those bits which must match the
83 opcode field, and zeroes indicating those bits which need not
84 match (and are presumably filled in by operands). */
85 unsigned char mask[6];
86
87 /* The opcode length in bytes. */
88 int oplen;
89
90 /* An array of operand codes. Each code is an index into the
91 operand table. They appear in the order which the operands must
92 appear in assembly code, and are terminated by a zero. */
93 unsigned char operands[6];
94
95 /* Bitmask of execution modes this opcode is available for. */
96 unsigned int modes;
97
98 /* First cpu this opcode is available for. */
99 enum s390_opcode_cpu_val min_cpu;
100 };
101
102 /* The table itself is sorted by major opcode number, and is otherwise
103 in the order in which the disassembler should consider
104 instructions. */
105 /* QEMU: Mark these static. */
106 static const struct s390_opcode s390_opcodes[];
107 static const int s390_num_opcodes;
108
109 /* Values defined for the flags field of a struct powerpc_opcode. */
110
111 /* The operands table is an array of struct s390_operand. */
112
113 struct s390_operand
114 {
115 /* The number of bits in the operand. */
116 int bits;
117
118 /* How far the operand is left shifted in the instruction. */
119 int shift;
120
121 /* One bit syntax flags. */
122 unsigned long flags;
123 };
124
125 /* Elements in the table are retrieved by indexing with values from
126 the operands field of the powerpc_opcodes table. */
127
128 static const struct s390_operand s390_operands[];
129
130 /* Values defined for the flags field of a struct s390_operand. */
131
132 /* This operand names a register. The disassembler uses this to print
133 register names with a leading 'r'. */
134 #define S390_OPERAND_GPR 0x1
135
136 /* This operand names a floating point register. The disassembler
137 prints these with a leading 'f'. */
138 #define S390_OPERAND_FPR 0x2
139
140 /* This operand names an access register. The disassembler
141 prints these with a leading 'a'. */
142 #define S390_OPERAND_AR 0x4
143
144 /* This operand names a control register. The disassembler
145 prints these with a leading 'c'. */
146 #define S390_OPERAND_CR 0x8
147
148 /* This operand is a displacement. */
149 #define S390_OPERAND_DISP 0x10
150
151 /* This operand names a base register. */
152 #define S390_OPERAND_BASE 0x20
153
154 /* This operand names an index register, it can be skipped. */
155 #define S390_OPERAND_INDEX 0x40
156
157 /* This operand is a relative branch displacement. The disassembler
158 prints these symbolically if possible. */
159 #define S390_OPERAND_PCREL 0x80
160
161 /* This operand takes signed values. */
162 #define S390_OPERAND_SIGNED 0x100
163
164 /* This operand is a length. */
165 #define S390_OPERAND_LENGTH 0x200
166
167 /* This operand is optional. Only a single operand at the end of
168 the instruction may be optional. */
169 #define S390_OPERAND_OPTIONAL 0x400
170
171 /* QEMU-ADD */
172 /* ??? Not quite the format the assembler takes, but easy to implement
173 without recourse to the table generator. */
174 #define S390_OPERAND_CCODE 0x800
175
176 static const char s390_ccode_name[16][4] = {
177 "n", /* 0000 */
178 "o", /* 0001 */
179 "h", /* 0010 */
180 "nle", /* 0011 */
181 "l", /* 0100 */
182 "nhe", /* 0101 */
183 "lh", /* 0110 */
184 "ne", /* 0111 */
185 "e", /* 1000 */
186 "nlh", /* 1001 */
187 "he", /* 1010 */
188 "nl", /* 1011 */
189 "le", /* 1100 */
190 "nh", /* 1101 */
191 "no", /* 1110 */
192 "a" /* 1111 */
193 };
194 /* QEMU-END */
195
196 #endif /* S390_H */
197
198 static int init_flag = 0;
199 static int opc_index[256];
200
201 /* QEMU: We've disabled the architecture check below. */
202 /* static int current_arch_mask = 0; */
203
204 /* Set up index table for first opcode byte. */
205
206 static void
207 init_disasm (struct disassemble_info *info)
208 {
209 int i;
210
211 memset (opc_index, 0, sizeof (opc_index));
212
213 /* Reverse order, such that each opc_index ends up pointing to the
214 first matching entry instead of the last. */
215 for (i = s390_num_opcodes; i--; )
216 opc_index[s390_opcodes[i].opcode[0]] = i;
217
218 #ifdef QEMU_DISABLE
219 switch (info->mach)
220 {
221 case bfd_mach_s390_31:
222 current_arch_mask = 1 << S390_OPCODE_ESA;
223 break;
224 case bfd_mach_s390_64:
225 current_arch_mask = 1 << S390_OPCODE_ZARCH;
226 break;
227 default:
228 abort ();
229 }
230 #endif /* QEMU_DISABLE */
231
232 init_flag = 1;
233 }
234
235 /* Extracts an operand value from an instruction. */
236
237 static inline unsigned int
238 s390_extract_operand (unsigned char *insn, const struct s390_operand *operand)
239 {
240 unsigned int val;
241 int bits;
242
243 /* Extract fragments of the operand byte for byte. */
244 insn += operand->shift / 8;
245 bits = (operand->shift & 7) + operand->bits;
246 val = 0;
247 do
248 {
249 val <<= 8;
250 val |= (unsigned int) *insn++;
251 bits -= 8;
252 }
253 while (bits > 0);
254 val >>= -bits;
255 val &= ((1U << (operand->bits - 1)) << 1) - 1;
256
257 /* Check for special long displacement case. */
258 if (operand->bits == 20 && operand->shift == 20)
259 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8;
260
261 /* Sign extend value if the operand is signed or pc relative. */
262 if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
263 && (val & (1U << (operand->bits - 1))))
264 val |= (-1U << (operand->bits - 1)) << 1;
265
266 /* Double value if the operand is pc relative. */
267 if (operand->flags & S390_OPERAND_PCREL)
268 val <<= 1;
269
270 /* Length x in an instructions has real length x + 1. */
271 if (operand->flags & S390_OPERAND_LENGTH)
272 val++;
273 return val;
274 }
275
276 /* Print a S390 instruction. */
277
278 int
279 print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
280 {
281 bfd_byte buffer[6];
282 const struct s390_opcode *opcode;
283 const struct s390_opcode *opcode_end;
284 unsigned int value;
285 int status, opsize, bufsize;
286 char separator;
287
288 if (init_flag == 0)
289 init_disasm (info);
290
291 /* The output looks better if we put 6 bytes on a line. */
292 info->bytes_per_line = 6;
293
294 /* Every S390 instruction is max 6 bytes long. */
295 memset (buffer, 0, 6);
296 status = (*info->read_memory_func) (memaddr, buffer, 6, info);
297 if (status != 0)
298 {
299 for (bufsize = 0; bufsize < 6; bufsize++)
300 if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0)
301 break;
302 if (bufsize <= 0)
303 {
304 (*info->memory_error_func) (status, memaddr, info);
305 return -1;
306 }
307 /* Opsize calculation looks strange but it works
308 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes,
309 11xxxxxx -> 6 bytes. */
310 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
311 status = opsize > bufsize;
312 }
313 else
314 {
315 bufsize = 6;
316 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
317 }
318
319 if (status == 0)
320 {
321 /* Find the first match in the opcode table. */
322 opcode_end = s390_opcodes + s390_num_opcodes;
323 for (opcode = s390_opcodes + opc_index[(int) buffer[0]];
324 (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]);
325 opcode++)
326 {
327 const struct s390_operand *operand;
328 const unsigned char *opindex;
329
330 #ifdef QEMU_DISABLE
331 /* Check architecture. */
332 if (!(opcode->modes & current_arch_mask))
333 continue;
334 #endif /* QEMU_DISABLE */
335
336 /* Check signature of the opcode. */
337 if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
338 || (buffer[2] & opcode->mask[2]) != opcode->opcode[2]
339 || (buffer[3] & opcode->mask[3]) != opcode->opcode[3]
340 || (buffer[4] & opcode->mask[4]) != opcode->opcode[4]
341 || (buffer[5] & opcode->mask[5]) != opcode->opcode[5])
342 continue;
343
344 /* The instruction is valid. */
345 /* QEMU-MOD */
346 (*info->fprintf_func) (info->stream, "%s", opcode->name);
347
348 if (s390_operands[opcode->operands[0]].flags & S390_OPERAND_CCODE)
349 separator = 0;
350 else
351 separator = '\t';
352 /* QEMU-END */
353
354 /* Extract the operands. */
355 for (opindex = opcode->operands; *opindex != 0; opindex++)
356 {
357 unsigned int value;
358
359 operand = s390_operands + *opindex;
360 value = s390_extract_operand (buffer, operand);
361
362 if ((operand->flags & S390_OPERAND_INDEX) && value == 0)
363 continue;
364 if ((operand->flags & S390_OPERAND_BASE) &&
365 value == 0 && separator == '(')
366 {
367 separator = ',';
368 continue;
369 }
370
371 if (separator)
372 (*info->fprintf_func) (info->stream, "%c", separator);
373
374 if (operand->flags & S390_OPERAND_GPR)
375 (*info->fprintf_func) (info->stream, "%%r%i", value);
376 else if (operand->flags & S390_OPERAND_FPR)
377 (*info->fprintf_func) (info->stream, "%%f%i", value);
378 else if (operand->flags & S390_OPERAND_AR)
379 (*info->fprintf_func) (info->stream, "%%a%i", value);
380 else if (operand->flags & S390_OPERAND_CR)
381 (*info->fprintf_func) (info->stream, "%%c%i", value);
382 else if (operand->flags & S390_OPERAND_PCREL)
383 (*info->print_address_func) (memaddr + (int) value, info);
384 else if (operand->flags & S390_OPERAND_SIGNED)
385 (*info->fprintf_func) (info->stream, "%i", (int) value);
386 /* QEMU-ADD */
387 else if (operand->flags & S390_OPERAND_CCODE)
388 {
389 (*info->fprintf_func) (info->stream, "%s",
390 s390_ccode_name[(int) value]);
391 separator = '\t';
392 continue;
393 }
394 /* QEMU-END */
395 else
396 (*info->fprintf_func) (info->stream, "%u", value);
397
398 if (operand->flags & S390_OPERAND_DISP)
399 {
400 separator = '(';
401 }
402 else if (operand->flags & S390_OPERAND_BASE)
403 {
404 (*info->fprintf_func) (info->stream, ")");
405 separator = ',';
406 }
407 else
408 separator = ',';
409 }
410
411 /* Found instruction, printed it, return its size. */
412 return opsize;
413 }
414 /* No matching instruction found, fall through to hex print. */
415 }
416
417 if (bufsize >= 4)
418 {
419 value = (unsigned int) buffer[0];
420 value = (value << 8) + (unsigned int) buffer[1];
421 value = (value << 8) + (unsigned int) buffer[2];
422 value = (value << 8) + (unsigned int) buffer[3];
423 (*info->fprintf_func) (info->stream, ".long\t0x%08x", value);
424 return 4;
425 }
426 else if (bufsize >= 2)
427 {
428 value = (unsigned int) buffer[0];
429 value = (value << 8) + (unsigned int) buffer[1];
430 (*info->fprintf_func) (info->stream, ".short\t0x%04x", value);
431 return 2;
432 }
433 else
434 {
435 value = (unsigned int) buffer[0];
436 (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value);
437 return 1;
438 }
439 }
440
441 /* opcodes/s390-opc.c revision 1.16 */
442 /* s390-opc.c -- S390 opcode list
443 Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
444 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
445
446 This file is part of GDB, GAS, and the GNU binutils.
447
448 This program is free software; you can redistribute it and/or modify
449 it under the terms of the GNU General Public License as published by
450 the Free Software Foundation; either version 2 of the License, or
451 (at your option) any later version.
452
453 This program is distributed in the hope that it will be useful,
454 but WITHOUT ANY WARRANTY; without even the implied warranty of
455 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
456 GNU General Public License for more details.
457
458 You should have received a copy of the GNU General Public License
459 along with this program; if not, write to the Free Software
460 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
461 02110-1301, USA. */
462
463 /* This file holds the S390 opcode table. The opcode table
464 includes almost all of the extended instruction mnemonics. This
465 permits the disassembler to use them, and simplifies the assembler
466 logic, at the cost of increasing the table size. The table is
467 strictly constant data, so the compiler should be able to put it in
468 the .text section.
469
470 This file also holds the operand table. All knowledge about
471 inserting operands into instructions and vice-versa is kept in this
472 file. */
473
474 /* The operands table.
475 The fields are bits, shift, insert, extract, flags. */
476
477 static const struct s390_operand s390_operands[] =
478 {
479 #define UNUSED 0
480 { 0, 0, 0 }, /* Indicates the end of the operand list */
481
482 #define R_8 1 /* GPR starting at position 8 */
483 { 4, 8, S390_OPERAND_GPR },
484 #define R_12 2 /* GPR starting at position 12 */
485 { 4, 12, S390_OPERAND_GPR },
486 #define R_16 3 /* GPR starting at position 16 */
487 { 4, 16, S390_OPERAND_GPR },
488 #define R_20 4 /* GPR starting at position 20 */
489 { 4, 20, S390_OPERAND_GPR },
490 #define R_24 5 /* GPR starting at position 24 */
491 { 4, 24, S390_OPERAND_GPR },
492 #define R_28 6 /* GPR starting at position 28 */
493 { 4, 28, S390_OPERAND_GPR },
494 #define R_32 7 /* GPR starting at position 32 */
495 { 4, 32, S390_OPERAND_GPR },
496
497 #define F_8 8 /* FPR starting at position 8 */
498 { 4, 8, S390_OPERAND_FPR },
499 #define F_12 9 /* FPR starting at position 12 */
500 { 4, 12, S390_OPERAND_FPR },
501 #define F_16 10 /* FPR starting at position 16 */
502 { 4, 16, S390_OPERAND_FPR },
503 #define F_20 11 /* FPR starting at position 16 */
504 { 4, 16, S390_OPERAND_FPR },
505 #define F_24 12 /* FPR starting at position 24 */
506 { 4, 24, S390_OPERAND_FPR },
507 #define F_28 13 /* FPR starting at position 28 */
508 { 4, 28, S390_OPERAND_FPR },
509 #define F_32 14 /* FPR starting at position 32 */
510 { 4, 32, S390_OPERAND_FPR },
511
512 #define A_8 15 /* Access reg. starting at position 8 */
513 { 4, 8, S390_OPERAND_AR },
514 #define A_12 16 /* Access reg. starting at position 12 */
515 { 4, 12, S390_OPERAND_AR },
516 #define A_24 17 /* Access reg. starting at position 24 */
517 { 4, 24, S390_OPERAND_AR },
518 #define A_28 18 /* Access reg. starting at position 28 */
519 { 4, 28, S390_OPERAND_AR },
520
521 #define C_8 19 /* Control reg. starting at position 8 */
522 { 4, 8, S390_OPERAND_CR },
523 #define C_12 20 /* Control reg. starting at position 12 */
524 { 4, 12, S390_OPERAND_CR },
525
526 #define B_16 21 /* Base register starting at position 16 */
527 { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
528 #define B_32 22 /* Base register starting at position 32 */
529 { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
530
531 #define X_12 23 /* Index register starting at position 12 */
532 { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
533
534 #define D_20 24 /* Displacement starting at position 20 */
535 { 12, 20, S390_OPERAND_DISP },
536 #define D_36 25 /* Displacement starting at position 36 */
537 { 12, 36, S390_OPERAND_DISP },
538 #define D20_20 26 /* 20 bit displacement starting at 20 */
539 { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
540
541 #define L4_8 27 /* 4 bit length starting at position 8 */
542 { 4, 8, S390_OPERAND_LENGTH },
543 #define L4_12 28 /* 4 bit length starting at position 12 */
544 { 4, 12, S390_OPERAND_LENGTH },
545 #define L8_8 29 /* 8 bit length starting at position 8 */
546 { 8, 8, S390_OPERAND_LENGTH },
547
548 #define U4_8 30 /* 4 bit unsigned value starting at 8 */
549 { 4, 8, 0 },
550 #define U4_12 31 /* 4 bit unsigned value starting at 12 */
551 { 4, 12, 0 },
552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */
553 { 4, 16, 0 },
554 #define U4_20 33 /* 4 bit unsigned value starting at 20 */
555 { 4, 20, 0 },
556 #define U8_8 34 /* 8 bit unsigned value starting at 8 */
557 { 8, 8, 0 },
558 #define U8_16 35 /* 8 bit unsigned value starting at 16 */
559 { 8, 16, 0 },
560 #define I16_16 36 /* 16 bit signed value starting at 16 */
561 { 16, 16, S390_OPERAND_SIGNED },
562 #define U16_16 37 /* 16 bit unsigned value starting at 16 */
563 { 16, 16, 0 },
564 #define J16_16 38 /* PC relative jump offset at 16 */
565 { 16, 16, S390_OPERAND_PCREL },
566 #define J32_16 39 /* PC relative long offset at 16 */
567 { 32, 16, S390_OPERAND_PCREL },
568 #define I32_16 40 /* 32 bit signed value starting at 16 */
569 { 32, 16, S390_OPERAND_SIGNED },
570 #define U32_16 41 /* 32 bit unsigned value starting at 16 */
571 { 32, 16, 0 },
572 #define M_16 42 /* 4 bit optional mask starting at 16 */
573 { 4, 16, S390_OPERAND_OPTIONAL },
574 #define RO_28 43 /* optional GPR starting at position 28 */
575 { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
576
577 /* QEMU-ADD: */
578 #define M4_12 44 /* 4-bit condition-code starting at 12 */
579 { 4, 12, S390_OPERAND_CCODE },
580 #define M4_32 45 /* 4-bit condition-code starting at 32 */
581 { 4, 32, S390_OPERAND_CCODE },
582 #define I8_32 46 /* 8 bit signed value starting at 32 */
583 { 8, 32, S390_OPERAND_SIGNED },
584 #define U8_24 47 /* 8 bit unsigned value starting at 24 */
585 { 8, 24, 0 },
586 #define U8_32 48 /* 8 bit unsigned value starting at 32 */
587 { 8, 32, 0 },
588 #define I16_32 49
589 { 16, 32, S390_OPERAND_SIGNED },
590 #define M4_16 50 /* 4-bit condition-code starting at 12 */
591 { 4, 16, S390_OPERAND_CCODE },
592 #define I8_16 51
593 { 8, 16, S390_OPERAND_SIGNED },
594 /* QEMU-END */
595 };
596
597
598 /* Macros used to form opcodes. */
599
600 /* 8/16/48 bit opcodes. */
601 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
602 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
603 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
604 (x >> 16) & 255, (x >> 8) & 255, x & 255}
605
606 /* The new format of the INSTR_x_y and MASK_x_y defines is based
607 on the following rules:
608 1) the middle part of the definition (x in INSTR_x_y) is the official
609 names of the instruction format that you can find in the principals
610 of operation.
611 2) the last part of the definition (y in INSTR_x_y) gives you an idea
612 which operands the binary representation of the instruction has.
613 The meanings of the letters in y are:
614 a - access register
615 c - control register
616 d - displacement, 12 bit
617 f - floating pointer register
618 i - signed integer, 4, 8, 16 or 32 bit
619 l - length, 4 or 8 bit
620 p - pc relative
621 r - general purpose register
622 u - unsigned integer, 4, 8, 16 or 32 bit
623 m - mode field, 4 bit
624 0 - operand skipped.
625 The order of the letters reflects the layout of the format in
626 storage and not the order of the parameters of the instructions.
627 The use of the letters is not a 100% match with the PoP but it is
628 quite close.
629
630 For example the instruction "mvo" is defined in the PoP as follows:
631
632 MVO D1(L1,B1),D2(L2,B2) [SS]
633
634 --------------------------------------
635 | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
636 --------------------------------------
637 0 8 12 16 20 32 36
638
639 The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
640
641 #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
643 #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
645 #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
648 #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
649 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
650 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
651 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
652 #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
653 #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
654 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
655 #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
656 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
657 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
658 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
659 #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
660 #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
661 #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
662 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
663 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
664 /* Actually efpc and sfpc do not take an optional operand.
665 This is just a workaround for existing code e.g. glibc. */
666 #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
667 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
668 /* QEMU-MOD */
669 #define INSTR_RRF_F0FF2 4, { F_24,F_28,F_16,0,0,0 } /* e.g. cpsdr */
670 /* QEMU-END */
671 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
672 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
673 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
674 #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
678 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
679 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
680 #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */
681 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
682 #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
683 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
684 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
685 #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
686 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
687 #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */
688 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
689 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
690 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
691 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */
692 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
693 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
694 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */
695 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */
696 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */
697 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
698 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
699 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
700 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
701 #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
702 #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
703 #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
704 #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
705 #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
706 #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */
707 #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
708 #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
709 #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
710 #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
711 #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
712 #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
713 #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
714 #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
715 #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
716 #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
717 #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
718 #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
719 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
720 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
721 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
722 #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
723 #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
724 #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
725
726 #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
727 #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
728 #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
729 #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
730 #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
731 #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
732 #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
733 #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
734 #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
735 #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
736 #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
737 #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
738 #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
739 #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
740 #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
741 #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
742 #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
743 #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
744 #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
745 #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
746 #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
747 #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
748 #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
749 #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
750 #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
751 #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
752 #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
753 #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
754 #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
755 #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
756 #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
757 #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
758 #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
759 #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
760 #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
761 #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
762 #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
763 #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
764 #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
765 #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
766 #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
767 #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
768 #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
769 #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
770 #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
771 #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
772 #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
773 #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
774 #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
775 #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
776 #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
777 #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
778 #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
779 #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
780 #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
781 #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
782 #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
783 #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
784 #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
785 #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
786 #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
787 #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
788 #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
789 #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
790 #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
791 #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
792 #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
793 #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
794 #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
795 #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
796 #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
797 #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
798 #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
799 #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
800 #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
801 #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
802 #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
803 #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
804 #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
805 #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
806
807 /* QEMU-ADD: */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
809 #define MASK_RIE_MRRP { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
810
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
812 #define MASK_RIE_MRIP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
813
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
815 #define MASK_RIE_RRIII { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
817 #define MASK_RIE_MRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
818 #define INSTR_RIE_MRU 6, { M4_32, R_8, U16_16, 0, 0, 0 } /* e.g. clfit */
819 #define MASK_RIE_MRU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
821 #define MASK_RIE_RRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
822
823 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 }
824 #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
825
826 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 }
827 #define MASK_SIL_DRI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
828
829 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 }
830 #define MASK_SRY_MRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
831
832 #define INSTR_RRF_MRR 6, { M4_16, R_24, R_28, 0, 0, 0 }
833 #define MASK_RRF_MRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
834
835 #define INSTR_SIY_DRI 6, { D20_20, B_16, I8_16, 0, 0, 0 }
836 #define MASK_SIY_DRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
837 /* QEMU-END */
838
839 /* include "s390-opc.tab" generated from opcodes/s390-opc.txt rev 1.17 */
840 /* The opcode table. This file was generated by s390-mkopc.
841
842 The format of the opcode table is:
843
844 NAME OPCODE MASK OPERANDS
845
846 Name is the name of the instruction.
847 OPCODE is the instruction opcode.
848 MASK is the opcode mask; this is used to tell the disassembler
849 which bits in the actual opcode must match OPCODE.
850 OPERANDS is the list of operands.
851
852 The disassembler reads the table in order and prints the first
853 instruction which matches. */
854
855 static const struct s390_opcode s390_opcodes[] =
856 {
857 { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
858 { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
859 { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
860 { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
861 { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
862 { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
863 { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
864 { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
865 { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
866 { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0},
867 { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2},
868 { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0},
869 { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
870 { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
871 { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
872 { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
873 { "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
874 { "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
875 { "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
876 { "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
877 { "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
878 { "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
879 { "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
880 { "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
881 { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
882 { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
883 { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
884 { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
885 { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
886 { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
887 { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
888 { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
889 { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
890 { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
891 { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
892 { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
893 { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
894 { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
895 { "lxe", OP48(0xed0000000026LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
896 { "lxd", OP48(0xed0000000025LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
897 { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
898 { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
899 { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
900 { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
901 { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
902 { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
903 { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
904 { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
905 { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
906 { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
907 { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
908 { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
909 { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
910 { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
911 { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
912 { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
913 { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
914 { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
915 { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
916 { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
917 { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
918 { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
919 { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
920 { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
921 { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
922 { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
923 { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
924 { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
925 { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
926 /* QEMU-ADD: */
927 { "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
928 { "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
929 { "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
930 { "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
931 { "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
932 { "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
933 { "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
934 { "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
935 { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
936 { "risbhg", OP48(0xec000000005dLL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
937 { "risblg", OP48(0xec0000000051LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
938 { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
939 { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
940 { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
941 { "cit", OP48(0xec0000000072LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
942 { "cgit", OP48(0xec0000000070LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
943 { "clfit", OP48(0xec0000000073LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
944 { "clgit", OP48(0xec0000000071LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
945 { "ahik", OP48(0xec00000000d8LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
946 { "aghik", OP48(0xec00000000d9LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
947 { "alhsik", OP48(0xec00000000daLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
948 { "alghsik", OP48(0xec00000000dbLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
949 /* QEMU-END */
950 { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0},
951 { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
952 { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
953 { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
954 { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
955 { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
956 { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
957 { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
958 { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
959 { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0},
960 { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
961 { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
962 { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
963 { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
964 { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
965 { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
966 { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
967 { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
968 { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
969 { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
970 { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
971 { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
972 { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
973 { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
974 { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
975 { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
976 { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
977 { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
978 { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
979 { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
980 { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
981 { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
982 { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
983 { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
984 { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
985 { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
986 { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
987 { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
988 { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
989 { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
990 { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
991 { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
992 { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
993 { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2},
994 { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
995 { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
996 { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
997 { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
998 { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
999 { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1000 { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1001 { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1002 { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1003 { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1004 { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1005 { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1006 { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1007 { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1008 { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1009 /* QEMU-ADD: */
1010 { "loc", OP48(0xeb00000000f2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1011 { "locg", OP48(0xeb00000000e2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1012 { "stoc", OP48(0xeb00000000f3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1013 { "stocg", OP48(0xeb00000000e3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1014 { "srak", OP48(0xeb00000000dcLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1015 { "slak", OP48(0xeb00000000ddLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1016 { "srlk", OP48(0xeb00000000deLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1017 { "sllk", OP48(0xeb00000000dfLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1018 { "asi", OP48(0xeb000000006aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1019 { "alsi", OP48(0xeb000000006eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1020 { "agsi", OP48(0xeb000000007aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1021 { "algsi", OP48(0xeb000000007eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1022 /* QEMU-END */
1023 { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1024 { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0},
1025 { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1026 { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1027 { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1028 { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1029 { "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2},
1030 { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1031 /* QEMU-ADD: */
1032 { "mvhhi", OP16(0xe544LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1033 { "mvghi", OP16(0xe548LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1034 { "mvhi", OP16(0xe54cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1035 { "chhsi", OP16(0xe554LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1036 { "clhhsi", OP16(0xe555LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1037 { "cghsi", OP16(0xe558LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1038 { "clghsi", OP16(0xe559LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1039 { "chsi", OP16(0xe55cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1040 { "clfhsi", OP16(0xe55dLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1041 /* QEMU-END */
1042 { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1043 { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1044 { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1045 { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1046 { "dl", OP48(0xe30000000097LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1047 { "dl", OP48(0xe30000000097LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1048 { "ml", OP48(0xe30000000096LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1049 { "ml", OP48(0xe30000000096LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1050 { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1051 { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1052 { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1053 { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1054 { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1055 { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1056 { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1057 { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1058 { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1059 { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1060 { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1061 { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1062 { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1063 { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1064 { "dlg", OP48(0xe30000000087LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1065 { "dlg", OP48(0xe30000000087LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1066 { "mlg", OP48(0xe30000000086LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1067 { "mlg", OP48(0xe30000000086LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1068 { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1069 { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1070 { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1071 { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1072 { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1073 { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1074 { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1075 { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1076 { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1077 { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1078 { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1079 { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1080 { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1081 { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1082 { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1083 { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1084 { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1085 { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1086 { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1087 { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1088 { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1089 { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1090 { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1091 { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1092 { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1093 { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1094 { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1095 { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1096 { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1097 { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1098 { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1099 { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1100 { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1101 { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1102 { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1103 { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1104 { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1105 { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1106 { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1107 { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1108 { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1109 { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1110 { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1111 { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1112 { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1113 { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1114 { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1115 { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1116 { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1117 { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1118 { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1119 { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1120 { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1121 { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1122 { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1123 { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1124 { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1125 { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1126 { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1127 { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1128 { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1129 { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1130 { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1131 { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1132 { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1133 { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1134 { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1135 { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1136 { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1137 { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1138 { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1139 { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1140 { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1141 { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1142 { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1143 { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1144 { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1145 { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1146 { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1147 { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1148 { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1149 { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1150 { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1151 { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1152 { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1153 { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1154 { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1155 { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1156 { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1157 { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1158 { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1159 { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1160 { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1161 { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1162 { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1163 { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1164 { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1165 /* QEMU-ADD: */
1166 { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 3, 6},
1167 /* QEMU-END */
1168 { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1169 { "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1170 { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1171 { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1172 { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1173 { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1174 { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1175 { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1176 { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1177 { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1178 { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1179 { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1180 { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1181 { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1182 { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1183 { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1184 { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
1185 { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
1186 { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4},
1187 /* QEMU-ADD: */
1188 { "exrl", OP16(0xc600ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1189 { "pfdrl", OP16(0xc602ll), MASK_RIL_UP, INSTR_RIL_UP, 3, 6},
1190 { "cghrl", OP16(0xc604ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1191 { "chrl", OP16(0xc605ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1192 { "clghrl", OP16(0xc606ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1193 { "clhrl", OP16(0xc607ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1194 { "cgrl", OP16(0xc608ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1195 { "clgrl", OP16(0xc60all), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1196 { "cgfrl", OP16(0xc60cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1197 { "crl", OP16(0xc60dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1198 { "clgfrl", OP16(0xc60ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1199 { "clrl", OP16(0xc60fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1200
1201 { "llhrl", OP16(0xc400ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1202 { "lghrl", OP16(0xc404ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1203 { "lhrl", OP16(0xc405ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1204 { "llghrl", OP16(0xc406ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1205 { "sthrl", OP16(0xc407ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1206 { "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1207 { "stgrl", OP16(0xc40bll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1208 { "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1209 { "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1210 { "llgfrl", OP16(0xc40ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1211 { "strl", OP16(0xc40fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1212 /* QEMU-END */
1213 { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1214 { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1215 { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1216 { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1217 { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1218 { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1219 { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1220 { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1221 { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1222 { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1223 /* QEMU-ADD: */
1224 { "msfi", OP16(0xc201ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
1225 { "msgfi", OP16(0xc200ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
1226 /* QEMU-END */
1227 { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1228 { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1229 { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1230 { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1231 { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1232 { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1233 { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1234 { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1235 { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1236 { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1237 { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1238 { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1239 { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1240 { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1241 { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1242 { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1243 { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1244 { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1245 { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1246 { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1247 { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1248 { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1249 { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1250 { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1251 { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1252 { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1253 { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1254 { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1255 { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1256 { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1257 { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1258 { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
1259 { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2},
1260 { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1261 { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
1262 { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1263 { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1264 { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1265 { "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1266 { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1267 { "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1268 { "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1269 { "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1270 { "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1271 { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4},
1272 { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2},
1273 { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1274 { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1275 { "dlr", OP16(0xb997LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1276 { "mlr", OP16(0xb996LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1277 { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1278 { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1279 { "troo", OP16(0xb993LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1280 { "troo", OP16(0xb993LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1281 { "trot", OP16(0xb992LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1282 { "trot", OP16(0xb992LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1283 { "trto", OP16(0xb991LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1284 { "trto", OP16(0xb991LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1285 { "trtt", OP16(0xb990LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1286 { "trtt", OP16(0xb990LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1287 { "idte", OP16(0xb98eLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 3},
1288 { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1289 { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3},
1290 { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1291 { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1292 { "dlgr", OP16(0xb987LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1293 { "mlgr", OP16(0xb986LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1294 { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1295 { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1296 { "flogr", OP16(0xb983LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1297 { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1298 { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1299 { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1300 { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1301 { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1302 { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1303 { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1304 { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1305 { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1306 { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1307 { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1308 { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1309 { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1310 { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1311 { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1312 { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1313 { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1314 { "dsgfr", OP16(0xb91dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1315 { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1316 { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1317 { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1318 { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1319 { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1320 { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1321 { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1322 { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1323 { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1324 { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1325 { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1326 { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1327 { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1328 { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1329 { "dsgr", OP16(0xb90dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1330 { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1331 { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1332 { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1333 { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1334 { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1335 { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1336 { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1337 { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1338 { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1339 { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1340 { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1341 { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1342 { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1343 /* QEMU-ADD: */
1344 { "crt", OP16(0xb972LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1345 { "cgrt", OP16(0xb960LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1346 { "clrt", OP16(0xb973LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1347 { "clgrt", OP16(0xb961LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1348 { "locr", OP16(0xb9f2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
1349 { "locgr", OP16(0xb9e2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
1350 { "popcnt", OP16(0xb9e1LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 6},
1351 { "ngrk", OP16(0xb9e4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1352 { "ogrk", OP16(0xb9e6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1353 { "xgrk", OP16(0xb9e7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1354 { "agrk", OP16(0xb9e8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1355 { "sgrk", OP16(0xb9e9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1356 { "algrk", OP16(0xb9eaLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1357 { "slgrk", OP16(0xb9ebLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1358 { "nrk", OP16(0xb9f4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1359 { "ork", OP16(0xb9f6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1360 { "xrk", OP16(0xb9f7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1361 { "ark", OP16(0xb9f8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1362 { "srk", OP16(0xb9f9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1363 { "alrk", OP16(0xb9faLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1364 { "slrk", OP16(0xb9fbLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1365 /* QEMU-END */
1366 { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
1367 { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
1368 { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1369 { "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
1370 { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1371 { "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1372 { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1373 { "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1374 { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1375 { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1376 { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
1377 { "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1378 { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1379 { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1380 { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1381 { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1382 { "esxtr", OP16(0xb3efLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1383 { "eextr", OP16(0xb3edLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1384 { "cxtr", OP16(0xb3ecLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1385 { "csxtr", OP16(0xb3ebLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1386 { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1387 { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
1388 { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1389 { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1390 { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1391 { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1392 { "csdtr", OP16(0xb3e3LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1393 { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1394 { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
1395 { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1396 { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1397 { "ltxtr", OP16(0xb3deLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1398 { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1399 { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
1400 { "sxtr", OP16(0xb3dbLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1401 { "axtr", OP16(0xb3daLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1402 { "dxtr", OP16(0xb3d9LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1403 { "mxtr", OP16(0xb3d8LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1404 { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1405 { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1406 { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1407 { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
1408 { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1409 { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1410 { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1411 { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1412 { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1413 { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1414 { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1415 { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1416 { "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1417 { "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1418 { "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1419 { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1420 { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1421 { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1422 { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1423 { "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1424 { "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1425 { "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1426 { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1427 { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1428 { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1429 { "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1430 { "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1431 { "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1432 { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1433 { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1434 { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1435 { "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1436 { "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1437 { "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1438 { "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
1439 { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5},
1440 { "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
1441 { "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1442 { "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1443 { "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1444 { "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1445 { "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1446 { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1447 { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5},
1448 { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1449 { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1450 { "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1451 { "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1452 { "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1453 { "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1454 { "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1455 { "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1456 { "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1457 { "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1458 { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1459 { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
1460 { "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1461 { "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1462 { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1463 { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
1464 { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1465 { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1466 { "dxbr", OP16(0xb34dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1467 { "mxbr", OP16(0xb34cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1468 { "sxbr", OP16(0xb34bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1469 { "axbr", OP16(0xb34aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1470 { "cxbr", OP16(0xb349LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1471 { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1472 { "fixbr", OP16(0xb347LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1473 { "lexbr", OP16(0xb346LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1474 { "ldxbr", OP16(0xb345LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1475 { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1476 { "lcxbr", OP16(0xb343LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1477 { "ltxbr", OP16(0xb342LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1478 { "lnxbr", OP16(0xb341LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1479 { "lpxbr", OP16(0xb340LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1480 { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1481 { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1482 { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1483 { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1484 { "myr", OP16(0xb33bLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1485 { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1486 { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1487 { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1488 { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1489 { "sqxr", OP16(0xb336LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1490 { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1491 { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1492 { "lxer", OP16(0xb326LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1493 { "lxdr", OP16(0xb325LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1494 { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1495 { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1496 { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1497 { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1498 { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1499 { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1500 { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1501 { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1502 { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1503 { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1504 { "sqxbr", OP16(0xb316LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1505 { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1506 { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1507 { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1508 { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1509 { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1510 { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1511 { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1512 { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1513 { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1514 { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1515 { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1516 { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1517 { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1518 { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1519 { "mxdbr", OP16(0xb307LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1520 { "lxebr", OP16(0xb306LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1521 { "lxdbr", OP16(0xb305LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1522 { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1523 { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1524 { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1525 { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1526 { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1527 /* QEMU-ADD: */
1528 { "clfebr", OP16(0xb39cLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1529 { "clfdbr", OP16(0xb39dLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1530 { "clfxbr", OP16(0xb39eLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1531 { "clgebr", OP16(0xb3acLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1532 { "clgdbr", OP16(0xb3adLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1533 { "clgxbr", OP16(0xb3aeLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1534 { "celfbr", OP16(0xb390LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1535 { "cdlfbr", OP16(0xb391LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1536 { "cxlfbr", OP16(0xb392LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1537 { "celgbr", OP16(0xb3a0LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1538 { "cdlgbr", OP16(0xb3a1LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1539 { "cxlgbr", OP16(0xb3a2LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1540 /* QEMU-END */
1541 { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1542 { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5},
1543 { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5},
1544 { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2},
1545 { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2},
1546 { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4},
1547 { "cu12", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1548 { "cutfu", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1549 { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1550 { "cu21", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1551 { "cuutf", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1552 { "cuutf", OP16(0xb2a6LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1553 { "tre", OP16(0xb2a5LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1554 { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1555 { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1556 { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1557 { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1558 { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4},
1559 { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1560 { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1561 { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1562 { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0},
1563 { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1564 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1565 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1566 { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1567 { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1568 { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1569 { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1570 { "cuse", OP16(0xb257LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1571 { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1572 { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1573 { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1574 { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1575 { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0},
1576 { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
1577 { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0},
1578 { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
1579 { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1580 { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1581 { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1582 { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0},
1583 { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1584 { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1585 { "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1586 { "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1587 { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1588 { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1589 { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0},
1590 { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0},
1591 { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1592 { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1593 { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0},
1594 { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0},
1595 { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1596 { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1597 { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1598 { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1599 { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1600 { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0},
1601 { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0},
1602 { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1603 { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1604 { "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1605 { "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0},
1606 { "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1607 { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1608 { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1609 { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1610 { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1611 { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1612 { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1613 { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1614 { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1615 { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1616 { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1617 { "ipte", OP16(0xb221LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1618 { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1619 { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1620 { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1621 { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1622 { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1623 { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1624 { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1625 { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0},
1626 { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0},
1627 { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1628 { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1629 { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1630 { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1631 { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1632 { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1633 { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1634 { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1635 { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1636 { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1637 { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1638 { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1639 { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1640 { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1641 { "mvcle", OP8(0xa8LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1642 { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1643 { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1644 { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1645 { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1646 { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1647 { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1648 { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1649 { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1650 { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1651 { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1652 { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1653 { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1654 { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1655 { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1656 { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1657 { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1658 { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1659 { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1660 { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1661 { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1662 { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1663 { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1664 { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1665 { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1666 { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1667 { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1668 { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1669 { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1670 { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1671 { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2},
1672 { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
1673 { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
1674 { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0},
1675 { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1676 { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1677 { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1678 { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1679 { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1680 { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1681 { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1682 { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1683 { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1684 { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1685 { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1686 { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1687 { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1688 { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1689 { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1690 { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1691 { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1692 { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1693 { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1694 { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1695 { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1696 { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1697 { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
1698 { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
1699 { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1700 { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1701 { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1702 { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1703 { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1704 { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1705 { "ts", OP8(0x93LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1706 { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1707 { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1708 { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1709 { "slda", OP8(0x8fLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1710 { "srda", OP8(0x8eLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1711 { "sldl", OP8(0x8dLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1712 { "srdl", OP8(0x8cLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1713 { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1714 { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1715 { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1716 { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1717 { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1718 { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1719 { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
1720 { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
1721 { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1722 { "lpsw", OP8(0x82LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1723 { "ssm", OP8(0x80LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1724 { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1725 { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1726 { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1727 { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1728 { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1729 { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1730 { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1731 { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1732 { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1733 { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1734 { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1735 { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1736 { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1737 { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1738 { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1739 { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1740 { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1741 { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1742 { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1743 { "mxd", OP8(0x67LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1744 { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1745 { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1746 { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1747 { "d", OP8(0x5dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1748 { "m", OP8(0x5cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1749 { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1750 { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1751 { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1752 { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1753 { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1754 { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1755 { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1756 { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1757 { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1758 { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1759 { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1760 { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1761 { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1762 { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1763 { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1764 { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1765 { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1766 { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1767 { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1768 { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1769 { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1770 { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1771 { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1772 { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1773 { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1774 { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1775 { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1776 { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1777 { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1778 { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1779 { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1780 { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1781 { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1782 { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1783 { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1784 { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1785 { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1786 { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1787 { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1788 { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0},
1789 { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1790 { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1791 { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1792 { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1793 { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1794 { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1795 { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1796 { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1797 { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1798 { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1799 { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1800 { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1801 { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1802 { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1803 { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1804 { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1805 { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1806 { "sxr", OP8(0x37LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1807 { "axr", OP8(0x36LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1808 { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1809 { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1810 { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1811 { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1812 { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1813 { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1814 { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1815 { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1816 { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1817 { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1818 { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1819 { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1820 { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1821 { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1822 { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1823 { "mxdr", OP8(0x27LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1824 { "mxr", OP8(0x26LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1825 { "lrdr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1826 { "ldxr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1827 { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1828 { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1829 { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1830 { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1831 { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1832 { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1833 { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1834 { "dr", OP8(0x1dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1835 { "mr", OP8(0x1cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1836 { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1837 { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1838 { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1839 { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1840 { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1841 { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1842 { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1843 { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1844 { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1845 { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1846 { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1847 { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1848 { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1849 { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1850 { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1851 { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1852 { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1853 { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0},
1854 { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1855 { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1856 { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1857 { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1858 { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1859 { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1860 { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1861 { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1862 { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1863 { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1864 { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1865 { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1866 { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1867 { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1868 { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1869 { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1870 { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1871 { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1872 { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1873 { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1874 { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1875 { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0},
1876 { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1877 { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1878 { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1879 { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0},
1880 { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0},
1881 { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2},
1882 { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2},
1883 { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2},
1884 { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2},
1885 { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5},
1886 { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0},
1887 { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0},
1888 { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0},
1889 };
1890
1891 static const int s390_num_opcodes =
1892 sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);