m25p80: don't let rogue SPI controllers cause buffer overruns
[qemu.git] / dma-helpers.c
1 /*
2 * DMA helper functions
3 *
4 * Copyright (c) 2009 Red Hat
5 *
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
9
10 #include "qemu/osdep.h"
11 #include "sysemu/block-backend.h"
12 #include "sysemu/dma.h"
13 #include "trace.h"
14 #include "qemu/thread.h"
15 #include "qemu/main-loop.h"
16
17 /* #define DEBUG_IOMMU */
18
19 int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
20 {
21 dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
22
23 #define FILLBUF_SIZE 512
24 uint8_t fillbuf[FILLBUF_SIZE];
25 int l;
26 bool error = false;
27
28 memset(fillbuf, c, FILLBUF_SIZE);
29 while (len > 0) {
30 l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
31 error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
32 fillbuf, l, true);
33 len -= l;
34 addr += l;
35 }
36
37 return error;
38 }
39
40 void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
41 AddressSpace *as)
42 {
43 qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
44 qsg->nsg = 0;
45 qsg->nalloc = alloc_hint;
46 qsg->size = 0;
47 qsg->as = as;
48 qsg->dev = dev;
49 object_ref(OBJECT(dev));
50 }
51
52 void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
53 {
54 if (qsg->nsg == qsg->nalloc) {
55 qsg->nalloc = 2 * qsg->nalloc + 1;
56 qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
57 }
58 qsg->sg[qsg->nsg].base = base;
59 qsg->sg[qsg->nsg].len = len;
60 qsg->size += len;
61 ++qsg->nsg;
62 }
63
64 void qemu_sglist_destroy(QEMUSGList *qsg)
65 {
66 object_unref(OBJECT(qsg->dev));
67 g_free(qsg->sg);
68 memset(qsg, 0, sizeof(*qsg));
69 }
70
71 typedef struct {
72 BlockAIOCB common;
73 AioContext *ctx;
74 BlockAIOCB *acb;
75 QEMUSGList *sg;
76 uint32_t align;
77 uint64_t offset;
78 DMADirection dir;
79 int sg_cur_index;
80 dma_addr_t sg_cur_byte;
81 QEMUIOVector iov;
82 QEMUBH *bh;
83 DMAIOFunc *io_func;
84 void *io_func_opaque;
85 } DMAAIOCB;
86
87 static void dma_blk_cb(void *opaque, int ret);
88
89 static void reschedule_dma(void *opaque)
90 {
91 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
92
93 qemu_bh_delete(dbs->bh);
94 dbs->bh = NULL;
95 dma_blk_cb(dbs, 0);
96 }
97
98 static void dma_blk_unmap(DMAAIOCB *dbs)
99 {
100 int i;
101
102 for (i = 0; i < dbs->iov.niov; ++i) {
103 dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
104 dbs->iov.iov[i].iov_len, dbs->dir,
105 dbs->iov.iov[i].iov_len);
106 }
107 qemu_iovec_reset(&dbs->iov);
108 }
109
110 static void dma_complete(DMAAIOCB *dbs, int ret)
111 {
112 trace_dma_complete(dbs, ret, dbs->common.cb);
113
114 dma_blk_unmap(dbs);
115 if (dbs->common.cb) {
116 dbs->common.cb(dbs->common.opaque, ret);
117 }
118 qemu_iovec_destroy(&dbs->iov);
119 if (dbs->bh) {
120 qemu_bh_delete(dbs->bh);
121 dbs->bh = NULL;
122 }
123 qemu_aio_unref(dbs);
124 }
125
126 static void dma_blk_cb(void *opaque, int ret)
127 {
128 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
129 dma_addr_t cur_addr, cur_len;
130 void *mem;
131
132 trace_dma_blk_cb(dbs, ret);
133
134 dbs->acb = NULL;
135 dbs->offset += dbs->iov.size;
136
137 if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
138 dma_complete(dbs, ret);
139 return;
140 }
141 dma_blk_unmap(dbs);
142
143 while (dbs->sg_cur_index < dbs->sg->nsg) {
144 cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
145 cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
146 mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir);
147 if (!mem)
148 break;
149 qemu_iovec_add(&dbs->iov, mem, cur_len);
150 dbs->sg_cur_byte += cur_len;
151 if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
152 dbs->sg_cur_byte = 0;
153 ++dbs->sg_cur_index;
154 }
155 }
156
157 if (dbs->iov.size == 0) {
158 trace_dma_map_wait(dbs);
159 dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs);
160 cpu_register_map_client(dbs->bh);
161 return;
162 }
163
164 if (!QEMU_IS_ALIGNED(dbs->iov.size, dbs->align)) {
165 qemu_iovec_discard_back(&dbs->iov,
166 QEMU_ALIGN_DOWN(dbs->iov.size, dbs->align));
167 }
168
169 dbs->acb = dbs->io_func(dbs->offset, &dbs->iov,
170 dma_blk_cb, dbs, dbs->io_func_opaque);
171 assert(dbs->acb);
172 }
173
174 static void dma_aio_cancel(BlockAIOCB *acb)
175 {
176 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
177
178 trace_dma_aio_cancel(dbs);
179
180 if (dbs->acb) {
181 blk_aio_cancel_async(dbs->acb);
182 }
183 if (dbs->bh) {
184 cpu_unregister_map_client(dbs->bh);
185 qemu_bh_delete(dbs->bh);
186 dbs->bh = NULL;
187 }
188 }
189
190 static AioContext *dma_get_aio_context(BlockAIOCB *acb)
191 {
192 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
193
194 return dbs->ctx;
195 }
196
197 static const AIOCBInfo dma_aiocb_info = {
198 .aiocb_size = sizeof(DMAAIOCB),
199 .cancel_async = dma_aio_cancel,
200 .get_aio_context = dma_get_aio_context,
201 };
202
203 BlockAIOCB *dma_blk_io(AioContext *ctx,
204 QEMUSGList *sg, uint64_t offset, uint32_t align,
205 DMAIOFunc *io_func, void *io_func_opaque,
206 BlockCompletionFunc *cb,
207 void *opaque, DMADirection dir)
208 {
209 DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque);
210
211 trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE));
212
213 dbs->acb = NULL;
214 dbs->sg = sg;
215 dbs->ctx = ctx;
216 dbs->offset = offset;
217 dbs->align = align;
218 dbs->sg_cur_index = 0;
219 dbs->sg_cur_byte = 0;
220 dbs->dir = dir;
221 dbs->io_func = io_func;
222 dbs->io_func_opaque = io_func_opaque;
223 dbs->bh = NULL;
224 qemu_iovec_init(&dbs->iov, sg->nsg);
225 dma_blk_cb(dbs, 0);
226 return &dbs->common;
227 }
228
229
230 static
231 BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov,
232 BlockCompletionFunc *cb, void *cb_opaque,
233 void *opaque)
234 {
235 BlockBackend *blk = opaque;
236 return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque);
237 }
238
239 BlockAIOCB *dma_blk_read(BlockBackend *blk,
240 QEMUSGList *sg, uint64_t offset, uint32_t align,
241 void (*cb)(void *opaque, int ret), void *opaque)
242 {
243 return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
244 dma_blk_read_io_func, blk, cb, opaque,
245 DMA_DIRECTION_FROM_DEVICE);
246 }
247
248 static
249 BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov,
250 BlockCompletionFunc *cb, void *cb_opaque,
251 void *opaque)
252 {
253 BlockBackend *blk = opaque;
254 return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque);
255 }
256
257 BlockAIOCB *dma_blk_write(BlockBackend *blk,
258 QEMUSGList *sg, uint64_t offset, uint32_t align,
259 void (*cb)(void *opaque, int ret), void *opaque)
260 {
261 return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
262 dma_blk_write_io_func, blk, cb, opaque,
263 DMA_DIRECTION_TO_DEVICE);
264 }
265
266
267 static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
268 DMADirection dir)
269 {
270 uint64_t resid;
271 int sg_cur_index;
272
273 resid = sg->size;
274 sg_cur_index = 0;
275 len = MIN(len, resid);
276 while (len > 0) {
277 ScatterGatherEntry entry = sg->sg[sg_cur_index++];
278 int32_t xfer = MIN(len, entry.len);
279 dma_memory_rw(sg->as, entry.base, ptr, xfer, dir);
280 ptr += xfer;
281 len -= xfer;
282 resid -= xfer;
283 }
284
285 return resid;
286 }
287
288 uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
289 {
290 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
291 }
292
293 uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
294 {
295 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
296 }
297
298 void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
299 QEMUSGList *sg, enum BlockAcctType type)
300 {
301 block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
302 }