vfio/pci: Add IGD documentation
[qemu.git] / dma-helpers.c
1 /*
2 * DMA helper functions
3 *
4 * Copyright (c) 2009 Red Hat
5 *
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
9
10 #include "qemu/osdep.h"
11 #include "sysemu/block-backend.h"
12 #include "sysemu/dma.h"
13 #include "trace.h"
14 #include "qemu/thread.h"
15 #include "qemu/main-loop.h"
16
17 /* #define DEBUG_IOMMU */
18
19 int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
20 {
21 dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
22
23 #define FILLBUF_SIZE 512
24 uint8_t fillbuf[FILLBUF_SIZE];
25 int l;
26 bool error = false;
27
28 memset(fillbuf, c, FILLBUF_SIZE);
29 while (len > 0) {
30 l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
31 error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
32 fillbuf, l, true);
33 len -= l;
34 addr += l;
35 }
36
37 return error;
38 }
39
40 void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
41 AddressSpace *as)
42 {
43 qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
44 qsg->nsg = 0;
45 qsg->nalloc = alloc_hint;
46 qsg->size = 0;
47 qsg->as = as;
48 qsg->dev = dev;
49 object_ref(OBJECT(dev));
50 }
51
52 void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
53 {
54 if (qsg->nsg == qsg->nalloc) {
55 qsg->nalloc = 2 * qsg->nalloc + 1;
56 qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
57 }
58 qsg->sg[qsg->nsg].base = base;
59 qsg->sg[qsg->nsg].len = len;
60 qsg->size += len;
61 ++qsg->nsg;
62 }
63
64 void qemu_sglist_destroy(QEMUSGList *qsg)
65 {
66 object_unref(OBJECT(qsg->dev));
67 g_free(qsg->sg);
68 memset(qsg, 0, sizeof(*qsg));
69 }
70
71 typedef struct {
72 BlockAIOCB common;
73 AioContext *ctx;
74 BlockAIOCB *acb;
75 QEMUSGList *sg;
76 uint64_t offset;
77 DMADirection dir;
78 int sg_cur_index;
79 dma_addr_t sg_cur_byte;
80 QEMUIOVector iov;
81 QEMUBH *bh;
82 DMAIOFunc *io_func;
83 void *io_func_opaque;
84 } DMAAIOCB;
85
86 static void dma_blk_cb(void *opaque, int ret);
87
88 static void reschedule_dma(void *opaque)
89 {
90 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
91
92 qemu_bh_delete(dbs->bh);
93 dbs->bh = NULL;
94 dma_blk_cb(dbs, 0);
95 }
96
97 static void dma_blk_unmap(DMAAIOCB *dbs)
98 {
99 int i;
100
101 for (i = 0; i < dbs->iov.niov; ++i) {
102 dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
103 dbs->iov.iov[i].iov_len, dbs->dir,
104 dbs->iov.iov[i].iov_len);
105 }
106 qemu_iovec_reset(&dbs->iov);
107 }
108
109 static void dma_complete(DMAAIOCB *dbs, int ret)
110 {
111 trace_dma_complete(dbs, ret, dbs->common.cb);
112
113 dma_blk_unmap(dbs);
114 if (dbs->common.cb) {
115 dbs->common.cb(dbs->common.opaque, ret);
116 }
117 qemu_iovec_destroy(&dbs->iov);
118 if (dbs->bh) {
119 qemu_bh_delete(dbs->bh);
120 dbs->bh = NULL;
121 }
122 qemu_aio_unref(dbs);
123 }
124
125 static void dma_blk_cb(void *opaque, int ret)
126 {
127 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
128 dma_addr_t cur_addr, cur_len;
129 void *mem;
130
131 trace_dma_blk_cb(dbs, ret);
132
133 dbs->acb = NULL;
134 dbs->offset += dbs->iov.size;
135
136 if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
137 dma_complete(dbs, ret);
138 return;
139 }
140 dma_blk_unmap(dbs);
141
142 while (dbs->sg_cur_index < dbs->sg->nsg) {
143 cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
144 cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
145 mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir);
146 if (!mem)
147 break;
148 qemu_iovec_add(&dbs->iov, mem, cur_len);
149 dbs->sg_cur_byte += cur_len;
150 if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
151 dbs->sg_cur_byte = 0;
152 ++dbs->sg_cur_index;
153 }
154 }
155
156 if (dbs->iov.size == 0) {
157 trace_dma_map_wait(dbs);
158 dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs);
159 cpu_register_map_client(dbs->bh);
160 return;
161 }
162
163 if (dbs->iov.size & ~BDRV_SECTOR_MASK) {
164 qemu_iovec_discard_back(&dbs->iov, dbs->iov.size & ~BDRV_SECTOR_MASK);
165 }
166
167 dbs->acb = dbs->io_func(dbs->offset, &dbs->iov,
168 dma_blk_cb, dbs, dbs->io_func_opaque);
169 assert(dbs->acb);
170 }
171
172 static void dma_aio_cancel(BlockAIOCB *acb)
173 {
174 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
175
176 trace_dma_aio_cancel(dbs);
177
178 if (dbs->acb) {
179 blk_aio_cancel_async(dbs->acb);
180 }
181 if (dbs->bh) {
182 cpu_unregister_map_client(dbs->bh);
183 qemu_bh_delete(dbs->bh);
184 dbs->bh = NULL;
185 }
186 }
187
188
189 static const AIOCBInfo dma_aiocb_info = {
190 .aiocb_size = sizeof(DMAAIOCB),
191 .cancel_async = dma_aio_cancel,
192 };
193
194 BlockAIOCB *dma_blk_io(AioContext *ctx,
195 QEMUSGList *sg, uint64_t offset,
196 DMAIOFunc *io_func, void *io_func_opaque,
197 BlockCompletionFunc *cb,
198 void *opaque, DMADirection dir)
199 {
200 DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque);
201
202 trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE));
203
204 dbs->acb = NULL;
205 dbs->sg = sg;
206 dbs->ctx = ctx;
207 dbs->offset = offset;
208 dbs->sg_cur_index = 0;
209 dbs->sg_cur_byte = 0;
210 dbs->dir = dir;
211 dbs->io_func = io_func;
212 dbs->io_func_opaque = io_func_opaque;
213 dbs->bh = NULL;
214 qemu_iovec_init(&dbs->iov, sg->nsg);
215 dma_blk_cb(dbs, 0);
216 return &dbs->common;
217 }
218
219
220 static
221 BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov,
222 BlockCompletionFunc *cb, void *cb_opaque,
223 void *opaque)
224 {
225 BlockBackend *blk = opaque;
226 return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque);
227 }
228
229 BlockAIOCB *dma_blk_read(BlockBackend *blk,
230 QEMUSGList *sg, uint64_t offset,
231 void (*cb)(void *opaque, int ret), void *opaque)
232 {
233 return dma_blk_io(blk_get_aio_context(blk),
234 sg, offset, dma_blk_read_io_func, blk, cb, opaque,
235 DMA_DIRECTION_FROM_DEVICE);
236 }
237
238 static
239 BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov,
240 BlockCompletionFunc *cb, void *cb_opaque,
241 void *opaque)
242 {
243 BlockBackend *blk = opaque;
244 return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque);
245 }
246
247 BlockAIOCB *dma_blk_write(BlockBackend *blk,
248 QEMUSGList *sg, uint64_t offset,
249 void (*cb)(void *opaque, int ret), void *opaque)
250 {
251 return dma_blk_io(blk_get_aio_context(blk),
252 sg, offset, dma_blk_write_io_func, blk, cb, opaque,
253 DMA_DIRECTION_TO_DEVICE);
254 }
255
256
257 static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
258 DMADirection dir)
259 {
260 uint64_t resid;
261 int sg_cur_index;
262
263 resid = sg->size;
264 sg_cur_index = 0;
265 len = MIN(len, resid);
266 while (len > 0) {
267 ScatterGatherEntry entry = sg->sg[sg_cur_index++];
268 int32_t xfer = MIN(len, entry.len);
269 dma_memory_rw(sg->as, entry.base, ptr, xfer, dir);
270 ptr += xfer;
271 len -= xfer;
272 resid -= xfer;
273 }
274
275 return resid;
276 }
277
278 uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
279 {
280 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
281 }
282
283 uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
284 {
285 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
286 }
287
288 void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
289 QEMUSGList *sg, enum BlockAcctType type)
290 {
291 block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
292 }