tcg: extend max tcg opcodes when using 64-on-32bit
[qemu.git] / exec-all.h
1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef _EXEC_ALL_H_
21 #define _EXEC_ALL_H_
22
23 #include "qemu-common.h"
24
25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
26 #define DEBUG_DISAS
27
28 /* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
30 type. */
31 #if defined(CONFIG_USER_ONLY)
32 typedef abi_ulong tb_page_addr_t;
33 #else
34 typedef ram_addr_t tb_page_addr_t;
35 #endif
36
37 /* is_jmp field values */
38 #define DISAS_NEXT 0 /* next instruction can be analyzed */
39 #define DISAS_JUMP 1 /* only pc was modified dynamically */
40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
42
43 typedef struct TranslationBlock TranslationBlock;
44
45 /* XXX: make safe guess about sizes */
46 #if (HOST_LONG_BITS == 32) && (TARGET_LONG_BITS == 64)
47 #define MAX_OP_PER_INSTR 128
48 #else
49 #define MAX_OP_PER_INSTR 96
50 #endif
51
52 #if HOST_LONG_BITS == 32
53 #define MAX_OPC_PARAM_PER_ARG 2
54 #else
55 #define MAX_OPC_PARAM_PER_ARG 1
56 #endif
57 #define MAX_OPC_PARAM_IARGS 4
58 #define MAX_OPC_PARAM_OARGS 1
59 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
60
61 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
62 * and up to 4 + N parameters on 64-bit archs
63 * (N = number of input arguments + output arguments). */
64 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
65 #define OPC_BUF_SIZE 640
66 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
67
68 /* Maximum size a TCG op can expand to. This is complicated because a
69 single op may require several host instructions and register reloads.
70 For now take a wild guess at 192 bytes, which should allow at least
71 a couple of fixup instructions per argument. */
72 #define TCG_MAX_OP_SIZE 192
73
74 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
75
76 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
77 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
78 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
79
80 #include "qemu-log.h"
81
82 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
83 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
84 void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
85 int pc_pos);
86
87 void cpu_gen_init(void);
88 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
89 int *gen_code_size_ptr);
90 int cpu_restore_state(struct TranslationBlock *tb,
91 CPUState *env, unsigned long searched_pc);
92 void cpu_resume_from_signal(CPUState *env1, void *puc);
93 void cpu_io_recompile(CPUState *env, void *retaddr);
94 TranslationBlock *tb_gen_code(CPUState *env,
95 target_ulong pc, target_ulong cs_base, int flags,
96 int cflags);
97 void cpu_exec_init(CPUState *env);
98 void QEMU_NORETURN cpu_loop_exit(void);
99 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
100 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
101 int is_cpu_write_access);
102 void tb_invalidate_page_range(target_ulong start, target_ulong end);
103 void tlb_flush_page(CPUState *env, target_ulong addr);
104 void tlb_flush(CPUState *env, int flush_global);
105 #if !defined(CONFIG_USER_ONLY)
106 void tlb_set_page(CPUState *env, target_ulong vaddr,
107 target_phys_addr_t paddr, int prot,
108 int mmu_idx, target_ulong size);
109 #endif
110
111 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
112
113 #define CODE_GEN_PHYS_HASH_BITS 15
114 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
115
116 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
117
118 /* estimated block size for TB allocation */
119 /* XXX: use a per code average code fragment size and modulate it
120 according to the host CPU */
121 #if defined(CONFIG_SOFTMMU)
122 #define CODE_GEN_AVG_BLOCK_SIZE 128
123 #else
124 #define CODE_GEN_AVG_BLOCK_SIZE 64
125 #endif
126
127 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
128 #define USE_DIRECT_JUMP
129 #endif
130
131 struct TranslationBlock {
132 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
133 target_ulong cs_base; /* CS base for this block */
134 uint64_t flags; /* flags defining in which context the code was generated */
135 uint16_t size; /* size of target code for this block (1 <=
136 size <= TARGET_PAGE_SIZE) */
137 uint16_t cflags; /* compile flags */
138 #define CF_COUNT_MASK 0x7fff
139 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
140
141 uint8_t *tc_ptr; /* pointer to the translated code */
142 /* next matching tb for physical address. */
143 struct TranslationBlock *phys_hash_next;
144 /* first and second physical page containing code. The lower bit
145 of the pointer tells the index in page_next[] */
146 struct TranslationBlock *page_next[2];
147 tb_page_addr_t page_addr[2];
148
149 /* the following data are used to directly call another TB from
150 the code of this one. */
151 uint16_t tb_next_offset[2]; /* offset of original jump target */
152 #ifdef USE_DIRECT_JUMP
153 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
154 #else
155 unsigned long tb_next[2]; /* address of jump generated code */
156 #endif
157 /* list of TBs jumping to this one. This is a circular list using
158 the two least significant bits of the pointers to tell what is
159 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
160 jmp_first */
161 struct TranslationBlock *jmp_next[2];
162 struct TranslationBlock *jmp_first;
163 uint32_t icount;
164 };
165
166 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
167 {
168 target_ulong tmp;
169 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
170 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
171 }
172
173 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
174 {
175 target_ulong tmp;
176 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
177 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
178 | (tmp & TB_JMP_ADDR_MASK));
179 }
180
181 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
182 {
183 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
184 }
185
186 void tb_free(TranslationBlock *tb);
187 void tb_flush(CPUState *env);
188 void tb_link_page(TranslationBlock *tb,
189 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
190 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
191
192 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
193
194 #if defined(USE_DIRECT_JUMP)
195
196 #if defined(_ARCH_PPC)
197 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
198 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
199 #elif defined(__i386__) || defined(__x86_64__)
200 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
201 {
202 /* patch the branch destination */
203 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
204 /* no need to flush icache explicitly */
205 }
206 #elif defined(__arm__)
207 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
208 {
209 #if !QEMU_GNUC_PREREQ(4, 1)
210 register unsigned long _beg __asm ("a1");
211 register unsigned long _end __asm ("a2");
212 register unsigned long _flg __asm ("a3");
213 #endif
214
215 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
216 *(uint32_t *)jmp_addr =
217 (*(uint32_t *)jmp_addr & ~0xffffff)
218 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
219
220 #if QEMU_GNUC_PREREQ(4, 1)
221 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
222 #else
223 /* flush icache */
224 _beg = jmp_addr;
225 _end = jmp_addr + 4;
226 _flg = 0;
227 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
228 #endif
229 }
230 #endif
231
232 static inline void tb_set_jmp_target(TranslationBlock *tb,
233 int n, unsigned long addr)
234 {
235 unsigned long offset;
236
237 offset = tb->tb_jmp_offset[n];
238 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
239 }
240
241 #else
242
243 /* set the jump target */
244 static inline void tb_set_jmp_target(TranslationBlock *tb,
245 int n, unsigned long addr)
246 {
247 tb->tb_next[n] = addr;
248 }
249
250 #endif
251
252 static inline void tb_add_jump(TranslationBlock *tb, int n,
253 TranslationBlock *tb_next)
254 {
255 /* NOTE: this test is only needed for thread safety */
256 if (!tb->jmp_next[n]) {
257 /* patch the native jump address */
258 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
259
260 /* add in TB jmp circular list */
261 tb->jmp_next[n] = tb_next->jmp_first;
262 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
263 }
264 }
265
266 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
267
268 #include "qemu-lock.h"
269
270 extern spinlock_t tb_lock;
271
272 extern int tb_invalidated_flag;
273
274 #if !defined(CONFIG_USER_ONLY)
275
276 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
277 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
278 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
279
280 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
281 void *retaddr);
282
283 #include "softmmu_defs.h"
284
285 #define ACCESS_TYPE (NB_MMU_MODES + 1)
286 #define MEMSUFFIX _code
287 #define env cpu_single_env
288
289 #define DATA_SIZE 1
290 #include "softmmu_header.h"
291
292 #define DATA_SIZE 2
293 #include "softmmu_header.h"
294
295 #define DATA_SIZE 4
296 #include "softmmu_header.h"
297
298 #define DATA_SIZE 8
299 #include "softmmu_header.h"
300
301 #undef ACCESS_TYPE
302 #undef MEMSUFFIX
303 #undef env
304
305 #endif
306
307 #if defined(CONFIG_USER_ONLY)
308 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
309 {
310 return addr;
311 }
312 #else
313 /* NOTE: this function can trigger an exception */
314 /* NOTE2: the returned address is not exactly the physical address: it
315 is the offset relative to phys_ram_base */
316 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
317 {
318 int mmu_idx, page_index, pd;
319 void *p;
320
321 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
322 mmu_idx = cpu_mmu_index(env1);
323 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
324 (addr & TARGET_PAGE_MASK))) {
325 ldub_code(addr);
326 }
327 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
328 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
329 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
330 do_unassigned_access(addr, 0, 1, 0, 4);
331 #else
332 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
333 #endif
334 }
335 p = (void *)(unsigned long)addr
336 + env1->tlb_table[mmu_idx][page_index].addend;
337 return qemu_ram_addr_from_host_nofail(p);
338 }
339 #endif
340
341 typedef void (CPUDebugExcpHandler)(CPUState *env);
342
343 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
344
345 /* vl.c */
346 extern int singlestep;
347
348 /* cpu-exec.c */
349 extern volatile sig_atomic_t exit_request;
350
351 #endif