PPC: Enable doorbell excp handlers
[qemu.git] / exec-all.h
1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef _EXEC_ALL_H_
21 #define _EXEC_ALL_H_
22
23 #include "qemu-common.h"
24
25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
26 #define DEBUG_DISAS
27
28 /* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
30 type. */
31 #if defined(CONFIG_USER_ONLY)
32 typedef abi_ulong tb_page_addr_t;
33 #else
34 typedef ram_addr_t tb_page_addr_t;
35 #endif
36
37 /* is_jmp field values */
38 #define DISAS_NEXT 0 /* next instruction can be analyzed */
39 #define DISAS_JUMP 1 /* only pc was modified dynamically */
40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
42
43 struct TranslationBlock;
44 typedef struct TranslationBlock TranslationBlock;
45
46 /* XXX: make safe guess about sizes */
47 #define MAX_OP_PER_INSTR 208
48
49 #if HOST_LONG_BITS == 32
50 #define MAX_OPC_PARAM_PER_ARG 2
51 #else
52 #define MAX_OPC_PARAM_PER_ARG 1
53 #endif
54 #define MAX_OPC_PARAM_IARGS 4
55 #define MAX_OPC_PARAM_OARGS 1
56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
57
58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
59 * and up to 4 + N parameters on 64-bit archs
60 * (N = number of input arguments + output arguments). */
61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
62 #define OPC_BUF_SIZE 640
63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
64
65 /* Maximum size a TCG op can expand to. This is complicated because a
66 single op may require several host instructions and register reloads.
67 For now take a wild guess at 192 bytes, which should allow at least
68 a couple of fixup instructions per argument. */
69 #define TCG_MAX_OP_SIZE 192
70
71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
72
73 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
74 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
75 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
76
77 #include "qemu-log.h"
78
79 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
80 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
81 void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
82 int pc_pos);
83
84 void cpu_gen_init(void);
85 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
86 int *gen_code_size_ptr);
87 int cpu_restore_state(struct TranslationBlock *tb,
88 CPUState *env, unsigned long searched_pc);
89 void cpu_resume_from_signal(CPUState *env1, void *puc);
90 void cpu_io_recompile(CPUState *env, void *retaddr);
91 TranslationBlock *tb_gen_code(CPUState *env,
92 target_ulong pc, target_ulong cs_base, int flags,
93 int cflags);
94 void cpu_exec_init(CPUState *env);
95 void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
96 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
97 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
98 int is_cpu_write_access);
99 void tlb_flush_page(CPUState *env, target_ulong addr);
100 void tlb_flush(CPUState *env, int flush_global);
101 #if !defined(CONFIG_USER_ONLY)
102 void tlb_set_page(CPUState *env, target_ulong vaddr,
103 target_phys_addr_t paddr, int prot,
104 int mmu_idx, target_ulong size);
105 #endif
106
107 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
108
109 #define CODE_GEN_PHYS_HASH_BITS 15
110 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
111
112 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
113
114 /* estimated block size for TB allocation */
115 /* XXX: use a per code average code fragment size and modulate it
116 according to the host CPU */
117 #if defined(CONFIG_SOFTMMU)
118 #define CODE_GEN_AVG_BLOCK_SIZE 128
119 #else
120 #define CODE_GEN_AVG_BLOCK_SIZE 64
121 #endif
122
123 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
124 #define USE_DIRECT_JUMP
125 #elif defined(CONFIG_TCG_INTERPRETER)
126 #define USE_DIRECT_JUMP
127 #endif
128
129 struct TranslationBlock {
130 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
131 target_ulong cs_base; /* CS base for this block */
132 uint64_t flags; /* flags defining in which context the code was generated */
133 uint16_t size; /* size of target code for this block (1 <=
134 size <= TARGET_PAGE_SIZE) */
135 uint16_t cflags; /* compile flags */
136 #define CF_COUNT_MASK 0x7fff
137 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
138
139 uint8_t *tc_ptr; /* pointer to the translated code */
140 /* next matching tb for physical address. */
141 struct TranslationBlock *phys_hash_next;
142 /* first and second physical page containing code. The lower bit
143 of the pointer tells the index in page_next[] */
144 struct TranslationBlock *page_next[2];
145 tb_page_addr_t page_addr[2];
146
147 /* the following data are used to directly call another TB from
148 the code of this one. */
149 uint16_t tb_next_offset[2]; /* offset of original jump target */
150 #ifdef USE_DIRECT_JUMP
151 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
152 #else
153 unsigned long tb_next[2]; /* address of jump generated code */
154 #endif
155 /* list of TBs jumping to this one. This is a circular list using
156 the two least significant bits of the pointers to tell what is
157 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
158 jmp_first */
159 struct TranslationBlock *jmp_next[2];
160 struct TranslationBlock *jmp_first;
161 uint32_t icount;
162 };
163
164 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
165 {
166 target_ulong tmp;
167 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
168 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
169 }
170
171 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
172 {
173 target_ulong tmp;
174 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
175 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
176 | (tmp & TB_JMP_ADDR_MASK));
177 }
178
179 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
180 {
181 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
182 }
183
184 void tb_free(TranslationBlock *tb);
185 void tb_flush(CPUState *env);
186 void tb_link_page(TranslationBlock *tb,
187 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
188 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
189
190 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
191
192 #if defined(USE_DIRECT_JUMP)
193
194 #if defined(CONFIG_TCG_INTERPRETER)
195 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
196 {
197 /* patch the branch destination */
198 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
199 /* no need to flush icache explicitly */
200 }
201 #elif defined(_ARCH_PPC)
202 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
203 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
204 #elif defined(__i386__) || defined(__x86_64__)
205 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
206 {
207 /* patch the branch destination */
208 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
209 /* no need to flush icache explicitly */
210 }
211 #elif defined(__arm__)
212 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
213 {
214 #if !QEMU_GNUC_PREREQ(4, 1)
215 register unsigned long _beg __asm ("a1");
216 register unsigned long _end __asm ("a2");
217 register unsigned long _flg __asm ("a3");
218 #endif
219
220 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
221 *(uint32_t *)jmp_addr =
222 (*(uint32_t *)jmp_addr & ~0xffffff)
223 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
224
225 #if QEMU_GNUC_PREREQ(4, 1)
226 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
227 #else
228 /* flush icache */
229 _beg = jmp_addr;
230 _end = jmp_addr + 4;
231 _flg = 0;
232 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
233 #endif
234 }
235 #else
236 #error tb_set_jmp_target1 is missing
237 #endif
238
239 static inline void tb_set_jmp_target(TranslationBlock *tb,
240 int n, unsigned long addr)
241 {
242 unsigned long offset;
243
244 offset = tb->tb_jmp_offset[n];
245 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
246 }
247
248 #else
249
250 /* set the jump target */
251 static inline void tb_set_jmp_target(TranslationBlock *tb,
252 int n, unsigned long addr)
253 {
254 tb->tb_next[n] = addr;
255 }
256
257 #endif
258
259 static inline void tb_add_jump(TranslationBlock *tb, int n,
260 TranslationBlock *tb_next)
261 {
262 /* NOTE: this test is only needed for thread safety */
263 if (!tb->jmp_next[n]) {
264 /* patch the native jump address */
265 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
266
267 /* add in TB jmp circular list */
268 tb->jmp_next[n] = tb_next->jmp_first;
269 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
270 }
271 }
272
273 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
274
275 #include "qemu-lock.h"
276
277 extern spinlock_t tb_lock;
278
279 extern int tb_invalidated_flag;
280
281 /* The return address may point to the start of the next instruction.
282 Subtracting one gets us the call instruction itself. */
283 #if defined(CONFIG_TCG_INTERPRETER)
284 /* Alpha and SH4 user mode emulations and Softmmu call GETPC().
285 For all others, GETPC remains undefined (which makes TCI a little faster. */
286 # if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
287 extern void *tci_tb_ptr;
288 # define GETPC() tci_tb_ptr
289 # endif
290 #elif defined(__s390__) && !defined(__s390x__)
291 # define GETPC() ((void*)(((unsigned long)__builtin_return_address(0) & 0x7fffffffUL) - 1))
292 #elif defined(__arm__)
293 /* Thumb return addresses have the low bit set, so we need to subtract two.
294 This is still safe in ARM mode because instructions are 4 bytes. */
295 # define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 2))
296 #else
297 # define GETPC() ((void *)((unsigned long)__builtin_return_address(0) - 1))
298 #endif
299
300 #if !defined(CONFIG_USER_ONLY)
301
302 uint64_t io_mem_read(int index, target_phys_addr_t addr, unsigned size);
303 void io_mem_write(int index, target_phys_addr_t addr, uint64_t value,
304 unsigned size);
305 extern struct MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
306
307 void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
308 void *retaddr);
309
310 #include "softmmu_defs.h"
311
312 #define ACCESS_TYPE (NB_MMU_MODES + 1)
313 #define MEMSUFFIX _code
314 #define env cpu_single_env
315
316 #define DATA_SIZE 1
317 #include "softmmu_header.h"
318
319 #define DATA_SIZE 2
320 #include "softmmu_header.h"
321
322 #define DATA_SIZE 4
323 #include "softmmu_header.h"
324
325 #define DATA_SIZE 8
326 #include "softmmu_header.h"
327
328 #undef ACCESS_TYPE
329 #undef MEMSUFFIX
330 #undef env
331
332 #endif
333
334 #if defined(CONFIG_USER_ONLY)
335 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
336 {
337 return addr;
338 }
339 #else
340 tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr);
341 #endif
342
343 typedef void (CPUDebugExcpHandler)(CPUState *env);
344
345 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
346
347 /* vl.c */
348 extern int singlestep;
349
350 /* cpu-exec.c */
351 extern volatile sig_atomic_t exit_request;
352
353 /* Deterministic execution requires that IO only be performed on the last
354 instruction of a TB so that interrupts take effect immediately. */
355 static inline int can_do_io(CPUState *env)
356 {
357 if (!use_icount) {
358 return 1;
359 }
360 /* If not executing code then assume we are ok. */
361 if (!env->current_tb) {
362 return 1;
363 }
364 return env->can_do_io != 0;
365 }
366
367 #endif