Delete unused tb_invalidate_page_range
[qemu.git] / exec-all.h
1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef _EXEC_ALL_H_
21 #define _EXEC_ALL_H_
22
23 #include "qemu-common.h"
24
25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
26 #define DEBUG_DISAS
27
28 /* Page tracking code uses ram addresses in system mode, and virtual
29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate
30 type. */
31 #if defined(CONFIG_USER_ONLY)
32 typedef abi_ulong tb_page_addr_t;
33 #else
34 typedef ram_addr_t tb_page_addr_t;
35 #endif
36
37 /* is_jmp field values */
38 #define DISAS_NEXT 0 /* next instruction can be analyzed */
39 #define DISAS_JUMP 1 /* only pc was modified dynamically */
40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
42
43 typedef struct TranslationBlock TranslationBlock;
44
45 /* XXX: make safe guess about sizes */
46 #define MAX_OP_PER_INSTR 96
47
48 #if HOST_LONG_BITS == 32
49 #define MAX_OPC_PARAM_PER_ARG 2
50 #else
51 #define MAX_OPC_PARAM_PER_ARG 1
52 #endif
53 #define MAX_OPC_PARAM_IARGS 4
54 #define MAX_OPC_PARAM_OARGS 1
55 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
56
57 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
58 * and up to 4 + N parameters on 64-bit archs
59 * (N = number of input arguments + output arguments). */
60 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
61 #define OPC_BUF_SIZE 640
62 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
63
64 /* Maximum size a TCG op can expand to. This is complicated because a
65 single op may require several host instructions and register reloads.
66 For now take a wild guess at 192 bytes, which should allow at least
67 a couple of fixup instructions per argument. */
68 #define TCG_MAX_OP_SIZE 192
69
70 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
71
72 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
73 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
74 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
75
76 #include "qemu-log.h"
77
78 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
79 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
80 void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
81 int pc_pos);
82
83 void cpu_gen_init(void);
84 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
85 int *gen_code_size_ptr);
86 int cpu_restore_state(struct TranslationBlock *tb,
87 CPUState *env, unsigned long searched_pc);
88 void cpu_resume_from_signal(CPUState *env1, void *puc);
89 void cpu_io_recompile(CPUState *env, void *retaddr);
90 TranslationBlock *tb_gen_code(CPUState *env,
91 target_ulong pc, target_ulong cs_base, int flags,
92 int cflags);
93 void cpu_exec_init(CPUState *env);
94 void QEMU_NORETURN cpu_loop_exit(void);
95 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
96 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
97 int is_cpu_write_access);
98 void tlb_flush_page(CPUState *env, target_ulong addr);
99 void tlb_flush(CPUState *env, int flush_global);
100 #if !defined(CONFIG_USER_ONLY)
101 void tlb_set_page(CPUState *env, target_ulong vaddr,
102 target_phys_addr_t paddr, int prot,
103 int mmu_idx, target_ulong size);
104 #endif
105
106 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
107
108 #define CODE_GEN_PHYS_HASH_BITS 15
109 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
110
111 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
112
113 /* estimated block size for TB allocation */
114 /* XXX: use a per code average code fragment size and modulate it
115 according to the host CPU */
116 #if defined(CONFIG_SOFTMMU)
117 #define CODE_GEN_AVG_BLOCK_SIZE 128
118 #else
119 #define CODE_GEN_AVG_BLOCK_SIZE 64
120 #endif
121
122 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
123 #define USE_DIRECT_JUMP
124 #endif
125
126 struct TranslationBlock {
127 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
128 target_ulong cs_base; /* CS base for this block */
129 uint64_t flags; /* flags defining in which context the code was generated */
130 uint16_t size; /* size of target code for this block (1 <=
131 size <= TARGET_PAGE_SIZE) */
132 uint16_t cflags; /* compile flags */
133 #define CF_COUNT_MASK 0x7fff
134 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
135
136 uint8_t *tc_ptr; /* pointer to the translated code */
137 /* next matching tb for physical address. */
138 struct TranslationBlock *phys_hash_next;
139 /* first and second physical page containing code. The lower bit
140 of the pointer tells the index in page_next[] */
141 struct TranslationBlock *page_next[2];
142 tb_page_addr_t page_addr[2];
143
144 /* the following data are used to directly call another TB from
145 the code of this one. */
146 uint16_t tb_next_offset[2]; /* offset of original jump target */
147 #ifdef USE_DIRECT_JUMP
148 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
149 #else
150 unsigned long tb_next[2]; /* address of jump generated code */
151 #endif
152 /* list of TBs jumping to this one. This is a circular list using
153 the two least significant bits of the pointers to tell what is
154 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
155 jmp_first */
156 struct TranslationBlock *jmp_next[2];
157 struct TranslationBlock *jmp_first;
158 uint32_t icount;
159 };
160
161 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
162 {
163 target_ulong tmp;
164 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
165 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
166 }
167
168 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
169 {
170 target_ulong tmp;
171 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
172 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
173 | (tmp & TB_JMP_ADDR_MASK));
174 }
175
176 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
177 {
178 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
179 }
180
181 void tb_free(TranslationBlock *tb);
182 void tb_flush(CPUState *env);
183 void tb_link_page(TranslationBlock *tb,
184 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
185 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
186
187 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
188
189 #if defined(USE_DIRECT_JUMP)
190
191 #if defined(_ARCH_PPC)
192 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
193 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
194 #elif defined(__i386__) || defined(__x86_64__)
195 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
196 {
197 /* patch the branch destination */
198 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
199 /* no need to flush icache explicitly */
200 }
201 #elif defined(__arm__)
202 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
203 {
204 #if !QEMU_GNUC_PREREQ(4, 1)
205 register unsigned long _beg __asm ("a1");
206 register unsigned long _end __asm ("a2");
207 register unsigned long _flg __asm ("a3");
208 #endif
209
210 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
211 *(uint32_t *)jmp_addr =
212 (*(uint32_t *)jmp_addr & ~0xffffff)
213 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
214
215 #if QEMU_GNUC_PREREQ(4, 1)
216 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
217 #else
218 /* flush icache */
219 _beg = jmp_addr;
220 _end = jmp_addr + 4;
221 _flg = 0;
222 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
223 #endif
224 }
225 #endif
226
227 static inline void tb_set_jmp_target(TranslationBlock *tb,
228 int n, unsigned long addr)
229 {
230 unsigned long offset;
231
232 offset = tb->tb_jmp_offset[n];
233 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
234 }
235
236 #else
237
238 /* set the jump target */
239 static inline void tb_set_jmp_target(TranslationBlock *tb,
240 int n, unsigned long addr)
241 {
242 tb->tb_next[n] = addr;
243 }
244
245 #endif
246
247 static inline void tb_add_jump(TranslationBlock *tb, int n,
248 TranslationBlock *tb_next)
249 {
250 /* NOTE: this test is only needed for thread safety */
251 if (!tb->jmp_next[n]) {
252 /* patch the native jump address */
253 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
254
255 /* add in TB jmp circular list */
256 tb->jmp_next[n] = tb_next->jmp_first;
257 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
258 }
259 }
260
261 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
262
263 #include "qemu-lock.h"
264
265 extern spinlock_t tb_lock;
266
267 extern int tb_invalidated_flag;
268
269 #if !defined(CONFIG_USER_ONLY)
270
271 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
272 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
273 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
274
275 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
276 void *retaddr);
277
278 #include "softmmu_defs.h"
279
280 #define ACCESS_TYPE (NB_MMU_MODES + 1)
281 #define MEMSUFFIX _code
282 #define env cpu_single_env
283
284 #define DATA_SIZE 1
285 #include "softmmu_header.h"
286
287 #define DATA_SIZE 2
288 #include "softmmu_header.h"
289
290 #define DATA_SIZE 4
291 #include "softmmu_header.h"
292
293 #define DATA_SIZE 8
294 #include "softmmu_header.h"
295
296 #undef ACCESS_TYPE
297 #undef MEMSUFFIX
298 #undef env
299
300 #endif
301
302 #if defined(CONFIG_USER_ONLY)
303 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
304 {
305 return addr;
306 }
307 #else
308 /* NOTE: this function can trigger an exception */
309 /* NOTE2: the returned address is not exactly the physical address: it
310 is the offset relative to phys_ram_base */
311 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
312 {
313 int mmu_idx, page_index, pd;
314 void *p;
315
316 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
317 mmu_idx = cpu_mmu_index(env1);
318 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
319 (addr & TARGET_PAGE_MASK))) {
320 ldub_code(addr);
321 }
322 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
323 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
324 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
325 do_unassigned_access(addr, 0, 1, 0, 4);
326 #else
327 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
328 #endif
329 }
330 p = (void *)(unsigned long)addr
331 + env1->tlb_table[mmu_idx][page_index].addend;
332 return qemu_ram_addr_from_host_nofail(p);
333 }
334 #endif
335
336 typedef void (CPUDebugExcpHandler)(CPUState *env);
337
338 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
339
340 /* vl.c */
341 extern int singlestep;
342
343 /* cpu-exec.c */
344 extern volatile sig_atomic_t exit_request;
345
346 #endif