linux-user,mips: update syscall-args-o32.c.inc
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg/tcg.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
34 #endif
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/qtest.h"
39 #include "qemu/timer.h"
40 #include "qemu/config-file.h"
41 #include "qemu/error-report.h"
42 #include "qemu/qemu-print.h"
43 #if defined(CONFIG_USER_ONLY)
44 #include "qemu.h"
45 #else /* !CONFIG_USER_ONLY */
46 #include "exec/memory.h"
47 #include "exec/ioport.h"
48 #include "sysemu/dma.h"
49 #include "sysemu/hostmem.h"
50 #include "sysemu/hw_accel.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/xen-mapcache.h"
53 #include "trace-root.h"
54
55 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
56 #include <linux/falloc.h>
57 #endif
58
59 #endif
60 #include "qemu/rcu_queue.h"
61 #include "qemu/main-loop.h"
62 #include "translate-all.h"
63 #include "sysemu/replay.h"
64
65 #include "exec/memory-internal.h"
66 #include "exec/ram_addr.h"
67 #include "exec/log.h"
68
69 #include "qemu/pmem.h"
70
71 #include "migration/vmstate.h"
72
73 #include "qemu/range.h"
74 #ifndef _WIN32
75 #include "qemu/mmap-alloc.h"
76 #endif
77
78 #include "monitor/monitor.h"
79
80 //#define DEBUG_SUBPAGE
81
82 #if !defined(CONFIG_USER_ONLY)
83 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
84 * are protected by the ramlist lock.
85 */
86 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
87
88 static MemoryRegion *system_memory;
89 static MemoryRegion *system_io;
90
91 AddressSpace address_space_io;
92 AddressSpace address_space_memory;
93
94 static MemoryRegion io_mem_unassigned;
95 #endif
96
97 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
98
99 /* current CPU in the current thread. It is only valid inside
100 cpu_exec() */
101 __thread CPUState *current_cpu;
102
103 uintptr_t qemu_host_page_size;
104 intptr_t qemu_host_page_mask;
105
106 #if !defined(CONFIG_USER_ONLY)
107 /* 0 = Do not count executed instructions.
108 1 = Precise instruction counting.
109 2 = Adaptive rate instruction counting. */
110 int use_icount;
111
112 typedef struct PhysPageEntry PhysPageEntry;
113
114 struct PhysPageEntry {
115 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
116 uint32_t skip : 6;
117 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
118 uint32_t ptr : 26;
119 };
120
121 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
122
123 /* Size of the L2 (and L3, etc) page tables. */
124 #define ADDR_SPACE_BITS 64
125
126 #define P_L2_BITS 9
127 #define P_L2_SIZE (1 << P_L2_BITS)
128
129 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
130
131 typedef PhysPageEntry Node[P_L2_SIZE];
132
133 typedef struct PhysPageMap {
134 struct rcu_head rcu;
135
136 unsigned sections_nb;
137 unsigned sections_nb_alloc;
138 unsigned nodes_nb;
139 unsigned nodes_nb_alloc;
140 Node *nodes;
141 MemoryRegionSection *sections;
142 } PhysPageMap;
143
144 struct AddressSpaceDispatch {
145 MemoryRegionSection *mru_section;
146 /* This is a multi-level map on the physical address space.
147 * The bottom level has pointers to MemoryRegionSections.
148 */
149 PhysPageEntry phys_map;
150 PhysPageMap map;
151 };
152
153 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
154 typedef struct subpage_t {
155 MemoryRegion iomem;
156 FlatView *fv;
157 hwaddr base;
158 uint16_t sub_section[];
159 } subpage_t;
160
161 #define PHYS_SECTION_UNASSIGNED 0
162
163 static void io_mem_init(void);
164 static void memory_map_init(void);
165 static void tcg_log_global_after_sync(MemoryListener *listener);
166 static void tcg_commit(MemoryListener *listener);
167
168 /**
169 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
170 * @cpu: the CPU whose AddressSpace this is
171 * @as: the AddressSpace itself
172 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
173 * @tcg_as_listener: listener for tracking changes to the AddressSpace
174 */
175 struct CPUAddressSpace {
176 CPUState *cpu;
177 AddressSpace *as;
178 struct AddressSpaceDispatch *memory_dispatch;
179 MemoryListener tcg_as_listener;
180 };
181
182 struct DirtyBitmapSnapshot {
183 ram_addr_t start;
184 ram_addr_t end;
185 unsigned long dirty[];
186 };
187
188 #endif
189
190 #if !defined(CONFIG_USER_ONLY)
191
192 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
193 {
194 static unsigned alloc_hint = 16;
195 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
196 map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes);
197 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
198 alloc_hint = map->nodes_nb_alloc;
199 }
200 }
201
202 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
203 {
204 unsigned i;
205 uint32_t ret;
206 PhysPageEntry e;
207 PhysPageEntry *p;
208
209 ret = map->nodes_nb++;
210 p = map->nodes[ret];
211 assert(ret != PHYS_MAP_NODE_NIL);
212 assert(ret != map->nodes_nb_alloc);
213
214 e.skip = leaf ? 0 : 1;
215 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
216 for (i = 0; i < P_L2_SIZE; ++i) {
217 memcpy(&p[i], &e, sizeof(e));
218 }
219 return ret;
220 }
221
222 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
223 hwaddr *index, uint64_t *nb, uint16_t leaf,
224 int level)
225 {
226 PhysPageEntry *p;
227 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
228
229 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
230 lp->ptr = phys_map_node_alloc(map, level == 0);
231 }
232 p = map->nodes[lp->ptr];
233 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
234
235 while (*nb && lp < &p[P_L2_SIZE]) {
236 if ((*index & (step - 1)) == 0 && *nb >= step) {
237 lp->skip = 0;
238 lp->ptr = leaf;
239 *index += step;
240 *nb -= step;
241 } else {
242 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
243 }
244 ++lp;
245 }
246 }
247
248 static void phys_page_set(AddressSpaceDispatch *d,
249 hwaddr index, uint64_t nb,
250 uint16_t leaf)
251 {
252 /* Wildly overreserve - it doesn't matter much. */
253 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
254
255 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
256 }
257
258 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
259 * and update our entry so we can skip it and go directly to the destination.
260 */
261 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
262 {
263 unsigned valid_ptr = P_L2_SIZE;
264 int valid = 0;
265 PhysPageEntry *p;
266 int i;
267
268 if (lp->ptr == PHYS_MAP_NODE_NIL) {
269 return;
270 }
271
272 p = nodes[lp->ptr];
273 for (i = 0; i < P_L2_SIZE; i++) {
274 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
275 continue;
276 }
277
278 valid_ptr = i;
279 valid++;
280 if (p[i].skip) {
281 phys_page_compact(&p[i], nodes);
282 }
283 }
284
285 /* We can only compress if there's only one child. */
286 if (valid != 1) {
287 return;
288 }
289
290 assert(valid_ptr < P_L2_SIZE);
291
292 /* Don't compress if it won't fit in the # of bits we have. */
293 if (P_L2_LEVELS >= (1 << 6) &&
294 lp->skip + p[valid_ptr].skip >= (1 << 6)) {
295 return;
296 }
297
298 lp->ptr = p[valid_ptr].ptr;
299 if (!p[valid_ptr].skip) {
300 /* If our only child is a leaf, make this a leaf. */
301 /* By design, we should have made this node a leaf to begin with so we
302 * should never reach here.
303 * But since it's so simple to handle this, let's do it just in case we
304 * change this rule.
305 */
306 lp->skip = 0;
307 } else {
308 lp->skip += p[valid_ptr].skip;
309 }
310 }
311
312 void address_space_dispatch_compact(AddressSpaceDispatch *d)
313 {
314 if (d->phys_map.skip) {
315 phys_page_compact(&d->phys_map, d->map.nodes);
316 }
317 }
318
319 static inline bool section_covers_addr(const MemoryRegionSection *section,
320 hwaddr addr)
321 {
322 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
323 * the section must cover the entire address space.
324 */
325 return int128_gethi(section->size) ||
326 range_covers_byte(section->offset_within_address_space,
327 int128_getlo(section->size), addr);
328 }
329
330 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
331 {
332 PhysPageEntry lp = d->phys_map, *p;
333 Node *nodes = d->map.nodes;
334 MemoryRegionSection *sections = d->map.sections;
335 hwaddr index = addr >> TARGET_PAGE_BITS;
336 int i;
337
338 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
339 if (lp.ptr == PHYS_MAP_NODE_NIL) {
340 return &sections[PHYS_SECTION_UNASSIGNED];
341 }
342 p = nodes[lp.ptr];
343 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
344 }
345
346 if (section_covers_addr(&sections[lp.ptr], addr)) {
347 return &sections[lp.ptr];
348 } else {
349 return &sections[PHYS_SECTION_UNASSIGNED];
350 }
351 }
352
353 /* Called from RCU critical section */
354 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
355 hwaddr addr,
356 bool resolve_subpage)
357 {
358 MemoryRegionSection *section = atomic_read(&d->mru_section);
359 subpage_t *subpage;
360
361 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
362 !section_covers_addr(section, addr)) {
363 section = phys_page_find(d, addr);
364 atomic_set(&d->mru_section, section);
365 }
366 if (resolve_subpage && section->mr->subpage) {
367 subpage = container_of(section->mr, subpage_t, iomem);
368 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
369 }
370 return section;
371 }
372
373 /* Called from RCU critical section */
374 static MemoryRegionSection *
375 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
376 hwaddr *plen, bool resolve_subpage)
377 {
378 MemoryRegionSection *section;
379 MemoryRegion *mr;
380 Int128 diff;
381
382 section = address_space_lookup_region(d, addr, resolve_subpage);
383 /* Compute offset within MemoryRegionSection */
384 addr -= section->offset_within_address_space;
385
386 /* Compute offset within MemoryRegion */
387 *xlat = addr + section->offset_within_region;
388
389 mr = section->mr;
390
391 /* MMIO registers can be expected to perform full-width accesses based only
392 * on their address, without considering adjacent registers that could
393 * decode to completely different MemoryRegions. When such registers
394 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
395 * regions overlap wildly. For this reason we cannot clamp the accesses
396 * here.
397 *
398 * If the length is small (as is the case for address_space_ldl/stl),
399 * everything works fine. If the incoming length is large, however,
400 * the caller really has to do the clamping through memory_access_size.
401 */
402 if (memory_region_is_ram(mr)) {
403 diff = int128_sub(section->size, int128_make64(addr));
404 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
405 }
406 return section;
407 }
408
409 /**
410 * address_space_translate_iommu - translate an address through an IOMMU
411 * memory region and then through the target address space.
412 *
413 * @iommu_mr: the IOMMU memory region that we start the translation from
414 * @addr: the address to be translated through the MMU
415 * @xlat: the translated address offset within the destination memory region.
416 * It cannot be %NULL.
417 * @plen_out: valid read/write length of the translated address. It
418 * cannot be %NULL.
419 * @page_mask_out: page mask for the translated address. This
420 * should only be meaningful for IOMMU translated
421 * addresses, since there may be huge pages that this bit
422 * would tell. It can be %NULL if we don't care about it.
423 * @is_write: whether the translation operation is for write
424 * @is_mmio: whether this can be MMIO, set true if it can
425 * @target_as: the address space targeted by the IOMMU
426 * @attrs: transaction attributes
427 *
428 * This function is called from RCU critical section. It is the common
429 * part of flatview_do_translate and address_space_translate_cached.
430 */
431 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
432 hwaddr *xlat,
433 hwaddr *plen_out,
434 hwaddr *page_mask_out,
435 bool is_write,
436 bool is_mmio,
437 AddressSpace **target_as,
438 MemTxAttrs attrs)
439 {
440 MemoryRegionSection *section;
441 hwaddr page_mask = (hwaddr)-1;
442
443 do {
444 hwaddr addr = *xlat;
445 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
446 int iommu_idx = 0;
447 IOMMUTLBEntry iotlb;
448
449 if (imrc->attrs_to_index) {
450 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
451 }
452
453 iotlb = imrc->translate(iommu_mr, addr, is_write ?
454 IOMMU_WO : IOMMU_RO, iommu_idx);
455
456 if (!(iotlb.perm & (1 << is_write))) {
457 goto unassigned;
458 }
459
460 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
461 | (addr & iotlb.addr_mask));
462 page_mask &= iotlb.addr_mask;
463 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
464 *target_as = iotlb.target_as;
465
466 section = address_space_translate_internal(
467 address_space_to_dispatch(iotlb.target_as), addr, xlat,
468 plen_out, is_mmio);
469
470 iommu_mr = memory_region_get_iommu(section->mr);
471 } while (unlikely(iommu_mr));
472
473 if (page_mask_out) {
474 *page_mask_out = page_mask;
475 }
476 return *section;
477
478 unassigned:
479 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
480 }
481
482 /**
483 * flatview_do_translate - translate an address in FlatView
484 *
485 * @fv: the flat view that we want to translate on
486 * @addr: the address to be translated in above address space
487 * @xlat: the translated address offset within memory region. It
488 * cannot be @NULL.
489 * @plen_out: valid read/write length of the translated address. It
490 * can be @NULL when we don't care about it.
491 * @page_mask_out: page mask for the translated address. This
492 * should only be meaningful for IOMMU translated
493 * addresses, since there may be huge pages that this bit
494 * would tell. It can be @NULL if we don't care about it.
495 * @is_write: whether the translation operation is for write
496 * @is_mmio: whether this can be MMIO, set true if it can
497 * @target_as: the address space targeted by the IOMMU
498 * @attrs: memory transaction attributes
499 *
500 * This function is called from RCU critical section
501 */
502 static MemoryRegionSection flatview_do_translate(FlatView *fv,
503 hwaddr addr,
504 hwaddr *xlat,
505 hwaddr *plen_out,
506 hwaddr *page_mask_out,
507 bool is_write,
508 bool is_mmio,
509 AddressSpace **target_as,
510 MemTxAttrs attrs)
511 {
512 MemoryRegionSection *section;
513 IOMMUMemoryRegion *iommu_mr;
514 hwaddr plen = (hwaddr)(-1);
515
516 if (!plen_out) {
517 plen_out = &plen;
518 }
519
520 section = address_space_translate_internal(
521 flatview_to_dispatch(fv), addr, xlat,
522 plen_out, is_mmio);
523
524 iommu_mr = memory_region_get_iommu(section->mr);
525 if (unlikely(iommu_mr)) {
526 return address_space_translate_iommu(iommu_mr, xlat,
527 plen_out, page_mask_out,
528 is_write, is_mmio,
529 target_as, attrs);
530 }
531 if (page_mask_out) {
532 /* Not behind an IOMMU, use default page size. */
533 *page_mask_out = ~TARGET_PAGE_MASK;
534 }
535
536 return *section;
537 }
538
539 /* Called from RCU critical section */
540 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
541 bool is_write, MemTxAttrs attrs)
542 {
543 MemoryRegionSection section;
544 hwaddr xlat, page_mask;
545
546 /*
547 * This can never be MMIO, and we don't really care about plen,
548 * but page mask.
549 */
550 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
551 NULL, &page_mask, is_write, false, &as,
552 attrs);
553
554 /* Illegal translation */
555 if (section.mr == &io_mem_unassigned) {
556 goto iotlb_fail;
557 }
558
559 /* Convert memory region offset into address space offset */
560 xlat += section.offset_within_address_space -
561 section.offset_within_region;
562
563 return (IOMMUTLBEntry) {
564 .target_as = as,
565 .iova = addr & ~page_mask,
566 .translated_addr = xlat & ~page_mask,
567 .addr_mask = page_mask,
568 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
569 .perm = IOMMU_RW,
570 };
571
572 iotlb_fail:
573 return (IOMMUTLBEntry) {0};
574 }
575
576 /* Called from RCU critical section */
577 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
578 hwaddr *plen, bool is_write,
579 MemTxAttrs attrs)
580 {
581 MemoryRegion *mr;
582 MemoryRegionSection section;
583 AddressSpace *as = NULL;
584
585 /* This can be MMIO, so setup MMIO bit. */
586 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
587 is_write, true, &as, attrs);
588 mr = section.mr;
589
590 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
591 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
592 *plen = MIN(page, *plen);
593 }
594
595 return mr;
596 }
597
598 typedef struct TCGIOMMUNotifier {
599 IOMMUNotifier n;
600 MemoryRegion *mr;
601 CPUState *cpu;
602 int iommu_idx;
603 bool active;
604 } TCGIOMMUNotifier;
605
606 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
607 {
608 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
609
610 if (!notifier->active) {
611 return;
612 }
613 tlb_flush(notifier->cpu);
614 notifier->active = false;
615 /* We leave the notifier struct on the list to avoid reallocating it later.
616 * Generally the number of IOMMUs a CPU deals with will be small.
617 * In any case we can't unregister the iommu notifier from a notify
618 * callback.
619 */
620 }
621
622 static void tcg_register_iommu_notifier(CPUState *cpu,
623 IOMMUMemoryRegion *iommu_mr,
624 int iommu_idx)
625 {
626 /* Make sure this CPU has an IOMMU notifier registered for this
627 * IOMMU/IOMMU index combination, so that we can flush its TLB
628 * when the IOMMU tells us the mappings we've cached have changed.
629 */
630 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
631 TCGIOMMUNotifier *notifier;
632 Error *err = NULL;
633 int i, ret;
634
635 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
636 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
637 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
638 break;
639 }
640 }
641 if (i == cpu->iommu_notifiers->len) {
642 /* Not found, add a new entry at the end of the array */
643 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
644 notifier = g_new0(TCGIOMMUNotifier, 1);
645 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
646
647 notifier->mr = mr;
648 notifier->iommu_idx = iommu_idx;
649 notifier->cpu = cpu;
650 /* Rather than trying to register interest in the specific part
651 * of the iommu's address space that we've accessed and then
652 * expand it later as subsequent accesses touch more of it, we
653 * just register interest in the whole thing, on the assumption
654 * that iommu reconfiguration will be rare.
655 */
656 iommu_notifier_init(&notifier->n,
657 tcg_iommu_unmap_notify,
658 IOMMU_NOTIFIER_UNMAP,
659 0,
660 HWADDR_MAX,
661 iommu_idx);
662 ret = memory_region_register_iommu_notifier(notifier->mr, &notifier->n,
663 &err);
664 if (ret) {
665 error_report_err(err);
666 exit(1);
667 }
668 }
669
670 if (!notifier->active) {
671 notifier->active = true;
672 }
673 }
674
675 static void tcg_iommu_free_notifier_list(CPUState *cpu)
676 {
677 /* Destroy the CPU's notifier list */
678 int i;
679 TCGIOMMUNotifier *notifier;
680
681 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
682 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
683 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
684 g_free(notifier);
685 }
686 g_array_free(cpu->iommu_notifiers, true);
687 }
688
689 /* Called from RCU critical section */
690 MemoryRegionSection *
691 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
692 hwaddr *xlat, hwaddr *plen,
693 MemTxAttrs attrs, int *prot)
694 {
695 MemoryRegionSection *section;
696 IOMMUMemoryRegion *iommu_mr;
697 IOMMUMemoryRegionClass *imrc;
698 IOMMUTLBEntry iotlb;
699 int iommu_idx;
700 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
701
702 for (;;) {
703 section = address_space_translate_internal(d, addr, &addr, plen, false);
704
705 iommu_mr = memory_region_get_iommu(section->mr);
706 if (!iommu_mr) {
707 break;
708 }
709
710 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
711
712 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
713 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
714 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
715 * doesn't short-cut its translation table walk.
716 */
717 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
718 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
719 | (addr & iotlb.addr_mask));
720 /* Update the caller's prot bits to remove permissions the IOMMU
721 * is giving us a failure response for. If we get down to no
722 * permissions left at all we can give up now.
723 */
724 if (!(iotlb.perm & IOMMU_RO)) {
725 *prot &= ~(PAGE_READ | PAGE_EXEC);
726 }
727 if (!(iotlb.perm & IOMMU_WO)) {
728 *prot &= ~PAGE_WRITE;
729 }
730
731 if (!*prot) {
732 goto translate_fail;
733 }
734
735 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
736 }
737
738 assert(!memory_region_is_iommu(section->mr));
739 *xlat = addr;
740 return section;
741
742 translate_fail:
743 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
744 }
745 #endif
746
747 #if !defined(CONFIG_USER_ONLY)
748
749 static int cpu_common_post_load(void *opaque, int version_id)
750 {
751 CPUState *cpu = opaque;
752
753 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
754 version_id is increased. */
755 cpu->interrupt_request &= ~0x01;
756 tlb_flush(cpu);
757
758 /* loadvm has just updated the content of RAM, bypassing the
759 * usual mechanisms that ensure we flush TBs for writes to
760 * memory we've translated code from. So we must flush all TBs,
761 * which will now be stale.
762 */
763 tb_flush(cpu);
764
765 return 0;
766 }
767
768 static int cpu_common_pre_load(void *opaque)
769 {
770 CPUState *cpu = opaque;
771
772 cpu->exception_index = -1;
773
774 return 0;
775 }
776
777 static bool cpu_common_exception_index_needed(void *opaque)
778 {
779 CPUState *cpu = opaque;
780
781 return tcg_enabled() && cpu->exception_index != -1;
782 }
783
784 static const VMStateDescription vmstate_cpu_common_exception_index = {
785 .name = "cpu_common/exception_index",
786 .version_id = 1,
787 .minimum_version_id = 1,
788 .needed = cpu_common_exception_index_needed,
789 .fields = (VMStateField[]) {
790 VMSTATE_INT32(exception_index, CPUState),
791 VMSTATE_END_OF_LIST()
792 }
793 };
794
795 static bool cpu_common_crash_occurred_needed(void *opaque)
796 {
797 CPUState *cpu = opaque;
798
799 return cpu->crash_occurred;
800 }
801
802 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
803 .name = "cpu_common/crash_occurred",
804 .version_id = 1,
805 .minimum_version_id = 1,
806 .needed = cpu_common_crash_occurred_needed,
807 .fields = (VMStateField[]) {
808 VMSTATE_BOOL(crash_occurred, CPUState),
809 VMSTATE_END_OF_LIST()
810 }
811 };
812
813 const VMStateDescription vmstate_cpu_common = {
814 .name = "cpu_common",
815 .version_id = 1,
816 .minimum_version_id = 1,
817 .pre_load = cpu_common_pre_load,
818 .post_load = cpu_common_post_load,
819 .fields = (VMStateField[]) {
820 VMSTATE_UINT32(halted, CPUState),
821 VMSTATE_UINT32(interrupt_request, CPUState),
822 VMSTATE_END_OF_LIST()
823 },
824 .subsections = (const VMStateDescription*[]) {
825 &vmstate_cpu_common_exception_index,
826 &vmstate_cpu_common_crash_occurred,
827 NULL
828 }
829 };
830
831 #endif
832
833 CPUState *qemu_get_cpu(int index)
834 {
835 CPUState *cpu;
836
837 CPU_FOREACH(cpu) {
838 if (cpu->cpu_index == index) {
839 return cpu;
840 }
841 }
842
843 return NULL;
844 }
845
846 #if !defined(CONFIG_USER_ONLY)
847 void cpu_address_space_init(CPUState *cpu, int asidx,
848 const char *prefix, MemoryRegion *mr)
849 {
850 CPUAddressSpace *newas;
851 AddressSpace *as = g_new0(AddressSpace, 1);
852 char *as_name;
853
854 assert(mr);
855 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
856 address_space_init(as, mr, as_name);
857 g_free(as_name);
858
859 /* Target code should have set num_ases before calling us */
860 assert(asidx < cpu->num_ases);
861
862 if (asidx == 0) {
863 /* address space 0 gets the convenience alias */
864 cpu->as = as;
865 }
866
867 /* KVM cannot currently support multiple address spaces. */
868 assert(asidx == 0 || !kvm_enabled());
869
870 if (!cpu->cpu_ases) {
871 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
872 }
873
874 newas = &cpu->cpu_ases[asidx];
875 newas->cpu = cpu;
876 newas->as = as;
877 if (tcg_enabled()) {
878 newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync;
879 newas->tcg_as_listener.commit = tcg_commit;
880 memory_listener_register(&newas->tcg_as_listener, as);
881 }
882 }
883
884 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
885 {
886 /* Return the AddressSpace corresponding to the specified index */
887 return cpu->cpu_ases[asidx].as;
888 }
889 #endif
890
891 void cpu_exec_unrealizefn(CPUState *cpu)
892 {
893 CPUClass *cc = CPU_GET_CLASS(cpu);
894
895 cpu_list_remove(cpu);
896
897 if (cc->vmsd != NULL) {
898 vmstate_unregister(NULL, cc->vmsd, cpu);
899 }
900 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
901 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
902 }
903 #ifndef CONFIG_USER_ONLY
904 tcg_iommu_free_notifier_list(cpu);
905 #endif
906 }
907
908 Property cpu_common_props[] = {
909 #ifndef CONFIG_USER_ONLY
910 /* Create a memory property for softmmu CPU object,
911 * so users can wire up its memory. (This can't go in hw/core/cpu.c
912 * because that file is compiled only once for both user-mode
913 * and system builds.) The default if no link is set up is to use
914 * the system address space.
915 */
916 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
917 MemoryRegion *),
918 #endif
919 DEFINE_PROP_END_OF_LIST(),
920 };
921
922 void cpu_exec_initfn(CPUState *cpu)
923 {
924 cpu->as = NULL;
925 cpu->num_ases = 0;
926
927 #ifndef CONFIG_USER_ONLY
928 cpu->thread_id = qemu_get_thread_id();
929 cpu->memory = system_memory;
930 object_ref(OBJECT(cpu->memory));
931 #endif
932 }
933
934 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
935 {
936 CPUClass *cc = CPU_GET_CLASS(cpu);
937 static bool tcg_target_initialized;
938
939 cpu_list_add(cpu);
940
941 if (tcg_enabled() && !tcg_target_initialized) {
942 tcg_target_initialized = true;
943 cc->tcg_initialize();
944 }
945 tlb_init(cpu);
946
947 qemu_plugin_vcpu_init_hook(cpu);
948
949 #ifndef CONFIG_USER_ONLY
950 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
951 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
952 }
953 if (cc->vmsd != NULL) {
954 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
955 }
956
957 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
958 #endif
959 }
960
961 const char *parse_cpu_option(const char *cpu_option)
962 {
963 ObjectClass *oc;
964 CPUClass *cc;
965 gchar **model_pieces;
966 const char *cpu_type;
967
968 model_pieces = g_strsplit(cpu_option, ",", 2);
969 if (!model_pieces[0]) {
970 error_report("-cpu option cannot be empty");
971 exit(1);
972 }
973
974 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
975 if (oc == NULL) {
976 error_report("unable to find CPU model '%s'", model_pieces[0]);
977 g_strfreev(model_pieces);
978 exit(EXIT_FAILURE);
979 }
980
981 cpu_type = object_class_get_name(oc);
982 cc = CPU_CLASS(oc);
983 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
984 g_strfreev(model_pieces);
985 return cpu_type;
986 }
987
988 #if defined(CONFIG_USER_ONLY)
989 void tb_invalidate_phys_addr(target_ulong addr)
990 {
991 mmap_lock();
992 tb_invalidate_phys_page_range(addr, addr + 1);
993 mmap_unlock();
994 }
995
996 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
997 {
998 tb_invalidate_phys_addr(pc);
999 }
1000 #else
1001 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
1002 {
1003 ram_addr_t ram_addr;
1004 MemoryRegion *mr;
1005 hwaddr l = 1;
1006
1007 if (!tcg_enabled()) {
1008 return;
1009 }
1010
1011 RCU_READ_LOCK_GUARD();
1012 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1013 if (!(memory_region_is_ram(mr)
1014 || memory_region_is_romd(mr))) {
1015 return;
1016 }
1017 ram_addr = memory_region_get_ram_addr(mr) + addr;
1018 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
1019 }
1020
1021 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1022 {
1023 /*
1024 * There may not be a virtual to physical translation for the pc
1025 * right now, but there may exist cached TB for this pc.
1026 * Flush the whole TB cache to force re-translation of such TBs.
1027 * This is heavyweight, but we're debugging anyway.
1028 */
1029 tb_flush(cpu);
1030 }
1031 #endif
1032
1033 #ifndef CONFIG_USER_ONLY
1034 /* Add a watchpoint. */
1035 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1036 int flags, CPUWatchpoint **watchpoint)
1037 {
1038 CPUWatchpoint *wp;
1039
1040 /* forbid ranges which are empty or run off the end of the address space */
1041 if (len == 0 || (addr + len - 1) < addr) {
1042 error_report("tried to set invalid watchpoint at %"
1043 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1044 return -EINVAL;
1045 }
1046 wp = g_malloc(sizeof(*wp));
1047
1048 wp->vaddr = addr;
1049 wp->len = len;
1050 wp->flags = flags;
1051
1052 /* keep all GDB-injected watchpoints in front */
1053 if (flags & BP_GDB) {
1054 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1055 } else {
1056 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1057 }
1058
1059 tlb_flush_page(cpu, addr);
1060
1061 if (watchpoint)
1062 *watchpoint = wp;
1063 return 0;
1064 }
1065
1066 /* Remove a specific watchpoint. */
1067 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1068 int flags)
1069 {
1070 CPUWatchpoint *wp;
1071
1072 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1073 if (addr == wp->vaddr && len == wp->len
1074 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1075 cpu_watchpoint_remove_by_ref(cpu, wp);
1076 return 0;
1077 }
1078 }
1079 return -ENOENT;
1080 }
1081
1082 /* Remove a specific watchpoint by reference. */
1083 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1084 {
1085 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1086
1087 tlb_flush_page(cpu, watchpoint->vaddr);
1088
1089 g_free(watchpoint);
1090 }
1091
1092 /* Remove all matching watchpoints. */
1093 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1094 {
1095 CPUWatchpoint *wp, *next;
1096
1097 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1098 if (wp->flags & mask) {
1099 cpu_watchpoint_remove_by_ref(cpu, wp);
1100 }
1101 }
1102 }
1103
1104 /* Return true if this watchpoint address matches the specified
1105 * access (ie the address range covered by the watchpoint overlaps
1106 * partially or completely with the address range covered by the
1107 * access).
1108 */
1109 static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
1110 vaddr addr, vaddr len)
1111 {
1112 /* We know the lengths are non-zero, but a little caution is
1113 * required to avoid errors in the case where the range ends
1114 * exactly at the top of the address space and so addr + len
1115 * wraps round to zero.
1116 */
1117 vaddr wpend = wp->vaddr + wp->len - 1;
1118 vaddr addrend = addr + len - 1;
1119
1120 return !(addr > wpend || wp->vaddr > addrend);
1121 }
1122
1123 /* Return flags for watchpoints that match addr + prot. */
1124 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
1125 {
1126 CPUWatchpoint *wp;
1127 int ret = 0;
1128
1129 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1130 if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
1131 ret |= wp->flags;
1132 }
1133 }
1134 return ret;
1135 }
1136 #endif /* !CONFIG_USER_ONLY */
1137
1138 /* Add a breakpoint. */
1139 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1140 CPUBreakpoint **breakpoint)
1141 {
1142 CPUBreakpoint *bp;
1143
1144 bp = g_malloc(sizeof(*bp));
1145
1146 bp->pc = pc;
1147 bp->flags = flags;
1148
1149 /* keep all GDB-injected breakpoints in front */
1150 if (flags & BP_GDB) {
1151 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1152 } else {
1153 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1154 }
1155
1156 breakpoint_invalidate(cpu, pc);
1157
1158 if (breakpoint) {
1159 *breakpoint = bp;
1160 }
1161 return 0;
1162 }
1163
1164 /* Remove a specific breakpoint. */
1165 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1166 {
1167 CPUBreakpoint *bp;
1168
1169 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1170 if (bp->pc == pc && bp->flags == flags) {
1171 cpu_breakpoint_remove_by_ref(cpu, bp);
1172 return 0;
1173 }
1174 }
1175 return -ENOENT;
1176 }
1177
1178 /* Remove a specific breakpoint by reference. */
1179 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1180 {
1181 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1182
1183 breakpoint_invalidate(cpu, breakpoint->pc);
1184
1185 g_free(breakpoint);
1186 }
1187
1188 /* Remove all matching breakpoints. */
1189 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1190 {
1191 CPUBreakpoint *bp, *next;
1192
1193 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1194 if (bp->flags & mask) {
1195 cpu_breakpoint_remove_by_ref(cpu, bp);
1196 }
1197 }
1198 }
1199
1200 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1201 CPU loop after each instruction */
1202 void cpu_single_step(CPUState *cpu, int enabled)
1203 {
1204 if (cpu->singlestep_enabled != enabled) {
1205 cpu->singlestep_enabled = enabled;
1206 if (kvm_enabled()) {
1207 kvm_update_guest_debug(cpu, 0);
1208 } else {
1209 /* must flush all the translated code to avoid inconsistencies */
1210 /* XXX: only flush what is necessary */
1211 tb_flush(cpu);
1212 }
1213 }
1214 }
1215
1216 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1217 {
1218 va_list ap;
1219 va_list ap2;
1220
1221 va_start(ap, fmt);
1222 va_copy(ap2, ap);
1223 fprintf(stderr, "qemu: fatal: ");
1224 vfprintf(stderr, fmt, ap);
1225 fprintf(stderr, "\n");
1226 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1227 if (qemu_log_separate()) {
1228 FILE *logfile = qemu_log_lock();
1229 qemu_log("qemu: fatal: ");
1230 qemu_log_vprintf(fmt, ap2);
1231 qemu_log("\n");
1232 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1233 qemu_log_flush();
1234 qemu_log_unlock(logfile);
1235 qemu_log_close();
1236 }
1237 va_end(ap2);
1238 va_end(ap);
1239 replay_finish();
1240 #if defined(CONFIG_USER_ONLY)
1241 {
1242 struct sigaction act;
1243 sigfillset(&act.sa_mask);
1244 act.sa_handler = SIG_DFL;
1245 act.sa_flags = 0;
1246 sigaction(SIGABRT, &act, NULL);
1247 }
1248 #endif
1249 abort();
1250 }
1251
1252 #if !defined(CONFIG_USER_ONLY)
1253 /* Called from RCU critical section */
1254 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1255 {
1256 RAMBlock *block;
1257
1258 block = atomic_rcu_read(&ram_list.mru_block);
1259 if (block && addr - block->offset < block->max_length) {
1260 return block;
1261 }
1262 RAMBLOCK_FOREACH(block) {
1263 if (addr - block->offset < block->max_length) {
1264 goto found;
1265 }
1266 }
1267
1268 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1269 abort();
1270
1271 found:
1272 /* It is safe to write mru_block outside the iothread lock. This
1273 * is what happens:
1274 *
1275 * mru_block = xxx
1276 * rcu_read_unlock()
1277 * xxx removed from list
1278 * rcu_read_lock()
1279 * read mru_block
1280 * mru_block = NULL;
1281 * call_rcu(reclaim_ramblock, xxx);
1282 * rcu_read_unlock()
1283 *
1284 * atomic_rcu_set is not needed here. The block was already published
1285 * when it was placed into the list. Here we're just making an extra
1286 * copy of the pointer.
1287 */
1288 ram_list.mru_block = block;
1289 return block;
1290 }
1291
1292 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1293 {
1294 CPUState *cpu;
1295 ram_addr_t start1;
1296 RAMBlock *block;
1297 ram_addr_t end;
1298
1299 assert(tcg_enabled());
1300 end = TARGET_PAGE_ALIGN(start + length);
1301 start &= TARGET_PAGE_MASK;
1302
1303 RCU_READ_LOCK_GUARD();
1304 block = qemu_get_ram_block(start);
1305 assert(block == qemu_get_ram_block(end - 1));
1306 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1307 CPU_FOREACH(cpu) {
1308 tlb_reset_dirty(cpu, start1, length);
1309 }
1310 }
1311
1312 /* Note: start and end must be within the same ram block. */
1313 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1314 ram_addr_t length,
1315 unsigned client)
1316 {
1317 DirtyMemoryBlocks *blocks;
1318 unsigned long end, page;
1319 bool dirty = false;
1320 RAMBlock *ramblock;
1321 uint64_t mr_offset, mr_size;
1322
1323 if (length == 0) {
1324 return false;
1325 }
1326
1327 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1328 page = start >> TARGET_PAGE_BITS;
1329
1330 WITH_RCU_READ_LOCK_GUARD() {
1331 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1332 ramblock = qemu_get_ram_block(start);
1333 /* Range sanity check on the ramblock */
1334 assert(start >= ramblock->offset &&
1335 start + length <= ramblock->offset + ramblock->used_length);
1336
1337 while (page < end) {
1338 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1339 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1340 unsigned long num = MIN(end - page,
1341 DIRTY_MEMORY_BLOCK_SIZE - offset);
1342
1343 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1344 offset, num);
1345 page += num;
1346 }
1347
1348 mr_offset = (ram_addr_t)(page << TARGET_PAGE_BITS) - ramblock->offset;
1349 mr_size = (end - page) << TARGET_PAGE_BITS;
1350 memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
1351 }
1352
1353 if (dirty && tcg_enabled()) {
1354 tlb_reset_dirty_range_all(start, length);
1355 }
1356
1357 return dirty;
1358 }
1359
1360 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1361 (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client)
1362 {
1363 DirtyMemoryBlocks *blocks;
1364 ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
1365 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1366 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1367 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1368 DirtyBitmapSnapshot *snap;
1369 unsigned long page, end, dest;
1370
1371 snap = g_malloc0(sizeof(*snap) +
1372 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1373 snap->start = first;
1374 snap->end = last;
1375
1376 page = first >> TARGET_PAGE_BITS;
1377 end = last >> TARGET_PAGE_BITS;
1378 dest = 0;
1379
1380 WITH_RCU_READ_LOCK_GUARD() {
1381 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1382
1383 while (page < end) {
1384 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1385 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1386 unsigned long num = MIN(end - page,
1387 DIRTY_MEMORY_BLOCK_SIZE - offset);
1388
1389 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1390 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1391 offset >>= BITS_PER_LEVEL;
1392
1393 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1394 blocks->blocks[idx] + offset,
1395 num);
1396 page += num;
1397 dest += num >> BITS_PER_LEVEL;
1398 }
1399 }
1400
1401 if (tcg_enabled()) {
1402 tlb_reset_dirty_range_all(start, length);
1403 }
1404
1405 memory_region_clear_dirty_bitmap(mr, offset, length);
1406
1407 return snap;
1408 }
1409
1410 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1411 ram_addr_t start,
1412 ram_addr_t length)
1413 {
1414 unsigned long page, end;
1415
1416 assert(start >= snap->start);
1417 assert(start + length <= snap->end);
1418
1419 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1420 page = (start - snap->start) >> TARGET_PAGE_BITS;
1421
1422 while (page < end) {
1423 if (test_bit(page, snap->dirty)) {
1424 return true;
1425 }
1426 page++;
1427 }
1428 return false;
1429 }
1430
1431 /* Called from RCU critical section */
1432 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1433 MemoryRegionSection *section)
1434 {
1435 AddressSpaceDispatch *d = flatview_to_dispatch(section->fv);
1436 return section - d->map.sections;
1437 }
1438 #endif /* defined(CONFIG_USER_ONLY) */
1439
1440 #if !defined(CONFIG_USER_ONLY)
1441
1442 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
1443 uint16_t section);
1444 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1445
1446 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1447 qemu_anon_ram_alloc;
1448
1449 /*
1450 * Set a custom physical guest memory alloator.
1451 * Accelerators with unusual needs may need this. Hopefully, we can
1452 * get rid of it eventually.
1453 */
1454 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1455 {
1456 phys_mem_alloc = alloc;
1457 }
1458
1459 static uint16_t phys_section_add(PhysPageMap *map,
1460 MemoryRegionSection *section)
1461 {
1462 /* The physical section number is ORed with a page-aligned
1463 * pointer to produce the iotlb entries. Thus it should
1464 * never overflow into the page-aligned value.
1465 */
1466 assert(map->sections_nb < TARGET_PAGE_SIZE);
1467
1468 if (map->sections_nb == map->sections_nb_alloc) {
1469 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1470 map->sections = g_renew(MemoryRegionSection, map->sections,
1471 map->sections_nb_alloc);
1472 }
1473 map->sections[map->sections_nb] = *section;
1474 memory_region_ref(section->mr);
1475 return map->sections_nb++;
1476 }
1477
1478 static void phys_section_destroy(MemoryRegion *mr)
1479 {
1480 bool have_sub_page = mr->subpage;
1481
1482 memory_region_unref(mr);
1483
1484 if (have_sub_page) {
1485 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1486 object_unref(OBJECT(&subpage->iomem));
1487 g_free(subpage);
1488 }
1489 }
1490
1491 static void phys_sections_free(PhysPageMap *map)
1492 {
1493 while (map->sections_nb > 0) {
1494 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1495 phys_section_destroy(section->mr);
1496 }
1497 g_free(map->sections);
1498 g_free(map->nodes);
1499 }
1500
1501 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1502 {
1503 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1504 subpage_t *subpage;
1505 hwaddr base = section->offset_within_address_space
1506 & TARGET_PAGE_MASK;
1507 MemoryRegionSection *existing = phys_page_find(d, base);
1508 MemoryRegionSection subsection = {
1509 .offset_within_address_space = base,
1510 .size = int128_make64(TARGET_PAGE_SIZE),
1511 };
1512 hwaddr start, end;
1513
1514 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1515
1516 if (!(existing->mr->subpage)) {
1517 subpage = subpage_init(fv, base);
1518 subsection.fv = fv;
1519 subsection.mr = &subpage->iomem;
1520 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1521 phys_section_add(&d->map, &subsection));
1522 } else {
1523 subpage = container_of(existing->mr, subpage_t, iomem);
1524 }
1525 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1526 end = start + int128_get64(section->size) - 1;
1527 subpage_register(subpage, start, end,
1528 phys_section_add(&d->map, section));
1529 }
1530
1531
1532 static void register_multipage(FlatView *fv,
1533 MemoryRegionSection *section)
1534 {
1535 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1536 hwaddr start_addr = section->offset_within_address_space;
1537 uint16_t section_index = phys_section_add(&d->map, section);
1538 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1539 TARGET_PAGE_BITS));
1540
1541 assert(num_pages);
1542 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1543 }
1544
1545 /*
1546 * The range in *section* may look like this:
1547 *
1548 * |s|PPPPPPP|s|
1549 *
1550 * where s stands for subpage and P for page.
1551 */
1552 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1553 {
1554 MemoryRegionSection remain = *section;
1555 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1556
1557 /* register first subpage */
1558 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1559 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1560 - remain.offset_within_address_space;
1561
1562 MemoryRegionSection now = remain;
1563 now.size = int128_min(int128_make64(left), now.size);
1564 register_subpage(fv, &now);
1565 if (int128_eq(remain.size, now.size)) {
1566 return;
1567 }
1568 remain.size = int128_sub(remain.size, now.size);
1569 remain.offset_within_address_space += int128_get64(now.size);
1570 remain.offset_within_region += int128_get64(now.size);
1571 }
1572
1573 /* register whole pages */
1574 if (int128_ge(remain.size, page_size)) {
1575 MemoryRegionSection now = remain;
1576 now.size = int128_and(now.size, int128_neg(page_size));
1577 register_multipage(fv, &now);
1578 if (int128_eq(remain.size, now.size)) {
1579 return;
1580 }
1581 remain.size = int128_sub(remain.size, now.size);
1582 remain.offset_within_address_space += int128_get64(now.size);
1583 remain.offset_within_region += int128_get64(now.size);
1584 }
1585
1586 /* register last subpage */
1587 register_subpage(fv, &remain);
1588 }
1589
1590 void qemu_flush_coalesced_mmio_buffer(void)
1591 {
1592 if (kvm_enabled())
1593 kvm_flush_coalesced_mmio_buffer();
1594 }
1595
1596 void qemu_mutex_lock_ramlist(void)
1597 {
1598 qemu_mutex_lock(&ram_list.mutex);
1599 }
1600
1601 void qemu_mutex_unlock_ramlist(void)
1602 {
1603 qemu_mutex_unlock(&ram_list.mutex);
1604 }
1605
1606 void ram_block_dump(Monitor *mon)
1607 {
1608 RAMBlock *block;
1609 char *psize;
1610
1611 RCU_READ_LOCK_GUARD();
1612 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1613 "Block Name", "PSize", "Offset", "Used", "Total");
1614 RAMBLOCK_FOREACH(block) {
1615 psize = size_to_str(block->page_size);
1616 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1617 " 0x%016" PRIx64 "\n", block->idstr, psize,
1618 (uint64_t)block->offset,
1619 (uint64_t)block->used_length,
1620 (uint64_t)block->max_length);
1621 g_free(psize);
1622 }
1623 }
1624
1625 #ifdef __linux__
1626 /*
1627 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1628 * may or may not name the same files / on the same filesystem now as
1629 * when we actually open and map them. Iterate over the file
1630 * descriptors instead, and use qemu_fd_getpagesize().
1631 */
1632 static int find_min_backend_pagesize(Object *obj, void *opaque)
1633 {
1634 long *hpsize_min = opaque;
1635
1636 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1637 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1638 long hpsize = host_memory_backend_pagesize(backend);
1639
1640 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1641 *hpsize_min = hpsize;
1642 }
1643 }
1644
1645 return 0;
1646 }
1647
1648 static int find_max_backend_pagesize(Object *obj, void *opaque)
1649 {
1650 long *hpsize_max = opaque;
1651
1652 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1653 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1654 long hpsize = host_memory_backend_pagesize(backend);
1655
1656 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1657 *hpsize_max = hpsize;
1658 }
1659 }
1660
1661 return 0;
1662 }
1663
1664 /*
1665 * TODO: We assume right now that all mapped host memory backends are
1666 * used as RAM, however some might be used for different purposes.
1667 */
1668 long qemu_minrampagesize(void)
1669 {
1670 long hpsize = LONG_MAX;
1671 Object *memdev_root = object_resolve_path("/objects", NULL);
1672
1673 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1674 return hpsize;
1675 }
1676
1677 long qemu_maxrampagesize(void)
1678 {
1679 long pagesize = 0;
1680 Object *memdev_root = object_resolve_path("/objects", NULL);
1681
1682 object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize);
1683 return pagesize;
1684 }
1685 #else
1686 long qemu_minrampagesize(void)
1687 {
1688 return qemu_real_host_page_size;
1689 }
1690 long qemu_maxrampagesize(void)
1691 {
1692 return qemu_real_host_page_size;
1693 }
1694 #endif
1695
1696 #ifdef CONFIG_POSIX
1697 static int64_t get_file_size(int fd)
1698 {
1699 int64_t size;
1700 #if defined(__linux__)
1701 struct stat st;
1702
1703 if (fstat(fd, &st) < 0) {
1704 return -errno;
1705 }
1706
1707 /* Special handling for devdax character devices */
1708 if (S_ISCHR(st.st_mode)) {
1709 g_autofree char *subsystem_path = NULL;
1710 g_autofree char *subsystem = NULL;
1711
1712 subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem",
1713 major(st.st_rdev), minor(st.st_rdev));
1714 subsystem = g_file_read_link(subsystem_path, NULL);
1715
1716 if (subsystem && g_str_has_suffix(subsystem, "/dax")) {
1717 g_autofree char *size_path = NULL;
1718 g_autofree char *size_str = NULL;
1719
1720 size_path = g_strdup_printf("/sys/dev/char/%d:%d/size",
1721 major(st.st_rdev), minor(st.st_rdev));
1722
1723 if (g_file_get_contents(size_path, &size_str, NULL, NULL)) {
1724 return g_ascii_strtoll(size_str, NULL, 0);
1725 }
1726 }
1727 }
1728 #endif /* defined(__linux__) */
1729
1730 /* st.st_size may be zero for special files yet lseek(2) works */
1731 size = lseek(fd, 0, SEEK_END);
1732 if (size < 0) {
1733 return -errno;
1734 }
1735 return size;
1736 }
1737
1738 static int file_ram_open(const char *path,
1739 const char *region_name,
1740 bool *created,
1741 Error **errp)
1742 {
1743 char *filename;
1744 char *sanitized_name;
1745 char *c;
1746 int fd = -1;
1747
1748 *created = false;
1749 for (;;) {
1750 fd = open(path, O_RDWR);
1751 if (fd >= 0) {
1752 /* @path names an existing file, use it */
1753 break;
1754 }
1755 if (errno == ENOENT) {
1756 /* @path names a file that doesn't exist, create it */
1757 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1758 if (fd >= 0) {
1759 *created = true;
1760 break;
1761 }
1762 } else if (errno == EISDIR) {
1763 /* @path names a directory, create a file there */
1764 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1765 sanitized_name = g_strdup(region_name);
1766 for (c = sanitized_name; *c != '\0'; c++) {
1767 if (*c == '/') {
1768 *c = '_';
1769 }
1770 }
1771
1772 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1773 sanitized_name);
1774 g_free(sanitized_name);
1775
1776 fd = mkstemp(filename);
1777 if (fd >= 0) {
1778 unlink(filename);
1779 g_free(filename);
1780 break;
1781 }
1782 g_free(filename);
1783 }
1784 if (errno != EEXIST && errno != EINTR) {
1785 error_setg_errno(errp, errno,
1786 "can't open backing store %s for guest RAM",
1787 path);
1788 return -1;
1789 }
1790 /*
1791 * Try again on EINTR and EEXIST. The latter happens when
1792 * something else creates the file between our two open().
1793 */
1794 }
1795
1796 return fd;
1797 }
1798
1799 static void *file_ram_alloc(RAMBlock *block,
1800 ram_addr_t memory,
1801 int fd,
1802 bool truncate,
1803 Error **errp)
1804 {
1805 void *area;
1806
1807 block->page_size = qemu_fd_getpagesize(fd);
1808 if (block->mr->align % block->page_size) {
1809 error_setg(errp, "alignment 0x%" PRIx64
1810 " must be multiples of page size 0x%zx",
1811 block->mr->align, block->page_size);
1812 return NULL;
1813 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1814 error_setg(errp, "alignment 0x%" PRIx64
1815 " must be a power of two", block->mr->align);
1816 return NULL;
1817 }
1818 block->mr->align = MAX(block->page_size, block->mr->align);
1819 #if defined(__s390x__)
1820 if (kvm_enabled()) {
1821 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1822 }
1823 #endif
1824
1825 if (memory < block->page_size) {
1826 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1827 "or larger than page size 0x%zx",
1828 memory, block->page_size);
1829 return NULL;
1830 }
1831
1832 memory = ROUND_UP(memory, block->page_size);
1833
1834 /*
1835 * ftruncate is not supported by hugetlbfs in older
1836 * hosts, so don't bother bailing out on errors.
1837 * If anything goes wrong with it under other filesystems,
1838 * mmap will fail.
1839 *
1840 * Do not truncate the non-empty backend file to avoid corrupting
1841 * the existing data in the file. Disabling shrinking is not
1842 * enough. For example, the current vNVDIMM implementation stores
1843 * the guest NVDIMM labels at the end of the backend file. If the
1844 * backend file is later extended, QEMU will not be able to find
1845 * those labels. Therefore, extending the non-empty backend file
1846 * is disabled as well.
1847 */
1848 if (truncate && ftruncate(fd, memory)) {
1849 perror("ftruncate");
1850 }
1851
1852 area = qemu_ram_mmap(fd, memory, block->mr->align,
1853 block->flags & RAM_SHARED, block->flags & RAM_PMEM);
1854 if (area == MAP_FAILED) {
1855 error_setg_errno(errp, errno,
1856 "unable to map backing store for guest RAM");
1857 return NULL;
1858 }
1859
1860 block->fd = fd;
1861 return area;
1862 }
1863 #endif
1864
1865 /* Allocate space within the ram_addr_t space that governs the
1866 * dirty bitmaps.
1867 * Called with the ramlist lock held.
1868 */
1869 static ram_addr_t find_ram_offset(ram_addr_t size)
1870 {
1871 RAMBlock *block, *next_block;
1872 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1873
1874 assert(size != 0); /* it would hand out same offset multiple times */
1875
1876 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1877 return 0;
1878 }
1879
1880 RAMBLOCK_FOREACH(block) {
1881 ram_addr_t candidate, next = RAM_ADDR_MAX;
1882
1883 /* Align blocks to start on a 'long' in the bitmap
1884 * which makes the bitmap sync'ing take the fast path.
1885 */
1886 candidate = block->offset + block->max_length;
1887 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1888
1889 /* Search for the closest following block
1890 * and find the gap.
1891 */
1892 RAMBLOCK_FOREACH(next_block) {
1893 if (next_block->offset >= candidate) {
1894 next = MIN(next, next_block->offset);
1895 }
1896 }
1897
1898 /* If it fits remember our place and remember the size
1899 * of gap, but keep going so that we might find a smaller
1900 * gap to fill so avoiding fragmentation.
1901 */
1902 if (next - candidate >= size && next - candidate < mingap) {
1903 offset = candidate;
1904 mingap = next - candidate;
1905 }
1906
1907 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1908 }
1909
1910 if (offset == RAM_ADDR_MAX) {
1911 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1912 (uint64_t)size);
1913 abort();
1914 }
1915
1916 trace_find_ram_offset(size, offset);
1917
1918 return offset;
1919 }
1920
1921 static unsigned long last_ram_page(void)
1922 {
1923 RAMBlock *block;
1924 ram_addr_t last = 0;
1925
1926 RCU_READ_LOCK_GUARD();
1927 RAMBLOCK_FOREACH(block) {
1928 last = MAX(last, block->offset + block->max_length);
1929 }
1930 return last >> TARGET_PAGE_BITS;
1931 }
1932
1933 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1934 {
1935 int ret;
1936
1937 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1938 if (!machine_dump_guest_core(current_machine)) {
1939 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1940 if (ret) {
1941 perror("qemu_madvise");
1942 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1943 "but dump_guest_core=off specified\n");
1944 }
1945 }
1946 }
1947
1948 const char *qemu_ram_get_idstr(RAMBlock *rb)
1949 {
1950 return rb->idstr;
1951 }
1952
1953 void *qemu_ram_get_host_addr(RAMBlock *rb)
1954 {
1955 return rb->host;
1956 }
1957
1958 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
1959 {
1960 return rb->offset;
1961 }
1962
1963 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
1964 {
1965 return rb->used_length;
1966 }
1967
1968 bool qemu_ram_is_shared(RAMBlock *rb)
1969 {
1970 return rb->flags & RAM_SHARED;
1971 }
1972
1973 /* Note: Only set at the start of postcopy */
1974 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
1975 {
1976 return rb->flags & RAM_UF_ZEROPAGE;
1977 }
1978
1979 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
1980 {
1981 rb->flags |= RAM_UF_ZEROPAGE;
1982 }
1983
1984 bool qemu_ram_is_migratable(RAMBlock *rb)
1985 {
1986 return rb->flags & RAM_MIGRATABLE;
1987 }
1988
1989 void qemu_ram_set_migratable(RAMBlock *rb)
1990 {
1991 rb->flags |= RAM_MIGRATABLE;
1992 }
1993
1994 void qemu_ram_unset_migratable(RAMBlock *rb)
1995 {
1996 rb->flags &= ~RAM_MIGRATABLE;
1997 }
1998
1999 /* Called with iothread lock held. */
2000 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2001 {
2002 RAMBlock *block;
2003
2004 assert(new_block);
2005 assert(!new_block->idstr[0]);
2006
2007 if (dev) {
2008 char *id = qdev_get_dev_path(dev);
2009 if (id) {
2010 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2011 g_free(id);
2012 }
2013 }
2014 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2015
2016 RCU_READ_LOCK_GUARD();
2017 RAMBLOCK_FOREACH(block) {
2018 if (block != new_block &&
2019 !strcmp(block->idstr, new_block->idstr)) {
2020 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2021 new_block->idstr);
2022 abort();
2023 }
2024 }
2025 }
2026
2027 /* Called with iothread lock held. */
2028 void qemu_ram_unset_idstr(RAMBlock *block)
2029 {
2030 /* FIXME: arch_init.c assumes that this is not called throughout
2031 * migration. Ignore the problem since hot-unplug during migration
2032 * does not work anyway.
2033 */
2034 if (block) {
2035 memset(block->idstr, 0, sizeof(block->idstr));
2036 }
2037 }
2038
2039 size_t qemu_ram_pagesize(RAMBlock *rb)
2040 {
2041 return rb->page_size;
2042 }
2043
2044 /* Returns the largest size of page in use */
2045 size_t qemu_ram_pagesize_largest(void)
2046 {
2047 RAMBlock *block;
2048 size_t largest = 0;
2049
2050 RAMBLOCK_FOREACH(block) {
2051 largest = MAX(largest, qemu_ram_pagesize(block));
2052 }
2053
2054 return largest;
2055 }
2056
2057 static int memory_try_enable_merging(void *addr, size_t len)
2058 {
2059 if (!machine_mem_merge(current_machine)) {
2060 /* disabled by the user */
2061 return 0;
2062 }
2063
2064 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2065 }
2066
2067 /* Only legal before guest might have detected the memory size: e.g. on
2068 * incoming migration, or right after reset.
2069 *
2070 * As memory core doesn't know how is memory accessed, it is up to
2071 * resize callback to update device state and/or add assertions to detect
2072 * misuse, if necessary.
2073 */
2074 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2075 {
2076 assert(block);
2077
2078 newsize = HOST_PAGE_ALIGN(newsize);
2079
2080 if (block->used_length == newsize) {
2081 return 0;
2082 }
2083
2084 if (!(block->flags & RAM_RESIZEABLE)) {
2085 error_setg_errno(errp, EINVAL,
2086 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2087 " in != 0x" RAM_ADDR_FMT, block->idstr,
2088 newsize, block->used_length);
2089 return -EINVAL;
2090 }
2091
2092 if (block->max_length < newsize) {
2093 error_setg_errno(errp, EINVAL,
2094 "Length too large: %s: 0x" RAM_ADDR_FMT
2095 " > 0x" RAM_ADDR_FMT, block->idstr,
2096 newsize, block->max_length);
2097 return -EINVAL;
2098 }
2099
2100 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2101 block->used_length = newsize;
2102 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2103 DIRTY_CLIENTS_ALL);
2104 memory_region_set_size(block->mr, newsize);
2105 if (block->resized) {
2106 block->resized(block->idstr, newsize, block->host);
2107 }
2108 return 0;
2109 }
2110
2111 /*
2112 * Trigger sync on the given ram block for range [start, start + length]
2113 * with the backing store if one is available.
2114 * Otherwise no-op.
2115 * @Note: this is supposed to be a synchronous op.
2116 */
2117 void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length)
2118 {
2119 /* The requested range should fit in within the block range */
2120 g_assert((start + length) <= block->used_length);
2121
2122 #ifdef CONFIG_LIBPMEM
2123 /* The lack of support for pmem should not block the sync */
2124 if (ramblock_is_pmem(block)) {
2125 void *addr = ramblock_ptr(block, start);
2126 pmem_persist(addr, length);
2127 return;
2128 }
2129 #endif
2130 if (block->fd >= 0) {
2131 /**
2132 * Case there is no support for PMEM or the memory has not been
2133 * specified as persistent (or is not one) - use the msync.
2134 * Less optimal but still achieves the same goal
2135 */
2136 void *addr = ramblock_ptr(block, start);
2137 if (qemu_msync(addr, length, block->fd)) {
2138 warn_report("%s: failed to sync memory range: start: "
2139 RAM_ADDR_FMT " length: " RAM_ADDR_FMT,
2140 __func__, start, length);
2141 }
2142 }
2143 }
2144
2145 /* Called with ram_list.mutex held */
2146 static void dirty_memory_extend(ram_addr_t old_ram_size,
2147 ram_addr_t new_ram_size)
2148 {
2149 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2150 DIRTY_MEMORY_BLOCK_SIZE);
2151 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2152 DIRTY_MEMORY_BLOCK_SIZE);
2153 int i;
2154
2155 /* Only need to extend if block count increased */
2156 if (new_num_blocks <= old_num_blocks) {
2157 return;
2158 }
2159
2160 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2161 DirtyMemoryBlocks *old_blocks;
2162 DirtyMemoryBlocks *new_blocks;
2163 int j;
2164
2165 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
2166 new_blocks = g_malloc(sizeof(*new_blocks) +
2167 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2168
2169 if (old_num_blocks) {
2170 memcpy(new_blocks->blocks, old_blocks->blocks,
2171 old_num_blocks * sizeof(old_blocks->blocks[0]));
2172 }
2173
2174 for (j = old_num_blocks; j < new_num_blocks; j++) {
2175 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2176 }
2177
2178 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2179
2180 if (old_blocks) {
2181 g_free_rcu(old_blocks, rcu);
2182 }
2183 }
2184 }
2185
2186 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2187 {
2188 RAMBlock *block;
2189 RAMBlock *last_block = NULL;
2190 ram_addr_t old_ram_size, new_ram_size;
2191 Error *err = NULL;
2192
2193 old_ram_size = last_ram_page();
2194
2195 qemu_mutex_lock_ramlist();
2196 new_block->offset = find_ram_offset(new_block->max_length);
2197
2198 if (!new_block->host) {
2199 if (xen_enabled()) {
2200 xen_ram_alloc(new_block->offset, new_block->max_length,
2201 new_block->mr, &err);
2202 if (err) {
2203 error_propagate(errp, err);
2204 qemu_mutex_unlock_ramlist();
2205 return;
2206 }
2207 } else {
2208 new_block->host = phys_mem_alloc(new_block->max_length,
2209 &new_block->mr->align, shared);
2210 if (!new_block->host) {
2211 error_setg_errno(errp, errno,
2212 "cannot set up guest memory '%s'",
2213 memory_region_name(new_block->mr));
2214 qemu_mutex_unlock_ramlist();
2215 return;
2216 }
2217 memory_try_enable_merging(new_block->host, new_block->max_length);
2218 }
2219 }
2220
2221 new_ram_size = MAX(old_ram_size,
2222 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2223 if (new_ram_size > old_ram_size) {
2224 dirty_memory_extend(old_ram_size, new_ram_size);
2225 }
2226 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2227 * QLIST (which has an RCU-friendly variant) does not have insertion at
2228 * tail, so save the last element in last_block.
2229 */
2230 RAMBLOCK_FOREACH(block) {
2231 last_block = block;
2232 if (block->max_length < new_block->max_length) {
2233 break;
2234 }
2235 }
2236 if (block) {
2237 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2238 } else if (last_block) {
2239 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2240 } else { /* list is empty */
2241 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2242 }
2243 ram_list.mru_block = NULL;
2244
2245 /* Write list before version */
2246 smp_wmb();
2247 ram_list.version++;
2248 qemu_mutex_unlock_ramlist();
2249
2250 cpu_physical_memory_set_dirty_range(new_block->offset,
2251 new_block->used_length,
2252 DIRTY_CLIENTS_ALL);
2253
2254 if (new_block->host) {
2255 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2256 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2257 /*
2258 * MADV_DONTFORK is also needed by KVM in absence of synchronous MMU
2259 * Configure it unless the machine is a qtest server, in which case
2260 * KVM is not used and it may be forked (eg for fuzzing purposes).
2261 */
2262 if (!qtest_enabled()) {
2263 qemu_madvise(new_block->host, new_block->max_length,
2264 QEMU_MADV_DONTFORK);
2265 }
2266 ram_block_notify_add(new_block->host, new_block->max_length);
2267 }
2268 }
2269
2270 #ifdef CONFIG_POSIX
2271 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2272 uint32_t ram_flags, int fd,
2273 Error **errp)
2274 {
2275 RAMBlock *new_block;
2276 Error *local_err = NULL;
2277 int64_t file_size;
2278
2279 /* Just support these ram flags by now. */
2280 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2281
2282 if (xen_enabled()) {
2283 error_setg(errp, "-mem-path not supported with Xen");
2284 return NULL;
2285 }
2286
2287 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2288 error_setg(errp,
2289 "host lacks kvm mmu notifiers, -mem-path unsupported");
2290 return NULL;
2291 }
2292
2293 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2294 /*
2295 * file_ram_alloc() needs to allocate just like
2296 * phys_mem_alloc, but we haven't bothered to provide
2297 * a hook there.
2298 */
2299 error_setg(errp,
2300 "-mem-path not supported with this accelerator");
2301 return NULL;
2302 }
2303
2304 size = HOST_PAGE_ALIGN(size);
2305 file_size = get_file_size(fd);
2306 if (file_size > 0 && file_size < size) {
2307 error_setg(errp, "backing store size 0x%" PRIx64
2308 " does not match 'size' option 0x" RAM_ADDR_FMT,
2309 file_size, size);
2310 return NULL;
2311 }
2312
2313 new_block = g_malloc0(sizeof(*new_block));
2314 new_block->mr = mr;
2315 new_block->used_length = size;
2316 new_block->max_length = size;
2317 new_block->flags = ram_flags;
2318 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2319 if (!new_block->host) {
2320 g_free(new_block);
2321 return NULL;
2322 }
2323
2324 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2325 if (local_err) {
2326 g_free(new_block);
2327 error_propagate(errp, local_err);
2328 return NULL;
2329 }
2330 return new_block;
2331
2332 }
2333
2334
2335 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2336 uint32_t ram_flags, const char *mem_path,
2337 Error **errp)
2338 {
2339 int fd;
2340 bool created;
2341 RAMBlock *block;
2342
2343 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2344 if (fd < 0) {
2345 return NULL;
2346 }
2347
2348 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2349 if (!block) {
2350 if (created) {
2351 unlink(mem_path);
2352 }
2353 close(fd);
2354 return NULL;
2355 }
2356
2357 return block;
2358 }
2359 #endif
2360
2361 static
2362 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2363 void (*resized)(const char*,
2364 uint64_t length,
2365 void *host),
2366 void *host, bool resizeable, bool share,
2367 MemoryRegion *mr, Error **errp)
2368 {
2369 RAMBlock *new_block;
2370 Error *local_err = NULL;
2371
2372 size = HOST_PAGE_ALIGN(size);
2373 max_size = HOST_PAGE_ALIGN(max_size);
2374 new_block = g_malloc0(sizeof(*new_block));
2375 new_block->mr = mr;
2376 new_block->resized = resized;
2377 new_block->used_length = size;
2378 new_block->max_length = max_size;
2379 assert(max_size >= size);
2380 new_block->fd = -1;
2381 new_block->page_size = qemu_real_host_page_size;
2382 new_block->host = host;
2383 if (host) {
2384 new_block->flags |= RAM_PREALLOC;
2385 }
2386 if (resizeable) {
2387 new_block->flags |= RAM_RESIZEABLE;
2388 }
2389 ram_block_add(new_block, &local_err, share);
2390 if (local_err) {
2391 g_free(new_block);
2392 error_propagate(errp, local_err);
2393 return NULL;
2394 }
2395 return new_block;
2396 }
2397
2398 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2399 MemoryRegion *mr, Error **errp)
2400 {
2401 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2402 false, mr, errp);
2403 }
2404
2405 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2406 MemoryRegion *mr, Error **errp)
2407 {
2408 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2409 share, mr, errp);
2410 }
2411
2412 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2413 void (*resized)(const char*,
2414 uint64_t length,
2415 void *host),
2416 MemoryRegion *mr, Error **errp)
2417 {
2418 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2419 false, mr, errp);
2420 }
2421
2422 static void reclaim_ramblock(RAMBlock *block)
2423 {
2424 if (block->flags & RAM_PREALLOC) {
2425 ;
2426 } else if (xen_enabled()) {
2427 xen_invalidate_map_cache_entry(block->host);
2428 #ifndef _WIN32
2429 } else if (block->fd >= 0) {
2430 qemu_ram_munmap(block->fd, block->host, block->max_length);
2431 close(block->fd);
2432 #endif
2433 } else {
2434 qemu_anon_ram_free(block->host, block->max_length);
2435 }
2436 g_free(block);
2437 }
2438
2439 void qemu_ram_free(RAMBlock *block)
2440 {
2441 if (!block) {
2442 return;
2443 }
2444
2445 if (block->host) {
2446 ram_block_notify_remove(block->host, block->max_length);
2447 }
2448
2449 qemu_mutex_lock_ramlist();
2450 QLIST_REMOVE_RCU(block, next);
2451 ram_list.mru_block = NULL;
2452 /* Write list before version */
2453 smp_wmb();
2454 ram_list.version++;
2455 call_rcu(block, reclaim_ramblock, rcu);
2456 qemu_mutex_unlock_ramlist();
2457 }
2458
2459 #ifndef _WIN32
2460 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2461 {
2462 RAMBlock *block;
2463 ram_addr_t offset;
2464 int flags;
2465 void *area, *vaddr;
2466
2467 RAMBLOCK_FOREACH(block) {
2468 offset = addr - block->offset;
2469 if (offset < block->max_length) {
2470 vaddr = ramblock_ptr(block, offset);
2471 if (block->flags & RAM_PREALLOC) {
2472 ;
2473 } else if (xen_enabled()) {
2474 abort();
2475 } else {
2476 flags = MAP_FIXED;
2477 if (block->fd >= 0) {
2478 flags |= (block->flags & RAM_SHARED ?
2479 MAP_SHARED : MAP_PRIVATE);
2480 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2481 flags, block->fd, offset);
2482 } else {
2483 /*
2484 * Remap needs to match alloc. Accelerators that
2485 * set phys_mem_alloc never remap. If they did,
2486 * we'd need a remap hook here.
2487 */
2488 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2489
2490 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2491 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2492 flags, -1, 0);
2493 }
2494 if (area != vaddr) {
2495 error_report("Could not remap addr: "
2496 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2497 length, addr);
2498 exit(1);
2499 }
2500 memory_try_enable_merging(vaddr, length);
2501 qemu_ram_setup_dump(vaddr, length);
2502 }
2503 }
2504 }
2505 }
2506 #endif /* !_WIN32 */
2507
2508 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2509 * This should not be used for general purpose DMA. Use address_space_map
2510 * or address_space_rw instead. For local memory (e.g. video ram) that the
2511 * device owns, use memory_region_get_ram_ptr.
2512 *
2513 * Called within RCU critical section.
2514 */
2515 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2516 {
2517 RAMBlock *block = ram_block;
2518
2519 if (block == NULL) {
2520 block = qemu_get_ram_block(addr);
2521 addr -= block->offset;
2522 }
2523
2524 if (xen_enabled() && block->host == NULL) {
2525 /* We need to check if the requested address is in the RAM
2526 * because we don't want to map the entire memory in QEMU.
2527 * In that case just map until the end of the page.
2528 */
2529 if (block->offset == 0) {
2530 return xen_map_cache(addr, 0, 0, false);
2531 }
2532
2533 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2534 }
2535 return ramblock_ptr(block, addr);
2536 }
2537
2538 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2539 * but takes a size argument.
2540 *
2541 * Called within RCU critical section.
2542 */
2543 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2544 hwaddr *size, bool lock)
2545 {
2546 RAMBlock *block = ram_block;
2547 if (*size == 0) {
2548 return NULL;
2549 }
2550
2551 if (block == NULL) {
2552 block = qemu_get_ram_block(addr);
2553 addr -= block->offset;
2554 }
2555 *size = MIN(*size, block->max_length - addr);
2556
2557 if (xen_enabled() && block->host == NULL) {
2558 /* We need to check if the requested address is in the RAM
2559 * because we don't want to map the entire memory in QEMU.
2560 * In that case just map the requested area.
2561 */
2562 if (block->offset == 0) {
2563 return xen_map_cache(addr, *size, lock, lock);
2564 }
2565
2566 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2567 }
2568
2569 return ramblock_ptr(block, addr);
2570 }
2571
2572 /* Return the offset of a hostpointer within a ramblock */
2573 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2574 {
2575 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2576 assert((uintptr_t)host >= (uintptr_t)rb->host);
2577 assert(res < rb->max_length);
2578
2579 return res;
2580 }
2581
2582 /*
2583 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2584 * in that RAMBlock.
2585 *
2586 * ptr: Host pointer to look up
2587 * round_offset: If true round the result offset down to a page boundary
2588 * *ram_addr: set to result ram_addr
2589 * *offset: set to result offset within the RAMBlock
2590 *
2591 * Returns: RAMBlock (or NULL if not found)
2592 *
2593 * By the time this function returns, the returned pointer is not protected
2594 * by RCU anymore. If the caller is not within an RCU critical section and
2595 * does not hold the iothread lock, it must have other means of protecting the
2596 * pointer, such as a reference to the region that includes the incoming
2597 * ram_addr_t.
2598 */
2599 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2600 ram_addr_t *offset)
2601 {
2602 RAMBlock *block;
2603 uint8_t *host = ptr;
2604
2605 if (xen_enabled()) {
2606 ram_addr_t ram_addr;
2607 RCU_READ_LOCK_GUARD();
2608 ram_addr = xen_ram_addr_from_mapcache(ptr);
2609 block = qemu_get_ram_block(ram_addr);
2610 if (block) {
2611 *offset = ram_addr - block->offset;
2612 }
2613 return block;
2614 }
2615
2616 RCU_READ_LOCK_GUARD();
2617 block = atomic_rcu_read(&ram_list.mru_block);
2618 if (block && block->host && host - block->host < block->max_length) {
2619 goto found;
2620 }
2621
2622 RAMBLOCK_FOREACH(block) {
2623 /* This case append when the block is not mapped. */
2624 if (block->host == NULL) {
2625 continue;
2626 }
2627 if (host - block->host < block->max_length) {
2628 goto found;
2629 }
2630 }
2631
2632 return NULL;
2633
2634 found:
2635 *offset = (host - block->host);
2636 if (round_offset) {
2637 *offset &= TARGET_PAGE_MASK;
2638 }
2639 return block;
2640 }
2641
2642 /*
2643 * Finds the named RAMBlock
2644 *
2645 * name: The name of RAMBlock to find
2646 *
2647 * Returns: RAMBlock (or NULL if not found)
2648 */
2649 RAMBlock *qemu_ram_block_by_name(const char *name)
2650 {
2651 RAMBlock *block;
2652
2653 RAMBLOCK_FOREACH(block) {
2654 if (!strcmp(name, block->idstr)) {
2655 return block;
2656 }
2657 }
2658
2659 return NULL;
2660 }
2661
2662 /* Some of the softmmu routines need to translate from a host pointer
2663 (typically a TLB entry) back to a ram offset. */
2664 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2665 {
2666 RAMBlock *block;
2667 ram_addr_t offset;
2668
2669 block = qemu_ram_block_from_host(ptr, false, &offset);
2670 if (!block) {
2671 return RAM_ADDR_INVALID;
2672 }
2673
2674 return block->offset + offset;
2675 }
2676
2677 /* Generate a debug exception if a watchpoint has been hit. */
2678 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
2679 MemTxAttrs attrs, int flags, uintptr_t ra)
2680 {
2681 CPUClass *cc = CPU_GET_CLASS(cpu);
2682 CPUWatchpoint *wp;
2683
2684 assert(tcg_enabled());
2685 if (cpu->watchpoint_hit) {
2686 /*
2687 * We re-entered the check after replacing the TB.
2688 * Now raise the debug interrupt so that it will
2689 * trigger after the current instruction.
2690 */
2691 qemu_mutex_lock_iothread();
2692 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2693 qemu_mutex_unlock_iothread();
2694 return;
2695 }
2696
2697 addr = cc->adjust_watchpoint_address(cpu, addr, len);
2698 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2699 if (watchpoint_address_matches(wp, addr, len)
2700 && (wp->flags & flags)) {
2701 if (flags == BP_MEM_READ) {
2702 wp->flags |= BP_WATCHPOINT_HIT_READ;
2703 } else {
2704 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2705 }
2706 wp->hitaddr = MAX(addr, wp->vaddr);
2707 wp->hitattrs = attrs;
2708 if (!cpu->watchpoint_hit) {
2709 if (wp->flags & BP_CPU &&
2710 !cc->debug_check_watchpoint(cpu, wp)) {
2711 wp->flags &= ~BP_WATCHPOINT_HIT;
2712 continue;
2713 }
2714 cpu->watchpoint_hit = wp;
2715
2716 mmap_lock();
2717 tb_check_watchpoint(cpu, ra);
2718 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2719 cpu->exception_index = EXCP_DEBUG;
2720 mmap_unlock();
2721 cpu_loop_exit_restore(cpu, ra);
2722 } else {
2723 /* Force execution of one insn next time. */
2724 cpu->cflags_next_tb = 1 | curr_cflags();
2725 mmap_unlock();
2726 if (ra) {
2727 cpu_restore_state(cpu, ra, true);
2728 }
2729 cpu_loop_exit_noexc(cpu);
2730 }
2731 }
2732 } else {
2733 wp->flags &= ~BP_WATCHPOINT_HIT;
2734 }
2735 }
2736 }
2737
2738 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2739 MemTxAttrs attrs, void *buf, hwaddr len);
2740 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2741 const void *buf, hwaddr len);
2742 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2743 bool is_write, MemTxAttrs attrs);
2744
2745 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2746 unsigned len, MemTxAttrs attrs)
2747 {
2748 subpage_t *subpage = opaque;
2749 uint8_t buf[8];
2750 MemTxResult res;
2751
2752 #if defined(DEBUG_SUBPAGE)
2753 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2754 subpage, len, addr);
2755 #endif
2756 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2757 if (res) {
2758 return res;
2759 }
2760 *data = ldn_p(buf, len);
2761 return MEMTX_OK;
2762 }
2763
2764 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2765 uint64_t value, unsigned len, MemTxAttrs attrs)
2766 {
2767 subpage_t *subpage = opaque;
2768 uint8_t buf[8];
2769
2770 #if defined(DEBUG_SUBPAGE)
2771 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2772 " value %"PRIx64"\n",
2773 __func__, subpage, len, addr, value);
2774 #endif
2775 stn_p(buf, len, value);
2776 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2777 }
2778
2779 static bool subpage_accepts(void *opaque, hwaddr addr,
2780 unsigned len, bool is_write,
2781 MemTxAttrs attrs)
2782 {
2783 subpage_t *subpage = opaque;
2784 #if defined(DEBUG_SUBPAGE)
2785 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2786 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2787 #endif
2788
2789 return flatview_access_valid(subpage->fv, addr + subpage->base,
2790 len, is_write, attrs);
2791 }
2792
2793 static const MemoryRegionOps subpage_ops = {
2794 .read_with_attrs = subpage_read,
2795 .write_with_attrs = subpage_write,
2796 .impl.min_access_size = 1,
2797 .impl.max_access_size = 8,
2798 .valid.min_access_size = 1,
2799 .valid.max_access_size = 8,
2800 .valid.accepts = subpage_accepts,
2801 .endianness = DEVICE_NATIVE_ENDIAN,
2802 };
2803
2804 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
2805 uint16_t section)
2806 {
2807 int idx, eidx;
2808
2809 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2810 return -1;
2811 idx = SUBPAGE_IDX(start);
2812 eidx = SUBPAGE_IDX(end);
2813 #if defined(DEBUG_SUBPAGE)
2814 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2815 __func__, mmio, start, end, idx, eidx, section);
2816 #endif
2817 for (; idx <= eidx; idx++) {
2818 mmio->sub_section[idx] = section;
2819 }
2820
2821 return 0;
2822 }
2823
2824 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2825 {
2826 subpage_t *mmio;
2827
2828 /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */
2829 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2830 mmio->fv = fv;
2831 mmio->base = base;
2832 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2833 NULL, TARGET_PAGE_SIZE);
2834 mmio->iomem.subpage = true;
2835 #if defined(DEBUG_SUBPAGE)
2836 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2837 mmio, base, TARGET_PAGE_SIZE);
2838 #endif
2839
2840 return mmio;
2841 }
2842
2843 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2844 {
2845 assert(fv);
2846 MemoryRegionSection section = {
2847 .fv = fv,
2848 .mr = mr,
2849 .offset_within_address_space = 0,
2850 .offset_within_region = 0,
2851 .size = int128_2_64(),
2852 };
2853
2854 return phys_section_add(map, &section);
2855 }
2856
2857 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
2858 hwaddr index, MemTxAttrs attrs)
2859 {
2860 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2861 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2862 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2863 MemoryRegionSection *sections = d->map.sections;
2864
2865 return &sections[index & ~TARGET_PAGE_MASK];
2866 }
2867
2868 static void io_mem_init(void)
2869 {
2870 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2871 NULL, UINT64_MAX);
2872 }
2873
2874 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2875 {
2876 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2877 uint16_t n;
2878
2879 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2880 assert(n == PHYS_SECTION_UNASSIGNED);
2881
2882 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2883
2884 return d;
2885 }
2886
2887 void address_space_dispatch_free(AddressSpaceDispatch *d)
2888 {
2889 phys_sections_free(&d->map);
2890 g_free(d);
2891 }
2892
2893 static void do_nothing(CPUState *cpu, run_on_cpu_data d)
2894 {
2895 }
2896
2897 static void tcg_log_global_after_sync(MemoryListener *listener)
2898 {
2899 CPUAddressSpace *cpuas;
2900
2901 /* Wait for the CPU to end the current TB. This avoids the following
2902 * incorrect race:
2903 *
2904 * vCPU migration
2905 * ---------------------- -------------------------
2906 * TLB check -> slow path
2907 * notdirty_mem_write
2908 * write to RAM
2909 * mark dirty
2910 * clear dirty flag
2911 * TLB check -> fast path
2912 * read memory
2913 * write to RAM
2914 *
2915 * by pushing the migration thread's memory read after the vCPU thread has
2916 * written the memory.
2917 */
2918 if (replay_mode == REPLAY_MODE_NONE) {
2919 /*
2920 * VGA can make calls to this function while updating the screen.
2921 * In record/replay mode this causes a deadlock, because
2922 * run_on_cpu waits for rr mutex. Therefore no races are possible
2923 * in this case and no need for making run_on_cpu when
2924 * record/replay is not enabled.
2925 */
2926 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2927 run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL);
2928 }
2929 }
2930
2931 static void tcg_commit(MemoryListener *listener)
2932 {
2933 CPUAddressSpace *cpuas;
2934 AddressSpaceDispatch *d;
2935
2936 assert(tcg_enabled());
2937 /* since each CPU stores ram addresses in its TLB cache, we must
2938 reset the modified entries */
2939 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2940 cpu_reloading_memory_map();
2941 /* The CPU and TLB are protected by the iothread lock.
2942 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2943 * may have split the RCU critical section.
2944 */
2945 d = address_space_to_dispatch(cpuas->as);
2946 atomic_rcu_set(&cpuas->memory_dispatch, d);
2947 tlb_flush(cpuas->cpu);
2948 }
2949
2950 static void memory_map_init(void)
2951 {
2952 system_memory = g_malloc(sizeof(*system_memory));
2953
2954 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2955 address_space_init(&address_space_memory, system_memory, "memory");
2956
2957 system_io = g_malloc(sizeof(*system_io));
2958 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2959 65536);
2960 address_space_init(&address_space_io, system_io, "I/O");
2961 }
2962
2963 MemoryRegion *get_system_memory(void)
2964 {
2965 return system_memory;
2966 }
2967
2968 MemoryRegion *get_system_io(void)
2969 {
2970 return system_io;
2971 }
2972
2973 #endif /* !defined(CONFIG_USER_ONLY) */
2974
2975 /* physical memory access (slow version, mainly for debug) */
2976 #if defined(CONFIG_USER_ONLY)
2977 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2978 void *ptr, target_ulong len, bool is_write)
2979 {
2980 int flags;
2981 target_ulong l, page;
2982 void * p;
2983 uint8_t *buf = ptr;
2984
2985 while (len > 0) {
2986 page = addr & TARGET_PAGE_MASK;
2987 l = (page + TARGET_PAGE_SIZE) - addr;
2988 if (l > len)
2989 l = len;
2990 flags = page_get_flags(page);
2991 if (!(flags & PAGE_VALID))
2992 return -1;
2993 if (is_write) {
2994 if (!(flags & PAGE_WRITE))
2995 return -1;
2996 /* XXX: this code should not depend on lock_user */
2997 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2998 return -1;
2999 memcpy(p, buf, l);
3000 unlock_user(p, addr, l);
3001 } else {
3002 if (!(flags & PAGE_READ))
3003 return -1;
3004 /* XXX: this code should not depend on lock_user */
3005 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3006 return -1;
3007 memcpy(buf, p, l);
3008 unlock_user(p, addr, 0);
3009 }
3010 len -= l;
3011 buf += l;
3012 addr += l;
3013 }
3014 return 0;
3015 }
3016
3017 #else
3018
3019 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3020 hwaddr length)
3021 {
3022 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3023 addr += memory_region_get_ram_addr(mr);
3024
3025 /* No early return if dirty_log_mask is or becomes 0, because
3026 * cpu_physical_memory_set_dirty_range will still call
3027 * xen_modified_memory.
3028 */
3029 if (dirty_log_mask) {
3030 dirty_log_mask =
3031 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3032 }
3033 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3034 assert(tcg_enabled());
3035 tb_invalidate_phys_range(addr, addr + length);
3036 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3037 }
3038 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3039 }
3040
3041 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3042 {
3043 /*
3044 * In principle this function would work on other memory region types too,
3045 * but the ROM device use case is the only one where this operation is
3046 * necessary. Other memory regions should use the
3047 * address_space_read/write() APIs.
3048 */
3049 assert(memory_region_is_romd(mr));
3050
3051 invalidate_and_set_dirty(mr, addr, size);
3052 }
3053
3054 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3055 {
3056 unsigned access_size_max = mr->ops->valid.max_access_size;
3057
3058 /* Regions are assumed to support 1-4 byte accesses unless
3059 otherwise specified. */
3060 if (access_size_max == 0) {
3061 access_size_max = 4;
3062 }
3063
3064 /* Bound the maximum access by the alignment of the address. */
3065 if (!mr->ops->impl.unaligned) {
3066 unsigned align_size_max = addr & -addr;
3067 if (align_size_max != 0 && align_size_max < access_size_max) {
3068 access_size_max = align_size_max;
3069 }
3070 }
3071
3072 /* Don't attempt accesses larger than the maximum. */
3073 if (l > access_size_max) {
3074 l = access_size_max;
3075 }
3076 l = pow2floor(l);
3077
3078 return l;
3079 }
3080
3081 static bool prepare_mmio_access(MemoryRegion *mr)
3082 {
3083 bool unlocked = !qemu_mutex_iothread_locked();
3084 bool release_lock = false;
3085
3086 if (unlocked && mr->global_locking) {
3087 qemu_mutex_lock_iothread();
3088 unlocked = false;
3089 release_lock = true;
3090 }
3091 if (mr->flush_coalesced_mmio) {
3092 if (unlocked) {
3093 qemu_mutex_lock_iothread();
3094 }
3095 qemu_flush_coalesced_mmio_buffer();
3096 if (unlocked) {
3097 qemu_mutex_unlock_iothread();
3098 }
3099 }
3100
3101 return release_lock;
3102 }
3103
3104 /* Called within RCU critical section. */
3105 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3106 MemTxAttrs attrs,
3107 const void *ptr,
3108 hwaddr len, hwaddr addr1,
3109 hwaddr l, MemoryRegion *mr)
3110 {
3111 uint8_t *ram_ptr;
3112 uint64_t val;
3113 MemTxResult result = MEMTX_OK;
3114 bool release_lock = false;
3115 const uint8_t *buf = ptr;
3116
3117 for (;;) {
3118 if (!memory_access_is_direct(mr, true)) {
3119 release_lock |= prepare_mmio_access(mr);
3120 l = memory_access_size(mr, l, addr1);
3121 /* XXX: could force current_cpu to NULL to avoid
3122 potential bugs */
3123 val = ldn_he_p(buf, l);
3124 result |= memory_region_dispatch_write(mr, addr1, val,
3125 size_memop(l), attrs);
3126 } else {
3127 /* RAM case */
3128 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3129 memcpy(ram_ptr, buf, l);
3130 invalidate_and_set_dirty(mr, addr1, l);
3131 }
3132
3133 if (release_lock) {
3134 qemu_mutex_unlock_iothread();
3135 release_lock = false;
3136 }
3137
3138 len -= l;
3139 buf += l;
3140 addr += l;
3141
3142 if (!len) {
3143 break;
3144 }
3145
3146 l = len;
3147 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3148 }
3149
3150 return result;
3151 }
3152
3153 /* Called from RCU critical section. */
3154 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3155 const void *buf, hwaddr len)
3156 {
3157 hwaddr l;
3158 hwaddr addr1;
3159 MemoryRegion *mr;
3160 MemTxResult result = MEMTX_OK;
3161
3162 l = len;
3163 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3164 result = flatview_write_continue(fv, addr, attrs, buf, len,
3165 addr1, l, mr);
3166
3167 return result;
3168 }
3169
3170 /* Called within RCU critical section. */
3171 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3172 MemTxAttrs attrs, void *ptr,
3173 hwaddr len, hwaddr addr1, hwaddr l,
3174 MemoryRegion *mr)
3175 {
3176 uint8_t *ram_ptr;
3177 uint64_t val;
3178 MemTxResult result = MEMTX_OK;
3179 bool release_lock = false;
3180 uint8_t *buf = ptr;
3181
3182 for (;;) {
3183 if (!memory_access_is_direct(mr, false)) {
3184 /* I/O case */
3185 release_lock |= prepare_mmio_access(mr);
3186 l = memory_access_size(mr, l, addr1);
3187 result |= memory_region_dispatch_read(mr, addr1, &val,
3188 size_memop(l), attrs);
3189 stn_he_p(buf, l, val);
3190 } else {
3191 /* RAM case */
3192 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3193 memcpy(buf, ram_ptr, l);
3194 }
3195
3196 if (release_lock) {
3197 qemu_mutex_unlock_iothread();
3198 release_lock = false;
3199 }
3200
3201 len -= l;
3202 buf += l;
3203 addr += l;
3204
3205 if (!len) {
3206 break;
3207 }
3208
3209 l = len;
3210 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3211 }
3212
3213 return result;
3214 }
3215
3216 /* Called from RCU critical section. */
3217 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3218 MemTxAttrs attrs, void *buf, hwaddr len)
3219 {
3220 hwaddr l;
3221 hwaddr addr1;
3222 MemoryRegion *mr;
3223
3224 l = len;
3225 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3226 return flatview_read_continue(fv, addr, attrs, buf, len,
3227 addr1, l, mr);
3228 }
3229
3230 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3231 MemTxAttrs attrs, void *buf, hwaddr len)
3232 {
3233 MemTxResult result = MEMTX_OK;
3234 FlatView *fv;
3235
3236 if (len > 0) {
3237 RCU_READ_LOCK_GUARD();
3238 fv = address_space_to_flatview(as);
3239 result = flatview_read(fv, addr, attrs, buf, len);
3240 }
3241
3242 return result;
3243 }
3244
3245 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3246 MemTxAttrs attrs,
3247 const void *buf, hwaddr len)
3248 {
3249 MemTxResult result = MEMTX_OK;
3250 FlatView *fv;
3251
3252 if (len > 0) {
3253 RCU_READ_LOCK_GUARD();
3254 fv = address_space_to_flatview(as);
3255 result = flatview_write(fv, addr, attrs, buf, len);
3256 }
3257
3258 return result;
3259 }
3260
3261 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3262 void *buf, hwaddr len, bool is_write)
3263 {
3264 if (is_write) {
3265 return address_space_write(as, addr, attrs, buf, len);
3266 } else {
3267 return address_space_read_full(as, addr, attrs, buf, len);
3268 }
3269 }
3270
3271 void cpu_physical_memory_rw(hwaddr addr, void *buf,
3272 hwaddr len, bool is_write)
3273 {
3274 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3275 buf, len, is_write);
3276 }
3277
3278 enum write_rom_type {
3279 WRITE_DATA,
3280 FLUSH_CACHE,
3281 };
3282
3283 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3284 hwaddr addr,
3285 MemTxAttrs attrs,
3286 const void *ptr,
3287 hwaddr len,
3288 enum write_rom_type type)
3289 {
3290 hwaddr l;
3291 uint8_t *ram_ptr;
3292 hwaddr addr1;
3293 MemoryRegion *mr;
3294 const uint8_t *buf = ptr;
3295
3296 RCU_READ_LOCK_GUARD();
3297 while (len > 0) {
3298 l = len;
3299 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3300
3301 if (!(memory_region_is_ram(mr) ||
3302 memory_region_is_romd(mr))) {
3303 l = memory_access_size(mr, l, addr1);
3304 } else {
3305 /* ROM/RAM case */
3306 ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3307 switch (type) {
3308 case WRITE_DATA:
3309 memcpy(ram_ptr, buf, l);
3310 invalidate_and_set_dirty(mr, addr1, l);
3311 break;
3312 case FLUSH_CACHE:
3313 flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l);
3314 break;
3315 }
3316 }
3317 len -= l;
3318 buf += l;
3319 addr += l;
3320 }
3321 return MEMTX_OK;
3322 }
3323
3324 /* used for ROM loading : can write in RAM and ROM */
3325 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3326 MemTxAttrs attrs,
3327 const void *buf, hwaddr len)
3328 {
3329 return address_space_write_rom_internal(as, addr, attrs,
3330 buf, len, WRITE_DATA);
3331 }
3332
3333 void cpu_flush_icache_range(hwaddr start, hwaddr len)
3334 {
3335 /*
3336 * This function should do the same thing as an icache flush that was
3337 * triggered from within the guest. For TCG we are always cache coherent,
3338 * so there is no need to flush anything. For KVM / Xen we need to flush
3339 * the host's instruction cache at least.
3340 */
3341 if (tcg_enabled()) {
3342 return;
3343 }
3344
3345 address_space_write_rom_internal(&address_space_memory,
3346 start, MEMTXATTRS_UNSPECIFIED,
3347 NULL, len, FLUSH_CACHE);
3348 }
3349
3350 typedef struct {
3351 MemoryRegion *mr;
3352 void *buffer;
3353 hwaddr addr;
3354 hwaddr len;
3355 bool in_use;
3356 } BounceBuffer;
3357
3358 static BounceBuffer bounce;
3359
3360 typedef struct MapClient {
3361 QEMUBH *bh;
3362 QLIST_ENTRY(MapClient) link;
3363 } MapClient;
3364
3365 QemuMutex map_client_list_lock;
3366 static QLIST_HEAD(, MapClient) map_client_list
3367 = QLIST_HEAD_INITIALIZER(map_client_list);
3368
3369 static void cpu_unregister_map_client_do(MapClient *client)
3370 {
3371 QLIST_REMOVE(client, link);
3372 g_free(client);
3373 }
3374
3375 static void cpu_notify_map_clients_locked(void)
3376 {
3377 MapClient *client;
3378
3379 while (!QLIST_EMPTY(&map_client_list)) {
3380 client = QLIST_FIRST(&map_client_list);
3381 qemu_bh_schedule(client->bh);
3382 cpu_unregister_map_client_do(client);
3383 }
3384 }
3385
3386 void cpu_register_map_client(QEMUBH *bh)
3387 {
3388 MapClient *client = g_malloc(sizeof(*client));
3389
3390 qemu_mutex_lock(&map_client_list_lock);
3391 client->bh = bh;
3392 QLIST_INSERT_HEAD(&map_client_list, client, link);
3393 if (!atomic_read(&bounce.in_use)) {
3394 cpu_notify_map_clients_locked();
3395 }
3396 qemu_mutex_unlock(&map_client_list_lock);
3397 }
3398
3399 void cpu_exec_init_all(void)
3400 {
3401 qemu_mutex_init(&ram_list.mutex);
3402 /* The data structures we set up here depend on knowing the page size,
3403 * so no more changes can be made after this point.
3404 * In an ideal world, nothing we did before we had finished the
3405 * machine setup would care about the target page size, and we could
3406 * do this much later, rather than requiring board models to state
3407 * up front what their requirements are.
3408 */
3409 finalize_target_page_bits();
3410 io_mem_init();
3411 memory_map_init();
3412 qemu_mutex_init(&map_client_list_lock);
3413 }
3414
3415 void cpu_unregister_map_client(QEMUBH *bh)
3416 {
3417 MapClient *client;
3418
3419 qemu_mutex_lock(&map_client_list_lock);
3420 QLIST_FOREACH(client, &map_client_list, link) {
3421 if (client->bh == bh) {
3422 cpu_unregister_map_client_do(client);
3423 break;
3424 }
3425 }
3426 qemu_mutex_unlock(&map_client_list_lock);
3427 }
3428
3429 static void cpu_notify_map_clients(void)
3430 {
3431 qemu_mutex_lock(&map_client_list_lock);
3432 cpu_notify_map_clients_locked();
3433 qemu_mutex_unlock(&map_client_list_lock);
3434 }
3435
3436 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
3437 bool is_write, MemTxAttrs attrs)
3438 {
3439 MemoryRegion *mr;
3440 hwaddr l, xlat;
3441
3442 while (len > 0) {
3443 l = len;
3444 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3445 if (!memory_access_is_direct(mr, is_write)) {
3446 l = memory_access_size(mr, l, addr);
3447 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3448 return false;
3449 }
3450 }
3451
3452 len -= l;
3453 addr += l;
3454 }
3455 return true;
3456 }
3457
3458 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3459 hwaddr len, bool is_write,
3460 MemTxAttrs attrs)
3461 {
3462 FlatView *fv;
3463 bool result;
3464
3465 RCU_READ_LOCK_GUARD();
3466 fv = address_space_to_flatview(as);
3467 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3468 return result;
3469 }
3470
3471 static hwaddr
3472 flatview_extend_translation(FlatView *fv, hwaddr addr,
3473 hwaddr target_len,
3474 MemoryRegion *mr, hwaddr base, hwaddr len,
3475 bool is_write, MemTxAttrs attrs)
3476 {
3477 hwaddr done = 0;
3478 hwaddr xlat;
3479 MemoryRegion *this_mr;
3480
3481 for (;;) {
3482 target_len -= len;
3483 addr += len;
3484 done += len;
3485 if (target_len == 0) {
3486 return done;
3487 }
3488
3489 len = target_len;
3490 this_mr = flatview_translate(fv, addr, &xlat,
3491 &len, is_write, attrs);
3492 if (this_mr != mr || xlat != base + done) {
3493 return done;
3494 }
3495 }
3496 }
3497
3498 /* Map a physical memory region into a host virtual address.
3499 * May map a subset of the requested range, given by and returned in *plen.
3500 * May return NULL if resources needed to perform the mapping are exhausted.
3501 * Use only for reads OR writes - not for read-modify-write operations.
3502 * Use cpu_register_map_client() to know when retrying the map operation is
3503 * likely to succeed.
3504 */
3505 void *address_space_map(AddressSpace *as,
3506 hwaddr addr,
3507 hwaddr *plen,
3508 bool is_write,
3509 MemTxAttrs attrs)
3510 {
3511 hwaddr len = *plen;
3512 hwaddr l, xlat;
3513 MemoryRegion *mr;
3514 void *ptr;
3515 FlatView *fv;
3516
3517 if (len == 0) {
3518 return NULL;
3519 }
3520
3521 l = len;
3522 RCU_READ_LOCK_GUARD();
3523 fv = address_space_to_flatview(as);
3524 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3525
3526 if (!memory_access_is_direct(mr, is_write)) {
3527 if (atomic_xchg(&bounce.in_use, true)) {
3528 return NULL;
3529 }
3530 /* Avoid unbounded allocations */
3531 l = MIN(l, TARGET_PAGE_SIZE);
3532 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3533 bounce.addr = addr;
3534 bounce.len = l;
3535
3536 memory_region_ref(mr);
3537 bounce.mr = mr;
3538 if (!is_write) {
3539 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3540 bounce.buffer, l);
3541 }
3542
3543 *plen = l;
3544 return bounce.buffer;
3545 }
3546
3547
3548 memory_region_ref(mr);
3549 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3550 l, is_write, attrs);
3551 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3552
3553 return ptr;
3554 }
3555
3556 /* Unmaps a memory region previously mapped by address_space_map().
3557 * Will also mark the memory as dirty if is_write is true. access_len gives
3558 * the amount of memory that was actually read or written by the caller.
3559 */
3560 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3561 bool is_write, hwaddr access_len)
3562 {
3563 if (buffer != bounce.buffer) {
3564 MemoryRegion *mr;
3565 ram_addr_t addr1;
3566
3567 mr = memory_region_from_host(buffer, &addr1);
3568 assert(mr != NULL);
3569 if (is_write) {
3570 invalidate_and_set_dirty(mr, addr1, access_len);
3571 }
3572 if (xen_enabled()) {
3573 xen_invalidate_map_cache_entry(buffer);
3574 }
3575 memory_region_unref(mr);
3576 return;
3577 }
3578 if (is_write) {
3579 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3580 bounce.buffer, access_len);
3581 }
3582 qemu_vfree(bounce.buffer);
3583 bounce.buffer = NULL;