Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
34 #endif
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "qemu/timer.h"
39 #include "qemu/config-file.h"
40 #include "qemu/error-report.h"
41 #include "qemu/qemu-print.h"
42 #if defined(CONFIG_USER_ONLY)
43 #include "qemu.h"
44 #else /* !CONFIG_USER_ONLY */
45 #include "exec/memory.h"
46 #include "exec/ioport.h"
47 #include "sysemu/dma.h"
48 #include "sysemu/hostmem.h"
49 #include "sysemu/hw_accel.h"
50 #include "exec/address-spaces.h"
51 #include "sysemu/xen-mapcache.h"
52 #include "trace-root.h"
53
54 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
55 #include <linux/falloc.h>
56 #endif
57
58 #endif
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
63
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
66 #include "exec/log.h"
67
68 #include "migration/vmstate.h"
69
70 #include "qemu/range.h"
71 #ifndef _WIN32
72 #include "qemu/mmap-alloc.h"
73 #endif
74
75 #include "monitor/monitor.h"
76
77 //#define DEBUG_SUBPAGE
78
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
82 */
83 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
84
85 static MemoryRegion *system_memory;
86 static MemoryRegion *system_io;
87
88 AddressSpace address_space_io;
89 AddressSpace address_space_memory;
90
91 MemoryRegion io_mem_rom, io_mem_notdirty;
92 static MemoryRegion io_mem_unassigned;
93 #endif
94
95 #ifdef TARGET_PAGE_BITS_VARY
96 int target_page_bits;
97 bool target_page_bits_decided;
98 #endif
99
100 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
101
102 /* current CPU in the current thread. It is only valid inside
103 cpu_exec() */
104 __thread CPUState *current_cpu;
105 /* 0 = Do not count executed instructions.
106 1 = Precise instruction counting.
107 2 = Adaptive rate instruction counting. */
108 int use_icount;
109
110 uintptr_t qemu_host_page_size;
111 intptr_t qemu_host_page_mask;
112
113 bool set_preferred_target_page_bits(int bits)
114 {
115 /* The target page size is the lowest common denominator for all
116 * the CPUs in the system, so we can only make it smaller, never
117 * larger. And we can't make it smaller once we've committed to
118 * a particular size.
119 */
120 #ifdef TARGET_PAGE_BITS_VARY
121 assert(bits >= TARGET_PAGE_BITS_MIN);
122 if (target_page_bits == 0 || target_page_bits > bits) {
123 if (target_page_bits_decided) {
124 return false;
125 }
126 target_page_bits = bits;
127 }
128 #endif
129 return true;
130 }
131
132 #if !defined(CONFIG_USER_ONLY)
133
134 static void finalize_target_page_bits(void)
135 {
136 #ifdef TARGET_PAGE_BITS_VARY
137 if (target_page_bits == 0) {
138 target_page_bits = TARGET_PAGE_BITS_MIN;
139 }
140 target_page_bits_decided = true;
141 #endif
142 }
143
144 typedef struct PhysPageEntry PhysPageEntry;
145
146 struct PhysPageEntry {
147 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
148 uint32_t skip : 6;
149 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
150 uint32_t ptr : 26;
151 };
152
153 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
154
155 /* Size of the L2 (and L3, etc) page tables. */
156 #define ADDR_SPACE_BITS 64
157
158 #define P_L2_BITS 9
159 #define P_L2_SIZE (1 << P_L2_BITS)
160
161 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
162
163 typedef PhysPageEntry Node[P_L2_SIZE];
164
165 typedef struct PhysPageMap {
166 struct rcu_head rcu;
167
168 unsigned sections_nb;
169 unsigned sections_nb_alloc;
170 unsigned nodes_nb;
171 unsigned nodes_nb_alloc;
172 Node *nodes;
173 MemoryRegionSection *sections;
174 } PhysPageMap;
175
176 struct AddressSpaceDispatch {
177 MemoryRegionSection *mru_section;
178 /* This is a multi-level map on the physical address space.
179 * The bottom level has pointers to MemoryRegionSections.
180 */
181 PhysPageEntry phys_map;
182 PhysPageMap map;
183 };
184
185 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
186 typedef struct subpage_t {
187 MemoryRegion iomem;
188 FlatView *fv;
189 hwaddr base;
190 uint16_t sub_section[];
191 } subpage_t;
192
193 #define PHYS_SECTION_UNASSIGNED 0
194 #define PHYS_SECTION_NOTDIRTY 1
195 #define PHYS_SECTION_ROM 2
196 #define PHYS_SECTION_WATCH 3
197
198 static void io_mem_init(void);
199 static void memory_map_init(void);
200 static void tcg_log_global_after_sync(MemoryListener *listener);
201 static void tcg_commit(MemoryListener *listener);
202
203 static MemoryRegion io_mem_watch;
204
205 /**
206 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
207 * @cpu: the CPU whose AddressSpace this is
208 * @as: the AddressSpace itself
209 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
210 * @tcg_as_listener: listener for tracking changes to the AddressSpace
211 */
212 struct CPUAddressSpace {
213 CPUState *cpu;
214 AddressSpace *as;
215 struct AddressSpaceDispatch *memory_dispatch;
216 MemoryListener tcg_as_listener;
217 };
218
219 struct DirtyBitmapSnapshot {
220 ram_addr_t start;
221 ram_addr_t end;
222 unsigned long dirty[];
223 };
224
225 #endif
226
227 #if !defined(CONFIG_USER_ONLY)
228
229 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
230 {
231 static unsigned alloc_hint = 16;
232 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
233 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
234 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
235 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
236 alloc_hint = map->nodes_nb_alloc;
237 }
238 }
239
240 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
241 {
242 unsigned i;
243 uint32_t ret;
244 PhysPageEntry e;
245 PhysPageEntry *p;
246
247 ret = map->nodes_nb++;
248 p = map->nodes[ret];
249 assert(ret != PHYS_MAP_NODE_NIL);
250 assert(ret != map->nodes_nb_alloc);
251
252 e.skip = leaf ? 0 : 1;
253 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
254 for (i = 0; i < P_L2_SIZE; ++i) {
255 memcpy(&p[i], &e, sizeof(e));
256 }
257 return ret;
258 }
259
260 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
261 hwaddr *index, hwaddr *nb, uint16_t leaf,
262 int level)
263 {
264 PhysPageEntry *p;
265 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
266
267 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
268 lp->ptr = phys_map_node_alloc(map, level == 0);
269 }
270 p = map->nodes[lp->ptr];
271 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
272
273 while (*nb && lp < &p[P_L2_SIZE]) {
274 if ((*index & (step - 1)) == 0 && *nb >= step) {
275 lp->skip = 0;
276 lp->ptr = leaf;
277 *index += step;
278 *nb -= step;
279 } else {
280 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
281 }
282 ++lp;
283 }
284 }
285
286 static void phys_page_set(AddressSpaceDispatch *d,
287 hwaddr index, hwaddr nb,
288 uint16_t leaf)
289 {
290 /* Wildly overreserve - it doesn't matter much. */
291 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
292
293 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
294 }
295
296 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
297 * and update our entry so we can skip it and go directly to the destination.
298 */
299 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
300 {
301 unsigned valid_ptr = P_L2_SIZE;
302 int valid = 0;
303 PhysPageEntry *p;
304 int i;
305
306 if (lp->ptr == PHYS_MAP_NODE_NIL) {
307 return;
308 }
309
310 p = nodes[lp->ptr];
311 for (i = 0; i < P_L2_SIZE; i++) {
312 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
313 continue;
314 }
315
316 valid_ptr = i;
317 valid++;
318 if (p[i].skip) {
319 phys_page_compact(&p[i], nodes);
320 }
321 }
322
323 /* We can only compress if there's only one child. */
324 if (valid != 1) {
325 return;
326 }
327
328 assert(valid_ptr < P_L2_SIZE);
329
330 /* Don't compress if it won't fit in the # of bits we have. */
331 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
332 return;
333 }
334
335 lp->ptr = p[valid_ptr].ptr;
336 if (!p[valid_ptr].skip) {
337 /* If our only child is a leaf, make this a leaf. */
338 /* By design, we should have made this node a leaf to begin with so we
339 * should never reach here.
340 * But since it's so simple to handle this, let's do it just in case we
341 * change this rule.
342 */
343 lp->skip = 0;
344 } else {
345 lp->skip += p[valid_ptr].skip;
346 }
347 }
348
349 void address_space_dispatch_compact(AddressSpaceDispatch *d)
350 {
351 if (d->phys_map.skip) {
352 phys_page_compact(&d->phys_map, d->map.nodes);
353 }
354 }
355
356 static inline bool section_covers_addr(const MemoryRegionSection *section,
357 hwaddr addr)
358 {
359 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
360 * the section must cover the entire address space.
361 */
362 return int128_gethi(section->size) ||
363 range_covers_byte(section->offset_within_address_space,
364 int128_getlo(section->size), addr);
365 }
366
367 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
368 {
369 PhysPageEntry lp = d->phys_map, *p;
370 Node *nodes = d->map.nodes;
371 MemoryRegionSection *sections = d->map.sections;
372 hwaddr index = addr >> TARGET_PAGE_BITS;
373 int i;
374
375 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
376 if (lp.ptr == PHYS_MAP_NODE_NIL) {
377 return &sections[PHYS_SECTION_UNASSIGNED];
378 }
379 p = nodes[lp.ptr];
380 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
381 }
382
383 if (section_covers_addr(&sections[lp.ptr], addr)) {
384 return &sections[lp.ptr];
385 } else {
386 return &sections[PHYS_SECTION_UNASSIGNED];
387 }
388 }
389
390 /* Called from RCU critical section */
391 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
392 hwaddr addr,
393 bool resolve_subpage)
394 {
395 MemoryRegionSection *section = atomic_read(&d->mru_section);
396 subpage_t *subpage;
397
398 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
399 !section_covers_addr(section, addr)) {
400 section = phys_page_find(d, addr);
401 atomic_set(&d->mru_section, section);
402 }
403 if (resolve_subpage && section->mr->subpage) {
404 subpage = container_of(section->mr, subpage_t, iomem);
405 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
406 }
407 return section;
408 }
409
410 /* Called from RCU critical section */
411 static MemoryRegionSection *
412 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
413 hwaddr *plen, bool resolve_subpage)
414 {
415 MemoryRegionSection *section;
416 MemoryRegion *mr;
417 Int128 diff;
418
419 section = address_space_lookup_region(d, addr, resolve_subpage);
420 /* Compute offset within MemoryRegionSection */
421 addr -= section->offset_within_address_space;
422
423 /* Compute offset within MemoryRegion */
424 *xlat = addr + section->offset_within_region;
425
426 mr = section->mr;
427
428 /* MMIO registers can be expected to perform full-width accesses based only
429 * on their address, without considering adjacent registers that could
430 * decode to completely different MemoryRegions. When such registers
431 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
432 * regions overlap wildly. For this reason we cannot clamp the accesses
433 * here.
434 *
435 * If the length is small (as is the case for address_space_ldl/stl),
436 * everything works fine. If the incoming length is large, however,
437 * the caller really has to do the clamping through memory_access_size.
438 */
439 if (memory_region_is_ram(mr)) {
440 diff = int128_sub(section->size, int128_make64(addr));
441 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
442 }
443 return section;
444 }
445
446 /**
447 * address_space_translate_iommu - translate an address through an IOMMU
448 * memory region and then through the target address space.
449 *
450 * @iommu_mr: the IOMMU memory region that we start the translation from
451 * @addr: the address to be translated through the MMU
452 * @xlat: the translated address offset within the destination memory region.
453 * It cannot be %NULL.
454 * @plen_out: valid read/write length of the translated address. It
455 * cannot be %NULL.
456 * @page_mask_out: page mask for the translated address. This
457 * should only be meaningful for IOMMU translated
458 * addresses, since there may be huge pages that this bit
459 * would tell. It can be %NULL if we don't care about it.
460 * @is_write: whether the translation operation is for write
461 * @is_mmio: whether this can be MMIO, set true if it can
462 * @target_as: the address space targeted by the IOMMU
463 * @attrs: transaction attributes
464 *
465 * This function is called from RCU critical section. It is the common
466 * part of flatview_do_translate and address_space_translate_cached.
467 */
468 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
469 hwaddr *xlat,
470 hwaddr *plen_out,
471 hwaddr *page_mask_out,
472 bool is_write,
473 bool is_mmio,
474 AddressSpace **target_as,
475 MemTxAttrs attrs)
476 {
477 MemoryRegionSection *section;
478 hwaddr page_mask = (hwaddr)-1;
479
480 do {
481 hwaddr addr = *xlat;
482 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
483 int iommu_idx = 0;
484 IOMMUTLBEntry iotlb;
485
486 if (imrc->attrs_to_index) {
487 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
488 }
489
490 iotlb = imrc->translate(iommu_mr, addr, is_write ?
491 IOMMU_WO : IOMMU_RO, iommu_idx);
492
493 if (!(iotlb.perm & (1 << is_write))) {
494 goto unassigned;
495 }
496
497 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
498 | (addr & iotlb.addr_mask));
499 page_mask &= iotlb.addr_mask;
500 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
501 *target_as = iotlb.target_as;
502
503 section = address_space_translate_internal(
504 address_space_to_dispatch(iotlb.target_as), addr, xlat,
505 plen_out, is_mmio);
506
507 iommu_mr = memory_region_get_iommu(section->mr);
508 } while (unlikely(iommu_mr));
509
510 if (page_mask_out) {
511 *page_mask_out = page_mask;
512 }
513 return *section;
514
515 unassigned:
516 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
517 }
518
519 /**
520 * flatview_do_translate - translate an address in FlatView
521 *
522 * @fv: the flat view that we want to translate on
523 * @addr: the address to be translated in above address space
524 * @xlat: the translated address offset within memory region. It
525 * cannot be @NULL.
526 * @plen_out: valid read/write length of the translated address. It
527 * can be @NULL when we don't care about it.
528 * @page_mask_out: page mask for the translated address. This
529 * should only be meaningful for IOMMU translated
530 * addresses, since there may be huge pages that this bit
531 * would tell. It can be @NULL if we don't care about it.
532 * @is_write: whether the translation operation is for write
533 * @is_mmio: whether this can be MMIO, set true if it can
534 * @target_as: the address space targeted by the IOMMU
535 * @attrs: memory transaction attributes
536 *
537 * This function is called from RCU critical section
538 */
539 static MemoryRegionSection flatview_do_translate(FlatView *fv,
540 hwaddr addr,
541 hwaddr *xlat,
542 hwaddr *plen_out,
543 hwaddr *page_mask_out,
544 bool is_write,
545 bool is_mmio,
546 AddressSpace **target_as,
547 MemTxAttrs attrs)
548 {
549 MemoryRegionSection *section;
550 IOMMUMemoryRegion *iommu_mr;
551 hwaddr plen = (hwaddr)(-1);
552
553 if (!plen_out) {
554 plen_out = &plen;
555 }
556
557 section = address_space_translate_internal(
558 flatview_to_dispatch(fv), addr, xlat,
559 plen_out, is_mmio);
560
561 iommu_mr = memory_region_get_iommu(section->mr);
562 if (unlikely(iommu_mr)) {
563 return address_space_translate_iommu(iommu_mr, xlat,
564 plen_out, page_mask_out,
565 is_write, is_mmio,
566 target_as, attrs);
567 }
568 if (page_mask_out) {
569 /* Not behind an IOMMU, use default page size. */
570 *page_mask_out = ~TARGET_PAGE_MASK;
571 }
572
573 return *section;
574 }
575
576 /* Called from RCU critical section */
577 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
578 bool is_write, MemTxAttrs attrs)
579 {
580 MemoryRegionSection section;
581 hwaddr xlat, page_mask;
582
583 /*
584 * This can never be MMIO, and we don't really care about plen,
585 * but page mask.
586 */
587 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
588 NULL, &page_mask, is_write, false, &as,
589 attrs);
590
591 /* Illegal translation */
592 if (section.mr == &io_mem_unassigned) {
593 goto iotlb_fail;
594 }
595
596 /* Convert memory region offset into address space offset */
597 xlat += section.offset_within_address_space -
598 section.offset_within_region;
599
600 return (IOMMUTLBEntry) {
601 .target_as = as,
602 .iova = addr & ~page_mask,
603 .translated_addr = xlat & ~page_mask,
604 .addr_mask = page_mask,
605 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
606 .perm = IOMMU_RW,
607 };
608
609 iotlb_fail:
610 return (IOMMUTLBEntry) {0};
611 }
612
613 /* Called from RCU critical section */
614 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
615 hwaddr *plen, bool is_write,
616 MemTxAttrs attrs)
617 {
618 MemoryRegion *mr;
619 MemoryRegionSection section;
620 AddressSpace *as = NULL;
621
622 /* This can be MMIO, so setup MMIO bit. */
623 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
624 is_write, true, &as, attrs);
625 mr = section.mr;
626
627 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
628 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
629 *plen = MIN(page, *plen);
630 }
631
632 return mr;
633 }
634
635 typedef struct TCGIOMMUNotifier {
636 IOMMUNotifier n;
637 MemoryRegion *mr;
638 CPUState *cpu;
639 int iommu_idx;
640 bool active;
641 } TCGIOMMUNotifier;
642
643 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
644 {
645 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
646
647 if (!notifier->active) {
648 return;
649 }
650 tlb_flush(notifier->cpu);
651 notifier->active = false;
652 /* We leave the notifier struct on the list to avoid reallocating it later.
653 * Generally the number of IOMMUs a CPU deals with will be small.
654 * In any case we can't unregister the iommu notifier from a notify
655 * callback.
656 */
657 }
658
659 static void tcg_register_iommu_notifier(CPUState *cpu,
660 IOMMUMemoryRegion *iommu_mr,
661 int iommu_idx)
662 {
663 /* Make sure this CPU has an IOMMU notifier registered for this
664 * IOMMU/IOMMU index combination, so that we can flush its TLB
665 * when the IOMMU tells us the mappings we've cached have changed.
666 */
667 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
668 TCGIOMMUNotifier *notifier;
669 int i;
670
671 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
672 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
673 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
674 break;
675 }
676 }
677 if (i == cpu->iommu_notifiers->len) {
678 /* Not found, add a new entry at the end of the array */
679 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
680 notifier = g_new0(TCGIOMMUNotifier, 1);
681 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
682
683 notifier->mr = mr;
684 notifier->iommu_idx = iommu_idx;
685 notifier->cpu = cpu;
686 /* Rather than trying to register interest in the specific part
687 * of the iommu's address space that we've accessed and then
688 * expand it later as subsequent accesses touch more of it, we
689 * just register interest in the whole thing, on the assumption
690 * that iommu reconfiguration will be rare.
691 */
692 iommu_notifier_init(&notifier->n,
693 tcg_iommu_unmap_notify,
694 IOMMU_NOTIFIER_UNMAP,
695 0,
696 HWADDR_MAX,
697 iommu_idx);
698 memory_region_register_iommu_notifier(notifier->mr, &notifier->n);
699 }
700
701 if (!notifier->active) {
702 notifier->active = true;
703 }
704 }
705
706 static void tcg_iommu_free_notifier_list(CPUState *cpu)
707 {
708 /* Destroy the CPU's notifier list */
709 int i;
710 TCGIOMMUNotifier *notifier;
711
712 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
713 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
714 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
715 g_free(notifier);
716 }
717 g_array_free(cpu->iommu_notifiers, true);
718 }
719
720 /* Called from RCU critical section */
721 MemoryRegionSection *
722 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
723 hwaddr *xlat, hwaddr *plen,
724 MemTxAttrs attrs, int *prot)
725 {
726 MemoryRegionSection *section;
727 IOMMUMemoryRegion *iommu_mr;
728 IOMMUMemoryRegionClass *imrc;
729 IOMMUTLBEntry iotlb;
730 int iommu_idx;
731 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
732
733 for (;;) {
734 section = address_space_translate_internal(d, addr, &addr, plen, false);
735
736 iommu_mr = memory_region_get_iommu(section->mr);
737 if (!iommu_mr) {
738 break;
739 }
740
741 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
742
743 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
744 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
745 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
746 * doesn't short-cut its translation table walk.
747 */
748 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
749 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
750 | (addr & iotlb.addr_mask));
751 /* Update the caller's prot bits to remove permissions the IOMMU
752 * is giving us a failure response for. If we get down to no
753 * permissions left at all we can give up now.
754 */
755 if (!(iotlb.perm & IOMMU_RO)) {
756 *prot &= ~(PAGE_READ | PAGE_EXEC);
757 }
758 if (!(iotlb.perm & IOMMU_WO)) {
759 *prot &= ~PAGE_WRITE;
760 }
761
762 if (!*prot) {
763 goto translate_fail;
764 }
765
766 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
767 }
768
769 assert(!memory_region_is_iommu(section->mr));
770 *xlat = addr;
771 return section;
772
773 translate_fail:
774 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
775 }
776 #endif
777
778 #if !defined(CONFIG_USER_ONLY)
779
780 static int cpu_common_post_load(void *opaque, int version_id)
781 {
782 CPUState *cpu = opaque;
783
784 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
785 version_id is increased. */
786 cpu->interrupt_request &= ~0x01;
787 tlb_flush(cpu);
788
789 /* loadvm has just updated the content of RAM, bypassing the
790 * usual mechanisms that ensure we flush TBs for writes to
791 * memory we've translated code from. So we must flush all TBs,
792 * which will now be stale.
793 */
794 tb_flush(cpu);
795
796 return 0;
797 }
798
799 static int cpu_common_pre_load(void *opaque)
800 {
801 CPUState *cpu = opaque;
802
803 cpu->exception_index = -1;
804
805 return 0;
806 }
807
808 static bool cpu_common_exception_index_needed(void *opaque)
809 {
810 CPUState *cpu = opaque;
811
812 return tcg_enabled() && cpu->exception_index != -1;
813 }
814
815 static const VMStateDescription vmstate_cpu_common_exception_index = {
816 .name = "cpu_common/exception_index",
817 .version_id = 1,
818 .minimum_version_id = 1,
819 .needed = cpu_common_exception_index_needed,
820 .fields = (VMStateField[]) {
821 VMSTATE_INT32(exception_index, CPUState),
822 VMSTATE_END_OF_LIST()
823 }
824 };
825
826 static bool cpu_common_crash_occurred_needed(void *opaque)
827 {
828 CPUState *cpu = opaque;
829
830 return cpu->crash_occurred;
831 }
832
833 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
834 .name = "cpu_common/crash_occurred",
835 .version_id = 1,
836 .minimum_version_id = 1,
837 .needed = cpu_common_crash_occurred_needed,
838 .fields = (VMStateField[]) {
839 VMSTATE_BOOL(crash_occurred, CPUState),
840 VMSTATE_END_OF_LIST()
841 }
842 };
843
844 const VMStateDescription vmstate_cpu_common = {
845 .name = "cpu_common",
846 .version_id = 1,
847 .minimum_version_id = 1,
848 .pre_load = cpu_common_pre_load,
849 .post_load = cpu_common_post_load,
850 .fields = (VMStateField[]) {
851 VMSTATE_UINT32(halted, CPUState),
852 VMSTATE_UINT32(interrupt_request, CPUState),
853 VMSTATE_END_OF_LIST()
854 },
855 .subsections = (const VMStateDescription*[]) {
856 &vmstate_cpu_common_exception_index,
857 &vmstate_cpu_common_crash_occurred,
858 NULL
859 }
860 };
861
862 #endif
863
864 CPUState *qemu_get_cpu(int index)
865 {
866 CPUState *cpu;
867
868 CPU_FOREACH(cpu) {
869 if (cpu->cpu_index == index) {
870 return cpu;
871 }
872 }
873
874 return NULL;
875 }
876
877 #if !defined(CONFIG_USER_ONLY)
878 void cpu_address_space_init(CPUState *cpu, int asidx,
879 const char *prefix, MemoryRegion *mr)
880 {
881 CPUAddressSpace *newas;
882 AddressSpace *as = g_new0(AddressSpace, 1);
883 char *as_name;
884
885 assert(mr);
886 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
887 address_space_init(as, mr, as_name);
888 g_free(as_name);
889
890 /* Target code should have set num_ases before calling us */
891 assert(asidx < cpu->num_ases);
892
893 if (asidx == 0) {
894 /* address space 0 gets the convenience alias */
895 cpu->as = as;
896 }
897
898 /* KVM cannot currently support multiple address spaces. */
899 assert(asidx == 0 || !kvm_enabled());
900
901 if (!cpu->cpu_ases) {
902 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
903 }
904
905 newas = &cpu->cpu_ases[asidx];
906 newas->cpu = cpu;
907 newas->as = as;
908 if (tcg_enabled()) {
909 newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync;
910 newas->tcg_as_listener.commit = tcg_commit;
911 memory_listener_register(&newas->tcg_as_listener, as);
912 }
913 }
914
915 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
916 {
917 /* Return the AddressSpace corresponding to the specified index */
918 return cpu->cpu_ases[asidx].as;
919 }
920 #endif
921
922 void cpu_exec_unrealizefn(CPUState *cpu)
923 {
924 CPUClass *cc = CPU_GET_CLASS(cpu);
925
926 cpu_list_remove(cpu);
927
928 if (cc->vmsd != NULL) {
929 vmstate_unregister(NULL, cc->vmsd, cpu);
930 }
931 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
932 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
933 }
934 #ifndef CONFIG_USER_ONLY
935 tcg_iommu_free_notifier_list(cpu);
936 #endif
937 }
938
939 Property cpu_common_props[] = {
940 #ifndef CONFIG_USER_ONLY
941 /* Create a memory property for softmmu CPU object,
942 * so users can wire up its memory. (This can't go in hw/core/cpu.c
943 * because that file is compiled only once for both user-mode
944 * and system builds.) The default if no link is set up is to use
945 * the system address space.
946 */
947 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
948 MemoryRegion *),
949 #endif
950 DEFINE_PROP_END_OF_LIST(),
951 };
952
953 void cpu_exec_initfn(CPUState *cpu)
954 {
955 cpu->as = NULL;
956 cpu->num_ases = 0;
957
958 #ifndef CONFIG_USER_ONLY
959 cpu->thread_id = qemu_get_thread_id();
960 cpu->memory = system_memory;
961 object_ref(OBJECT(cpu->memory));
962 #endif
963 }
964
965 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
966 {
967 CPUClass *cc = CPU_GET_CLASS(cpu);
968 static bool tcg_target_initialized;
969
970 cpu_list_add(cpu);
971
972 if (tcg_enabled() && !tcg_target_initialized) {
973 tcg_target_initialized = true;
974 cc->tcg_initialize();
975 }
976 tlb_init(cpu);
977
978 #ifndef CONFIG_USER_ONLY
979 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
980 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
981 }
982 if (cc->vmsd != NULL) {
983 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
984 }
985
986 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
987 #endif
988 }
989
990 const char *parse_cpu_option(const char *cpu_option)
991 {
992 ObjectClass *oc;
993 CPUClass *cc;
994 gchar **model_pieces;
995 const char *cpu_type;
996
997 model_pieces = g_strsplit(cpu_option, ",", 2);
998 if (!model_pieces[0]) {
999 error_report("-cpu option cannot be empty");
1000 exit(1);
1001 }
1002
1003 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
1004 if (oc == NULL) {
1005 error_report("unable to find CPU model '%s'", model_pieces[0]);
1006 g_strfreev(model_pieces);
1007 exit(EXIT_FAILURE);
1008 }
1009
1010 cpu_type = object_class_get_name(oc);
1011 cc = CPU_CLASS(oc);
1012 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
1013 g_strfreev(model_pieces);
1014 return cpu_type;
1015 }
1016
1017 #if defined(CONFIG_USER_ONLY)
1018 void tb_invalidate_phys_addr(target_ulong addr)
1019 {
1020 mmap_lock();
1021 tb_invalidate_phys_page_range(addr, addr + 1, 0);
1022 mmap_unlock();
1023 }
1024
1025 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1026 {
1027 tb_invalidate_phys_addr(pc);
1028 }
1029 #else
1030 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
1031 {
1032 ram_addr_t ram_addr;
1033 MemoryRegion *mr;
1034 hwaddr l = 1;
1035
1036 if (!tcg_enabled()) {
1037 return;
1038 }
1039
1040 rcu_read_lock();
1041 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1042 if (!(memory_region_is_ram(mr)
1043 || memory_region_is_romd(mr))) {
1044 rcu_read_unlock();
1045 return;
1046 }
1047 ram_addr = memory_region_get_ram_addr(mr) + addr;
1048 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1049 rcu_read_unlock();
1050 }
1051
1052 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1053 {
1054 MemTxAttrs attrs;
1055 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
1056 int asidx = cpu_asidx_from_attrs(cpu, attrs);
1057 if (phys != -1) {
1058 /* Locks grabbed by tb_invalidate_phys_addr */
1059 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
1060 phys | (pc & ~TARGET_PAGE_MASK), attrs);
1061 }
1062 }
1063 #endif
1064
1065 #if defined(CONFIG_USER_ONLY)
1066 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1067
1068 {
1069 }
1070
1071 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1072 int flags)
1073 {
1074 return -ENOSYS;
1075 }
1076
1077 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1078 {
1079 }
1080
1081 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1082 int flags, CPUWatchpoint **watchpoint)
1083 {
1084 return -ENOSYS;
1085 }
1086 #else
1087 /* Add a watchpoint. */
1088 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1089 int flags, CPUWatchpoint **watchpoint)
1090 {
1091 CPUWatchpoint *wp;
1092
1093 /* forbid ranges which are empty or run off the end of the address space */
1094 if (len == 0 || (addr + len - 1) < addr) {
1095 error_report("tried to set invalid watchpoint at %"
1096 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1097 return -EINVAL;
1098 }
1099 wp = g_malloc(sizeof(*wp));
1100
1101 wp->vaddr = addr;
1102 wp->len = len;
1103 wp->flags = flags;
1104
1105 /* keep all GDB-injected watchpoints in front */
1106 if (flags & BP_GDB) {
1107 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1108 } else {
1109 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1110 }
1111
1112 tlb_flush_page(cpu, addr);
1113
1114 if (watchpoint)
1115 *watchpoint = wp;
1116 return 0;
1117 }
1118
1119 /* Remove a specific watchpoint. */
1120 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1121 int flags)
1122 {
1123 CPUWatchpoint *wp;
1124
1125 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1126 if (addr == wp->vaddr && len == wp->len
1127 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1128 cpu_watchpoint_remove_by_ref(cpu, wp);
1129 return 0;
1130 }
1131 }
1132 return -ENOENT;
1133 }
1134
1135 /* Remove a specific watchpoint by reference. */
1136 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1137 {
1138 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1139
1140 tlb_flush_page(cpu, watchpoint->vaddr);
1141
1142 g_free(watchpoint);
1143 }
1144
1145 /* Remove all matching watchpoints. */
1146 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1147 {
1148 CPUWatchpoint *wp, *next;
1149
1150 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1151 if (wp->flags & mask) {
1152 cpu_watchpoint_remove_by_ref(cpu, wp);
1153 }
1154 }
1155 }
1156
1157 /* Return true if this watchpoint address matches the specified
1158 * access (ie the address range covered by the watchpoint overlaps
1159 * partially or completely with the address range covered by the
1160 * access).
1161 */
1162 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
1163 vaddr addr,
1164 vaddr len)
1165 {
1166 /* We know the lengths are non-zero, but a little caution is
1167 * required to avoid errors in the case where the range ends
1168 * exactly at the top of the address space and so addr + len
1169 * wraps round to zero.
1170 */
1171 vaddr wpend = wp->vaddr + wp->len - 1;
1172 vaddr addrend = addr + len - 1;
1173
1174 return !(addr > wpend || wp->vaddr > addrend);
1175 }
1176
1177 #endif
1178
1179 /* Add a breakpoint. */
1180 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1181 CPUBreakpoint **breakpoint)
1182 {
1183 CPUBreakpoint *bp;
1184
1185 bp = g_malloc(sizeof(*bp));
1186
1187 bp->pc = pc;
1188 bp->flags = flags;
1189
1190 /* keep all GDB-injected breakpoints in front */
1191 if (flags & BP_GDB) {
1192 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1193 } else {
1194 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1195 }
1196
1197 breakpoint_invalidate(cpu, pc);
1198
1199 if (breakpoint) {
1200 *breakpoint = bp;
1201 }
1202 return 0;
1203 }
1204
1205 /* Remove a specific breakpoint. */
1206 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1207 {
1208 CPUBreakpoint *bp;
1209
1210 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1211 if (bp->pc == pc && bp->flags == flags) {
1212 cpu_breakpoint_remove_by_ref(cpu, bp);
1213 return 0;
1214 }
1215 }
1216 return -ENOENT;
1217 }
1218
1219 /* Remove a specific breakpoint by reference. */
1220 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1221 {
1222 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1223
1224 breakpoint_invalidate(cpu, breakpoint->pc);
1225
1226 g_free(breakpoint);
1227 }
1228
1229 /* Remove all matching breakpoints. */
1230 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1231 {
1232 CPUBreakpoint *bp, *next;
1233
1234 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1235 if (bp->flags & mask) {
1236 cpu_breakpoint_remove_by_ref(cpu, bp);
1237 }
1238 }
1239 }
1240
1241 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1242 CPU loop after each instruction */
1243 void cpu_single_step(CPUState *cpu, int enabled)
1244 {
1245 if (cpu->singlestep_enabled != enabled) {
1246 cpu->singlestep_enabled = enabled;
1247 if (kvm_enabled()) {
1248 kvm_update_guest_debug(cpu, 0);
1249 } else {
1250 /* must flush all the translated code to avoid inconsistencies */
1251 /* XXX: only flush what is necessary */
1252 tb_flush(cpu);
1253 }
1254 }
1255 }
1256
1257 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1258 {
1259 va_list ap;
1260 va_list ap2;
1261
1262 va_start(ap, fmt);
1263 va_copy(ap2, ap);
1264 fprintf(stderr, "qemu: fatal: ");
1265 vfprintf(stderr, fmt, ap);
1266 fprintf(stderr, "\n");
1267 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1268 if (qemu_log_separate()) {
1269 qemu_log_lock();
1270 qemu_log("qemu: fatal: ");
1271 qemu_log_vprintf(fmt, ap2);
1272 qemu_log("\n");
1273 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1274 qemu_log_flush();
1275 qemu_log_unlock();
1276 qemu_log_close();
1277 }
1278 va_end(ap2);
1279 va_end(ap);
1280 replay_finish();
1281 #if defined(CONFIG_USER_ONLY)
1282 {
1283 struct sigaction act;
1284 sigfillset(&act.sa_mask);
1285 act.sa_handler = SIG_DFL;
1286 act.sa_flags = 0;
1287 sigaction(SIGABRT, &act, NULL);
1288 }
1289 #endif
1290 abort();
1291 }
1292
1293 #if !defined(CONFIG_USER_ONLY)
1294 /* Called from RCU critical section */
1295 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1296 {
1297 RAMBlock *block;
1298
1299 block = atomic_rcu_read(&ram_list.mru_block);
1300 if (block && addr - block->offset < block->max_length) {
1301 return block;
1302 }
1303 RAMBLOCK_FOREACH(block) {
1304 if (addr - block->offset < block->max_length) {
1305 goto found;
1306 }
1307 }
1308
1309 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1310 abort();
1311
1312 found:
1313 /* It is safe to write mru_block outside the iothread lock. This
1314 * is what happens:
1315 *
1316 * mru_block = xxx
1317 * rcu_read_unlock()
1318 * xxx removed from list
1319 * rcu_read_lock()
1320 * read mru_block
1321 * mru_block = NULL;
1322 * call_rcu(reclaim_ramblock, xxx);
1323 * rcu_read_unlock()
1324 *
1325 * atomic_rcu_set is not needed here. The block was already published
1326 * when it was placed into the list. Here we're just making an extra
1327 * copy of the pointer.
1328 */
1329 ram_list.mru_block = block;
1330 return block;
1331 }
1332
1333 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1334 {
1335 CPUState *cpu;
1336 ram_addr_t start1;
1337 RAMBlock *block;
1338 ram_addr_t end;
1339
1340 assert(tcg_enabled());
1341 end = TARGET_PAGE_ALIGN(start + length);
1342 start &= TARGET_PAGE_MASK;
1343
1344 rcu_read_lock();
1345 block = qemu_get_ram_block(start);
1346 assert(block == qemu_get_ram_block(end - 1));
1347 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1348 CPU_FOREACH(cpu) {
1349 tlb_reset_dirty(cpu, start1, length);
1350 }
1351 rcu_read_unlock();
1352 }
1353
1354 /* Note: start and end must be within the same ram block. */
1355 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1356 ram_addr_t length,
1357 unsigned client)
1358 {
1359 DirtyMemoryBlocks *blocks;
1360 unsigned long end, page;
1361 bool dirty = false;
1362 RAMBlock *ramblock;
1363 uint64_t mr_offset, mr_size;
1364
1365 if (length == 0) {
1366 return false;
1367 }
1368
1369 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1370 page = start >> TARGET_PAGE_BITS;
1371
1372 rcu_read_lock();
1373
1374 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1375 ramblock = qemu_get_ram_block(start);
1376 /* Range sanity check on the ramblock */
1377 assert(start >= ramblock->offset &&
1378 start + length <= ramblock->offset + ramblock->used_length);
1379
1380 while (page < end) {
1381 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1382 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1383 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1384
1385 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1386 offset, num);
1387 page += num;
1388 }
1389
1390 mr_offset = (ram_addr_t)(page << TARGET_PAGE_BITS) - ramblock->offset;
1391 mr_size = (end - page) << TARGET_PAGE_BITS;
1392 memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
1393
1394 rcu_read_unlock();
1395
1396 if (dirty && tcg_enabled()) {
1397 tlb_reset_dirty_range_all(start, length);
1398 }
1399
1400 return dirty;
1401 }
1402
1403 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1404 (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client)
1405 {
1406 DirtyMemoryBlocks *blocks;
1407 ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
1408 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1409 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1410 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1411 DirtyBitmapSnapshot *snap;
1412 unsigned long page, end, dest;
1413
1414 snap = g_malloc0(sizeof(*snap) +
1415 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1416 snap->start = first;
1417 snap->end = last;
1418
1419 page = first >> TARGET_PAGE_BITS;
1420 end = last >> TARGET_PAGE_BITS;
1421 dest = 0;
1422
1423 rcu_read_lock();
1424
1425 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1426
1427 while (page < end) {
1428 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1429 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1430 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1431
1432 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1433 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1434 offset >>= BITS_PER_LEVEL;
1435
1436 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1437 blocks->blocks[idx] + offset,
1438 num);
1439 page += num;
1440 dest += num >> BITS_PER_LEVEL;
1441 }
1442
1443 rcu_read_unlock();
1444
1445 if (tcg_enabled()) {
1446 tlb_reset_dirty_range_all(start, length);
1447 }
1448
1449 memory_region_clear_dirty_bitmap(mr, offset, length);
1450
1451 return snap;
1452 }
1453
1454 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1455 ram_addr_t start,
1456 ram_addr_t length)
1457 {
1458 unsigned long page, end;
1459
1460 assert(start >= snap->start);
1461 assert(start + length <= snap->end);
1462
1463 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1464 page = (start - snap->start) >> TARGET_PAGE_BITS;
1465
1466 while (page < end) {
1467 if (test_bit(page, snap->dirty)) {
1468 return true;
1469 }
1470 page++;
1471 }
1472 return false;
1473 }
1474
1475 /* Called from RCU critical section */
1476 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1477 MemoryRegionSection *section,
1478 target_ulong vaddr,
1479 hwaddr paddr, hwaddr xlat,
1480 int prot,
1481 target_ulong *address)
1482 {
1483 hwaddr iotlb;
1484 CPUWatchpoint *wp;
1485
1486 if (memory_region_is_ram(section->mr)) {
1487 /* Normal RAM. */
1488 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1489 if (!section->readonly) {
1490 iotlb |= PHYS_SECTION_NOTDIRTY;
1491 } else {
1492 iotlb |= PHYS_SECTION_ROM;
1493 }
1494 } else {
1495 AddressSpaceDispatch *d;
1496
1497 d = flatview_to_dispatch(section->fv);
1498 iotlb = section - d->map.sections;
1499 iotlb += xlat;
1500 }
1501
1502 /* Make accesses to pages with watchpoints go via the
1503 watchpoint trap routines. */
1504 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1505 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1506 /* Avoid trapping reads of pages with a write breakpoint. */
1507 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1508 iotlb = PHYS_SECTION_WATCH + paddr;
1509 *address |= TLB_MMIO;
1510 break;
1511 }
1512 }
1513 }
1514
1515 return iotlb;
1516 }
1517 #endif /* defined(CONFIG_USER_ONLY) */
1518
1519 #if !defined(CONFIG_USER_ONLY)
1520
1521 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1522 uint16_t section);
1523 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1524
1525 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1526 qemu_anon_ram_alloc;
1527
1528 /*
1529 * Set a custom physical guest memory alloator.
1530 * Accelerators with unusual needs may need this. Hopefully, we can
1531 * get rid of it eventually.
1532 */
1533 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1534 {
1535 phys_mem_alloc = alloc;
1536 }
1537
1538 static uint16_t phys_section_add(PhysPageMap *map,
1539 MemoryRegionSection *section)
1540 {
1541 /* The physical section number is ORed with a page-aligned
1542 * pointer to produce the iotlb entries. Thus it should
1543 * never overflow into the page-aligned value.
1544 */
1545 assert(map->sections_nb < TARGET_PAGE_SIZE);
1546
1547 if (map->sections_nb == map->sections_nb_alloc) {
1548 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1549 map->sections = g_renew(MemoryRegionSection, map->sections,
1550 map->sections_nb_alloc);
1551 }
1552 map->sections[map->sections_nb] = *section;
1553 memory_region_ref(section->mr);
1554 return map->sections_nb++;
1555 }
1556
1557 static void phys_section_destroy(MemoryRegion *mr)
1558 {
1559 bool have_sub_page = mr->subpage;
1560
1561 memory_region_unref(mr);
1562
1563 if (have_sub_page) {
1564 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1565 object_unref(OBJECT(&subpage->iomem));
1566 g_free(subpage);
1567 }
1568 }
1569
1570 static void phys_sections_free(PhysPageMap *map)
1571 {
1572 while (map->sections_nb > 0) {
1573 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1574 phys_section_destroy(section->mr);
1575 }
1576 g_free(map->sections);
1577 g_free(map->nodes);
1578 }
1579
1580 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1581 {
1582 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1583 subpage_t *subpage;
1584 hwaddr base = section->offset_within_address_space
1585 & TARGET_PAGE_MASK;
1586 MemoryRegionSection *existing = phys_page_find(d, base);
1587 MemoryRegionSection subsection = {
1588 .offset_within_address_space = base,
1589 .size = int128_make64(TARGET_PAGE_SIZE),
1590 };
1591 hwaddr start, end;
1592
1593 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1594
1595 if (!(existing->mr->subpage)) {
1596 subpage = subpage_init(fv, base);
1597 subsection.fv = fv;
1598 subsection.mr = &subpage->iomem;
1599 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1600 phys_section_add(&d->map, &subsection));
1601 } else {
1602 subpage = container_of(existing->mr, subpage_t, iomem);
1603 }
1604 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1605 end = start + int128_get64(section->size) - 1;
1606 subpage_register(subpage, start, end,
1607 phys_section_add(&d->map, section));
1608 }
1609
1610
1611 static void register_multipage(FlatView *fv,
1612 MemoryRegionSection *section)
1613 {
1614 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1615 hwaddr start_addr = section->offset_within_address_space;
1616 uint16_t section_index = phys_section_add(&d->map, section);
1617 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1618 TARGET_PAGE_BITS));
1619
1620 assert(num_pages);
1621 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1622 }
1623
1624 /*
1625 * The range in *section* may look like this:
1626 *
1627 * |s|PPPPPPP|s|
1628 *
1629 * where s stands for subpage and P for page.
1630 */
1631 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1632 {
1633 MemoryRegionSection remain = *section;
1634 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1635
1636 /* register first subpage */
1637 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1638 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1639 - remain.offset_within_address_space;
1640
1641 MemoryRegionSection now = remain;
1642 now.size = int128_min(int128_make64(left), now.size);
1643 register_subpage(fv, &now);
1644 if (int128_eq(remain.size, now.size)) {
1645 return;
1646 }
1647 remain.size = int128_sub(remain.size, now.size);
1648 remain.offset_within_address_space += int128_get64(now.size);
1649 remain.offset_within_region += int128_get64(now.size);
1650 }
1651
1652 /* register whole pages */
1653 if (int128_ge(remain.size, page_size)) {
1654 MemoryRegionSection now = remain;
1655 now.size = int128_and(now.size, int128_neg(page_size));
1656 register_multipage(fv, &now);
1657 if (int128_eq(remain.size, now.size)) {
1658 return;
1659 }
1660 remain.size = int128_sub(remain.size, now.size);
1661 remain.offset_within_address_space += int128_get64(now.size);
1662 remain.offset_within_region += int128_get64(now.size);
1663 }
1664
1665 /* register last subpage */
1666 register_subpage(fv, &remain);
1667 }
1668
1669 void qemu_flush_coalesced_mmio_buffer(void)
1670 {
1671 if (kvm_enabled())
1672 kvm_flush_coalesced_mmio_buffer();
1673 }
1674
1675 void qemu_mutex_lock_ramlist(void)
1676 {
1677 qemu_mutex_lock(&ram_list.mutex);
1678 }
1679
1680 void qemu_mutex_unlock_ramlist(void)
1681 {
1682 qemu_mutex_unlock(&ram_list.mutex);
1683 }
1684
1685 void ram_block_dump(Monitor *mon)
1686 {
1687 RAMBlock *block;
1688 char *psize;
1689
1690 rcu_read_lock();
1691 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1692 "Block Name", "PSize", "Offset", "Used", "Total");
1693 RAMBLOCK_FOREACH(block) {
1694 psize = size_to_str(block->page_size);
1695 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1696 " 0x%016" PRIx64 "\n", block->idstr, psize,
1697 (uint64_t)block->offset,
1698 (uint64_t)block->used_length,
1699 (uint64_t)block->max_length);
1700 g_free(psize);
1701 }
1702 rcu_read_unlock();
1703 }
1704
1705 #ifdef __linux__
1706 /*
1707 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1708 * may or may not name the same files / on the same filesystem now as
1709 * when we actually open and map them. Iterate over the file
1710 * descriptors instead, and use qemu_fd_getpagesize().
1711 */
1712 static int find_min_backend_pagesize(Object *obj, void *opaque)
1713 {
1714 long *hpsize_min = opaque;
1715
1716 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1717 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1718 long hpsize = host_memory_backend_pagesize(backend);
1719
1720 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1721 *hpsize_min = hpsize;
1722 }
1723 }
1724
1725 return 0;
1726 }
1727
1728 static int find_max_backend_pagesize(Object *obj, void *opaque)
1729 {
1730 long *hpsize_max = opaque;
1731
1732 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1733 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1734 long hpsize = host_memory_backend_pagesize(backend);
1735
1736 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1737 *hpsize_max = hpsize;
1738 }
1739 }
1740
1741 return 0;
1742 }
1743
1744 /*
1745 * TODO: We assume right now that all mapped host memory backends are
1746 * used as RAM, however some might be used for different purposes.
1747 */
1748 long qemu_minrampagesize(void)
1749 {
1750 long hpsize = LONG_MAX;
1751 long mainrampagesize;
1752 Object *memdev_root;
1753
1754 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1755
1756 /* it's possible we have memory-backend objects with
1757 * hugepage-backed RAM. these may get mapped into system
1758 * address space via -numa parameters or memory hotplug
1759 * hooks. we want to take these into account, but we
1760 * also want to make sure these supported hugepage
1761 * sizes are applicable across the entire range of memory
1762 * we may boot from, so we take the min across all
1763 * backends, and assume normal pages in cases where a
1764 * backend isn't backed by hugepages.
1765 */
1766 memdev_root = object_resolve_path("/objects", NULL);
1767 if (memdev_root) {
1768 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1769 }
1770 if (hpsize == LONG_MAX) {
1771 /* No additional memory regions found ==> Report main RAM page size */
1772 return mainrampagesize;
1773 }
1774
1775 /* If NUMA is disabled or the NUMA nodes are not backed with a
1776 * memory-backend, then there is at least one node using "normal" RAM,
1777 * so if its page size is smaller we have got to report that size instead.
1778 */
1779 if (hpsize > mainrampagesize &&
1780 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1781 static bool warned;
1782 if (!warned) {
1783 error_report("Huge page support disabled (n/a for main memory).");
1784 warned = true;
1785 }
1786 return mainrampagesize;
1787 }
1788
1789 return hpsize;
1790 }
1791
1792 long qemu_maxrampagesize(void)
1793 {
1794 long pagesize = qemu_mempath_getpagesize(mem_path);
1795 Object *memdev_root = object_resolve_path("/objects", NULL);
1796
1797 if (memdev_root) {
1798 object_child_foreach(memdev_root, find_max_backend_pagesize,
1799 &pagesize);
1800 }
1801 return pagesize;
1802 }
1803 #else
1804 long qemu_minrampagesize(void)
1805 {
1806 return getpagesize();
1807 }
1808 long qemu_maxrampagesize(void)
1809 {
1810 return getpagesize();
1811 }
1812 #endif
1813
1814 #ifdef CONFIG_POSIX
1815 static int64_t get_file_size(int fd)
1816 {
1817 int64_t size = lseek(fd, 0, SEEK_END);
1818 if (size < 0) {
1819 return -errno;
1820 }
1821 return size;
1822 }
1823
1824 static int file_ram_open(const char *path,
1825 const char *region_name,
1826 bool *created,
1827 Error **errp)
1828 {
1829 char *filename;
1830 char *sanitized_name;
1831 char *c;
1832 int fd = -1;
1833
1834 *created = false;
1835 for (;;) {
1836 fd = open(path, O_RDWR);
1837 if (fd >= 0) {
1838 /* @path names an existing file, use it */
1839 break;
1840 }
1841 if (errno == ENOENT) {
1842 /* @path names a file that doesn't exist, create it */
1843 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1844 if (fd >= 0) {
1845 *created = true;
1846 break;
1847 }
1848 } else if (errno == EISDIR) {
1849 /* @path names a directory, create a file there */
1850 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1851 sanitized_name = g_strdup(region_name);
1852 for (c = sanitized_name; *c != '\0'; c++) {
1853 if (*c == '/') {
1854 *c = '_';
1855 }
1856 }
1857
1858 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1859 sanitized_name);
1860 g_free(sanitized_name);
1861
1862 fd = mkstemp(filename);
1863 if (fd >= 0) {
1864 unlink(filename);
1865 g_free(filename);
1866 break;
1867 }
1868 g_free(filename);
1869 }
1870 if (errno != EEXIST && errno != EINTR) {
1871 error_setg_errno(errp, errno,
1872 "can't open backing store %s for guest RAM",
1873 path);
1874 return -1;
1875 }
1876 /*
1877 * Try again on EINTR and EEXIST. The latter happens when
1878 * something else creates the file between our two open().
1879 */
1880 }
1881
1882 return fd;
1883 }
1884
1885 static void *file_ram_alloc(RAMBlock *block,
1886 ram_addr_t memory,
1887 int fd,
1888 bool truncate,
1889 Error **errp)
1890 {
1891 MachineState *ms = MACHINE(qdev_get_machine());
1892 void *area;
1893
1894 block->page_size = qemu_fd_getpagesize(fd);
1895 if (block->mr->align % block->page_size) {
1896 error_setg(errp, "alignment 0x%" PRIx64
1897 " must be multiples of page size 0x%zx",
1898 block->mr->align, block->page_size);
1899 return NULL;
1900 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1901 error_setg(errp, "alignment 0x%" PRIx64
1902 " must be a power of two", block->mr->align);
1903 return NULL;
1904 }
1905 block->mr->align = MAX(block->page_size, block->mr->align);
1906 #if defined(__s390x__)
1907 if (kvm_enabled()) {
1908 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1909 }
1910 #endif
1911
1912 if (memory < block->page_size) {
1913 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1914 "or larger than page size 0x%zx",
1915 memory, block->page_size);
1916 return NULL;
1917 }
1918
1919 memory = ROUND_UP(memory, block->page_size);
1920
1921 /*
1922 * ftruncate is not supported by hugetlbfs in older
1923 * hosts, so don't bother bailing out on errors.
1924 * If anything goes wrong with it under other filesystems,
1925 * mmap will fail.
1926 *
1927 * Do not truncate the non-empty backend file to avoid corrupting
1928 * the existing data in the file. Disabling shrinking is not
1929 * enough. For example, the current vNVDIMM implementation stores
1930 * the guest NVDIMM labels at the end of the backend file. If the
1931 * backend file is later extended, QEMU will not be able to find
1932 * those labels. Therefore, extending the non-empty backend file
1933 * is disabled as well.
1934 */
1935 if (truncate && ftruncate(fd, memory)) {
1936 perror("ftruncate");
1937 }
1938
1939 area = qemu_ram_mmap(fd, memory, block->mr->align,
1940 block->flags & RAM_SHARED, block->flags & RAM_PMEM);
1941 if (area == MAP_FAILED) {
1942 error_setg_errno(errp, errno,
1943 "unable to map backing store for guest RAM");
1944 return NULL;
1945 }
1946
1947 if (mem_prealloc) {
1948 os_mem_prealloc(fd, area, memory, ms->smp.cpus, errp);
1949 if (errp && *errp) {
1950 qemu_ram_munmap(fd, area, memory);
1951 return NULL;
1952 }
1953 }
1954
1955 block->fd = fd;
1956 return area;
1957 }
1958 #endif
1959
1960 /* Allocate space within the ram_addr_t space that governs the
1961 * dirty bitmaps.
1962 * Called with the ramlist lock held.
1963 */
1964 static ram_addr_t find_ram_offset(ram_addr_t size)
1965 {
1966 RAMBlock *block, *next_block;
1967 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1968
1969 assert(size != 0); /* it would hand out same offset multiple times */
1970
1971 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1972 return 0;
1973 }
1974
1975 RAMBLOCK_FOREACH(block) {
1976 ram_addr_t candidate, next = RAM_ADDR_MAX;
1977
1978 /* Align blocks to start on a 'long' in the bitmap
1979 * which makes the bitmap sync'ing take the fast path.
1980 */
1981 candidate = block->offset + block->max_length;
1982 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1983
1984 /* Search for the closest following block
1985 * and find the gap.
1986 */
1987 RAMBLOCK_FOREACH(next_block) {
1988 if (next_block->offset >= candidate) {
1989 next = MIN(next, next_block->offset);
1990 }
1991 }
1992
1993 /* If it fits remember our place and remember the size
1994 * of gap, but keep going so that we might find a smaller
1995 * gap to fill so avoiding fragmentation.
1996 */
1997 if (next - candidate >= size && next - candidate < mingap) {
1998 offset = candidate;
1999 mingap = next - candidate;
2000 }
2001
2002 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
2003 }
2004
2005 if (offset == RAM_ADDR_MAX) {
2006 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
2007 (uint64_t)size);
2008 abort();
2009 }
2010
2011 trace_find_ram_offset(size, offset);
2012
2013 return offset;
2014 }
2015
2016 static unsigned long last_ram_page(void)
2017 {
2018 RAMBlock *block;
2019 ram_addr_t last = 0;
2020
2021 rcu_read_lock();
2022 RAMBLOCK_FOREACH(block) {
2023 last = MAX(last, block->offset + block->max_length);
2024 }
2025 rcu_read_unlock();
2026 return last >> TARGET_PAGE_BITS;
2027 }
2028
2029 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
2030 {
2031 int ret;
2032
2033 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2034 if (!machine_dump_guest_core(current_machine)) {
2035 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
2036 if (ret) {
2037 perror("qemu_madvise");
2038 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
2039 "but dump_guest_core=off specified\n");
2040 }
2041 }
2042 }
2043
2044 const char *qemu_ram_get_idstr(RAMBlock *rb)
2045 {
2046 return rb->idstr;
2047 }
2048
2049 void *qemu_ram_get_host_addr(RAMBlock *rb)
2050 {
2051 return rb->host;
2052 }
2053
2054 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
2055 {
2056 return rb->offset;
2057 }
2058
2059 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
2060 {
2061 return rb->used_length;
2062 }
2063
2064 bool qemu_ram_is_shared(RAMBlock *rb)
2065 {
2066 return rb->flags & RAM_SHARED;
2067 }
2068
2069 /* Note: Only set at the start of postcopy */
2070 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
2071 {
2072 return rb->flags & RAM_UF_ZEROPAGE;
2073 }
2074
2075 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
2076 {
2077 rb->flags |= RAM_UF_ZEROPAGE;
2078 }
2079
2080 bool qemu_ram_is_migratable(RAMBlock *rb)
2081 {
2082 return rb->flags & RAM_MIGRATABLE;
2083 }
2084
2085 void qemu_ram_set_migratable(RAMBlock *rb)
2086 {
2087 rb->flags |= RAM_MIGRATABLE;
2088 }
2089
2090 void qemu_ram_unset_migratable(RAMBlock *rb)
2091 {
2092 rb->flags &= ~RAM_MIGRATABLE;
2093 }
2094
2095 /* Called with iothread lock held. */
2096 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2097 {
2098 RAMBlock *block;
2099
2100 assert(new_block);
2101 assert(!new_block->idstr[0]);
2102
2103 if (dev) {
2104 char *id = qdev_get_dev_path(dev);
2105 if (id) {
2106 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2107 g_free(id);
2108 }
2109 }
2110 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2111
2112 rcu_read_lock();
2113 RAMBLOCK_FOREACH(block) {
2114 if (block != new_block &&
2115 !strcmp(block->idstr, new_block->idstr)) {
2116 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2117 new_block->idstr);
2118 abort();
2119 }
2120 }
2121 rcu_read_unlock();
2122 }
2123
2124 /* Called with iothread lock held. */
2125 void qemu_ram_unset_idstr(RAMBlock *block)
2126 {
2127 /* FIXME: arch_init.c assumes that this is not called throughout
2128 * migration. Ignore the problem since hot-unplug during migration
2129 * does not work anyway.
2130 */
2131 if (block) {
2132 memset(block->idstr, 0, sizeof(block->idstr));
2133 }
2134 }
2135
2136 size_t qemu_ram_pagesize(RAMBlock *rb)
2137 {
2138 return rb->page_size;
2139 }
2140
2141 /* Returns the largest size of page in use */
2142 size_t qemu_ram_pagesize_largest(void)
2143 {
2144 RAMBlock *block;
2145 size_t largest = 0;
2146
2147 RAMBLOCK_FOREACH(block) {
2148 largest = MAX(largest, qemu_ram_pagesize(block));
2149 }
2150
2151 return largest;
2152 }
2153
2154 static int memory_try_enable_merging(void *addr, size_t len)
2155 {
2156 if (!machine_mem_merge(current_machine)) {
2157 /* disabled by the user */
2158 return 0;
2159 }
2160
2161 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2162 }
2163
2164 /* Only legal before guest might have detected the memory size: e.g. on
2165 * incoming migration, or right after reset.
2166 *
2167 * As memory core doesn't know how is memory accessed, it is up to
2168 * resize callback to update device state and/or add assertions to detect
2169 * misuse, if necessary.
2170 */
2171 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2172 {
2173 assert(block);
2174
2175 newsize = HOST_PAGE_ALIGN(newsize);
2176
2177 if (block->used_length == newsize) {
2178 return 0;
2179 }
2180
2181 if (!(block->flags & RAM_RESIZEABLE)) {
2182 error_setg_errno(errp, EINVAL,
2183 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2184 " in != 0x" RAM_ADDR_FMT, block->idstr,
2185 newsize, block->used_length);
2186 return -EINVAL;
2187 }
2188
2189 if (block->max_length < newsize) {
2190 error_setg_errno(errp, EINVAL,
2191 "Length too large: %s: 0x" RAM_ADDR_FMT
2192 " > 0x" RAM_ADDR_FMT, block->idstr,
2193 newsize, block->max_length);
2194 return -EINVAL;
2195 }
2196
2197 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2198 block->used_length = newsize;
2199 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2200 DIRTY_CLIENTS_ALL);
2201 memory_region_set_size(block->mr, newsize);
2202 if (block->resized) {
2203 block->resized(block->idstr, newsize, block->host);
2204 }
2205 return 0;
2206 }
2207
2208 /* Called with ram_list.mutex held */
2209 static void dirty_memory_extend(ram_addr_t old_ram_size,
2210 ram_addr_t new_ram_size)
2211 {
2212 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2213 DIRTY_MEMORY_BLOCK_SIZE);
2214 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2215 DIRTY_MEMORY_BLOCK_SIZE);
2216 int i;
2217
2218 /* Only need to extend if block count increased */
2219 if (new_num_blocks <= old_num_blocks) {
2220 return;
2221 }
2222
2223 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2224 DirtyMemoryBlocks *old_blocks;
2225 DirtyMemoryBlocks *new_blocks;
2226 int j;
2227
2228 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
2229 new_blocks = g_malloc(sizeof(*new_blocks) +
2230 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2231
2232 if (old_num_blocks) {
2233 memcpy(new_blocks->blocks, old_blocks->blocks,
2234 old_num_blocks * sizeof(old_blocks->blocks[0]));
2235 }
2236
2237 for (j = old_num_blocks; j < new_num_blocks; j++) {
2238 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2239 }
2240
2241 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2242
2243 if (old_blocks) {
2244 g_free_rcu(old_blocks, rcu);
2245 }
2246 }
2247 }
2248
2249 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2250 {
2251 RAMBlock *block;
2252 RAMBlock *last_block = NULL;
2253 ram_addr_t old_ram_size, new_ram_size;
2254 Error *err = NULL;
2255
2256 old_ram_size = last_ram_page();
2257
2258 qemu_mutex_lock_ramlist();
2259 new_block->offset = find_ram_offset(new_block->max_length);
2260
2261 if (!new_block->host) {
2262 if (xen_enabled()) {
2263 xen_ram_alloc(new_block->offset, new_block->max_length,
2264 new_block->mr, &err);
2265 if (err) {
2266 error_propagate(errp, err);
2267 qemu_mutex_unlock_ramlist();
2268 return;
2269 }
2270 } else {
2271 new_block->host = phys_mem_alloc(new_block->max_length,
2272 &new_block->mr->align, shared);
2273 if (!new_block->host) {
2274 error_setg_errno(errp, errno,
2275 "cannot set up guest memory '%s'",
2276 memory_region_name(new_block->mr));
2277 qemu_mutex_unlock_ramlist();
2278 return;
2279 }
2280 memory_try_enable_merging(new_block->host, new_block->max_length);
2281 }
2282 }
2283
2284 new_ram_size = MAX(old_ram_size,
2285 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2286 if (new_ram_size > old_ram_size) {
2287 dirty_memory_extend(old_ram_size, new_ram_size);
2288 }
2289 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2290 * QLIST (which has an RCU-friendly variant) does not have insertion at
2291 * tail, so save the last element in last_block.
2292 */
2293 RAMBLOCK_FOREACH(block) {
2294 last_block = block;
2295 if (block->max_length < new_block->max_length) {
2296 break;
2297 }
2298 }
2299 if (block) {
2300 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2301 } else if (last_block) {
2302 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2303 } else { /* list is empty */
2304 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2305 }
2306 ram_list.mru_block = NULL;
2307
2308 /* Write list before version */
2309 smp_wmb();
2310 ram_list.version++;
2311 qemu_mutex_unlock_ramlist();
2312
2313 cpu_physical_memory_set_dirty_range(new_block->offset,
2314 new_block->used_length,
2315 DIRTY_CLIENTS_ALL);
2316
2317 if (new_block->host) {
2318 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2319 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2320 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2321 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
2322 ram_block_notify_add(new_block->host, new_block->max_length);
2323 }
2324 }
2325
2326 #ifdef CONFIG_POSIX
2327 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2328 uint32_t ram_flags, int fd,
2329 Error **errp)
2330 {
2331 RAMBlock *new_block;
2332 Error *local_err = NULL;
2333 int64_t file_size;
2334
2335 /* Just support these ram flags by now. */
2336 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2337
2338 if (xen_enabled()) {
2339 error_setg(errp, "-mem-path not supported with Xen");
2340 return NULL;
2341 }
2342
2343 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2344 error_setg(errp,
2345 "host lacks kvm mmu notifiers, -mem-path unsupported");
2346 return NULL;
2347 }
2348
2349 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2350 /*
2351 * file_ram_alloc() needs to allocate just like
2352 * phys_mem_alloc, but we haven't bothered to provide
2353 * a hook there.
2354 */
2355 error_setg(errp,
2356 "-mem-path not supported with this accelerator");
2357 return NULL;
2358 }
2359
2360 size = HOST_PAGE_ALIGN(size);
2361 file_size = get_file_size(fd);
2362 if (file_size > 0 && file_size < size) {
2363 error_setg(errp, "backing store %s size 0x%" PRIx64
2364 " does not match 'size' option 0x" RAM_ADDR_FMT,
2365 mem_path, file_size, size);
2366 return NULL;
2367 }
2368
2369 new_block = g_malloc0(sizeof(*new_block));
2370 new_block->mr = mr;
2371 new_block->used_length = size;
2372 new_block->max_length = size;
2373 new_block->flags = ram_flags;
2374 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2375 if (!new_block->host) {
2376 g_free(new_block);
2377 return NULL;
2378 }
2379
2380 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2381 if (local_err) {
2382 g_free(new_block);
2383 error_propagate(errp, local_err);
2384 return NULL;
2385 }
2386 return new_block;
2387
2388 }
2389
2390
2391 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2392 uint32_t ram_flags, const char *mem_path,
2393 Error **errp)
2394 {
2395 int fd;
2396 bool created;
2397 RAMBlock *block;
2398
2399 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2400 if (fd < 0) {
2401 return NULL;
2402 }
2403
2404 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2405 if (!block) {
2406 if (created) {
2407 unlink(mem_path);
2408 }
2409 close(fd);
2410 return NULL;
2411 }
2412
2413 return block;
2414 }
2415 #endif
2416
2417 static
2418 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2419 void (*resized)(const char*,
2420 uint64_t length,
2421 void *host),
2422 void *host, bool resizeable, bool share,
2423 MemoryRegion *mr, Error **errp)
2424 {
2425 RAMBlock *new_block;
2426 Error *local_err = NULL;
2427
2428 size = HOST_PAGE_ALIGN(size);
2429 max_size = HOST_PAGE_ALIGN(max_size);
2430 new_block = g_malloc0(sizeof(*new_block));
2431 new_block->mr = mr;
2432 new_block->resized = resized;
2433 new_block->used_length = size;
2434 new_block->max_length = max_size;
2435 assert(max_size >= size);
2436 new_block->fd = -1;
2437 new_block->page_size = getpagesize();
2438 new_block->host = host;
2439 if (host) {
2440 new_block->flags |= RAM_PREALLOC;
2441 }
2442 if (resizeable) {
2443 new_block->flags |= RAM_RESIZEABLE;
2444 }
2445 ram_block_add(new_block, &local_err, share);
2446 if (local_err) {
2447 g_free(new_block);
2448 error_propagate(errp, local_err);
2449 return NULL;
2450 }
2451 return new_block;
2452 }
2453
2454 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2455 MemoryRegion *mr, Error **errp)
2456 {
2457 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2458 false, mr, errp);
2459 }
2460
2461 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2462 MemoryRegion *mr, Error **errp)
2463 {
2464 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2465 share, mr, errp);
2466 }
2467
2468 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2469 void (*resized)(const char*,
2470 uint64_t length,
2471 void *host),
2472 MemoryRegion *mr, Error **errp)
2473 {
2474 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2475 false, mr, errp);
2476 }
2477
2478 static void reclaim_ramblock(RAMBlock *block)
2479 {
2480 if (block->flags & RAM_PREALLOC) {
2481 ;
2482 } else if (xen_enabled()) {
2483 xen_invalidate_map_cache_entry(block->host);
2484 #ifndef _WIN32
2485 } else if (block->fd >= 0) {
2486 qemu_ram_munmap(block->fd, block->host, block->max_length);
2487 close(block->fd);
2488 #endif
2489 } else {
2490 qemu_anon_ram_free(block->host, block->max_length);
2491 }
2492 g_free(block);
2493 }
2494
2495 void qemu_ram_free(RAMBlock *block)
2496 {
2497 if (!block) {
2498 return;
2499 }
2500
2501 if (block->host) {
2502 ram_block_notify_remove(block->host, block->max_length);
2503 }
2504
2505 qemu_mutex_lock_ramlist();
2506 QLIST_REMOVE_RCU(block, next);
2507 ram_list.mru_block = NULL;
2508 /* Write list before version */
2509 smp_wmb();
2510 ram_list.version++;
2511 call_rcu(block, reclaim_ramblock, rcu);
2512 qemu_mutex_unlock_ramlist();
2513 }
2514
2515 #ifndef _WIN32
2516 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2517 {
2518 RAMBlock *block;
2519 ram_addr_t offset;
2520 int flags;
2521 void *area, *vaddr;
2522
2523 RAMBLOCK_FOREACH(block) {
2524 offset = addr - block->offset;
2525 if (offset < block->max_length) {
2526 vaddr = ramblock_ptr(block, offset);
2527 if (block->flags & RAM_PREALLOC) {
2528 ;
2529 } else if (xen_enabled()) {
2530 abort();
2531 } else {
2532 flags = MAP_FIXED;
2533 if (block->fd >= 0) {
2534 flags |= (block->flags & RAM_SHARED ?
2535 MAP_SHARED : MAP_PRIVATE);
2536 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2537 flags, block->fd, offset);
2538 } else {
2539 /*
2540 * Remap needs to match alloc. Accelerators that
2541 * set phys_mem_alloc never remap. If they did,
2542 * we'd need a remap hook here.
2543 */
2544 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2545
2546 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2547 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2548 flags, -1, 0);
2549 }
2550 if (area != vaddr) {
2551 error_report("Could not remap addr: "
2552 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2553 length, addr);
2554 exit(1);
2555 }
2556 memory_try_enable_merging(vaddr, length);
2557 qemu_ram_setup_dump(vaddr, length);
2558 }
2559 }
2560 }
2561 }
2562 #endif /* !_WIN32 */
2563
2564 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2565 * This should not be used for general purpose DMA. Use address_space_map
2566 * or address_space_rw instead. For local memory (e.g. video ram) that the
2567 * device owns, use memory_region_get_ram_ptr.
2568 *
2569 * Called within RCU critical section.
2570 */
2571 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2572 {
2573 RAMBlock *block = ram_block;
2574
2575 if (block == NULL) {
2576 block = qemu_get_ram_block(addr);
2577 addr -= block->offset;
2578 }
2579
2580 if (xen_enabled() && block->host == NULL) {
2581 /* We need to check if the requested address is in the RAM
2582 * because we don't want to map the entire memory in QEMU.
2583 * In that case just map until the end of the page.
2584 */
2585 if (block->offset == 0) {
2586 return xen_map_cache(addr, 0, 0, false);
2587 }
2588
2589 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2590 }
2591 return ramblock_ptr(block, addr);
2592 }
2593
2594 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2595 * but takes a size argument.
2596 *
2597 * Called within RCU critical section.
2598 */
2599 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2600 hwaddr *size, bool lock)
2601 {
2602 RAMBlock *block = ram_block;
2603 if (*size == 0) {
2604 return NULL;
2605 }
2606
2607 if (block == NULL) {
2608 block = qemu_get_ram_block(addr);
2609 addr -= block->offset;
2610 }
2611 *size = MIN(*size, block->max_length - addr);
2612
2613 if (xen_enabled() && block->host == NULL) {
2614 /* We need to check if the requested address is in the RAM
2615 * because we don't want to map the entire memory in QEMU.
2616 * In that case just map the requested area.
2617 */
2618 if (block->offset == 0) {
2619 return xen_map_cache(addr, *size, lock, lock);
2620 }
2621
2622 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2623 }
2624
2625 return ramblock_ptr(block, addr);
2626 }
2627
2628 /* Return the offset of a hostpointer within a ramblock */
2629 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2630 {
2631 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2632 assert((uintptr_t)host >= (uintptr_t)rb->host);
2633 assert(res < rb->max_length);
2634
2635 return res;
2636 }
2637
2638 /*
2639 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2640 * in that RAMBlock.
2641 *
2642 * ptr: Host pointer to look up
2643 * round_offset: If true round the result offset down to a page boundary
2644 * *ram_addr: set to result ram_addr
2645 * *offset: set to result offset within the RAMBlock
2646 *
2647 * Returns: RAMBlock (or NULL if not found)
2648 *
2649 * By the time this function returns, the returned pointer is not protected
2650 * by RCU anymore. If the caller is not within an RCU critical section and
2651 * does not hold the iothread lock, it must have other means of protecting the
2652 * pointer, such as a reference to the region that includes the incoming
2653 * ram_addr_t.
2654 */
2655 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2656 ram_addr_t *offset)
2657 {
2658 RAMBlock *block;
2659 uint8_t *host = ptr;
2660
2661 if (xen_enabled()) {
2662 ram_addr_t ram_addr;
2663 rcu_read_lock();
2664 ram_addr = xen_ram_addr_from_mapcache(ptr);
2665 block = qemu_get_ram_block(ram_addr);
2666 if (block) {
2667 *offset = ram_addr - block->offset;
2668 }
2669 rcu_read_unlock();
2670 return block;
2671 }
2672
2673 rcu_read_lock();
2674 block = atomic_rcu_read(&ram_list.mru_block);
2675 if (block && block->host && host - block->host < block->max_length) {
2676 goto found;
2677 }
2678
2679 RAMBLOCK_FOREACH(block) {
2680 /* This case append when the block is not mapped. */
2681 if (block->host == NULL) {
2682 continue;
2683 }
2684 if (host - block->host < block->max_length) {
2685 goto found;
2686 }
2687 }
2688
2689 rcu_read_unlock();
2690 return NULL;
2691
2692 found:
2693 *offset = (host - block->host);
2694 if (round_offset) {
2695 *offset &= TARGET_PAGE_MASK;
2696 }
2697 rcu_read_unlock();
2698 return block;
2699 }
2700
2701 /*
2702 * Finds the named RAMBlock
2703 *
2704 * name: The name of RAMBlock to find
2705 *
2706 * Returns: RAMBlock (or NULL if not found)
2707 */
2708 RAMBlock *qemu_ram_block_by_name(const char *name)
2709 {
2710 RAMBlock *block;
2711
2712 RAMBLOCK_FOREACH(block) {
2713 if (!strcmp(name, block->idstr)) {
2714 return block;
2715 }
2716 }
2717
2718 return NULL;
2719 }
2720
2721 /* Some of the softmmu routines need to translate from a host pointer
2722 (typically a TLB entry) back to a ram offset. */
2723 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2724 {
2725 RAMBlock *block;
2726 ram_addr_t offset;
2727
2728 block = qemu_ram_block_from_host(ptr, false, &offset);
2729 if (!block) {
2730 return RAM_ADDR_INVALID;
2731 }
2732
2733 return block->offset + offset;
2734 }
2735
2736 /* Called within RCU critical section. */
2737 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2738 CPUState *cpu,
2739 vaddr mem_vaddr,
2740 ram_addr_t ram_addr,
2741 unsigned size)
2742 {
2743 ndi->cpu = cpu;
2744 ndi->ram_addr = ram_addr;
2745 ndi->mem_vaddr = mem_vaddr;
2746 ndi->size = size;
2747 ndi->pages = NULL;
2748
2749 assert(tcg_enabled());
2750 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2751 ndi->pages = page_collection_lock(ram_addr, ram_addr + size);
2752 tb_invalidate_phys_page_fast(ndi->pages, ram_addr, size);
2753 }
2754 }
2755
2756 /* Called within RCU critical section. */
2757 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2758 {
2759 if (ndi->pages) {
2760 assert(tcg_enabled());
2761 page_collection_unlock(ndi->pages);
2762 ndi->pages = NULL;
2763 }
2764
2765 /* Set both VGA and migration bits for simplicity and to remove
2766 * the notdirty callback faster.
2767 */
2768 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2769 DIRTY_CLIENTS_NOCODE);
2770 /* we remove the notdirty callback only if the code has been
2771 flushed */
2772 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2773 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2774 }
2775 }
2776
2777 /* Called within RCU critical section. */
2778 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2779 uint64_t val, unsigned size)
2780 {
2781 NotDirtyInfo ndi;
2782
2783 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2784 ram_addr, size);
2785
2786 stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val);
2787 memory_notdirty_write_complete(&ndi);
2788 }
2789
2790 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2791 unsigned size, bool is_write,
2792 MemTxAttrs attrs)
2793 {
2794 return is_write;
2795 }
2796
2797 static const MemoryRegionOps notdirty_mem_ops = {
2798 .write = notdirty_mem_write,
2799 .valid.accepts = notdirty_mem_accepts,
2800 .endianness = DEVICE_NATIVE_ENDIAN,
2801 .valid = {
2802 .min_access_size = 1,
2803 .max_access_size = 8,
2804 .unaligned = false,
2805 },
2806 .impl = {
2807 .min_access_size = 1,
2808 .max_access_size = 8,
2809 .unaligned = false,
2810 },
2811 };
2812
2813 /* Generate a debug exception if a watchpoint has been hit. */
2814 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2815 {
2816 CPUState *cpu = current_cpu;
2817 CPUClass *cc = CPU_GET_CLASS(cpu);
2818 target_ulong vaddr;
2819 CPUWatchpoint *wp;
2820
2821 assert(tcg_enabled());
2822 if (cpu->watchpoint_hit) {
2823 /* We re-entered the check after replacing the TB. Now raise
2824 * the debug interrupt so that is will trigger after the
2825 * current instruction. */
2826 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2827 return;
2828 }
2829 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2830 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2831 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2832 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2833 && (wp->flags & flags)) {
2834 if (flags == BP_MEM_READ) {
2835 wp->flags |= BP_WATCHPOINT_HIT_READ;
2836 } else {
2837 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2838 }
2839 wp->hitaddr = vaddr;
2840 wp->hitattrs = attrs;
2841 if (!cpu->watchpoint_hit) {
2842 if (wp->flags & BP_CPU &&
2843 !cc->debug_check_watchpoint(cpu, wp)) {
2844 wp->flags &= ~BP_WATCHPOINT_HIT;
2845 continue;
2846 }
2847 cpu->watchpoint_hit = wp;
2848
2849 mmap_lock();
2850 tb_check_watchpoint(cpu);
2851 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2852 cpu->exception_index = EXCP_DEBUG;
2853 mmap_unlock();
2854 cpu_loop_exit(cpu);
2855 } else {
2856 /* Force execution of one insn next time. */
2857 cpu->cflags_next_tb = 1 | curr_cflags();
2858 mmap_unlock();
2859 cpu_loop_exit_noexc(cpu);
2860 }
2861 }
2862 } else {
2863 wp->flags &= ~BP_WATCHPOINT_HIT;
2864 }
2865 }
2866 }
2867
2868 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2869 so these check for a hit then pass through to the normal out-of-line
2870 phys routines. */
2871 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2872 unsigned size, MemTxAttrs attrs)
2873 {
2874 MemTxResult res;
2875 uint64_t data;
2876 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2877 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2878
2879 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2880 switch (size) {
2881 case 1:
2882 data = address_space_ldub(as, addr, attrs, &res);
2883 break;
2884 case 2:
2885 data = address_space_lduw(as, addr, attrs, &res);
2886 break;
2887 case 4:
2888 data = address_space_ldl(as, addr, attrs, &res);
2889 break;
2890 case 8:
2891 data = address_space_ldq(as, addr, attrs, &res);
2892 break;
2893 default: abort();
2894 }
2895 *pdata = data;
2896 return res;
2897 }
2898
2899 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2900 uint64_t val, unsigned size,
2901 MemTxAttrs attrs)
2902 {
2903 MemTxResult res;
2904 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2905 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2906
2907 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2908 switch (size) {
2909 case 1:
2910 address_space_stb(as, addr, val, attrs, &res);
2911 break;
2912 case 2:
2913 address_space_stw(as, addr, val, attrs, &res);
2914 break;
2915 case 4:
2916 address_space_stl(as, addr, val, attrs, &res);
2917 break;
2918 case 8:
2919 address_space_stq(as, addr, val, attrs, &res);
2920 break;
2921 default: abort();
2922 }
2923 return res;
2924 }
2925
2926 static const MemoryRegionOps watch_mem_ops = {
2927 .read_with_attrs = watch_mem_read,
2928 .write_with_attrs = watch_mem_write,
2929 .endianness = DEVICE_NATIVE_ENDIAN,
2930 .valid = {
2931 .min_access_size = 1,
2932 .max_access_size = 8,
2933 .unaligned = false,
2934 },
2935 .impl = {
2936 .min_access_size = 1,
2937 .max_access_size = 8,
2938 .unaligned = false,
2939 },
2940 };
2941
2942 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2943 MemTxAttrs attrs, uint8_t *buf, hwaddr len);
2944 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2945 const uint8_t *buf, hwaddr len);
2946 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2947 bool is_write, MemTxAttrs attrs);
2948
2949 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2950 unsigned len, MemTxAttrs attrs)
2951 {
2952 subpage_t *subpage = opaque;
2953 uint8_t buf[8];
2954 MemTxResult res;
2955
2956 #if defined(DEBUG_SUBPAGE)
2957 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2958 subpage, len, addr);
2959 #endif
2960 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2961 if (res) {
2962 return res;
2963 }
2964 *data = ldn_p(buf, len);
2965 return MEMTX_OK;
2966 }
2967
2968 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2969 uint64_t value, unsigned len, MemTxAttrs attrs)
2970 {
2971 subpage_t *subpage = opaque;
2972 uint8_t buf[8];
2973
2974 #if defined(DEBUG_SUBPAGE)
2975 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2976 " value %"PRIx64"\n",
2977 __func__, subpage, len, addr, value);
2978 #endif
2979 stn_p(buf, len, value);
2980 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2981 }
2982
2983 static bool subpage_accepts(void *opaque, hwaddr addr,
2984 unsigned len, bool is_write,
2985 MemTxAttrs attrs)
2986 {
2987 subpage_t *subpage = opaque;
2988 #if defined(DEBUG_SUBPAGE)
2989 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2990 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2991 #endif
2992
2993 return flatview_access_valid(subpage->fv, addr + subpage->base,
2994 len, is_write, attrs);
2995 }
2996
2997 static const MemoryRegionOps subpage_ops = {
2998 .read_with_attrs = subpage_read,
2999 .write_with_attrs = subpage_write,
3000 .impl.min_access_size = 1,
3001 .impl.max_access_size = 8,
3002 .valid.min_access_size = 1,
3003 .valid.max_access_size = 8,
3004 .valid.accepts = subpage_accepts,
3005 .endianness = DEVICE_NATIVE_ENDIAN,
3006 };
3007
3008 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
3009 uint16_t section)
3010 {
3011 int idx, eidx;
3012
3013 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
3014 return -1;
3015 idx = SUBPAGE_IDX(start);
3016 eidx = SUBPAGE_IDX(end);
3017 #if defined(DEBUG_SUBPAGE)
3018 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
3019 __func__, mmio, start, end, idx, eidx, section);
3020 #endif
3021 for (; idx <= eidx; idx++) {
3022 mmio->sub_section[idx] = section;
3023 }
3024
3025 return 0;
3026 }
3027
3028 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
3029 {
3030 subpage_t *mmio;
3031
3032 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
3033 mmio->fv = fv;
3034 mmio->base = base;
3035 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
3036 NULL, TARGET_PAGE_SIZE);
3037 mmio->iomem.subpage = true;
3038 #if defined(DEBUG_SUBPAGE)
3039 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
3040 mmio, base, TARGET_PAGE_SIZE);
3041 #endif
3042 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
3043
3044 return mmio;
3045 }
3046
3047 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
3048 {
3049 assert(fv);
3050 MemoryRegionSection section = {
3051 .fv = fv,
3052 .mr = mr,
3053 .offset_within_address_space = 0,
3054 .offset_within_region = 0,
3055 .size = int128_2_64(),
3056 };
3057
3058 return phys_section_add(map, &section);
3059 }
3060
3061 static void readonly_mem_write(void *opaque, hwaddr addr,
3062 uint64_t val, unsigned size)
3063 {
3064 /* Ignore any write to ROM. */
3065 }
3066
3067 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
3068 unsigned size, bool is_write,
3069 MemTxAttrs attrs)
3070 {
3071 return is_write;
3072 }
3073
3074 /* This will only be used for writes, because reads are special cased
3075 * to directly access the underlying host ram.
3076 */
3077 static const MemoryRegionOps readonly_mem_ops = {
3078 .write = readonly_mem_write,
3079 .valid.accepts = readonly_mem_accepts,
3080 .endianness = DEVICE_NATIVE_ENDIAN,
3081 .valid = {
3082 .min_access_size = 1,
3083 .max_access_size = 8,
3084 .unaligned = false,
3085 },
3086 .impl = {
3087 .min_access_size = 1,
3088 .max_access_size = 8,
3089 .unaligned = false,
3090 },
3091 };
3092
3093 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
3094 hwaddr index, MemTxAttrs attrs)
3095 {
3096 int asidx = cpu_asidx_from_attrs(cpu, attrs);
3097 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
3098 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
3099 MemoryRegionSection *sections = d->map.sections;
3100
3101 return &sections[index & ~TARGET_PAGE_MASK];
3102 }
3103
3104 static void io_mem_init(void)
3105 {
3106 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
3107 NULL, NULL, UINT64_MAX);
3108 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
3109 NULL, UINT64_MAX);
3110
3111 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3112 * which can be called without the iothread mutex.
3113 */
3114 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
3115 NULL, UINT64_MAX);
3116 memory_region_clear_global_locking(&io_mem_notdirty);
3117
3118 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
3119 NULL, UINT64_MAX);
3120 }
3121
3122 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
3123 {
3124 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
3125 uint16_t n;
3126
3127 n = dummy_section(&d->map, fv, &io_mem_unassigned);
3128 assert(n == PHYS_SECTION_UNASSIGNED);
3129 n = dummy_section(&d->map, fv, &io_mem_notdirty);
3130 assert(n == PHYS_SECTION_NOTDIRTY);
3131 n = dummy_section(&d->map, fv, &io_mem_rom);
3132 assert(n == PHYS_SECTION_ROM);
3133 n = dummy_section(&d->map, fv, &io_mem_watch);
3134 assert(n == PHYS_SECTION_WATCH);
3135
3136 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
3137
3138 return d;
3139 }
3140
3141 void address_space_dispatch_free(AddressSpaceDispatch *d)
3142 {
3143 phys_sections_free(&d->map);
3144 g_free(d);
3145 }
3146
3147 static void do_nothing(CPUState *cpu, run_on_cpu_data d)
3148 {
3149 }
3150
3151 static void tcg_log_global_after_sync(MemoryListener *listener)
3152 {
3153 CPUAddressSpace *cpuas;
3154
3155 /* Wait for the CPU to end the current TB. This avoids the following
3156 * incorrect race:
3157 *
3158 * vCPU migration
3159 * ---------------------- -------------------------
3160 * TLB check -> slow path
3161 * notdirty_mem_write
3162 * write to RAM
3163 * mark dirty
3164 * clear dirty flag
3165 * TLB check -> fast path
3166 * read memory
3167 * write to RAM
3168 *
3169 * by pushing the migration thread's memory read after the vCPU thread has
3170 * written the memory.
3171 */
3172 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
3173 run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL);
3174 }
3175
3176 static void tcg_commit(MemoryListener *listener)
3177 {
3178 CPUAddressSpace *cpuas;
3179 AddressSpaceDispatch *d;
3180
3181 assert(tcg_enabled());
3182 /* since each CPU stores ram addresses in its TLB cache, we must
3183 reset the modified entries */
3184 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
3185 cpu_reloading_memory_map();
3186 /* The CPU and TLB are protected by the iothread lock.
3187 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3188 * may have split the RCU critical section.
3189 */
3190 d = address_space_to_dispatch(cpuas->as);
3191 atomic_rcu_set(&cpuas->memory_dispatch, d);
3192 tlb_flush(cpuas->cpu);
3193 }
3194
3195 static void memory_map_init(void)
3196 {
3197 system_memory = g_malloc(sizeof(*system_memory));
3198
3199 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
3200 address_space_init(&address_space_memory, system_memory, "memory");
3201
3202 system_io = g_malloc(sizeof(*system_io));
3203 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
3204 65536);
3205 address_space_init(&address_space_io, system_io, "I/O");
3206 }
3207
3208 MemoryRegion *get_system_memory(void)
3209 {
3210 return system_memory;
3211 }
3212
3213 MemoryRegion *get_system_io(void)
3214 {
3215 return system_io;
3216 }
3217
3218 #endif /* !defined(CONFIG_USER_ONLY) */
3219
3220 /* physical memory access (slow version, mainly for debug) */
3221 #if defined(CONFIG_USER_ONLY)
3222 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3223 uint8_t *buf, target_ulong len, int is_write)
3224 {
3225 int flags;
3226 target_ulong l, page;
3227 void * p;
3228
3229 while (len > 0) {
3230 page = addr & TARGET_PAGE_MASK;
3231 l = (page + TARGET_PAGE_SIZE) - addr;
3232 if (l > len)
3233 l = len;
3234 flags = page_get_flags(page);
3235 if (!(flags & PAGE_VALID))
3236 return -1;
3237 if (is_write) {
3238 if (!(flags & PAGE_WRITE))
3239 return -1;
3240 /* XXX: this code should not depend on lock_user */
3241 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3242 return -1;
3243 memcpy(p, buf, l);
3244 unlock_user(p, addr, l);
3245 } else {
3246 if (!(flags & PAGE_READ))
3247 return -1;
3248 /* XXX: this code should not depend on lock_user */
3249 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3250 return -1;
3251 memcpy(buf, p, l);
3252 unlock_user(p, addr, 0);
3253 }
3254 len -= l;
3255 buf += l;
3256 addr += l;
3257 }
3258 return 0;
3259 }
3260
3261 #else
3262
3263 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3264 hwaddr length)
3265 {
3266 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3267 addr += memory_region_get_ram_addr(mr);
3268
3269 /* No early return if dirty_log_mask is or becomes 0, because
3270 * cpu_physical_memory_set_dirty_range will still call
3271 * xen_modified_memory.
3272 */
3273 if (dirty_log_mask) {
3274 dirty_log_mask =
3275 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3276 }
3277 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3278 assert(tcg_enabled());
3279 tb_invalidate_phys_range(addr, addr + length);
3280 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3281 }
3282 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3283 }
3284
3285 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3286 {
3287 /*
3288 * In principle this function would work on other memory region types too,
3289 * but the ROM device use case is the only one where this operation is
3290 * necessary. Other memory regions should use the
3291 * address_space_read/write() APIs.
3292 */
3293 assert(memory_region_is_romd(mr));
3294
3295 invalidate_and_set_dirty(mr, addr, size);
3296 }
3297
3298 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3299 {
3300 unsigned access_size_max = mr->ops->valid.max_access_size;
3301
3302 /* Regions are assumed to support 1-4 byte accesses unless
3303 otherwise specified. */
3304 if (access_size_max == 0) {
3305 access_size_max = 4;
3306 }
3307
3308 /* Bound the maximum access by the alignment of the address. */
3309 if (!mr->ops->impl.unaligned) {
3310 unsigned align_size_max = addr & -addr;
3311 if (align_size_max != 0 && align_size_max < access_size_max) {
3312 access_size_max = align_size_max;
3313 }
3314 }
3315
3316 /* Don't attempt accesses larger than the maximum. */
3317 if (l > access_size_max) {
3318 l = access_size_max;
3319 }
3320 l = pow2floor(l);
3321
3322 return l;
3323 }
3324
3325 static bool prepare_mmio_access(MemoryRegion *mr)
3326 {
3327 bool unlocked = !qemu_mutex_iothread_locked();
3328 bool release_lock = false;
3329
3330 if (unlocked && mr->global_locking) {
3331 qemu_mutex_lock_iothread();
3332 unlocked = false;
3333 release_lock = true;
3334 }
3335 if (mr->flush_coalesced_mmio) {
3336 if (unlocked) {
3337 qemu_mutex_lock_iothread();
3338 }
3339 qemu_flush_coalesced_mmio_buffer();
3340 if (unlocked) {
3341 qemu_mutex_unlock_iothread();
3342 }
3343 }
3344
3345 return release_lock;
3346 }
3347
3348 /* Called within RCU critical section. */
3349 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3350 MemTxAttrs attrs,
3351 const uint8_t *buf,
3352 hwaddr len, hwaddr addr1,
3353 hwaddr l, MemoryRegion *mr)
3354 {
3355 uint8_t *ptr;
3356 uint64_t val;
3357 MemTxResult result = MEMTX_OK;
3358 bool release_lock = false;
3359
3360 for (;;) {
3361 if (!memory_access_is_direct(mr, true)) {
3362 release_lock |= prepare_mmio_access(mr);
3363 l = memory_access_size(mr, l, addr1);
3364 /* XXX: could force current_cpu to NULL to avoid
3365 potential bugs */
3366 val = ldn_p(buf, l);
3367 result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
3368 } else {
3369 /* RAM case */
3370 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3371 memcpy(ptr, buf, l);
3372 invalidate_and_set_dirty(mr, addr1, l);
3373 }
3374
3375 if (release_lock) {
3376 qemu_mutex_unlock_iothread();
3377 release_lock = false;
3378 }
3379
3380 len -= l;
3381 buf += l;
3382 addr += l;
3383
3384 if (!len) {
3385 break;
3386 }
3387
3388 l = len;
3389 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3390 }
3391
3392 return result;
3393 }
3394
3395 /* Called from RCU critical section. */
3396 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3397 const uint8_t *buf, hwaddr len)
3398 {
3399 hwaddr l;
3400 hwaddr addr1;
3401 MemoryRegion *mr;
3402 MemTxResult result = MEMTX_OK;
3403
3404 l = len;
3405 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3406 result = flatview_write_continue(fv, addr, attrs, buf, len,
3407 addr1, l, mr);
3408
3409 return result;
3410 }
3411
3412 /* Called within RCU critical section. */
3413 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3414 MemTxAttrs attrs, uint8_t *buf,
3415 hwaddr len, hwaddr addr1, hwaddr l,
3416 MemoryRegion *mr)
3417 {
3418 uint8_t *ptr;
3419 uint64_t val;
3420 MemTxResult result = MEMTX_OK;
3421 bool release_lock = false;
3422
3423 for (;;) {
3424 if (!memory_access_is_direct(mr, false)) {
3425 /* I/O case */
3426 release_lock |= prepare_mmio_access(mr);
3427 l = memory_access_size(mr, l, addr1);
3428 result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
3429 stn_p(buf, l, val);
3430 } else {
3431 /* RAM case */
3432 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3433 memcpy(buf, ptr, l);
3434 }
3435
3436 if (release_lock) {
3437 qemu_mutex_unlock_iothread();
3438 release_lock = false;
3439 }
3440
3441 len -= l;
3442 buf += l;
3443 addr += l;
3444
3445 if (!len) {
3446 break;
3447 }
3448
3449 l = len;
3450 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3451 }
3452
3453 return result;
3454 }
3455
3456 /* Called from RCU critical section. */
3457 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3458 MemTxAttrs attrs, uint8_t *buf, hwaddr len)
3459 {
3460 hwaddr l;
3461 hwaddr addr1;
3462 MemoryRegion *mr;
3463
3464 l = len;
3465 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3466 return flatview_read_continue(fv, addr, attrs, buf, len,
3467 addr1, l, mr);
3468 }
3469
3470 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3471 MemTxAttrs attrs, uint8_t *buf, hwaddr len)
3472 {
3473 MemTxResult result = MEMTX_OK;
3474 FlatView *fv;
3475
3476 if (len > 0) {
3477 rcu_read_lock();
3478 fv = address_space_to_flatview(as);
3479 result = flatview_read(fv, addr, attrs, buf, len);
3480 rcu_read_unlock();
3481 }
3482
3483 return result;
3484 }
3485
3486 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3487 MemTxAttrs attrs,
3488 const uint8_t *buf, hwaddr len)
3489 {
3490 MemTxResult result = MEMTX_OK;
3491 FlatView *fv;
3492
3493 if (len > 0) {
3494 rcu_read_lock();
3495 fv = address_space_to_flatview(as);
3496 result = flatview_write(fv, addr, attrs, buf, len);
3497 rcu_read_unlock();
3498 }
3499
3500 return result;
3501 }
3502
3503 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3504 uint8_t *buf, hwaddr len, bool is_write)
3505 {
3506 if (is_write) {
3507 return address_space_write(as, addr, attrs, buf, len);
3508 } else {
3509 return address_space_read_full(as, addr, attrs, buf, len);
3510 }
3511 }
3512
3513 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3514 hwaddr len, int is_write)
3515 {
3516 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3517 buf, len, is_write);
3518 }
3519
3520 enum write_rom_type {
3521 WRITE_DATA,
3522 FLUSH_CACHE,
3523 };
3524
3525 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3526 hwaddr addr,
3527 MemTxAttrs attrs,
3528 const uint8_t *buf,
3529 hwaddr len,
3530 enum write_rom_type type)
3531 {
3532 hwaddr l;
3533 uint8_t *ptr;
3534 hwaddr addr1;
3535 MemoryRegion *mr;
3536
3537 rcu_read_lock();
3538 while (len > 0) {
3539 l = len;
3540 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3541
3542 if (!(memory_region_is_ram(mr) ||
3543 memory_region_is_romd(mr))) {
3544 l = memory_access_size(mr, l, addr1);
3545 } else {
3546 /* ROM/RAM case */
3547 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3548 switch (type) {
3549 case WRITE_DATA:
3550 memcpy(ptr, buf, l);
3551 invalidate_and_set_dirty(mr, addr1, l);
3552 break;
3553 case FLUSH_CACHE:
3554 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3555 break;
3556 }
3557 }
3558 len -= l;
3559 buf += l;
3560 addr += l;
3561 }
3562 rcu_read_unlock();
3563 return MEMTX_OK;
3564 }
3565
3566 /* used for ROM loading : can write in RAM and ROM */
3567 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3568 MemTxAttrs attrs,
3569 const uint8_t *buf, hwaddr len)
3570 {
3571 return address_space_write_rom_internal(as, addr, attrs,
3572 buf, len, WRITE_DATA);
3573 }
3574
3575 void cpu_flush_icache_range(hwaddr start, hwaddr len)
3576 {
3577 /*
3578 * This function should do the same thing as an icache flush that was
3579 * triggered from within the guest. For TCG we are always cach