virtio-pci: address space translation service (ATS) support
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "tcg.h"
28 #include "hw/qdev-core.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "exec/address-spaces.h"
46 #include "sysemu/xen-mapcache.h"
47 #include "trace.h"
48 #endif
49 #include "exec/cpu-all.h"
50 #include "qemu/rcu_queue.h"
51 #include "qemu/main-loop.h"
52 #include "translate-all.h"
53 #include "sysemu/replay.h"
54
55 #include "exec/memory-internal.h"
56 #include "exec/ram_addr.h"
57 #include "exec/log.h"
58
59 #include "migration/vmstate.h"
60
61 #include "qemu/range.h"
62 #ifndef _WIN32
63 #include "qemu/mmap-alloc.h"
64 #endif
65
66 //#define DEBUG_SUBPAGE
67
68 #if !defined(CONFIG_USER_ONLY)
69 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
70 * are protected by the ramlist lock.
71 */
72 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
73
74 static MemoryRegion *system_memory;
75 static MemoryRegion *system_io;
76
77 AddressSpace address_space_io;
78 AddressSpace address_space_memory;
79
80 MemoryRegion io_mem_rom, io_mem_notdirty;
81 static MemoryRegion io_mem_unassigned;
82
83 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
84 #define RAM_PREALLOC (1 << 0)
85
86 /* RAM is mmap-ed with MAP_SHARED */
87 #define RAM_SHARED (1 << 1)
88
89 /* Only a portion of RAM (used_length) is actually used, and migrated.
90 * This used_length size can change across reboots.
91 */
92 #define RAM_RESIZEABLE (1 << 2)
93
94 #endif
95
96 #ifdef TARGET_PAGE_BITS_VARY
97 int target_page_bits;
98 bool target_page_bits_decided;
99 #endif
100
101 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
102 /* current CPU in the current thread. It is only valid inside
103 cpu_exec() */
104 __thread CPUState *current_cpu;
105 /* 0 = Do not count executed instructions.
106 1 = Precise instruction counting.
107 2 = Adaptive rate instruction counting. */
108 int use_icount;
109
110 bool set_preferred_target_page_bits(int bits)
111 {
112 /* The target page size is the lowest common denominator for all
113 * the CPUs in the system, so we can only make it smaller, never
114 * larger. And we can't make it smaller once we've committed to
115 * a particular size.
116 */
117 #ifdef TARGET_PAGE_BITS_VARY
118 assert(bits >= TARGET_PAGE_BITS_MIN);
119 if (target_page_bits == 0 || target_page_bits > bits) {
120 if (target_page_bits_decided) {
121 return false;
122 }
123 target_page_bits = bits;
124 }
125 #endif
126 return true;
127 }
128
129 #if !defined(CONFIG_USER_ONLY)
130
131 static void finalize_target_page_bits(void)
132 {
133 #ifdef TARGET_PAGE_BITS_VARY
134 if (target_page_bits == 0) {
135 target_page_bits = TARGET_PAGE_BITS_MIN;
136 }
137 target_page_bits_decided = true;
138 #endif
139 }
140
141 typedef struct PhysPageEntry PhysPageEntry;
142
143 struct PhysPageEntry {
144 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
145 uint32_t skip : 6;
146 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
147 uint32_t ptr : 26;
148 };
149
150 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
151
152 /* Size of the L2 (and L3, etc) page tables. */
153 #define ADDR_SPACE_BITS 64
154
155 #define P_L2_BITS 9
156 #define P_L2_SIZE (1 << P_L2_BITS)
157
158 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
159
160 typedef PhysPageEntry Node[P_L2_SIZE];
161
162 typedef struct PhysPageMap {
163 struct rcu_head rcu;
164
165 unsigned sections_nb;
166 unsigned sections_nb_alloc;
167 unsigned nodes_nb;
168 unsigned nodes_nb_alloc;
169 Node *nodes;
170 MemoryRegionSection *sections;
171 } PhysPageMap;
172
173 struct AddressSpaceDispatch {
174 struct rcu_head rcu;
175
176 MemoryRegionSection *mru_section;
177 /* This is a multi-level map on the physical address space.
178 * The bottom level has pointers to MemoryRegionSections.
179 */
180 PhysPageEntry phys_map;
181 PhysPageMap map;
182 AddressSpace *as;
183 };
184
185 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
186 typedef struct subpage_t {
187 MemoryRegion iomem;
188 AddressSpace *as;
189 hwaddr base;
190 uint16_t sub_section[];
191 } subpage_t;
192
193 #define PHYS_SECTION_UNASSIGNED 0
194 #define PHYS_SECTION_NOTDIRTY 1
195 #define PHYS_SECTION_ROM 2
196 #define PHYS_SECTION_WATCH 3
197
198 static void io_mem_init(void);
199 static void memory_map_init(void);
200 static void tcg_commit(MemoryListener *listener);
201
202 static MemoryRegion io_mem_watch;
203
204 /**
205 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
206 * @cpu: the CPU whose AddressSpace this is
207 * @as: the AddressSpace itself
208 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
209 * @tcg_as_listener: listener for tracking changes to the AddressSpace
210 */
211 struct CPUAddressSpace {
212 CPUState *cpu;
213 AddressSpace *as;
214 struct AddressSpaceDispatch *memory_dispatch;
215 MemoryListener tcg_as_listener;
216 };
217
218 #endif
219
220 #if !defined(CONFIG_USER_ONLY)
221
222 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
223 {
224 static unsigned alloc_hint = 16;
225 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
226 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
227 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
228 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
229 alloc_hint = map->nodes_nb_alloc;
230 }
231 }
232
233 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
234 {
235 unsigned i;
236 uint32_t ret;
237 PhysPageEntry e;
238 PhysPageEntry *p;
239
240 ret = map->nodes_nb++;
241 p = map->nodes[ret];
242 assert(ret != PHYS_MAP_NODE_NIL);
243 assert(ret != map->nodes_nb_alloc);
244
245 e.skip = leaf ? 0 : 1;
246 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
247 for (i = 0; i < P_L2_SIZE; ++i) {
248 memcpy(&p[i], &e, sizeof(e));
249 }
250 return ret;
251 }
252
253 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
254 hwaddr *index, hwaddr *nb, uint16_t leaf,
255 int level)
256 {
257 PhysPageEntry *p;
258 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
259
260 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
261 lp->ptr = phys_map_node_alloc(map, level == 0);
262 }
263 p = map->nodes[lp->ptr];
264 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
265
266 while (*nb && lp < &p[P_L2_SIZE]) {
267 if ((*index & (step - 1)) == 0 && *nb >= step) {
268 lp->skip = 0;
269 lp->ptr = leaf;
270 *index += step;
271 *nb -= step;
272 } else {
273 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
274 }
275 ++lp;
276 }
277 }
278
279 static void phys_page_set(AddressSpaceDispatch *d,
280 hwaddr index, hwaddr nb,
281 uint16_t leaf)
282 {
283 /* Wildly overreserve - it doesn't matter much. */
284 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
285
286 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
287 }
288
289 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
290 * and update our entry so we can skip it and go directly to the destination.
291 */
292 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
293 {
294 unsigned valid_ptr = P_L2_SIZE;
295 int valid = 0;
296 PhysPageEntry *p;
297 int i;
298
299 if (lp->ptr == PHYS_MAP_NODE_NIL) {
300 return;
301 }
302
303 p = nodes[lp->ptr];
304 for (i = 0; i < P_L2_SIZE; i++) {
305 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
306 continue;
307 }
308
309 valid_ptr = i;
310 valid++;
311 if (p[i].skip) {
312 phys_page_compact(&p[i], nodes);
313 }
314 }
315
316 /* We can only compress if there's only one child. */
317 if (valid != 1) {
318 return;
319 }
320
321 assert(valid_ptr < P_L2_SIZE);
322
323 /* Don't compress if it won't fit in the # of bits we have. */
324 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
325 return;
326 }
327
328 lp->ptr = p[valid_ptr].ptr;
329 if (!p[valid_ptr].skip) {
330 /* If our only child is a leaf, make this a leaf. */
331 /* By design, we should have made this node a leaf to begin with so we
332 * should never reach here.
333 * But since it's so simple to handle this, let's do it just in case we
334 * change this rule.
335 */
336 lp->skip = 0;
337 } else {
338 lp->skip += p[valid_ptr].skip;
339 }
340 }
341
342 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
343 {
344 if (d->phys_map.skip) {
345 phys_page_compact(&d->phys_map, d->map.nodes);
346 }
347 }
348
349 static inline bool section_covers_addr(const MemoryRegionSection *section,
350 hwaddr addr)
351 {
352 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
353 * the section must cover the entire address space.
354 */
355 return int128_gethi(section->size) ||
356 range_covers_byte(section->offset_within_address_space,
357 int128_getlo(section->size), addr);
358 }
359
360 static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr,
361 Node *nodes, MemoryRegionSection *sections)
362 {
363 PhysPageEntry *p;
364 hwaddr index = addr >> TARGET_PAGE_BITS;
365 int i;
366
367 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
368 if (lp.ptr == PHYS_MAP_NODE_NIL) {
369 return &sections[PHYS_SECTION_UNASSIGNED];
370 }
371 p = nodes[lp.ptr];
372 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
373 }
374
375 if (section_covers_addr(&sections[lp.ptr], addr)) {
376 return &sections[lp.ptr];
377 } else {
378 return &sections[PHYS_SECTION_UNASSIGNED];
379 }
380 }
381
382 bool memory_region_is_unassigned(MemoryRegion *mr)
383 {
384 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
385 && mr != &io_mem_watch;
386 }
387
388 /* Called from RCU critical section */
389 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
390 hwaddr addr,
391 bool resolve_subpage)
392 {
393 MemoryRegionSection *section = atomic_read(&d->mru_section);
394 subpage_t *subpage;
395 bool update;
396
397 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
398 section_covers_addr(section, addr)) {
399 update = false;
400 } else {
401 section = phys_page_find(d->phys_map, addr, d->map.nodes,
402 d->map.sections);
403 update = true;
404 }
405 if (resolve_subpage && section->mr->subpage) {
406 subpage = container_of(section->mr, subpage_t, iomem);
407 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
408 }
409 if (update) {
410 atomic_set(&d->mru_section, section);
411 }
412 return section;
413 }
414
415 /* Called from RCU critical section */
416 static MemoryRegionSection *
417 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
418 hwaddr *plen, bool resolve_subpage)
419 {
420 MemoryRegionSection *section;
421 MemoryRegion *mr;
422 Int128 diff;
423
424 section = address_space_lookup_region(d, addr, resolve_subpage);
425 /* Compute offset within MemoryRegionSection */
426 addr -= section->offset_within_address_space;
427
428 /* Compute offset within MemoryRegion */
429 *xlat = addr + section->offset_within_region;
430
431 mr = section->mr;
432
433 /* MMIO registers can be expected to perform full-width accesses based only
434 * on their address, without considering adjacent registers that could
435 * decode to completely different MemoryRegions. When such registers
436 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
437 * regions overlap wildly. For this reason we cannot clamp the accesses
438 * here.
439 *
440 * If the length is small (as is the case for address_space_ldl/stl),
441 * everything works fine. If the incoming length is large, however,
442 * the caller really has to do the clamping through memory_access_size.
443 */
444 if (memory_region_is_ram(mr)) {
445 diff = int128_sub(section->size, int128_make64(addr));
446 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
447 }
448 return section;
449 }
450
451 /* Called from RCU critical section */
452 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
453 bool is_write)
454 {
455 IOMMUTLBEntry iotlb = {0};
456 MemoryRegionSection *section;
457 MemoryRegion *mr;
458
459 for (;;) {
460 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
461 section = address_space_lookup_region(d, addr, false);
462 addr = addr - section->offset_within_address_space
463 + section->offset_within_region;
464 mr = section->mr;
465
466 if (!mr->iommu_ops) {
467 break;
468 }
469
470 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
471 if (!(iotlb.perm & (1 << is_write))) {
472 iotlb.target_as = NULL;
473 break;
474 }
475
476 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
477 | (addr & iotlb.addr_mask));
478 as = iotlb.target_as;
479 }
480
481 return iotlb;
482 }
483
484 /* Called from RCU critical section */
485 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
486 hwaddr *xlat, hwaddr *plen,
487 bool is_write)
488 {
489 IOMMUTLBEntry iotlb;
490 MemoryRegionSection *section;
491 MemoryRegion *mr;
492
493 for (;;) {
494 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
495 section = address_space_translate_internal(d, addr, &addr, plen, true);
496 mr = section->mr;
497
498 if (!mr->iommu_ops) {
499 break;
500 }
501
502 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
503 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
504 | (addr & iotlb.addr_mask));
505 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
506 if (!(iotlb.perm & (1 << is_write))) {
507 mr = &io_mem_unassigned;
508 break;
509 }
510
511 as = iotlb.target_as;
512 }
513
514 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
515 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
516 *plen = MIN(page, *plen);
517 }
518
519 *xlat = addr;
520 return mr;
521 }
522
523 /* Called from RCU critical section */
524 MemoryRegionSection *
525 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
526 hwaddr *xlat, hwaddr *plen)
527 {
528 MemoryRegionSection *section;
529 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
530
531 section = address_space_translate_internal(d, addr, xlat, plen, false);
532
533 assert(!section->mr->iommu_ops);
534 return section;
535 }
536 #endif
537
538 #if !defined(CONFIG_USER_ONLY)
539
540 static int cpu_common_post_load(void *opaque, int version_id)
541 {
542 CPUState *cpu = opaque;
543
544 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
545 version_id is increased. */
546 cpu->interrupt_request &= ~0x01;
547 tlb_flush(cpu, 1);
548
549 return 0;
550 }
551
552 static int cpu_common_pre_load(void *opaque)
553 {
554 CPUState *cpu = opaque;
555
556 cpu->exception_index = -1;
557
558 return 0;
559 }
560
561 static bool cpu_common_exception_index_needed(void *opaque)
562 {
563 CPUState *cpu = opaque;
564
565 return tcg_enabled() && cpu->exception_index != -1;
566 }
567
568 static const VMStateDescription vmstate_cpu_common_exception_index = {
569 .name = "cpu_common/exception_index",
570 .version_id = 1,
571 .minimum_version_id = 1,
572 .needed = cpu_common_exception_index_needed,
573 .fields = (VMStateField[]) {
574 VMSTATE_INT32(exception_index, CPUState),
575 VMSTATE_END_OF_LIST()
576 }
577 };
578
579 static bool cpu_common_crash_occurred_needed(void *opaque)
580 {
581 CPUState *cpu = opaque;
582
583 return cpu->crash_occurred;
584 }
585
586 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
587 .name = "cpu_common/crash_occurred",
588 .version_id = 1,
589 .minimum_version_id = 1,
590 .needed = cpu_common_crash_occurred_needed,
591 .fields = (VMStateField[]) {
592 VMSTATE_BOOL(crash_occurred, CPUState),
593 VMSTATE_END_OF_LIST()
594 }
595 };
596
597 const VMStateDescription vmstate_cpu_common = {
598 .name = "cpu_common",
599 .version_id = 1,
600 .minimum_version_id = 1,
601 .pre_load = cpu_common_pre_load,
602 .post_load = cpu_common_post_load,
603 .fields = (VMStateField[]) {
604 VMSTATE_UINT32(halted, CPUState),
605 VMSTATE_UINT32(interrupt_request, CPUState),
606 VMSTATE_END_OF_LIST()
607 },
608 .subsections = (const VMStateDescription*[]) {
609 &vmstate_cpu_common_exception_index,
610 &vmstate_cpu_common_crash_occurred,
611 NULL
612 }
613 };
614
615 #endif
616
617 CPUState *qemu_get_cpu(int index)
618 {
619 CPUState *cpu;
620
621 CPU_FOREACH(cpu) {
622 if (cpu->cpu_index == index) {
623 return cpu;
624 }
625 }
626
627 return NULL;
628 }
629
630 #if !defined(CONFIG_USER_ONLY)
631 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
632 {
633 CPUAddressSpace *newas;
634
635 /* Target code should have set num_ases before calling us */
636 assert(asidx < cpu->num_ases);
637
638 if (asidx == 0) {
639 /* address space 0 gets the convenience alias */
640 cpu->as = as;
641 }
642
643 /* KVM cannot currently support multiple address spaces. */
644 assert(asidx == 0 || !kvm_enabled());
645
646 if (!cpu->cpu_ases) {
647 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
648 }
649
650 newas = &cpu->cpu_ases[asidx];
651 newas->cpu = cpu;
652 newas->as = as;
653 if (tcg_enabled()) {
654 newas->tcg_as_listener.commit = tcg_commit;
655 memory_listener_register(&newas->tcg_as_listener, as);
656 }
657 }
658
659 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
660 {
661 /* Return the AddressSpace corresponding to the specified index */
662 return cpu->cpu_ases[asidx].as;
663 }
664 #endif
665
666 void cpu_exec_unrealizefn(CPUState *cpu)
667 {
668 CPUClass *cc = CPU_GET_CLASS(cpu);
669
670 cpu_list_remove(cpu);
671
672 if (cc->vmsd != NULL) {
673 vmstate_unregister(NULL, cc->vmsd, cpu);
674 }
675 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
676 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
677 }
678 }
679
680 void cpu_exec_initfn(CPUState *cpu)
681 {
682 cpu->as = NULL;
683 cpu->num_ases = 0;
684
685 #ifndef CONFIG_USER_ONLY
686 cpu->thread_id = qemu_get_thread_id();
687
688 /* This is a softmmu CPU object, so create a property for it
689 * so users can wire up its memory. (This can't go in qom/cpu.c
690 * because that file is compiled only once for both user-mode
691 * and system builds.) The default if no link is set up is to use
692 * the system address space.
693 */
694 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
695 (Object **)&cpu->memory,
696 qdev_prop_allow_set_link_before_realize,
697 OBJ_PROP_LINK_UNREF_ON_RELEASE,
698 &error_abort);
699 cpu->memory = system_memory;
700 object_ref(OBJECT(cpu->memory));
701 #endif
702 }
703
704 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
705 {
706 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
707
708 cpu_list_add(cpu);
709
710 #ifndef CONFIG_USER_ONLY
711 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
712 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
713 }
714 if (cc->vmsd != NULL) {
715 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
716 }
717 #endif
718 }
719
720 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
721 {
722 /* Flush the whole TB as this will not have race conditions
723 * even if we don't have proper locking yet.
724 * Ideally we would just invalidate the TBs for the
725 * specified PC.
726 */
727 tb_flush(cpu);
728 }
729
730 #if defined(CONFIG_USER_ONLY)
731 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
732
733 {
734 }
735
736 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
737 int flags)
738 {
739 return -ENOSYS;
740 }
741
742 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
743 {
744 }
745
746 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
747 int flags, CPUWatchpoint **watchpoint)
748 {
749 return -ENOSYS;
750 }
751 #else
752 /* Add a watchpoint. */
753 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
754 int flags, CPUWatchpoint **watchpoint)
755 {
756 CPUWatchpoint *wp;
757
758 /* forbid ranges which are empty or run off the end of the address space */
759 if (len == 0 || (addr + len - 1) < addr) {
760 error_report("tried to set invalid watchpoint at %"
761 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
762 return -EINVAL;
763 }
764 wp = g_malloc(sizeof(*wp));
765
766 wp->vaddr = addr;
767 wp->len = len;
768 wp->flags = flags;
769
770 /* keep all GDB-injected watchpoints in front */
771 if (flags & BP_GDB) {
772 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
773 } else {
774 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
775 }
776
777 tlb_flush_page(cpu, addr);
778
779 if (watchpoint)
780 *watchpoint = wp;
781 return 0;
782 }
783
784 /* Remove a specific watchpoint. */
785 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
786 int flags)
787 {
788 CPUWatchpoint *wp;
789
790 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
791 if (addr == wp->vaddr && len == wp->len
792 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
793 cpu_watchpoint_remove_by_ref(cpu, wp);
794 return 0;
795 }
796 }
797 return -ENOENT;
798 }
799
800 /* Remove a specific watchpoint by reference. */
801 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
802 {
803 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
804
805 tlb_flush_page(cpu, watchpoint->vaddr);
806
807 g_free(watchpoint);
808 }
809
810 /* Remove all matching watchpoints. */
811 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
812 {
813 CPUWatchpoint *wp, *next;
814
815 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
816 if (wp->flags & mask) {
817 cpu_watchpoint_remove_by_ref(cpu, wp);
818 }
819 }
820 }
821
822 /* Return true if this watchpoint address matches the specified
823 * access (ie the address range covered by the watchpoint overlaps
824 * partially or completely with the address range covered by the
825 * access).
826 */
827 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
828 vaddr addr,
829 vaddr len)
830 {
831 /* We know the lengths are non-zero, but a little caution is
832 * required to avoid errors in the case where the range ends
833 * exactly at the top of the address space and so addr + len
834 * wraps round to zero.
835 */
836 vaddr wpend = wp->vaddr + wp->len - 1;
837 vaddr addrend = addr + len - 1;
838
839 return !(addr > wpend || wp->vaddr > addrend);
840 }
841
842 #endif
843
844 /* Add a breakpoint. */
845 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
846 CPUBreakpoint **breakpoint)
847 {
848 CPUBreakpoint *bp;
849
850 bp = g_malloc(sizeof(*bp));
851
852 bp->pc = pc;
853 bp->flags = flags;
854
855 /* keep all GDB-injected breakpoints in front */
856 if (flags & BP_GDB) {
857 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
858 } else {
859 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
860 }
861
862 breakpoint_invalidate(cpu, pc);
863
864 if (breakpoint) {
865 *breakpoint = bp;
866 }
867 return 0;
868 }
869
870 /* Remove a specific breakpoint. */
871 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
872 {
873 CPUBreakpoint *bp;
874
875 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
876 if (bp->pc == pc && bp->flags == flags) {
877 cpu_breakpoint_remove_by_ref(cpu, bp);
878 return 0;
879 }
880 }
881 return -ENOENT;
882 }
883
884 /* Remove a specific breakpoint by reference. */
885 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
886 {
887 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
888
889 breakpoint_invalidate(cpu, breakpoint->pc);
890
891 g_free(breakpoint);
892 }
893
894 /* Remove all matching breakpoints. */
895 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
896 {
897 CPUBreakpoint *bp, *next;
898
899 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
900 if (bp->flags & mask) {
901 cpu_breakpoint_remove_by_ref(cpu, bp);
902 }
903 }
904 }
905
906 /* enable or disable single step mode. EXCP_DEBUG is returned by the
907 CPU loop after each instruction */
908 void cpu_single_step(CPUState *cpu, int enabled)
909 {
910 if (cpu->singlestep_enabled != enabled) {
911 cpu->singlestep_enabled = enabled;
912 if (kvm_enabled()) {
913 kvm_update_guest_debug(cpu, 0);
914 } else {
915 /* must flush all the translated code to avoid inconsistencies */
916 /* XXX: only flush what is necessary */
917 tb_flush(cpu);
918 }
919 }
920 }
921
922 void cpu_abort(CPUState *cpu, const char *fmt, ...)
923 {
924 va_list ap;
925 va_list ap2;
926
927 va_start(ap, fmt);
928 va_copy(ap2, ap);
929 fprintf(stderr, "qemu: fatal: ");
930 vfprintf(stderr, fmt, ap);
931 fprintf(stderr, "\n");
932 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
933 if (qemu_log_separate()) {
934 qemu_log_lock();
935 qemu_log("qemu: fatal: ");
936 qemu_log_vprintf(fmt, ap2);
937 qemu_log("\n");
938 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
939 qemu_log_flush();
940 qemu_log_unlock();
941 qemu_log_close();
942 }
943 va_end(ap2);
944 va_end(ap);
945 replay_finish();
946 #if defined(CONFIG_USER_ONLY)
947 {
948 struct sigaction act;
949 sigfillset(&act.sa_mask);
950 act.sa_handler = SIG_DFL;
951 sigaction(SIGABRT, &act, NULL);
952 }
953 #endif
954 abort();
955 }
956
957 #if !defined(CONFIG_USER_ONLY)
958 /* Called from RCU critical section */
959 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
960 {
961 RAMBlock *block;
962
963 block = atomic_rcu_read(&ram_list.mru_block);
964 if (block && addr - block->offset < block->max_length) {
965 return block;
966 }
967 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
968 if (addr - block->offset < block->max_length) {
969 goto found;
970 }
971 }
972
973 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
974 abort();
975
976 found:
977 /* It is safe to write mru_block outside the iothread lock. This
978 * is what happens:
979 *
980 * mru_block = xxx
981 * rcu_read_unlock()
982 * xxx removed from list
983 * rcu_read_lock()
984 * read mru_block
985 * mru_block = NULL;
986 * call_rcu(reclaim_ramblock, xxx);
987 * rcu_read_unlock()
988 *
989 * atomic_rcu_set is not needed here. The block was already published
990 * when it was placed into the list. Here we're just making an extra
991 * copy of the pointer.
992 */
993 ram_list.mru_block = block;
994 return block;
995 }
996
997 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
998 {
999 CPUState *cpu;
1000 ram_addr_t start1;
1001 RAMBlock *block;
1002 ram_addr_t end;
1003
1004 end = TARGET_PAGE_ALIGN(start + length);
1005 start &= TARGET_PAGE_MASK;
1006
1007 rcu_read_lock();
1008 block = qemu_get_ram_block(start);
1009 assert(block == qemu_get_ram_block(end - 1));
1010 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1011 CPU_FOREACH(cpu) {
1012 tlb_reset_dirty(cpu, start1, length);
1013 }
1014 rcu_read_unlock();
1015 }
1016
1017 /* Note: start and end must be within the same ram block. */
1018 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1019 ram_addr_t length,
1020 unsigned client)
1021 {
1022 DirtyMemoryBlocks *blocks;
1023 unsigned long end, page;
1024 bool dirty = false;
1025
1026 if (length == 0) {
1027 return false;
1028 }
1029
1030 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1031 page = start >> TARGET_PAGE_BITS;
1032
1033 rcu_read_lock();
1034
1035 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1036
1037 while (page < end) {
1038 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1039 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1040 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1041
1042 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1043 offset, num);
1044 page += num;
1045 }
1046
1047 rcu_read_unlock();
1048
1049 if (dirty && tcg_enabled()) {
1050 tlb_reset_dirty_range_all(start, length);
1051 }
1052
1053 return dirty;
1054 }
1055
1056 /* Called from RCU critical section */
1057 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1058 MemoryRegionSection *section,
1059 target_ulong vaddr,
1060 hwaddr paddr, hwaddr xlat,
1061 int prot,
1062 target_ulong *address)
1063 {
1064 hwaddr iotlb;
1065 CPUWatchpoint *wp;
1066
1067 if (memory_region_is_ram(section->mr)) {
1068 /* Normal RAM. */
1069 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1070 if (!section->readonly) {
1071 iotlb |= PHYS_SECTION_NOTDIRTY;
1072 } else {
1073 iotlb |= PHYS_SECTION_ROM;
1074 }
1075 } else {
1076 AddressSpaceDispatch *d;
1077
1078 d = atomic_rcu_read(&section->address_space->dispatch);
1079 iotlb = section - d->map.sections;
1080 iotlb += xlat;
1081 }
1082
1083 /* Make accesses to pages with watchpoints go via the
1084 watchpoint trap routines. */
1085 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1086 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1087 /* Avoid trapping reads of pages with a write breakpoint. */
1088 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1089 iotlb = PHYS_SECTION_WATCH + paddr;
1090 *address |= TLB_MMIO;
1091 break;
1092 }
1093 }
1094 }
1095
1096 return iotlb;
1097 }
1098 #endif /* defined(CONFIG_USER_ONLY) */
1099
1100 #if !defined(CONFIG_USER_ONLY)
1101
1102 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1103 uint16_t section);
1104 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1105
1106 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1107 qemu_anon_ram_alloc;
1108
1109 /*
1110 * Set a custom physical guest memory alloator.
1111 * Accelerators with unusual needs may need this. Hopefully, we can
1112 * get rid of it eventually.
1113 */
1114 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1115 {
1116 phys_mem_alloc = alloc;
1117 }
1118
1119 static uint16_t phys_section_add(PhysPageMap *map,
1120 MemoryRegionSection *section)
1121 {
1122 /* The physical section number is ORed with a page-aligned
1123 * pointer to produce the iotlb entries. Thus it should
1124 * never overflow into the page-aligned value.
1125 */
1126 assert(map->sections_nb < TARGET_PAGE_SIZE);
1127
1128 if (map->sections_nb == map->sections_nb_alloc) {
1129 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1130 map->sections = g_renew(MemoryRegionSection, map->sections,
1131 map->sections_nb_alloc);
1132 }
1133 map->sections[map->sections_nb] = *section;
1134 memory_region_ref(section->mr);
1135 return map->sections_nb++;
1136 }
1137
1138 static void phys_section_destroy(MemoryRegion *mr)
1139 {
1140 bool have_sub_page = mr->subpage;
1141
1142 memory_region_unref(mr);
1143
1144 if (have_sub_page) {
1145 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1146 object_unref(OBJECT(&subpage->iomem));
1147 g_free(subpage);
1148 }
1149 }
1150
1151 static void phys_sections_free(PhysPageMap *map)
1152 {
1153 while (map->sections_nb > 0) {
1154 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1155 phys_section_destroy(section->mr);
1156 }
1157 g_free(map->sections);
1158 g_free(map->nodes);
1159 }
1160
1161 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1162 {
1163 subpage_t *subpage;
1164 hwaddr base = section->offset_within_address_space
1165 & TARGET_PAGE_MASK;
1166 MemoryRegionSection *existing = phys_page_find(d->phys_map, base,
1167 d->map.nodes, d->map.sections);
1168 MemoryRegionSection subsection = {
1169 .offset_within_address_space = base,
1170 .size = int128_make64(TARGET_PAGE_SIZE),
1171 };
1172 hwaddr start, end;
1173
1174 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1175
1176 if (!(existing->mr->subpage)) {
1177 subpage = subpage_init(d->as, base);
1178 subsection.address_space = d->as;
1179 subsection.mr = &subpage->iomem;
1180 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1181 phys_section_add(&d->map, &subsection));
1182 } else {
1183 subpage = container_of(existing->mr, subpage_t, iomem);
1184 }
1185 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1186 end = start + int128_get64(section->size) - 1;
1187 subpage_register(subpage, start, end,
1188 phys_section_add(&d->map, section));
1189 }
1190
1191
1192 static void register_multipage(AddressSpaceDispatch *d,
1193 MemoryRegionSection *section)
1194 {
1195 hwaddr start_addr = section->offset_within_address_space;
1196 uint16_t section_index = phys_section_add(&d->map, section);
1197 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1198 TARGET_PAGE_BITS));
1199
1200 assert(num_pages);
1201 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1202 }
1203
1204 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1205 {
1206 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1207 AddressSpaceDispatch *d = as->next_dispatch;
1208 MemoryRegionSection now = *section, remain = *section;
1209 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1210
1211 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1212 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1213 - now.offset_within_address_space;
1214
1215 now.size = int128_min(int128_make64(left), now.size);
1216 register_subpage(d, &now);
1217 } else {
1218 now.size = int128_zero();
1219 }
1220 while (int128_ne(remain.size, now.size)) {
1221 remain.size = int128_sub(remain.size, now.size);
1222 remain.offset_within_address_space += int128_get64(now.size);
1223 remain.offset_within_region += int128_get64(now.size);
1224 now = remain;
1225 if (int128_lt(remain.size, page_size)) {
1226 register_subpage(d, &now);
1227 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1228 now.size = page_size;
1229 register_subpage(d, &now);
1230 } else {
1231 now.size = int128_and(now.size, int128_neg(page_size));
1232 register_multipage(d, &now);
1233 }
1234 }
1235 }
1236
1237 void qemu_flush_coalesced_mmio_buffer(void)
1238 {
1239 if (kvm_enabled())
1240 kvm_flush_coalesced_mmio_buffer();
1241 }
1242
1243 void qemu_mutex_lock_ramlist(void)
1244 {
1245 qemu_mutex_lock(&ram_list.mutex);
1246 }
1247
1248 void qemu_mutex_unlock_ramlist(void)
1249 {
1250 qemu_mutex_unlock(&ram_list.mutex);
1251 }
1252
1253 #ifdef __linux__
1254 static int64_t get_file_size(int fd)
1255 {
1256 int64_t size = lseek(fd, 0, SEEK_END);
1257 if (size < 0) {
1258 return -errno;
1259 }
1260 return size;
1261 }
1262
1263 static void *file_ram_alloc(RAMBlock *block,
1264 ram_addr_t memory,
1265 const char *path,
1266 Error **errp)
1267 {
1268 bool unlink_on_error = false;
1269 char *filename;
1270 char *sanitized_name;
1271 char *c;
1272 void *area = MAP_FAILED;
1273 int fd = -1;
1274 int64_t file_size;
1275
1276 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1277 error_setg(errp,
1278 "host lacks kvm mmu notifiers, -mem-path unsupported");
1279 return NULL;
1280 }
1281
1282 for (;;) {
1283 fd = open(path, O_RDWR);
1284 if (fd >= 0) {
1285 /* @path names an existing file, use it */
1286 break;
1287 }
1288 if (errno == ENOENT) {
1289 /* @path names a file that doesn't exist, create it */
1290 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1291 if (fd >= 0) {
1292 unlink_on_error = true;
1293 break;
1294 }
1295 } else if (errno == EISDIR) {
1296 /* @path names a directory, create a file there */
1297 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1298 sanitized_name = g_strdup(memory_region_name(block->mr));
1299 for (c = sanitized_name; *c != '\0'; c++) {
1300 if (*c == '/') {
1301 *c = '_';
1302 }
1303 }
1304
1305 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1306 sanitized_name);
1307 g_free(sanitized_name);
1308
1309 fd = mkstemp(filename);
1310 if (fd >= 0) {
1311 unlink(filename);
1312 g_free(filename);
1313 break;
1314 }
1315 g_free(filename);
1316 }
1317 if (errno != EEXIST && errno != EINTR) {
1318 error_setg_errno(errp, errno,
1319 "can't open backing store %s for guest RAM",
1320 path);
1321 goto error;
1322 }
1323 /*
1324 * Try again on EINTR and EEXIST. The latter happens when
1325 * something else creates the file between our two open().
1326 */
1327 }
1328
1329 block->page_size = qemu_fd_getpagesize(fd);
1330 block->mr->align = block->page_size;
1331 #if defined(__s390x__)
1332 if (kvm_enabled()) {
1333 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1334 }
1335 #endif
1336
1337 file_size = get_file_size(fd);
1338
1339 if (memory < block->page_size) {
1340 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1341 "or larger than page size 0x%zx",
1342 memory, block->page_size);
1343 goto error;
1344 }
1345
1346 if (file_size > 0 && file_size < memory) {
1347 error_setg(errp, "backing store %s size 0x%" PRIx64
1348 " does not match 'size' option 0x" RAM_ADDR_FMT,
1349 path, file_size, memory);
1350 goto error;
1351 }
1352
1353 memory = ROUND_UP(memory, block->page_size);
1354
1355 /*
1356 * ftruncate is not supported by hugetlbfs in older
1357 * hosts, so don't bother bailing out on errors.
1358 * If anything goes wrong with it under other filesystems,
1359 * mmap will fail.
1360 *
1361 * Do not truncate the non-empty backend file to avoid corrupting
1362 * the existing data in the file. Disabling shrinking is not
1363 * enough. For example, the current vNVDIMM implementation stores
1364 * the guest NVDIMM labels at the end of the backend file. If the
1365 * backend file is later extended, QEMU will not be able to find
1366 * those labels. Therefore, extending the non-empty backend file
1367 * is disabled as well.
1368 */
1369 if (!file_size && ftruncate(fd, memory)) {
1370 perror("ftruncate");
1371 }
1372
1373 area = qemu_ram_mmap(fd, memory, block->mr->align,
1374 block->flags & RAM_SHARED);
1375 if (area == MAP_FAILED) {
1376 error_setg_errno(errp, errno,
1377 "unable to map backing store for guest RAM");
1378 goto error;
1379 }
1380
1381 if (mem_prealloc) {
1382 os_mem_prealloc(fd, area, memory, errp);
1383 if (errp && *errp) {
1384 goto error;
1385 }
1386 }
1387
1388 block->fd = fd;
1389 return area;
1390
1391 error:
1392 if (area != MAP_FAILED) {
1393 qemu_ram_munmap(area, memory);
1394 }
1395 if (unlink_on_error) {
1396 unlink(path);
1397 }
1398 if (fd != -1) {
1399 close(fd);
1400 }
1401 return NULL;
1402 }
1403 #endif
1404
1405 /* Called with the ramlist lock held. */
1406 static ram_addr_t find_ram_offset(ram_addr_t size)
1407 {
1408 RAMBlock *block, *next_block;
1409 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1410
1411 assert(size != 0); /* it would hand out same offset multiple times */
1412
1413 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1414 return 0;
1415 }
1416
1417 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1418 ram_addr_t end, next = RAM_ADDR_MAX;
1419
1420 end = block->offset + block->max_length;
1421
1422 QLIST_FOREACH_RCU(next_block, &ram_list.blocks, next) {
1423 if (next_block->offset >= end) {
1424 next = MIN(next, next_block->offset);
1425 }
1426 }
1427 if (next - end >= size && next - end < mingap) {
1428 offset = end;
1429 mingap = next - end;
1430 }
1431 }
1432
1433 if (offset == RAM_ADDR_MAX) {
1434 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1435 (uint64_t)size);
1436 abort();
1437 }
1438
1439 return offset;
1440 }
1441
1442 ram_addr_t last_ram_offset(void)
1443 {
1444 RAMBlock *block;
1445 ram_addr_t last = 0;
1446
1447 rcu_read_lock();
1448 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1449 last = MAX(last, block->offset + block->max_length);
1450 }
1451 rcu_read_unlock();
1452 return last;
1453 }
1454
1455 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1456 {
1457 int ret;
1458
1459 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1460 if (!machine_dump_guest_core(current_machine)) {
1461 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1462 if (ret) {
1463 perror("qemu_madvise");
1464 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1465 "but dump_guest_core=off specified\n");
1466 }
1467 }
1468 }
1469
1470 const char *qemu_ram_get_idstr(RAMBlock *rb)
1471 {
1472 return rb->idstr;
1473 }
1474
1475 /* Called with iothread lock held. */
1476 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1477 {
1478 RAMBlock *block;
1479
1480 assert(new_block);
1481 assert(!new_block->idstr[0]);
1482
1483 if (dev) {
1484 char *id = qdev_get_dev_path(dev);
1485 if (id) {
1486 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1487 g_free(id);
1488 }
1489 }
1490 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1491
1492 rcu_read_lock();
1493 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1494 if (block != new_block &&
1495 !strcmp(block->idstr, new_block->idstr)) {
1496 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1497 new_block->idstr);
1498 abort();
1499 }
1500 }
1501 rcu_read_unlock();
1502 }
1503
1504 /* Called with iothread lock held. */
1505 void qemu_ram_unset_idstr(RAMBlock *block)
1506 {
1507 /* FIXME: arch_init.c assumes that this is not called throughout
1508 * migration. Ignore the problem since hot-unplug during migration
1509 * does not work anyway.
1510 */
1511 if (block) {
1512 memset(block->idstr, 0, sizeof(block->idstr));
1513 }
1514 }
1515
1516 size_t qemu_ram_pagesize(RAMBlock *rb)
1517 {
1518 return rb->page_size;
1519 }
1520
1521 static int memory_try_enable_merging(void *addr, size_t len)
1522 {
1523 if (!machine_mem_merge(current_machine)) {
1524 /* disabled by the user */
1525 return 0;
1526 }
1527
1528 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1529 }
1530
1531 /* Only legal before guest might have detected the memory size: e.g. on
1532 * incoming migration, or right after reset.
1533 *
1534 * As memory core doesn't know how is memory accessed, it is up to
1535 * resize callback to update device state and/or add assertions to detect
1536 * misuse, if necessary.
1537 */
1538 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1539 {
1540 assert(block);
1541
1542 newsize = HOST_PAGE_ALIGN(newsize);
1543
1544 if (block->used_length == newsize) {
1545 return 0;
1546 }
1547
1548 if (!(block->flags & RAM_RESIZEABLE)) {
1549 error_setg_errno(errp, EINVAL,
1550 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1551 " in != 0x" RAM_ADDR_FMT, block->idstr,
1552 newsize, block->used_length);
1553 return -EINVAL;
1554 }
1555
1556 if (block->max_length < newsize) {
1557 error_setg_errno(errp, EINVAL,
1558 "Length too large: %s: 0x" RAM_ADDR_FMT
1559 " > 0x" RAM_ADDR_FMT, block->idstr,
1560 newsize, block->max_length);
1561 return -EINVAL;
1562 }
1563
1564 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1565 block->used_length = newsize;
1566 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1567 DIRTY_CLIENTS_ALL);
1568 memory_region_set_size(block->mr, newsize);
1569 if (block->resized) {
1570 block->resized(block->idstr, newsize, block->host);
1571 }
1572 return 0;
1573 }
1574
1575 /* Called with ram_list.mutex held */
1576 static void dirty_memory_extend(ram_addr_t old_ram_size,
1577 ram_addr_t new_ram_size)
1578 {
1579 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1580 DIRTY_MEMORY_BLOCK_SIZE);
1581 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1582 DIRTY_MEMORY_BLOCK_SIZE);
1583 int i;
1584
1585 /* Only need to extend if block count increased */
1586 if (new_num_blocks <= old_num_blocks) {
1587 return;
1588 }
1589
1590 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1591 DirtyMemoryBlocks *old_blocks;
1592 DirtyMemoryBlocks *new_blocks;
1593 int j;
1594
1595 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1596 new_blocks = g_malloc(sizeof(*new_blocks) +
1597 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1598
1599 if (old_num_blocks) {
1600 memcpy(new_blocks->blocks, old_blocks->blocks,
1601 old_num_blocks * sizeof(old_blocks->blocks[0]));
1602 }
1603
1604 for (j = old_num_blocks; j < new_num_blocks; j++) {
1605 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1606 }
1607
1608 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1609
1610 if (old_blocks) {
1611 g_free_rcu(old_blocks, rcu);
1612 }
1613 }
1614 }
1615
1616 static void ram_block_add(RAMBlock *new_block, Error **errp)
1617 {
1618 RAMBlock *block;
1619 RAMBlock *last_block = NULL;
1620 ram_addr_t old_ram_size, new_ram_size;
1621 Error *err = NULL;
1622
1623 old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
1624
1625 qemu_mutex_lock_ramlist();
1626 new_block->offset = find_ram_offset(new_block->max_length);
1627
1628 if (!new_block->host) {
1629 if (xen_enabled()) {
1630 xen_ram_alloc(new_block->offset, new_block->max_length,
1631 new_block->mr, &err);
1632 if (err) {
1633 error_propagate(errp, err);
1634 qemu_mutex_unlock_ramlist();
1635 return;
1636 }
1637 } else {
1638 new_block->host = phys_mem_alloc(new_block->max_length,
1639 &new_block->mr->align);
1640 if (!new_block->host) {
1641 error_setg_errno(errp, errno,
1642 "cannot set up guest memory '%s'",
1643 memory_region_name(new_block->mr));
1644 qemu_mutex_unlock_ramlist();
1645 return;
1646 }
1647 memory_try_enable_merging(new_block->host, new_block->max_length);
1648 }
1649 }
1650
1651 new_ram_size = MAX(old_ram_size,
1652 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1653 if (new_ram_size > old_ram_size) {
1654 migration_bitmap_extend(old_ram_size, new_ram_size);
1655 dirty_memory_extend(old_ram_size, new_ram_size);
1656 }
1657 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1658 * QLIST (which has an RCU-friendly variant) does not have insertion at
1659 * tail, so save the last element in last_block.
1660 */
1661 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1662 last_block = block;
1663 if (block->max_length < new_block->max_length) {
1664 break;
1665 }
1666 }
1667 if (block) {
1668 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1669 } else if (last_block) {
1670 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1671 } else { /* list is empty */
1672 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1673 }
1674 ram_list.mru_block = NULL;
1675
1676 /* Write list before version */
1677 smp_wmb();
1678 ram_list.version++;
1679 qemu_mutex_unlock_ramlist();
1680
1681 cpu_physical_memory_set_dirty_range(new_block->offset,
1682 new_block->used_length,
1683 DIRTY_CLIENTS_ALL);
1684
1685 if (new_block->host) {
1686 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1687 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1688 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1689 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1690 }
1691 }
1692
1693 #ifdef __linux__
1694 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1695 bool share, const char *mem_path,
1696 Error **errp)
1697 {
1698 RAMBlock *new_block;
1699 Error *local_err = NULL;
1700
1701 if (xen_enabled()) {
1702 error_setg(errp, "-mem-path not supported with Xen");
1703 return NULL;
1704 }
1705
1706 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1707 /*
1708 * file_ram_alloc() needs to allocate just like
1709 * phys_mem_alloc, but we haven't bothered to provide
1710 * a hook there.
1711 */
1712 error_setg(errp,
1713 "-mem-path not supported with this accelerator");
1714 return NULL;
1715 }
1716
1717 size = HOST_PAGE_ALIGN(size);
1718 new_block = g_malloc0(sizeof(*new_block));
1719 new_block->mr = mr;
1720 new_block->used_length = size;
1721 new_block->max_length = size;
1722 new_block->flags = share ? RAM_SHARED : 0;
1723 new_block->host = file_ram_alloc(new_block, size,
1724 mem_path, errp);
1725 if (!new_block->host) {
1726 g_free(new_block);
1727 return NULL;
1728 }
1729
1730 ram_block_add(new_block, &local_err);
1731 if (local_err) {
1732 g_free(new_block);
1733 error_propagate(errp, local_err);
1734 return NULL;
1735 }
1736 return new_block;
1737 }
1738 #endif
1739
1740 static
1741 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
1742 void (*resized)(const char*,
1743 uint64_t length,
1744 void *host),
1745 void *host, bool resizeable,
1746 MemoryRegion *mr, Error **errp)
1747 {
1748 RAMBlock *new_block;
1749 Error *local_err = NULL;
1750
1751 size = HOST_PAGE_ALIGN(size);
1752 max_size = HOST_PAGE_ALIGN(max_size);
1753 new_block = g_malloc0(sizeof(*new_block));
1754 new_block->mr = mr;
1755 new_block->resized = resized;
1756 new_block->used_length = size;
1757 new_block->max_length = max_size;
1758 assert(max_size >= size);
1759 new_block->fd = -1;
1760 new_block->page_size = getpagesize();
1761 new_block->host = host;
1762 if (host) {
1763 new_block->flags |= RAM_PREALLOC;
1764 }
1765 if (resizeable) {
1766 new_block->flags |= RAM_RESIZEABLE;
1767 }
1768 ram_block_add(new_block, &local_err);
1769 if (local_err) {
1770 g_free(new_block);
1771 error_propagate(errp, local_err);
1772 return NULL;
1773 }
1774 return new_block;
1775 }
1776
1777 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
1778 MemoryRegion *mr, Error **errp)
1779 {
1780 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
1781 }
1782
1783 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
1784 {
1785 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
1786 }
1787
1788 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
1789 void (*resized)(const char*,
1790 uint64_t length,
1791 void *host),
1792 MemoryRegion *mr, Error **errp)
1793 {
1794 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
1795 }
1796
1797 static void reclaim_ramblock(RAMBlock *block)
1798 {
1799 if (block->flags & RAM_PREALLOC) {
1800 ;
1801 } else if (xen_enabled()) {
1802 xen_invalidate_map_cache_entry(block->host);
1803 #ifndef _WIN32
1804 } else if (block->fd >= 0) {
1805 qemu_ram_munmap(block->host, block->max_length);
1806 close(block->fd);
1807 #endif
1808 } else {
1809 qemu_anon_ram_free(block->host, block->max_length);
1810 }
1811 g_free(block);
1812 }
1813
1814 void qemu_ram_free(RAMBlock *block)
1815 {
1816 if (!block) {
1817 return;
1818 }
1819
1820 qemu_mutex_lock_ramlist();
1821 QLIST_REMOVE_RCU(block, next);
1822 ram_list.mru_block = NULL;
1823 /* Write list before version */
1824 smp_wmb();
1825 ram_list.version++;
1826 call_rcu(block, reclaim_ramblock, rcu);
1827 qemu_mutex_unlock_ramlist();
1828 }
1829
1830 #ifndef _WIN32
1831 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
1832 {
1833 RAMBlock *block;
1834 ram_addr_t offset;
1835 int flags;
1836 void *area, *vaddr;
1837
1838 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1839 offset = addr - block->offset;
1840 if (offset < block->max_length) {
1841 vaddr = ramblock_ptr(block, offset);
1842 if (block->flags & RAM_PREALLOC) {
1843 ;
1844 } else if (xen_enabled()) {
1845 abort();
1846 } else {
1847 flags = MAP_FIXED;
1848 if (block->fd >= 0) {
1849 flags |= (block->flags & RAM_SHARED ?
1850 MAP_SHARED : MAP_PRIVATE);
1851 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1852 flags, block->fd, offset);
1853 } else {
1854 /*
1855 * Remap needs to match alloc. Accelerators that
1856 * set phys_mem_alloc never remap. If they did,
1857 * we'd need a remap hook here.
1858 */
1859 assert(phys_mem_alloc == qemu_anon_ram_alloc);
1860
1861 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1862 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1863 flags, -1, 0);
1864 }
1865 if (area != vaddr) {
1866 fprintf(stderr, "Could not remap addr: "
1867 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
1868 length, addr);
1869 exit(1);
1870 }
1871 memory_try_enable_merging(vaddr, length);
1872 qemu_ram_setup_dump(vaddr, length);
1873 }
1874 }
1875 }
1876 }
1877 #endif /* !_WIN32 */
1878
1879 /* Return a host pointer to ram allocated with qemu_ram_alloc.
1880 * This should not be used for general purpose DMA. Use address_space_map
1881 * or address_space_rw instead. For local memory (e.g. video ram) that the
1882 * device owns, use memory_region_get_ram_ptr.
1883 *
1884 * Called within RCU critical section.
1885 */
1886 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
1887 {
1888 RAMBlock *block = ram_block;
1889
1890 if (block == NULL) {
1891 block = qemu_get_ram_block(addr);
1892 addr -= block->offset;
1893 }
1894
1895 if (xen_enabled() && block->host == NULL) {
1896 /* We need to check if the requested address is in the RAM
1897 * because we don't want to map the entire memory in QEMU.
1898 * In that case just map until the end of the page.
1899 */
1900 if (block->offset == 0) {
1901 return xen_map_cache(addr, 0, 0);
1902 }
1903
1904 block->host = xen_map_cache(block->offset, block->max_length, 1);
1905 }
1906 return ramblock_ptr(block, addr);
1907 }
1908
1909 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
1910 * but takes a size argument.
1911 *
1912 * Called within RCU critical section.
1913 */
1914 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
1915 hwaddr *size)
1916 {
1917 RAMBlock *block = ram_block;
1918 if (*size == 0) {
1919 return NULL;
1920 }
1921
1922 if (block == NULL) {
1923 block = qemu_get_ram_block(addr);
1924 addr -= block->offset;
1925 }
1926 *size = MIN(*size, block->max_length - addr);
1927
1928 if (xen_enabled() && block->host == NULL) {
1929 /* We need to check if the requested address is in the RAM
1930 * because we don't want to map the entire memory in QEMU.
1931 * In that case just map the requested area.
1932 */
1933 if (block->offset == 0) {
1934 return xen_map_cache(addr, *size, 1);
1935 }
1936
1937 block->host = xen_map_cache(block->offset, block->max_length, 1);
1938 }
1939
1940 return ramblock_ptr(block, addr);
1941 }
1942
1943 /*
1944 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
1945 * in that RAMBlock.
1946 *
1947 * ptr: Host pointer to look up
1948 * round_offset: If true round the result offset down to a page boundary
1949 * *ram_addr: set to result ram_addr
1950 * *offset: set to result offset within the RAMBlock
1951 *
1952 * Returns: RAMBlock (or NULL if not found)
1953 *
1954 * By the time this function returns, the returned pointer is not protected
1955 * by RCU anymore. If the caller is not within an RCU critical section and
1956 * does not hold the iothread lock, it must have other means of protecting the
1957 * pointer, such as a reference to the region that includes the incoming
1958 * ram_addr_t.
1959 */
1960 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
1961 ram_addr_t *offset)
1962 {
1963 RAMBlock *block;
1964 uint8_t *host = ptr;
1965
1966 if (xen_enabled()) {
1967 ram_addr_t ram_addr;
1968 rcu_read_lock();
1969 ram_addr = xen_ram_addr_from_mapcache(ptr);
1970 block = qemu_get_ram_block(ram_addr);
1971 if (block) {
1972 *offset = ram_addr - block->offset;
1973 }
1974 rcu_read_unlock();
1975 return block;
1976 }
1977
1978 rcu_read_lock();
1979 block = atomic_rcu_read(&ram_list.mru_block);
1980 if (block && block->host && host - block->host < block->max_length) {
1981 goto found;
1982 }
1983
1984 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1985 /* This case append when the block is not mapped. */
1986 if (block->host == NULL) {
1987 continue;
1988 }
1989 if (host - block->host < block->max_length) {
1990 goto found;
1991 }
1992 }
1993
1994 rcu_read_unlock();
1995 return NULL;
1996
1997 found:
1998 *offset = (host - block->host);
1999 if (round_offset) {
2000 *offset &= TARGET_PAGE_MASK;
2001 }
2002 rcu_read_unlock();
2003 return block;
2004 }
2005
2006 /*
2007 * Finds the named RAMBlock
2008 *
2009 * name: The name of RAMBlock to find
2010 *
2011 * Returns: RAMBlock (or NULL if not found)
2012 */
2013 RAMBlock *qemu_ram_block_by_name(const char *name)
2014 {
2015 RAMBlock *block;
2016
2017 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
2018 if (!strcmp(name, block->idstr)) {
2019 return block;
2020 }
2021 }
2022
2023 return NULL;
2024 }
2025
2026 /* Some of the softmmu routines need to translate from a host pointer
2027 (typically a TLB entry) back to a ram offset. */
2028 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2029 {
2030 RAMBlock *block;
2031 ram_addr_t offset;
2032
2033 block = qemu_ram_block_from_host(ptr, false, &offset);
2034 if (!block) {
2035 return RAM_ADDR_INVALID;
2036 }
2037
2038 return block->offset + offset;
2039 }
2040
2041 /* Called within RCU critical section. */
2042 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2043 uint64_t val, unsigned size)
2044 {
2045 bool locked = false;
2046
2047 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2048 locked = true;
2049 tb_lock();
2050 tb_invalidate_phys_page_fast(ram_addr, size);
2051 }
2052 switch (size) {
2053 case 1:
2054 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2055 break;
2056 case 2:
2057 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2058 break;
2059 case 4:
2060 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2061 break;
2062 default:
2063 abort();
2064 }
2065
2066 if (locked) {
2067 tb_unlock();
2068 }
2069
2070 /* Set both VGA and migration bits for simplicity and to remove
2071 * the notdirty callback faster.
2072 */
2073 cpu_physical_memory_set_dirty_range(ram_addr, size,
2074 DIRTY_CLIENTS_NOCODE);
2075 /* we remove the notdirty callback only if the code has been
2076 flushed */
2077 if (!cpu_physical_memory_is_clean(ram_addr)) {
2078 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2079 }
2080 }
2081
2082 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2083 unsigned size, bool is_write)
2084 {
2085 return is_write;
2086 }
2087
2088 static const MemoryRegionOps notdirty_mem_ops = {
2089 .write = notdirty_mem_write,
2090 .valid.accepts = notdirty_mem_accepts,
2091 .endianness = DEVICE_NATIVE_ENDIAN,
2092 };
2093
2094 /* Generate a debug exception if a watchpoint has been hit. */
2095 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2096 {
2097 CPUState *cpu = current_cpu;
2098 CPUClass *cc = CPU_GET_CLASS(cpu);
2099 CPUArchState *env = cpu->env_ptr;
2100 target_ulong pc, cs_base;
2101 target_ulong vaddr;
2102 CPUWatchpoint *wp;
2103 uint32_t cpu_flags;
2104
2105 if (cpu->watchpoint_hit) {
2106 /* We re-entered the check after replacing the TB. Now raise
2107 * the debug interrupt so that is will trigger after the
2108 * current instruction. */
2109 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2110 return;
2111 }
2112 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2113 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2114 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2115 && (wp->flags & flags)) {
2116 if (flags == BP_MEM_READ) {
2117 wp->flags |= BP_WATCHPOINT_HIT_READ;
2118 } else {
2119 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2120 }
2121 wp->hitaddr = vaddr;
2122 wp->hitattrs = attrs;
2123 if (!cpu->watchpoint_hit) {
2124 if (wp->flags & BP_CPU &&
2125 !cc->debug_check_watchpoint(cpu, wp)) {
2126 wp->flags &= ~BP_WATCHPOINT_HIT;
2127 continue;
2128 }
2129 cpu->watchpoint_hit = wp;
2130
2131 /* The tb_lock will be reset when cpu_loop_exit or
2132 * cpu_loop_exit_noexc longjmp back into the cpu_exec
2133 * main loop.
2134 */
2135 tb_lock();
2136 tb_check_watchpoint(cpu);
2137 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2138 cpu->exception_index = EXCP_DEBUG;
2139 cpu_loop_exit(cpu);
2140 } else {
2141 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2142 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2143 cpu_loop_exit_noexc(cpu);
2144 }
2145 }
2146 } else {
2147 wp->flags &= ~BP_WATCHPOINT_HIT;
2148 }
2149 }
2150 }
2151
2152 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2153 so these check for a hit then pass through to the normal out-of-line
2154 phys routines. */
2155 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2156 unsigned size, MemTxAttrs attrs)
2157 {
2158 MemTxResult res;
2159 uint64_t data;
2160 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2161 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2162
2163 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2164 switch (size) {
2165 case 1:
2166 data = address_space_ldub(as, addr, attrs, &res);
2167 break;
2168 case 2:
2169 data = address_space_lduw(as, addr, attrs, &res);
2170 break;
2171 case 4:
2172 data = address_space_ldl(as, addr, attrs, &res);
2173 break;
2174 default: abort();
2175 }
2176 *pdata = data;
2177 return res;
2178 }
2179
2180 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2181 uint64_t val, unsigned size,
2182 MemTxAttrs attrs)
2183 {
2184 MemTxResult res;
2185 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2186 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2187
2188 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2189 switch (size) {
2190 case 1:
2191 address_space_stb(as, addr, val, attrs, &res);
2192 break;
2193 case 2:
2194 address_space_stw(as, addr, val, attrs, &res);
2195 break;
2196 case 4:
2197 address_space_stl(as, addr, val, attrs, &res);
2198 break;
2199 default: abort();
2200 }
2201 return res;
2202 }
2203
2204 static const MemoryRegionOps watch_mem_ops = {
2205 .read_with_attrs = watch_mem_read,
2206 .write_with_attrs = watch_mem_write,
2207 .endianness = DEVICE_NATIVE_ENDIAN,
2208 };
2209
2210 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2211 unsigned len, MemTxAttrs attrs)
2212 {
2213 subpage_t *subpage = opaque;
2214 uint8_t buf[8];
2215 MemTxResult res;
2216
2217 #if defined(DEBUG_SUBPAGE)
2218 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2219 subpage, len, addr);
2220 #endif
2221 res = address_space_read(subpage->as, addr + subpage->base,
2222 attrs, buf, len);
2223 if (res) {
2224 return res;
2225 }
2226 switch (len) {
2227 case 1:
2228 *data = ldub_p(buf);
2229 return MEMTX_OK;
2230 case 2:
2231 *data = lduw_p(buf);
2232 return MEMTX_OK;
2233 case 4:
2234 *data = ldl_p(buf);
2235 return MEMTX_OK;
2236 case 8:
2237 *data = ldq_p(buf);
2238 return MEMTX_OK;
2239 default:
2240 abort();
2241 }
2242 }
2243
2244 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2245 uint64_t value, unsigned len, MemTxAttrs attrs)
2246 {
2247 subpage_t *subpage = opaque;
2248 uint8_t buf[8];
2249
2250 #if defined(DEBUG_SUBPAGE)
2251 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2252 " value %"PRIx64"\n",
2253 __func__, subpage, len, addr, value);
2254 #endif
2255 switch (len) {
2256 case 1:
2257 stb_p(buf, value);
2258 break;
2259 case 2:
2260 stw_p(buf, value);
2261 break;
2262 case 4:
2263 stl_p(buf, value);
2264 break;
2265 case 8:
2266 stq_p(buf, value);
2267 break;
2268 default:
2269 abort();
2270 }
2271 return address_space_write(subpage->as, addr + subpage->base,
2272 attrs, buf, len);
2273 }
2274
2275 static bool subpage_accepts(void *opaque, hwaddr addr,
2276 unsigned len, bool is_write)
2277 {
2278 subpage_t *subpage = opaque;
2279 #if defined(DEBUG_SUBPAGE)
2280 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2281 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2282 #endif
2283
2284 return address_space_access_valid(subpage->as, addr + subpage->base,
2285 len, is_write);
2286 }
2287
2288 static const MemoryRegionOps subpage_ops = {
2289 .read_with_attrs = subpage_read,
2290 .write_with_attrs = subpage_write,
2291 .impl.min_access_size = 1,
2292 .impl.max_access_size = 8,
2293 .valid.min_access_size = 1,
2294 .valid.max_access_size = 8,
2295 .valid.accepts = subpage_accepts,
2296 .endianness = DEVICE_NATIVE_ENDIAN,
2297 };
2298
2299 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2300 uint16_t section)
2301 {
2302 int idx, eidx;
2303
2304 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2305 return -1;
2306 idx = SUBPAGE_IDX(start);
2307 eidx = SUBPAGE_IDX(end);
2308 #if defined(DEBUG_SUBPAGE)
2309 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2310 __func__, mmio, start, end, idx, eidx, section);
2311 #endif
2312 for (; idx <= eidx; idx++) {
2313 mmio->sub_section[idx] = section;
2314 }
2315
2316 return 0;
2317 }
2318
2319 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2320 {
2321 subpage_t *mmio;
2322
2323 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2324 mmio->as = as;
2325 mmio->base = base;
2326 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2327 NULL, TARGET_PAGE_SIZE);
2328 mmio->iomem.subpage = true;
2329 #if defined(DEBUG_SUBPAGE)
2330 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2331 mmio, base, TARGET_PAGE_SIZE);
2332 #endif
2333 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2334
2335 return mmio;
2336 }
2337
2338 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2339 MemoryRegion *mr)
2340 {
2341 assert(as);
2342 MemoryRegionSection section = {
2343 .address_space = as,
2344 .mr = mr,
2345 .offset_within_address_space = 0,
2346 .offset_within_region = 0,
2347 .size = int128_2_64(),
2348 };
2349
2350 return phys_section_add(map, &section);
2351 }
2352
2353 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2354 {
2355 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2356 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2357 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2358 MemoryRegionSection *sections = d->map.sections;
2359
2360 return sections[index & ~TARGET_PAGE_MASK].mr;
2361 }
2362
2363 static void io_mem_init(void)
2364 {
2365 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2366 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2367 NULL, UINT64_MAX);
2368 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2369 NULL, UINT64_MAX);
2370 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2371 NULL, UINT64_MAX);
2372 }
2373
2374 static void mem_begin(MemoryListener *listener)
2375 {
2376 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2377 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2378 uint16_t n;
2379
2380 n = dummy_section(&d->map, as, &io_mem_unassigned);
2381 assert(n == PHYS_SECTION_UNASSIGNED);
2382 n = dummy_section(&d->map, as, &io_mem_notdirty);
2383 assert(n == PHYS_SECTION_NOTDIRTY);
2384 n = dummy_section(&d->map, as, &io_mem_rom);
2385 assert(n == PHYS_SECTION_ROM);
2386 n = dummy_section(&d->map, as, &io_mem_watch);
2387 assert(n == PHYS_SECTION_WATCH);
2388
2389 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2390 d->as = as;
2391 as->next_dispatch = d;
2392 }
2393
2394 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2395 {
2396 phys_sections_free(&d->map);
2397 g_free(d);
2398 }
2399
2400 static void mem_commit(MemoryListener *listener)
2401 {
2402 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2403 AddressSpaceDispatch *cur = as->dispatch;
2404 AddressSpaceDispatch *next = as->next_dispatch;
2405
2406 phys_page_compact_all(next, next->map.nodes_nb);
2407
2408 atomic_rcu_set(&as->dispatch, next);
2409 if (cur) {
2410 call_rcu(cur, address_space_dispatch_free, rcu);
2411 }
2412 }
2413
2414 static void tcg_commit(MemoryListener *listener)
2415 {
2416 CPUAddressSpace *cpuas;
2417 AddressSpaceDispatch *d;
2418
2419 /* since each CPU stores ram addresses in its TLB cache, we must
2420 reset the modified entries */
2421 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2422 cpu_reloading_memory_map();
2423 /* The CPU and TLB are protected by the iothread lock.
2424 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2425 * may have split the RCU critical section.
2426 */
2427 d = atomic_rcu_read(&cpuas->as->dispatch);
2428 atomic_rcu_set(&cpuas->memory_dispatch, d);
2429 tlb_flush(cpuas->cpu, 1);
2430 }
2431
2432 void address_space_init_dispatch(AddressSpace *as)
2433 {
2434 as->dispatch = NULL;
2435 as->dispatch_listener = (MemoryListener) {
2436 .begin = mem_begin,
2437 .commit = mem_commit,
2438 .region_add = mem_add,
2439 .region_nop = mem_add,
2440 .priority = 0,
2441 };
2442 memory_listener_register(&as->dispatch_listener, as);
2443 }
2444
2445 void address_space_unregister(AddressSpace *as)
2446 {
2447 memory_listener_unregister(&as->dispatch_listener);
2448 }
2449
2450 void address_space_destroy_dispatch(AddressSpace *as)
2451 {
2452 AddressSpaceDispatch *d = as->dispatch;
2453
2454 atomic_rcu_set(&as->dispatch, NULL);
2455 if (d) {
2456 call_rcu(d, address_space_dispatch_free, rcu);
2457 }
2458 }
2459
2460 static void memory_map_init(void)
2461 {
2462 system_memory = g_malloc(sizeof(*system_memory));
2463
2464 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2465 address_space_init(&address_space_memory, system_memory, "memory");
2466
2467 system_io = g_malloc(sizeof(*system_io));
2468 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2469 65536);
2470 address_space_init(&address_space_io, system_io, "I/O");
2471 }
2472
2473 MemoryRegion *get_system_memory(void)
2474 {
2475 return system_memory;
2476 }
2477
2478 MemoryRegion *get_system_io(void)
2479 {
2480 return system_io;
2481 }
2482
2483 #endif /* !defined(CONFIG_USER_ONLY) */
2484
2485 /* physical memory access (slow version, mainly for debug) */
2486 #if defined(CONFIG_USER_ONLY)
2487 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2488 uint8_t *buf, int len, int is_write)
2489 {
2490 int l, flags;
2491 target_ulong page;
2492 void * p;
2493
2494 while (len > 0) {
2495 page = addr & TARGET_PAGE_MASK;
2496 l = (page + TARGET_PAGE_SIZE) - addr;
2497 if (l > len)
2498 l = len;
2499 flags = page_get_flags(page);
2500 if (!(flags & PAGE_VALID))
2501 return -1;
2502 if (is_write) {
2503 if (!(flags & PAGE_WRITE))
2504 return -1;
2505 /* XXX: this code should not depend on lock_user */
2506 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2507 return -1;
2508 memcpy(p, buf, l);
2509 unlock_user(p, addr, l);
2510 } else {
2511 if (!(flags & PAGE_READ))
2512 return -1;
2513 /* XXX: this code should not depend on lock_user */
2514 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2515 return -1;
2516 memcpy(buf, p, l);
2517 unlock_user(p, addr, 0);
2518 }
2519 len -= l;
2520 buf += l;
2521 addr += l;
2522 }
2523 return 0;
2524 }
2525
2526 #else
2527
2528 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2529 hwaddr length)
2530 {
2531 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2532 addr += memory_region_get_ram_addr(mr);
2533
2534 /* No early return if dirty_log_mask is or becomes 0, because
2535 * cpu_physical_memory_set_dirty_range will still call
2536 * xen_modified_memory.
2537 */
2538 if (dirty_log_mask) {
2539 dirty_log_mask =
2540 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2541 }
2542 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2543 tb_lock();
2544 tb_invalidate_phys_range(addr, addr + length);
2545 tb_unlock();
2546 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2547 }
2548 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2549 }
2550
2551 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2552 {
2553 unsigned access_size_max = mr->ops->valid.max_access_size;
2554
2555 /* Regions are assumed to support 1-4 byte accesses unless
2556 otherwise specified. */
2557 if (access_size_max == 0) {
2558 access_size_max = 4;
2559 }
2560
2561 /* Bound the maximum access by the alignment of the address. */
2562 if (!mr->ops->impl.unaligned) {
2563 unsigned align_size_max = addr & -addr;
2564 if (align_size_max != 0 && align_size_max < access_size_max) {
2565 access_size_max = align_size_max;
2566 }
2567 }
2568
2569 /* Don't attempt accesses larger than the maximum. */
2570 if (l > access_size_max) {
2571 l = access_size_max;
2572 }
2573 l = pow2floor(l);
2574
2575 return l;
2576 }
2577
2578 static bool prepare_mmio_access(MemoryRegion *mr)
2579 {
2580 bool unlocked = !qemu_mutex_iothread_locked();
2581 bool release_lock = false;
2582
2583 if (unlocked && mr->global_locking) {
2584 qemu_mutex_lock_iothread();
2585 unlocked = false;
2586 release_lock = true;
2587 }
2588 if (mr->flush_coalesced_mmio) {
2589 if (unlocked) {
2590 qemu_mutex_lock_iothread();
2591 }
2592 qemu_flush_coalesced_mmio_buffer();
2593 if (unlocked) {
2594 qemu_mutex_unlock_iothread();
2595 }
2596 }
2597
2598 return release_lock;
2599 }
2600
2601 /* Called within RCU critical section. */
2602 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2603 MemTxAttrs attrs,
2604 const uint8_t *buf,
2605 int len, hwaddr addr1,
2606 hwaddr l, MemoryRegion *mr)
2607 {
2608 uint8_t *ptr;
2609 uint64_t val;
2610 MemTxResult result = MEMTX_OK;
2611 bool release_lock = false;
2612
2613 for (;;) {
2614 if (!memory_access_is_direct(mr, true)) {
2615 release_lock |= prepare_mmio_access(mr);
2616 l = memory_access_size(mr, l, addr1);
2617 /* XXX: could force current_cpu to NULL to avoid
2618 potential bugs */
2619 switch (l) {
2620 case 8:
2621 /* 64 bit write access */
2622 val = ldq_p(buf);
2623 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2624 attrs);
2625 break;
2626 case 4:
2627 /* 32 bit write access */
2628 val = ldl_p(buf);
2629 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2630 attrs);
2631 break;
2632 case 2:
2633 /* 16 bit write access */
2634 val = lduw_p(buf);
2635 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2636 attrs);
2637 break;
2638 case 1:
2639 /* 8 bit write access */
2640 val = ldub_p(buf);
2641 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2642 attrs);
2643 break;
2644 default:
2645 abort();
2646 }
2647 } else {
2648 /* RAM case */
2649 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2650 memcpy(ptr, buf, l);
2651 invalidate_and_set_dirty(mr, addr1, l);
2652 }
2653
2654 if (release_lock) {
2655 qemu_mutex_unlock_iothread();
2656 release_lock = false;
2657 }
2658
2659 len -= l;
2660 buf += l;
2661 addr += l;
2662
2663 if (!len) {
2664 break;
2665 }
2666
2667 l = len;
2668 mr = address_space_translate(as, addr, &addr1, &l, true);
2669 }
2670
2671 return result;
2672 }
2673
2674 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2675 const uint8_t *buf, int len)
2676 {
2677 hwaddr l;
2678 hwaddr addr1;
2679 MemoryRegion *mr;
2680 MemTxResult result = MEMTX_OK;
2681
2682 if (len > 0) {
2683 rcu_read_lock();
2684 l = len;
2685 mr = address_space_translate(as, addr, &addr1, &l, true);
2686 result = address_space_write_continue(as, addr, attrs, buf, len,
2687 addr1, l, mr);
2688 rcu_read_unlock();
2689 }
2690
2691 return result;
2692 }
2693
2694 /* Called within RCU critical section. */
2695 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2696 MemTxAttrs attrs, uint8_t *buf,
2697 int len, hwaddr addr1, hwaddr l,
2698 MemoryRegion *mr)
2699 {
2700 uint8_t *ptr;
2701 uint64_t val;
2702 MemTxResult result = MEMTX_OK;
2703 bool release_lock = false;
2704
2705 for (;;) {
2706 if (!memory_access_is_direct(mr, false)) {
2707 /* I/O case */
2708 release_lock |= prepare_mmio_access(mr);
2709 l = memory_access_size(mr, l, addr1);
2710 switch (l) {
2711 case 8:
2712 /* 64 bit read access */
2713 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2714 attrs);
2715 stq_p(buf, val);
2716 break;
2717 case 4:
2718 /* 32 bit read access */
2719 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
2720 attrs);
2721 stl_p(buf, val);
2722 break;
2723 case 2:
2724 /* 16 bit read access */
2725 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
2726 attrs);
2727 stw_p(buf, val);
2728 break;
2729 case 1:
2730 /* 8 bit read access */
2731 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
2732 attrs);
2733 stb_p(buf, val);
2734 break;
2735 default:
2736 abort();
2737 }
2738 } else {
2739 /* RAM case */
2740 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2741 memcpy(buf, ptr, l);
2742 }
2743
2744 if (release_lock) {
2745 qemu_mutex_unlock_iothread();
2746 release_lock = false;
2747 }
2748
2749 len -= l;
2750 buf += l;
2751 addr += l;
2752
2753 if (!len) {
2754 break;
2755 }
2756
2757 l = len;
2758 mr = address_space_translate(as, addr, &addr1, &l, false);
2759 }
2760
2761 return result;
2762 }
2763
2764 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
2765 MemTxAttrs attrs, uint8_t *buf, int len)
2766 {
2767 hwaddr l;
2768 hwaddr addr1;
2769 MemoryRegion *mr;
2770 MemTxResult result = MEMTX_OK;
2771
2772 if (len > 0) {
2773 rcu_read_lock();
2774 l = len;
2775 mr = address_space_translate(as, addr, &addr1, &l, false);
2776 result = address_space_read_continue(as, addr, attrs, buf, len,
2777 addr1, l, mr);
2778 rcu_read_unlock();
2779 }
2780
2781 return result;
2782 }
2783
2784 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2785 uint8_t *buf, int len, bool is_write)
2786 {
2787 if (is_write) {
2788 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
2789 } else {
2790 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
2791 }
2792 }
2793
2794 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
2795 int len, int is_write)
2796 {
2797 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
2798 buf, len, is_write);
2799 }
2800
2801 enum write_rom_type {
2802 WRITE_DATA,
2803 FLUSH_CACHE,
2804 };
2805
2806 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
2807 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
2808 {
2809 hwaddr l;
2810 uint8_t *ptr;
2811 hwaddr addr1;
2812 MemoryRegion *mr;
2813
2814 rcu_read_lock();
2815 while (len > 0) {
2816 l = len;
2817 mr = address_space_translate(as, addr, &addr1, &l, true);
2818
2819 if (!(memory_region_is_ram(mr) ||
2820 memory_region_is_romd(mr))) {
2821 l = memory_access_size(mr, l, addr1);
2822 } else {
2823 /* ROM/RAM case */
2824 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2825 switch (type) {
2826 case WRITE_DATA:
2827 memcpy(ptr, buf, l);
2828 invalidate_and_set_dirty(mr, addr1, l);
2829 break;
2830 case FLUSH_CACHE:
2831 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
2832 break;
2833 }
2834 }
2835 len -= l;
2836 buf += l;
2837 addr += l;
2838 }
2839 rcu_read_unlock();
2840 }
2841
2842 /* used for ROM loading : can write in RAM and ROM */
2843 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
2844 const uint8_t *buf, int len)
2845 {
2846 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
2847 }
2848
2849 void cpu_flush_icache_range(hwaddr start, int len)
2850 {
2851 /*
2852 * This function should do the same thing as an icache flush that was
2853 * triggered from within the guest. For TCG we are always cache coherent,
2854 * so there is no need to flush anything. For KVM / Xen we need to flush
2855 * the host's instruction cache at least.
2856 */
2857 if (tcg_enabled()) {
2858 return;
2859 }
2860
2861 cpu_physical_memory_write_rom_internal(&address_space_memory,
2862 start, NULL, len, FLUSH_CACHE);
2863 }
2864
2865 typedef struct {
2866 MemoryRegion *mr;
2867 void *buffer;
2868 hwaddr addr;
2869 hwaddr len;
2870 bool in_use;
2871 } BounceBuffer;
2872
2873 static BounceBuffer bounce;
2874
2875 typedef struct MapClient {
2876 QEMUBH *bh;
2877 QLIST_ENTRY(MapClient) link;
2878 } MapClient;
2879
2880 QemuMutex map_client_list_lock;
2881 static QLIST_HEAD(map_client_list, MapClient) map_client_list
2882 = QLIST_HEAD_INITIALIZER(map_client_list);
2883
2884 static void cpu_unregister_map_client_do(MapClient *client)
2885 {
2886 QLIST_REMOVE(client, link);
2887 g_free(client);
2888 }
2889
2890 static void cpu_notify_map_clients_locked(void)
2891 {
2892 MapClient *client;
2893
2894 while (!QLIST_EMPTY(&map_client_list)) {
2895 client = QLIST_FIRST(&map_client_list);
2896 qemu_bh_schedule(client->bh);
2897 cpu_unregister_map_client_do(client);
2898 }
2899 }
2900
2901 void cpu_register_map_client(QEMUBH *bh)
2902 {
2903 MapClient *client = g_malloc(sizeof(*client));
2904
2905 qemu_mutex_lock(&map_client_list_lock);
2906 client->bh = bh;
2907 QLIST_INSERT_HEAD(&map_client_list, client, link);
2908 if (!atomic_read(&bounce.in_use)) {
2909 cpu_notify_map_clients_locked();
2910 }
2911 qemu_mutex_unlock(&map_client_list_lock);
2912 }
2913
2914 void cpu_exec_init_all(void)
2915 {
2916 qemu_mutex_init(&ram_list.mutex);
2917 /* The data structures we set up here depend on knowing the page size,
2918 * so no more changes can be made after this point.
2919 * In an ideal world, nothing we did before we had finished the
2920 * machine setup would care about the target page size, and we could
2921 * do this much later, rather than requiring board models to state
2922 * up front what their requirements are.
2923 */
2924 finalize_target_page_bits();
2925 io_mem_init();
2926 memory_map_init();
2927 qemu_mutex_init(&map_client_list_lock);
2928 }
2929
2930 void cpu_unregister_map_client(QEMUBH *bh)
2931 {
2932 MapClient *client;
2933
2934 qemu_mutex_lock(&map_client_list_lock);
2935 QLIST_FOREACH(client, &map_client_list, link) {
2936 if (client->bh == bh) {
2937 cpu_unregister_map_client_do(client);
2938 break;
2939 }
2940 }
2941 qemu_mutex_unlock(&map_client_list_lock);
2942 }
2943
2944 static void cpu_notify_map_clients(void)
2945 {
2946 qemu_mutex_lock(&map_client_list_lock);
2947 cpu_notify_map_clients_locked();
2948 qemu_mutex_unlock(&map_client_list_lock);
2949 }
2950
2951 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
2952 {
2953 MemoryRegion *mr;
2954 hwaddr l, xlat;
2955
2956 rcu_read_lock();
2957 while (len > 0) {
2958 l = len;
2959 mr = address_space_translate(as, addr, &xlat, &l, is_write);
2960 if (!memory_access_is_direct(mr, is_write)) {
2961 l = memory_access_size(mr, l, addr);
2962 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
2963 return false;
2964 }
2965 }
2966
2967 len -= l;
2968 addr += l;
2969 }
2970 rcu_read_unlock();
2971 return true;
2972 }
2973
2974 static hwaddr
2975 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
2976 MemoryRegion *mr, hwaddr base, hwaddr len,
2977 bool is_write)
2978 {
2979 hwaddr done = 0;
2980 hwaddr xlat;
2981 MemoryRegion *this_mr;
2982
2983 for (;;) {
2984 target_len -= len;
2985 addr += len;
2986 done += len;
2987 if (target_len == 0) {
2988 return done;
2989 }
2990
2991 len = target_len;
2992 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
2993 if (this_mr != mr || xlat != base + done) {
2994 return done;
2995 }
2996 }
2997 }
2998
2999 /* Map a physical memory region into a host virtual address.
3000 * May map a subset of the requested range, given by and returned in *plen.
3001 * May return NULL if resources needed to perform the mapping are exhausted.
3002 * Use only for reads OR writes - not for read-modify-write operations.
3003 * Use cpu_register_map_client() to know when retrying the map operation is
3004 * likely to succeed.
3005 */
3006 void *address_space_map(AddressSpace *as,
3007 hwaddr addr,
3008 hwaddr *plen,
3009 bool is_write)
3010 {
3011 hwaddr len = *plen;
3012 hwaddr l, xlat;
3013 MemoryRegion *mr;
3014 void *ptr;
3015
3016 if (len == 0) {
3017 return NULL;
3018 }
3019
3020 l = len;
3021 rcu_read_lock();
3022 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3023
3024 if (!memory_access_is_direct(mr, is_write)) {
3025 if (atomic_xchg(&bounce.in_use, true)) {
3026 rcu_read_unlock();
3027 return NULL;
3028 }
3029 /* Avoid unbounded allocations */
3030 l = MIN(l, TARGET_PAGE_SIZE);
3031 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3032 bounce.addr = addr;
3033 bounce.len = l;
3034
3035 memory_region_ref(mr);
3036 bounce.mr = mr;
3037 if (!is_write) {
3038 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3039 bounce.buffer, l);
3040 }
3041
3042 rcu_read_unlock();
3043 *plen = l;
3044 return bounce.buffer;
3045 }
3046
3047
3048 memory_region_ref(mr);
3049 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3050 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3051 rcu_read_unlock();
3052
3053 return ptr;
3054 }
3055
3056 /* Unmaps a memory region previously mapped by address_space_map().
3057 * Will also mark the memory as dirty if is_write == 1. access_len gives
3058 * the amount of memory that was actually read or written by the caller.
3059 */
3060 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3061 int is_write, hwaddr access_len)
3062 {
3063 if (buffer != bounce.buffer) {
3064 MemoryRegion *mr;
3065 ram_addr_t addr1;
3066
3067 mr = memory_region_from_host(buffer, &addr1);
3068 assert(mr != NULL);
3069 if (is_write) {
3070 invalidate_and_set_dirty(mr, addr1, access_len);
3071 }
3072 if (xen_enabled()) {
3073 xen_invalidate_map_cache_entry(buffer);
3074 }
3075 memory_region_unref(mr);
3076 return;
3077 }
3078 if (is_write) {
3079 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3080 bounce.buffer, access_len);
3081 }
3082 qemu_vfree(bounce.buffer);
3083 bounce.buffer = NULL;
3084 memory_region_unref(bounce.mr);
3085 atomic_mb_set(&bounce.in_use, false);
3086 cpu_notify_map_clients();
3087 }
3088
3089 void *cpu_physical_memory_map(hwaddr addr,
3090 hwaddr *plen,
3091 int is_write)
3092 {
3093 return address_space_map(&address_space_memory, addr, plen, is_write);
3094 }
3095
3096 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3097 int is_write, hwaddr access_len)
3098 {
3099 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3100 }
3101
3102 #define ARG1_DECL AddressSpace *as
3103 #define ARG1 as
3104 #define SUFFIX
3105 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3106 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3107 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3108 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3109 #define RCU_READ_LOCK(...) rcu_read_lock()
3110 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3111 #include "memory_ldst.inc.c"
3112
3113 int64_t address_space_cache_init(MemoryRegionCache *cache,
3114 AddressSpace *as,
3115 hwaddr addr,
3116 hwaddr len,
3117 bool is_write)
3118 {
3119 hwaddr l, xlat;
3120 MemoryRegion *mr;
3121 void *ptr;
3122
3123 assert(len > 0);
3124
3125 l = len;
3126 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3127 if (!memory_access_is_direct(mr, is_write)) {
3128 return -EINVAL;
3129 }
3130
3131 l = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3132 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, &l);
3133
3134 cache->xlat = xlat;
3135 cache->is_write = is_write;
3136 cache->mr = mr;
3137 cache->ptr = ptr;
3138 cache->len = l;
3139 memory_region_ref(cache->mr);
3140
3141 return l;
3142 }
3143
3144 void address_space_cache_invalidate(MemoryRegionCache *cache,
3145 hwaddr addr,
3146 hwaddr access_len)
3147 {
3148 assert(cache->is_write);
3149 invalidate_and_set_dirty(cache->mr, addr + cache->xlat, access_len);
3150 }
3151
3152 void address_space_cache_destroy(MemoryRegionCache *cache)
3153 {
3154 if (!cache->mr) {
3155 return;
3156 }
3157
3158 if (xen_enabled()) {
3159 xen_invalidate_map_cache_entry(cache->ptr);
3160 }
3161 memory_region_unref(cache->mr);
3162 }
3163
3164 /* Called from RCU critical section. This function has the same
3165 * semantics as address_space_translate, but it only works on a
3166 * predefined range of a MemoryRegion that was mapped with
3167 * address_space_cache_init.
3168 */
3169 static inline MemoryRegion *address_space_translate_cached(
3170 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3171 hwaddr *plen, bool is_write)
3172 {
3173 assert(addr < cache->len && *plen <= cache->len - addr);
3174 *xlat = addr + cache->xlat;
3175 return cache->mr;
3176 }
3177
3178 #define ARG1_DECL MemoryRegionCache *cache
3179 #define ARG1 cache
3180 #define SUFFIX _cached
3181 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3182 #define IS_DIRECT(mr, is_write) true
3183 #define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat))
3184 #define INVALIDATE(mr, ofs, len) ((void)0)
3185 #define RCU_READ_LOCK() ((void)0)
3186 #define RCU_READ_UNLOCK() ((void)0)
3187 #include "memory_ldst.inc.c"
3188
3189 /* virtual memory access for debug (includes writing to ROM) */
3190 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3191 uint8_t *buf, int len, int is_write)
3192 {
3193 int l;
3194 hwaddr phys_addr;
3195 target_ulong page;
3196
3197 while (len > 0) {
3198 int asidx;
3199 MemTxAttrs attrs;
3200
3201 page = addr & TARGET_PAGE_MASK;
3202 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3203 asidx = cpu_asidx_from_attrs(cpu, attrs);
3204 /* if no physical page mapped, return an error */
3205 if (phys_addr == -1)
3206 return -1;
3207 l = (page + TARGET_PAGE_SIZE) - addr;
3208 if (l > len)
3209 l = len;
3210 phys_addr += (addr & ~TARGET_PAGE_MASK);
3211 if (is_write) {
3212 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3213 phys_addr, buf, l);
3214 } else {
3215 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3216 MEMTXATTRS_UNSPECIFIED,
3217 buf, l, 0);
3218 }
3219 len -= l;
3220 buf += l;
3221 addr += l;
3222 }
3223 return 0;
3224 }
3225
3226 /*
3227 * Allows code that needs to deal with migration bitmaps etc to still be built
3228 * target independent.
3229 */
3230 size_t qemu_target_page_bits(void)
3231 {
3232 return TARGET_PAGE_BITS;
3233 }
3234
3235 #endif
3236
3237 /*
3238 * A helper function for the _utterly broken_ virtio device model to find out if
3239 * it's running on a big endian machine. Don't do this at home kids!
3240 */
3241 bool target_words_bigendian(void);
3242 bool target_words_bigendian(void)
3243 {
3244 #if defined(TARGET_WORDS_BIGENDIAN)
3245 return true;
3246 #else
3247 return false;
3248 #endif
3249 }
3250
3251 #ifndef CONFIG_USER_ONLY
3252 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3253 {
3254 MemoryRegion*mr;
3255 hwaddr l = 1;
3256 bool res;
3257
3258 rcu_read_lock();
3259 mr = address_space_translate(&address_space_memory,
3260 phys_addr, &phys_addr, &l, false);
3261
3262 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3263 rcu_read_unlock();
3264 return res;
3265 }
3266
3267 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3268 {
3269 RAMBlock *block;
3270 int ret = 0;
3271
3272 rcu_read_lock();
3273 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
3274 ret = func(block->idstr, block->host, block->offset,
3275 block->used_length, opaque);
3276 if (ret) {
3277 break;
3278 }
3279 }
3280 rcu_read_unlock();
3281 return ret;
3282 }
3283 #endif