configure: move accelerator logic to meson
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg/tcg.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
34 #endif
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/qtest.h"
39 #include "qemu/timer.h"
40 #include "qemu/config-file.h"
41 #include "qemu/error-report.h"
42 #include "qemu/qemu-print.h"
43 #if defined(CONFIG_USER_ONLY)
44 #include "qemu.h"
45 #else /* !CONFIG_USER_ONLY */
46 #include "exec/memory.h"
47 #include "exec/ioport.h"
48 #include "sysemu/dma.h"
49 #include "sysemu/hostmem.h"
50 #include "sysemu/hw_accel.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/xen-mapcache.h"
53 #include "trace/trace-root.h"
54
55 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
56 #include <linux/falloc.h>
57 #endif
58
59 #endif
60 #include "qemu/rcu_queue.h"
61 #include "qemu/main-loop.h"
62 #include "translate-all.h"
63 #include "sysemu/replay.h"
64
65 #include "exec/memory-internal.h"
66 #include "exec/ram_addr.h"
67 #include "exec/log.h"
68
69 #include "qemu/pmem.h"
70
71 #include "migration/vmstate.h"
72
73 #include "qemu/range.h"
74 #ifndef _WIN32
75 #include "qemu/mmap-alloc.h"
76 #endif
77
78 #include "monitor/monitor.h"
79
80 #ifdef CONFIG_LIBDAXCTL
81 #include <daxctl/libdaxctl.h>
82 #endif
83
84 //#define DEBUG_SUBPAGE
85
86 #if !defined(CONFIG_USER_ONLY)
87 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
88 * are protected by the ramlist lock.
89 */
90 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
91
92 static MemoryRegion *system_memory;
93 static MemoryRegion *system_io;
94
95 AddressSpace address_space_io;
96 AddressSpace address_space_memory;
97
98 static MemoryRegion io_mem_unassigned;
99 #endif
100
101 uintptr_t qemu_host_page_size;
102 intptr_t qemu_host_page_mask;
103
104 #if !defined(CONFIG_USER_ONLY)
105 /* 0 = Do not count executed instructions.
106 1 = Precise instruction counting.
107 2 = Adaptive rate instruction counting. */
108 int use_icount;
109
110 typedef struct PhysPageEntry PhysPageEntry;
111
112 struct PhysPageEntry {
113 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
114 uint32_t skip : 6;
115 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
116 uint32_t ptr : 26;
117 };
118
119 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
120
121 /* Size of the L2 (and L3, etc) page tables. */
122 #define ADDR_SPACE_BITS 64
123
124 #define P_L2_BITS 9
125 #define P_L2_SIZE (1 << P_L2_BITS)
126
127 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
128
129 typedef PhysPageEntry Node[P_L2_SIZE];
130
131 typedef struct PhysPageMap {
132 struct rcu_head rcu;
133
134 unsigned sections_nb;
135 unsigned sections_nb_alloc;
136 unsigned nodes_nb;
137 unsigned nodes_nb_alloc;
138 Node *nodes;
139 MemoryRegionSection *sections;
140 } PhysPageMap;
141
142 struct AddressSpaceDispatch {
143 MemoryRegionSection *mru_section;
144 /* This is a multi-level map on the physical address space.
145 * The bottom level has pointers to MemoryRegionSections.
146 */
147 PhysPageEntry phys_map;
148 PhysPageMap map;
149 };
150
151 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
152 typedef struct subpage_t {
153 MemoryRegion iomem;
154 FlatView *fv;
155 hwaddr base;
156 uint16_t sub_section[];
157 } subpage_t;
158
159 #define PHYS_SECTION_UNASSIGNED 0
160
161 static void io_mem_init(void);
162 static void memory_map_init(void);
163 static void tcg_log_global_after_sync(MemoryListener *listener);
164 static void tcg_commit(MemoryListener *listener);
165
166 /**
167 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
168 * @cpu: the CPU whose AddressSpace this is
169 * @as: the AddressSpace itself
170 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
171 * @tcg_as_listener: listener for tracking changes to the AddressSpace
172 */
173 struct CPUAddressSpace {
174 CPUState *cpu;
175 AddressSpace *as;
176 struct AddressSpaceDispatch *memory_dispatch;
177 MemoryListener tcg_as_listener;
178 };
179
180 struct DirtyBitmapSnapshot {
181 ram_addr_t start;
182 ram_addr_t end;
183 unsigned long dirty[];
184 };
185
186 #endif
187
188 #if !defined(CONFIG_USER_ONLY)
189
190 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
191 {
192 static unsigned alloc_hint = 16;
193 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
194 map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes);
195 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
196 alloc_hint = map->nodes_nb_alloc;
197 }
198 }
199
200 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
201 {
202 unsigned i;
203 uint32_t ret;
204 PhysPageEntry e;
205 PhysPageEntry *p;
206
207 ret = map->nodes_nb++;
208 p = map->nodes[ret];
209 assert(ret != PHYS_MAP_NODE_NIL);
210 assert(ret != map->nodes_nb_alloc);
211
212 e.skip = leaf ? 0 : 1;
213 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
214 for (i = 0; i < P_L2_SIZE; ++i) {
215 memcpy(&p[i], &e, sizeof(e));
216 }
217 return ret;
218 }
219
220 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
221 hwaddr *index, uint64_t *nb, uint16_t leaf,
222 int level)
223 {
224 PhysPageEntry *p;
225 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
226
227 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
228 lp->ptr = phys_map_node_alloc(map, level == 0);
229 }
230 p = map->nodes[lp->ptr];
231 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
232
233 while (*nb && lp < &p[P_L2_SIZE]) {
234 if ((*index & (step - 1)) == 0 && *nb >= step) {
235 lp->skip = 0;
236 lp->ptr = leaf;
237 *index += step;
238 *nb -= step;
239 } else {
240 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
241 }
242 ++lp;
243 }
244 }
245
246 static void phys_page_set(AddressSpaceDispatch *d,
247 hwaddr index, uint64_t nb,
248 uint16_t leaf)
249 {
250 /* Wildly overreserve - it doesn't matter much. */
251 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
252
253 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
254 }
255
256 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
257 * and update our entry so we can skip it and go directly to the destination.
258 */
259 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
260 {
261 unsigned valid_ptr = P_L2_SIZE;
262 int valid = 0;
263 PhysPageEntry *p;
264 int i;
265
266 if (lp->ptr == PHYS_MAP_NODE_NIL) {
267 return;
268 }
269
270 p = nodes[lp->ptr];
271 for (i = 0; i < P_L2_SIZE; i++) {
272 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
273 continue;
274 }
275
276 valid_ptr = i;
277 valid++;
278 if (p[i].skip) {
279 phys_page_compact(&p[i], nodes);
280 }
281 }
282
283 /* We can only compress if there's only one child. */
284 if (valid != 1) {
285 return;
286 }
287
288 assert(valid_ptr < P_L2_SIZE);
289
290 /* Don't compress if it won't fit in the # of bits we have. */
291 if (P_L2_LEVELS >= (1 << 6) &&
292 lp->skip + p[valid_ptr].skip >= (1 << 6)) {
293 return;
294 }
295
296 lp->ptr = p[valid_ptr].ptr;
297 if (!p[valid_ptr].skip) {
298 /* If our only child is a leaf, make this a leaf. */
299 /* By design, we should have made this node a leaf to begin with so we
300 * should never reach here.
301 * But since it's so simple to handle this, let's do it just in case we
302 * change this rule.
303 */
304 lp->skip = 0;
305 } else {
306 lp->skip += p[valid_ptr].skip;
307 }
308 }
309
310 void address_space_dispatch_compact(AddressSpaceDispatch *d)
311 {
312 if (d->phys_map.skip) {
313 phys_page_compact(&d->phys_map, d->map.nodes);
314 }
315 }
316
317 static inline bool section_covers_addr(const MemoryRegionSection *section,
318 hwaddr addr)
319 {
320 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
321 * the section must cover the entire address space.
322 */
323 return int128_gethi(section->size) ||
324 range_covers_byte(section->offset_within_address_space,
325 int128_getlo(section->size), addr);
326 }
327
328 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
329 {
330 PhysPageEntry lp = d->phys_map, *p;
331 Node *nodes = d->map.nodes;
332 MemoryRegionSection *sections = d->map.sections;
333 hwaddr index = addr >> TARGET_PAGE_BITS;
334 int i;
335
336 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
337 if (lp.ptr == PHYS_MAP_NODE_NIL) {
338 return &sections[PHYS_SECTION_UNASSIGNED];
339 }
340 p = nodes[lp.ptr];
341 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
342 }
343
344 if (section_covers_addr(&sections[lp.ptr], addr)) {
345 return &sections[lp.ptr];
346 } else {
347 return &sections[PHYS_SECTION_UNASSIGNED];
348 }
349 }
350
351 /* Called from RCU critical section */
352 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
353 hwaddr addr,
354 bool resolve_subpage)
355 {
356 MemoryRegionSection *section = qatomic_read(&d->mru_section);
357 subpage_t *subpage;
358
359 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
360 !section_covers_addr(section, addr)) {
361 section = phys_page_find(d, addr);
362 qatomic_set(&d->mru_section, section);
363 }
364 if (resolve_subpage && section->mr->subpage) {
365 subpage = container_of(section->mr, subpage_t, iomem);
366 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
367 }
368 return section;
369 }
370
371 /* Called from RCU critical section */
372 static MemoryRegionSection *
373 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
374 hwaddr *plen, bool resolve_subpage)
375 {
376 MemoryRegionSection *section;
377 MemoryRegion *mr;
378 Int128 diff;
379
380 section = address_space_lookup_region(d, addr, resolve_subpage);
381 /* Compute offset within MemoryRegionSection */
382 addr -= section->offset_within_address_space;
383
384 /* Compute offset within MemoryRegion */
385 *xlat = addr + section->offset_within_region;
386
387 mr = section->mr;
388
389 /* MMIO registers can be expected to perform full-width accesses based only
390 * on their address, without considering adjacent registers that could
391 * decode to completely different MemoryRegions. When such registers
392 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
393 * regions overlap wildly. For this reason we cannot clamp the accesses
394 * here.
395 *
396 * If the length is small (as is the case for address_space_ldl/stl),
397 * everything works fine. If the incoming length is large, however,
398 * the caller really has to do the clamping through memory_access_size.
399 */
400 if (memory_region_is_ram(mr)) {
401 diff = int128_sub(section->size, int128_make64(addr));
402 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
403 }
404 return section;
405 }
406
407 /**
408 * address_space_translate_iommu - translate an address through an IOMMU
409 * memory region and then through the target address space.
410 *
411 * @iommu_mr: the IOMMU memory region that we start the translation from
412 * @addr: the address to be translated through the MMU
413 * @xlat: the translated address offset within the destination memory region.
414 * It cannot be %NULL.
415 * @plen_out: valid read/write length of the translated address. It
416 * cannot be %NULL.
417 * @page_mask_out: page mask for the translated address. This
418 * should only be meaningful for IOMMU translated
419 * addresses, since there may be huge pages that this bit
420 * would tell. It can be %NULL if we don't care about it.
421 * @is_write: whether the translation operation is for write
422 * @is_mmio: whether this can be MMIO, set true if it can
423 * @target_as: the address space targeted by the IOMMU
424 * @attrs: transaction attributes
425 *
426 * This function is called from RCU critical section. It is the common
427 * part of flatview_do_translate and address_space_translate_cached.
428 */
429 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
430 hwaddr *xlat,
431 hwaddr *plen_out,
432 hwaddr *page_mask_out,
433 bool is_write,
434 bool is_mmio,
435 AddressSpace **target_as,
436 MemTxAttrs attrs)
437 {
438 MemoryRegionSection *section;
439 hwaddr page_mask = (hwaddr)-1;
440
441 do {
442 hwaddr addr = *xlat;
443 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
444 int iommu_idx = 0;
445 IOMMUTLBEntry iotlb;
446
447 if (imrc->attrs_to_index) {
448 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
449 }
450
451 iotlb = imrc->translate(iommu_mr, addr, is_write ?
452 IOMMU_WO : IOMMU_RO, iommu_idx);
453
454 if (!(iotlb.perm & (1 << is_write))) {
455 goto unassigned;
456 }
457
458 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
459 | (addr & iotlb.addr_mask));
460 page_mask &= iotlb.addr_mask;
461 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
462 *target_as = iotlb.target_as;
463
464 section = address_space_translate_internal(
465 address_space_to_dispatch(iotlb.target_as), addr, xlat,
466 plen_out, is_mmio);
467
468 iommu_mr = memory_region_get_iommu(section->mr);
469 } while (unlikely(iommu_mr));
470
471 if (page_mask_out) {
472 *page_mask_out = page_mask;
473 }
474 return *section;
475
476 unassigned:
477 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
478 }
479
480 /**
481 * flatview_do_translate - translate an address in FlatView
482 *
483 * @fv: the flat view that we want to translate on
484 * @addr: the address to be translated in above address space
485 * @xlat: the translated address offset within memory region. It
486 * cannot be @NULL.
487 * @plen_out: valid read/write length of the translated address. It
488 * can be @NULL when we don't care about it.
489 * @page_mask_out: page mask for the translated address. This
490 * should only be meaningful for IOMMU translated
491 * addresses, since there may be huge pages that this bit
492 * would tell. It can be @NULL if we don't care about it.
493 * @is_write: whether the translation operation is for write
494 * @is_mmio: whether this can be MMIO, set true if it can
495 * @target_as: the address space targeted by the IOMMU
496 * @attrs: memory transaction attributes
497 *
498 * This function is called from RCU critical section
499 */
500 static MemoryRegionSection flatview_do_translate(FlatView *fv,
501 hwaddr addr,
502 hwaddr *xlat,
503 hwaddr *plen_out,
504 hwaddr *page_mask_out,
505 bool is_write,
506 bool is_mmio,
507 AddressSpace **target_as,
508 MemTxAttrs attrs)
509 {
510 MemoryRegionSection *section;
511 IOMMUMemoryRegion *iommu_mr;
512 hwaddr plen = (hwaddr)(-1);
513
514 if (!plen_out) {
515 plen_out = &plen;
516 }
517
518 section = address_space_translate_internal(
519 flatview_to_dispatch(fv), addr, xlat,
520 plen_out, is_mmio);
521
522 iommu_mr = memory_region_get_iommu(section->mr);
523 if (unlikely(iommu_mr)) {
524 return address_space_translate_iommu(iommu_mr, xlat,
525 plen_out, page_mask_out,
526 is_write, is_mmio,
527 target_as, attrs);
528 }
529 if (page_mask_out) {
530 /* Not behind an IOMMU, use default page size. */
531 *page_mask_out = ~TARGET_PAGE_MASK;
532 }
533
534 return *section;
535 }
536
537 /* Called from RCU critical section */
538 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
539 bool is_write, MemTxAttrs attrs)
540 {
541 MemoryRegionSection section;
542 hwaddr xlat, page_mask;
543
544 /*
545 * This can never be MMIO, and we don't really care about plen,
546 * but page mask.
547 */
548 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
549 NULL, &page_mask, is_write, false, &as,
550 attrs);
551
552 /* Illegal translation */
553 if (section.mr == &io_mem_unassigned) {
554 goto iotlb_fail;
555 }
556
557 /* Convert memory region offset into address space offset */
558 xlat += section.offset_within_address_space -
559 section.offset_within_region;
560
561 return (IOMMUTLBEntry) {
562 .target_as = as,
563 .iova = addr & ~page_mask,
564 .translated_addr = xlat & ~page_mask,
565 .addr_mask = page_mask,
566 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
567 .perm = IOMMU_RW,
568 };
569
570 iotlb_fail:
571 return (IOMMUTLBEntry) {0};
572 }
573
574 /* Called from RCU critical section */
575 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
576 hwaddr *plen, bool is_write,
577 MemTxAttrs attrs)
578 {
579 MemoryRegion *mr;
580 MemoryRegionSection section;
581 AddressSpace *as = NULL;
582
583 /* This can be MMIO, so setup MMIO bit. */
584 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
585 is_write, true, &as, attrs);
586 mr = section.mr;
587
588 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
589 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
590 *plen = MIN(page, *plen);
591 }
592
593 return mr;
594 }
595
596 typedef struct TCGIOMMUNotifier {
597 IOMMUNotifier n;
598 MemoryRegion *mr;
599 CPUState *cpu;
600 int iommu_idx;
601 bool active;
602 } TCGIOMMUNotifier;
603
604 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
605 {
606 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
607
608 if (!notifier->active) {
609 return;
610 }
611 tlb_flush(notifier->cpu);
612 notifier->active = false;
613 /* We leave the notifier struct on the list to avoid reallocating it later.
614 * Generally the number of IOMMUs a CPU deals with will be small.
615 * In any case we can't unregister the iommu notifier from a notify
616 * callback.
617 */
618 }
619
620 static void tcg_register_iommu_notifier(CPUState *cpu,
621 IOMMUMemoryRegion *iommu_mr,
622 int iommu_idx)
623 {
624 /* Make sure this CPU has an IOMMU notifier registered for this
625 * IOMMU/IOMMU index combination, so that we can flush its TLB
626 * when the IOMMU tells us the mappings we've cached have changed.
627 */
628 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
629 TCGIOMMUNotifier *notifier;
630 Error *err = NULL;
631 int i, ret;
632
633 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
634 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
635 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
636 break;
637 }
638 }
639 if (i == cpu->iommu_notifiers->len) {
640 /* Not found, add a new entry at the end of the array */
641 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
642 notifier = g_new0(TCGIOMMUNotifier, 1);
643 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
644
645 notifier->mr = mr;
646 notifier->iommu_idx = iommu_idx;
647 notifier->cpu = cpu;
648 /* Rather than trying to register interest in the specific part
649 * of the iommu's address space that we've accessed and then
650 * expand it later as subsequent accesses touch more of it, we
651 * just register interest in the whole thing, on the assumption
652 * that iommu reconfiguration will be rare.
653 */
654 iommu_notifier_init(&notifier->n,
655 tcg_iommu_unmap_notify,
656 IOMMU_NOTIFIER_UNMAP,
657 0,
658 HWADDR_MAX,
659 iommu_idx);
660 ret = memory_region_register_iommu_notifier(notifier->mr, &notifier->n,
661 &err);
662 if (ret) {
663 error_report_err(err);
664 exit(1);
665 }
666 }
667
668 if (!notifier->active) {
669 notifier->active = true;
670 }
671 }
672
673 static void tcg_iommu_free_notifier_list(CPUState *cpu)
674 {
675 /* Destroy the CPU's notifier list */
676 int i;
677 TCGIOMMUNotifier *notifier;
678
679 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
680 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
681 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
682 g_free(notifier);
683 }
684 g_array_free(cpu->iommu_notifiers, true);
685 }
686
687 /* Called from RCU critical section */
688 MemoryRegionSection *
689 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
690 hwaddr *xlat, hwaddr *plen,
691 MemTxAttrs attrs, int *prot)
692 {
693 MemoryRegionSection *section;
694 IOMMUMemoryRegion *iommu_mr;
695 IOMMUMemoryRegionClass *imrc;
696 IOMMUTLBEntry iotlb;
697 int iommu_idx;
698 AddressSpaceDispatch *d =
699 qatomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
700
701 for (;;) {
702 section = address_space_translate_internal(d, addr, &addr, plen, false);
703
704 iommu_mr = memory_region_get_iommu(section->mr);
705 if (!iommu_mr) {
706 break;
707 }
708
709 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
710
711 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
712 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
713 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
714 * doesn't short-cut its translation table walk.
715 */
716 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
717 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
718 | (addr & iotlb.addr_mask));
719 /* Update the caller's prot bits to remove permissions the IOMMU
720 * is giving us a failure response for. If we get down to no
721 * permissions left at all we can give up now.
722 */
723 if (!(iotlb.perm & IOMMU_RO)) {
724 *prot &= ~(PAGE_READ | PAGE_EXEC);
725 }
726 if (!(iotlb.perm & IOMMU_WO)) {
727 *prot &= ~PAGE_WRITE;
728 }
729
730 if (!*prot) {
731 goto translate_fail;
732 }
733
734 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
735 }
736
737 assert(!memory_region_is_iommu(section->mr));
738 *xlat = addr;
739 return section;
740
741 translate_fail:
742 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
743 }
744 #endif
745
746 #if !defined(CONFIG_USER_ONLY)
747
748 static int cpu_common_post_load(void *opaque, int version_id)
749 {
750 CPUState *cpu = opaque;
751
752 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
753 version_id is increased. */
754 cpu->interrupt_request &= ~0x01;
755 tlb_flush(cpu);
756
757 /* loadvm has just updated the content of RAM, bypassing the
758 * usual mechanisms that ensure we flush TBs for writes to
759 * memory we've translated code from. So we must flush all TBs,
760 * which will now be stale.
761 */
762 tb_flush(cpu);
763
764 return 0;
765 }
766
767 static int cpu_common_pre_load(void *opaque)
768 {
769 CPUState *cpu = opaque;
770
771 cpu->exception_index = -1;
772
773 return 0;
774 }
775
776 static bool cpu_common_exception_index_needed(void *opaque)
777 {
778 CPUState *cpu = opaque;
779
780 return tcg_enabled() && cpu->exception_index != -1;
781 }
782
783 static const VMStateDescription vmstate_cpu_common_exception_index = {
784 .name = "cpu_common/exception_index",
785 .version_id = 1,
786 .minimum_version_id = 1,
787 .needed = cpu_common_exception_index_needed,
788 .fields = (VMStateField[]) {
789 VMSTATE_INT32(exception_index, CPUState),
790 VMSTATE_END_OF_LIST()
791 }
792 };
793
794 static bool cpu_common_crash_occurred_needed(void *opaque)
795 {
796 CPUState *cpu = opaque;
797
798 return cpu->crash_occurred;
799 }
800
801 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
802 .name = "cpu_common/crash_occurred",
803 .version_id = 1,
804 .minimum_version_id = 1,
805 .needed = cpu_common_crash_occurred_needed,
806 .fields = (VMStateField[]) {
807 VMSTATE_BOOL(crash_occurred, CPUState),
808 VMSTATE_END_OF_LIST()
809 }
810 };
811
812 const VMStateDescription vmstate_cpu_common = {
813 .name = "cpu_common",
814 .version_id = 1,
815 .minimum_version_id = 1,
816 .pre_load = cpu_common_pre_load,
817 .post_load = cpu_common_post_load,
818 .fields = (VMStateField[]) {
819 VMSTATE_UINT32(halted, CPUState),
820 VMSTATE_UINT32(interrupt_request, CPUState),
821 VMSTATE_END_OF_LIST()
822 },
823 .subsections = (const VMStateDescription*[]) {
824 &vmstate_cpu_common_exception_index,
825 &vmstate_cpu_common_crash_occurred,
826 NULL
827 }
828 };
829
830 void cpu_address_space_init(CPUState *cpu, int asidx,
831 const char *prefix, MemoryRegion *mr)
832 {
833 CPUAddressSpace *newas;
834 AddressSpace *as = g_new0(AddressSpace, 1);
835 char *as_name;
836
837 assert(mr);
838 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
839 address_space_init(as, mr, as_name);
840 g_free(as_name);
841
842 /* Target code should have set num_ases before calling us */
843 assert(asidx < cpu->num_ases);
844
845 if (asidx == 0) {
846 /* address space 0 gets the convenience alias */
847 cpu->as = as;
848 }
849
850 /* KVM cannot currently support multiple address spaces. */
851 assert(asidx == 0 || !kvm_enabled());
852
853 if (!cpu->cpu_ases) {
854 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
855 }
856
857 newas = &cpu->cpu_ases[asidx];
858 newas->cpu = cpu;
859 newas->as = as;
860 if (tcg_enabled()) {
861 newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync;
862 newas->tcg_as_listener.commit = tcg_commit;
863 memory_listener_register(&newas->tcg_as_listener, as);
864 }
865 }
866
867 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
868 {
869 /* Return the AddressSpace corresponding to the specified index */
870 return cpu->cpu_ases[asidx].as;
871 }
872 #endif
873
874 void cpu_exec_unrealizefn(CPUState *cpu)
875 {
876 CPUClass *cc = CPU_GET_CLASS(cpu);
877
878 tlb_destroy(cpu);
879 cpu_list_remove(cpu);
880
881 if (cc->vmsd != NULL) {
882 vmstate_unregister(NULL, cc->vmsd, cpu);
883 }
884 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
885 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
886 }
887 #ifndef CONFIG_USER_ONLY
888 tcg_iommu_free_notifier_list(cpu);
889 #endif
890 }
891
892 Property cpu_common_props[] = {
893 #ifndef CONFIG_USER_ONLY
894 /* Create a memory property for softmmu CPU object,
895 * so users can wire up its memory. (This can't go in hw/core/cpu.c
896 * because that file is compiled only once for both user-mode
897 * and system builds.) The default if no link is set up is to use
898 * the system address space.
899 */
900 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
901 MemoryRegion *),
902 #endif
903 DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
904 DEFINE_PROP_END_OF_LIST(),
905 };
906
907 void cpu_exec_initfn(CPUState *cpu)
908 {
909 cpu->as = NULL;
910 cpu->num_ases = 0;
911
912 #ifndef CONFIG_USER_ONLY
913 cpu->thread_id = qemu_get_thread_id();
914 cpu->memory = system_memory;
915 object_ref(OBJECT(cpu->memory));
916 #endif
917 }
918
919 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
920 {
921 CPUClass *cc = CPU_GET_CLASS(cpu);
922 static bool tcg_target_initialized;
923
924 cpu_list_add(cpu);
925
926 if (tcg_enabled() && !tcg_target_initialized) {
927 tcg_target_initialized = true;
928 cc->tcg_initialize();
929 }
930 tlb_init(cpu);
931
932 qemu_plugin_vcpu_init_hook(cpu);
933
934 #ifdef CONFIG_USER_ONLY
935 assert(cc->vmsd == NULL);
936 #else /* !CONFIG_USER_ONLY */
937 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
938 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
939 }
940 if (cc->vmsd != NULL) {
941 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
942 }
943
944 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
945 #endif
946 }
947
948 const char *parse_cpu_option(const char *cpu_option)
949 {
950 ObjectClass *oc;
951 CPUClass *cc;
952 gchar **model_pieces;
953 const char *cpu_type;
954
955 model_pieces = g_strsplit(cpu_option, ",", 2);
956 if (!model_pieces[0]) {
957 error_report("-cpu option cannot be empty");
958 exit(1);
959 }
960
961 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
962 if (oc == NULL) {
963 error_report("unable to find CPU model '%s'", model_pieces[0]);
964 g_strfreev(model_pieces);
965 exit(EXIT_FAILURE);
966 }
967
968 cpu_type = object_class_get_name(oc);
969 cc = CPU_CLASS(oc);
970 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
971 g_strfreev(model_pieces);
972 return cpu_type;
973 }
974
975 #if defined(CONFIG_USER_ONLY)
976 void tb_invalidate_phys_addr(target_ulong addr)
977 {
978 mmap_lock();
979 tb_invalidate_phys_page_range(addr, addr + 1);
980 mmap_unlock();
981 }
982
983 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
984 {
985 tb_invalidate_phys_addr(pc);
986 }
987 #else
988 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
989 {
990 ram_addr_t ram_addr;
991 MemoryRegion *mr;
992 hwaddr l = 1;
993
994 if (!tcg_enabled()) {
995 return;
996 }
997
998 RCU_READ_LOCK_GUARD();
999 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1000 if (!(memory_region_is_ram(mr)
1001 || memory_region_is_romd(mr))) {
1002 return;
1003 }
1004 ram_addr = memory_region_get_ram_addr(mr) + addr;
1005 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
1006 }
1007
1008 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1009 {
1010 /*
1011 * There may not be a virtual to physical translation for the pc
1012 * right now, but there may exist cached TB for this pc.
1013 * Flush the whole TB cache to force re-translation of such TBs.
1014 * This is heavyweight, but we're debugging anyway.
1015 */
1016 tb_flush(cpu);
1017 }
1018 #endif
1019
1020 #ifndef CONFIG_USER_ONLY
1021 /* Add a watchpoint. */
1022 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1023 int flags, CPUWatchpoint **watchpoint)
1024 {
1025 CPUWatchpoint *wp;
1026 vaddr in_page;
1027
1028 /* forbid ranges which are empty or run off the end of the address space */
1029 if (len == 0 || (addr + len - 1) < addr) {
1030 error_report("tried to set invalid watchpoint at %"
1031 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1032 return -EINVAL;
1033 }
1034 wp = g_malloc(sizeof(*wp));
1035
1036 wp->vaddr = addr;
1037 wp->len = len;
1038 wp->flags = flags;
1039
1040 /* keep all GDB-injected watchpoints in front */
1041 if (flags & BP_GDB) {
1042 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1043 } else {
1044 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1045 }
1046
1047 in_page = -(addr | TARGET_PAGE_MASK);
1048 if (len <= in_page) {
1049 tlb_flush_page(cpu, addr);
1050 } else {
1051 tlb_flush(cpu);
1052 }
1053
1054 if (watchpoint)
1055 *watchpoint = wp;
1056 return 0;
1057 }
1058
1059 /* Remove a specific watchpoint. */
1060 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1061 int flags)
1062 {
1063 CPUWatchpoint *wp;
1064
1065 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1066 if (addr == wp->vaddr && len == wp->len
1067 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1068 cpu_watchpoint_remove_by_ref(cpu, wp);
1069 return 0;
1070 }
1071 }
1072 return -ENOENT;
1073 }
1074
1075 /* Remove a specific watchpoint by reference. */
1076 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1077 {
1078 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1079
1080 tlb_flush_page(cpu, watchpoint->vaddr);
1081
1082 g_free(watchpoint);
1083 }
1084
1085 /* Remove all matching watchpoints. */
1086 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1087 {
1088 CPUWatchpoint *wp, *next;
1089
1090 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1091 if (wp->flags & mask) {
1092 cpu_watchpoint_remove_by_ref(cpu, wp);
1093 }
1094 }
1095 }
1096
1097 /* Return true if this watchpoint address matches the specified
1098 * access (ie the address range covered by the watchpoint overlaps
1099 * partially or completely with the address range covered by the
1100 * access).
1101 */
1102 static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
1103 vaddr addr, vaddr len)
1104 {
1105 /* We know the lengths are non-zero, but a little caution is
1106 * required to avoid errors in the case where the range ends
1107 * exactly at the top of the address space and so addr + len
1108 * wraps round to zero.
1109 */
1110 vaddr wpend = wp->vaddr + wp->len - 1;
1111 vaddr addrend = addr + len - 1;
1112
1113 return !(addr > wpend || wp->vaddr > addrend);
1114 }
1115
1116 /* Return flags for watchpoints that match addr + prot. */
1117 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
1118 {
1119 CPUWatchpoint *wp;
1120 int ret = 0;
1121
1122 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1123 if (watchpoint_address_matches(wp, addr, len)) {
1124 ret |= wp->flags;
1125 }
1126 }
1127 return ret;
1128 }
1129 #endif /* !CONFIG_USER_ONLY */
1130
1131 /* Add a breakpoint. */
1132 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1133 CPUBreakpoint **breakpoint)
1134 {
1135 CPUBreakpoint *bp;
1136
1137 bp = g_malloc(sizeof(*bp));
1138
1139 bp->pc = pc;
1140 bp->flags = flags;
1141
1142 /* keep all GDB-injected breakpoints in front */
1143 if (flags & BP_GDB) {
1144 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1145 } else {
1146 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1147 }
1148
1149 breakpoint_invalidate(cpu, pc);
1150
1151 if (breakpoint) {
1152 *breakpoint = bp;
1153 }
1154 return 0;
1155 }
1156
1157 /* Remove a specific breakpoint. */
1158 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1159 {
1160 CPUBreakpoint *bp;
1161
1162 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1163 if (bp->pc == pc && bp->flags == flags) {
1164 cpu_breakpoint_remove_by_ref(cpu, bp);
1165 return 0;
1166 }
1167 }
1168 return -ENOENT;
1169 }
1170
1171 /* Remove a specific breakpoint by reference. */
1172 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1173 {
1174 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1175
1176 breakpoint_invalidate(cpu, breakpoint->pc);
1177
1178 g_free(breakpoint);
1179 }
1180
1181 /* Remove all matching breakpoints. */
1182 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1183 {
1184 CPUBreakpoint *bp, *next;
1185
1186 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1187 if (bp->flags & mask) {
1188 cpu_breakpoint_remove_by_ref(cpu, bp);
1189 }
1190 }
1191 }
1192
1193 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1194 CPU loop after each instruction */
1195 void cpu_single_step(CPUState *cpu, int enabled)
1196 {
1197 if (cpu->singlestep_enabled != enabled) {
1198 cpu->singlestep_enabled = enabled;
1199 if (kvm_enabled()) {
1200 kvm_update_guest_debug(cpu, 0);
1201 } else {
1202 /* must flush all the translated code to avoid inconsistencies */
1203 /* XXX: only flush what is necessary */
1204 tb_flush(cpu);
1205 }
1206 }
1207 }
1208
1209 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1210 {
1211 va_list ap;
1212 va_list ap2;
1213
1214 va_start(ap, fmt);
1215 va_copy(ap2, ap);
1216 fprintf(stderr, "qemu: fatal: ");
1217 vfprintf(stderr, fmt, ap);
1218 fprintf(stderr, "\n");
1219 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1220 if (qemu_log_separate()) {
1221 FILE *logfile = qemu_log_lock();
1222 qemu_log("qemu: fatal: ");
1223 qemu_log_vprintf(fmt, ap2);
1224 qemu_log("\n");
1225 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1226 qemu_log_flush();
1227 qemu_log_unlock(logfile);
1228 qemu_log_close();
1229 }
1230 va_end(ap2);
1231 va_end(ap);
1232 replay_finish();
1233 #if defined(CONFIG_USER_ONLY)
1234 {
1235 struct sigaction act;
1236 sigfillset(&act.sa_mask);
1237 act.sa_handler = SIG_DFL;
1238 act.sa_flags = 0;
1239 sigaction(SIGABRT, &act, NULL);
1240 }
1241 #endif
1242 abort();
1243 }
1244
1245 #if !defined(CONFIG_USER_ONLY)
1246 /* Called from RCU critical section */
1247 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1248 {
1249 RAMBlock *block;
1250
1251 block = qatomic_rcu_read(&ram_list.mru_block);
1252 if (block && addr - block->offset < block->max_length) {
1253 return block;
1254 }
1255 RAMBLOCK_FOREACH(block) {
1256 if (addr - block->offset < block->max_length) {
1257 goto found;
1258 }
1259 }
1260
1261 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1262 abort();
1263
1264 found:
1265 /* It is safe to write mru_block outside the iothread lock. This
1266 * is what happens:
1267 *
1268 * mru_block = xxx
1269 * rcu_read_unlock()
1270 * xxx removed from list
1271 * rcu_read_lock()
1272 * read mru_block
1273 * mru_block = NULL;
1274 * call_rcu(reclaim_ramblock, xxx);
1275 * rcu_read_unlock()
1276 *
1277 * qatomic_rcu_set is not needed here. The block was already published
1278 * when it was placed into the list. Here we're just making an extra
1279 * copy of the pointer.
1280 */
1281 ram_list.mru_block = block;
1282 return block;
1283 }
1284
1285 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1286 {
1287 CPUState *cpu;
1288 ram_addr_t start1;
1289 RAMBlock *block;
1290 ram_addr_t end;
1291
1292 assert(tcg_enabled());
1293 end = TARGET_PAGE_ALIGN(start + length);
1294 start &= TARGET_PAGE_MASK;
1295
1296 RCU_READ_LOCK_GUARD();
1297 block = qemu_get_ram_block(start);
1298 assert(block == qemu_get_ram_block(end - 1));
1299 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1300 CPU_FOREACH(cpu) {
1301 tlb_reset_dirty(cpu, start1, length);
1302 }
1303 }
1304
1305 /* Note: start and end must be within the same ram block. */
1306 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1307 ram_addr_t length,
1308 unsigned client)
1309 {
1310 DirtyMemoryBlocks *blocks;
1311 unsigned long end, page, start_page;
1312 bool dirty = false;
1313 RAMBlock *ramblock;
1314 uint64_t mr_offset, mr_size;
1315
1316 if (length == 0) {
1317 return false;
1318 }
1319
1320 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1321 start_page = start >> TARGET_PAGE_BITS;
1322 page = start_page;
1323
1324 WITH_RCU_READ_LOCK_GUARD() {
1325 blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]);
1326 ramblock = qemu_get_ram_block(start);
1327 /* Range sanity check on the ramblock */
1328 assert(start >= ramblock->offset &&
1329 start + length <= ramblock->offset + ramblock->used_length);
1330
1331 while (page < end) {
1332 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1333 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1334 unsigned long num = MIN(end - page,
1335 DIRTY_MEMORY_BLOCK_SIZE - offset);
1336
1337 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1338 offset, num);
1339 page += num;
1340 }
1341
1342 mr_offset = (ram_addr_t)(start_page << TARGET_PAGE_BITS) - ramblock->offset;
1343 mr_size = (end - start_page) << TARGET_PAGE_BITS;
1344 memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
1345 }
1346
1347 if (dirty && tcg_enabled()) {
1348 tlb_reset_dirty_range_all(start, length);
1349 }
1350
1351 return dirty;
1352 }
1353
1354 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1355 (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client)
1356 {
1357 DirtyMemoryBlocks *blocks;
1358 ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
1359 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1360 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1361 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1362 DirtyBitmapSnapshot *snap;
1363 unsigned long page, end, dest;
1364
1365 snap = g_malloc0(sizeof(*snap) +
1366 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1367 snap->start = first;
1368 snap->end = last;
1369
1370 page = first >> TARGET_PAGE_BITS;
1371 end = last >> TARGET_PAGE_BITS;
1372 dest = 0;
1373
1374 WITH_RCU_READ_LOCK_GUARD() {
1375 blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]);
1376
1377 while (page < end) {
1378 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1379 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1380 unsigned long num = MIN(end - page,
1381 DIRTY_MEMORY_BLOCK_SIZE - offset);
1382
1383 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1384 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1385 offset >>= BITS_PER_LEVEL;
1386
1387 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1388 blocks->blocks[idx] + offset,
1389 num);
1390 page += num;
1391 dest += num >> BITS_PER_LEVEL;
1392 }
1393 }
1394
1395 if (tcg_enabled()) {
1396 tlb_reset_dirty_range_all(start, length);
1397 }
1398
1399 memory_region_clear_dirty_bitmap(mr, offset, length);
1400
1401 return snap;
1402 }
1403
1404 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1405 ram_addr_t start,
1406 ram_addr_t length)
1407 {
1408 unsigned long page, end;
1409
1410 assert(start >= snap->start);
1411 assert(start + length <= snap->end);
1412
1413 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1414 page = (start - snap->start) >> TARGET_PAGE_BITS;
1415
1416 while (page < end) {
1417 if (test_bit(page, snap->dirty)) {
1418 return true;
1419 }
1420 page++;
1421 }
1422 return false;
1423 }
1424
1425 /* Called from RCU critical section */
1426 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1427 MemoryRegionSection *section)
1428 {
1429 AddressSpaceDispatch *d = flatview_to_dispatch(section->fv);
1430 return section - d->map.sections;
1431 }
1432 #endif /* defined(CONFIG_USER_ONLY) */
1433
1434 #if !defined(CONFIG_USER_ONLY)
1435
1436 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
1437 uint16_t section);
1438 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1439
1440 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1441 qemu_anon_ram_alloc;
1442
1443 /*
1444 * Set a custom physical guest memory alloator.
1445 * Accelerators with unusual needs may need this. Hopefully, we can
1446 * get rid of it eventually.
1447 */
1448 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1449 {
1450 phys_mem_alloc = alloc;
1451 }
1452
1453 static uint16_t phys_section_add(PhysPageMap *map,
1454 MemoryRegionSection *section)
1455 {
1456 /* The physical section number is ORed with a page-aligned
1457 * pointer to produce the iotlb entries. Thus it should
1458 * never overflow into the page-aligned value.
1459 */
1460 assert(map->sections_nb < TARGET_PAGE_SIZE);
1461
1462 if (map->sections_nb == map->sections_nb_alloc) {
1463 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1464 map->sections = g_renew(MemoryRegionSection, map->sections,
1465 map->sections_nb_alloc);
1466 }
1467 map->sections[map->sections_nb] = *section;
1468 memory_region_ref(section->mr);
1469 return map->sections_nb++;
1470 }
1471
1472 static void phys_section_destroy(MemoryRegion *mr)
1473 {
1474 bool have_sub_page = mr->subpage;
1475
1476 memory_region_unref(mr);
1477
1478 if (have_sub_page) {
1479 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1480 object_unref(OBJECT(&subpage->iomem));
1481 g_free(subpage);
1482 }
1483 }
1484
1485 static void phys_sections_free(PhysPageMap *map)
1486 {
1487 while (map->sections_nb > 0) {
1488 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1489 phys_section_destroy(section->mr);
1490 }
1491 g_free(map->sections);
1492 g_free(map->nodes);
1493 }
1494
1495 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1496 {
1497 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1498 subpage_t *subpage;
1499 hwaddr base = section->offset_within_address_space
1500 & TARGET_PAGE_MASK;
1501 MemoryRegionSection *existing = phys_page_find(d, base);
1502 MemoryRegionSection subsection = {
1503 .offset_within_address_space = base,
1504 .size = int128_make64(TARGET_PAGE_SIZE),
1505 };
1506 hwaddr start, end;
1507
1508 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1509
1510 if (!(existing->mr->subpage)) {
1511 subpage = subpage_init(fv, base);
1512 subsection.fv = fv;
1513 subsection.mr = &subpage->iomem;
1514 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1515 phys_section_add(&d->map, &subsection));
1516 } else {
1517 subpage = container_of(existing->mr, subpage_t, iomem);
1518 }
1519 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1520 end = start + int128_get64(section->size) - 1;
1521 subpage_register(subpage, start, end,
1522 phys_section_add(&d->map, section));
1523 }
1524
1525
1526 static void register_multipage(FlatView *fv,
1527 MemoryRegionSection *section)
1528 {
1529 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1530 hwaddr start_addr = section->offset_within_address_space;
1531 uint16_t section_index = phys_section_add(&d->map, section);
1532 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1533 TARGET_PAGE_BITS));
1534
1535 assert(num_pages);
1536 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1537 }
1538
1539 /*
1540 * The range in *section* may look like this:
1541 *
1542 * |s|PPPPPPP|s|
1543 *
1544 * where s stands for subpage and P for page.
1545 */
1546 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1547 {
1548 MemoryRegionSection remain = *section;
1549 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1550
1551 /* register first subpage */
1552 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1553 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1554 - remain.offset_within_address_space;
1555
1556 MemoryRegionSection now = remain;
1557 now.size = int128_min(int128_make64(left), now.size);
1558 register_subpage(fv, &now);
1559 if (int128_eq(remain.size, now.size)) {
1560 return;
1561 }
1562 remain.size = int128_sub(remain.size, now.size);
1563 remain.offset_within_address_space += int128_get64(now.size);
1564 remain.offset_within_region += int128_get64(now.size);
1565 }
1566
1567 /* register whole pages */
1568 if (int128_ge(remain.size, page_size)) {
1569 MemoryRegionSection now = remain;
1570 now.size = int128_and(now.size, int128_neg(page_size));
1571 register_multipage(fv, &now);
1572 if (int128_eq(remain.size, now.size)) {
1573 return;
1574 }
1575 remain.size = int128_sub(remain.size, now.size);
1576 remain.offset_within_address_space += int128_get64(now.size);
1577 remain.offset_within_region += int128_get64(now.size);
1578 }
1579
1580 /* register last subpage */
1581 register_subpage(fv, &remain);
1582 }
1583
1584 void qemu_flush_coalesced_mmio_buffer(void)
1585 {
1586 if (kvm_enabled())
1587 kvm_flush_coalesced_mmio_buffer();
1588 }
1589
1590 void qemu_mutex_lock_ramlist(void)
1591 {
1592 qemu_mutex_lock(&ram_list.mutex);
1593 }
1594
1595 void qemu_mutex_unlock_ramlist(void)
1596 {
1597 qemu_mutex_unlock(&ram_list.mutex);
1598 }
1599
1600 void ram_block_dump(Monitor *mon)
1601 {
1602 RAMBlock *block;
1603 char *psize;
1604
1605 RCU_READ_LOCK_GUARD();
1606 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1607 "Block Name", "PSize", "Offset", "Used", "Total");
1608 RAMBLOCK_FOREACH(block) {
1609 psize = size_to_str(block->page_size);
1610 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1611 " 0x%016" PRIx64 "\n", block->idstr, psize,
1612 (uint64_t)block->offset,
1613 (uint64_t)block->used_length,
1614 (uint64_t)block->max_length);
1615 g_free(psize);
1616 }
1617 }
1618
1619 #ifdef __linux__
1620 /*
1621 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1622 * may or may not name the same files / on the same filesystem now as
1623 * when we actually open and map them. Iterate over the file
1624 * descriptors instead, and use qemu_fd_getpagesize().
1625 */
1626 static int find_min_backend_pagesize(Object *obj, void *opaque)
1627 {
1628 long *hpsize_min = opaque;
1629
1630 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1631 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1632 long hpsize = host_memory_backend_pagesize(backend);
1633
1634 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1635 *hpsize_min = hpsize;
1636 }
1637 }
1638
1639 return 0;
1640 }
1641
1642 static int find_max_backend_pagesize(Object *obj, void *opaque)
1643 {
1644 long *hpsize_max = opaque;
1645
1646 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1647 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1648 long hpsize = host_memory_backend_pagesize(backend);
1649
1650 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1651 *hpsize_max = hpsize;
1652 }
1653 }
1654
1655 return 0;
1656 }
1657
1658 /*
1659 * TODO: We assume right now that all mapped host memory backends are
1660 * used as RAM, however some might be used for different purposes.
1661 */
1662 long qemu_minrampagesize(void)
1663 {
1664 long hpsize = LONG_MAX;
1665 Object *memdev_root = object_resolve_path("/objects", NULL);
1666
1667 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1668 return hpsize;
1669 }
1670
1671 long qemu_maxrampagesize(void)
1672 {
1673 long pagesize = 0;
1674 Object *memdev_root = object_resolve_path("/objects", NULL);
1675
1676 object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize);
1677 return pagesize;
1678 }
1679 #else
1680 long qemu_minrampagesize(void)
1681 {
1682 return qemu_real_host_page_size;
1683 }
1684 long qemu_maxrampagesize(void)
1685 {
1686 return qemu_real_host_page_size;
1687 }
1688 #endif
1689
1690 #ifdef CONFIG_POSIX
1691 static int64_t get_file_size(int fd)
1692 {
1693 int64_t size;
1694 #if defined(__linux__)
1695 struct stat st;
1696
1697 if (fstat(fd, &st) < 0) {
1698 return -errno;
1699 }
1700
1701 /* Special handling for devdax character devices */
1702 if (S_ISCHR(st.st_mode)) {
1703 g_autofree char *subsystem_path = NULL;
1704 g_autofree char *subsystem = NULL;
1705
1706 subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem",
1707 major(st.st_rdev), minor(st.st_rdev));
1708 subsystem = g_file_read_link(subsystem_path, NULL);
1709
1710 if (subsystem && g_str_has_suffix(subsystem, "/dax")) {
1711 g_autofree char *size_path = NULL;
1712 g_autofree char *size_str = NULL;
1713
1714 size_path = g_strdup_printf("/sys/dev/char/%d:%d/size",
1715 major(st.st_rdev), minor(st.st_rdev));
1716
1717 if (g_file_get_contents(size_path, &size_str, NULL, NULL)) {
1718 return g_ascii_strtoll(size_str, NULL, 0);
1719 }
1720 }
1721 }
1722 #endif /* defined(__linux__) */
1723
1724 /* st.st_size may be zero for special files yet lseek(2) works */
1725 size = lseek(fd, 0, SEEK_END);
1726 if (size < 0) {
1727 return -errno;
1728 }
1729 return size;
1730 }
1731
1732 static int64_t get_file_align(int fd)
1733 {
1734 int64_t align = -1;
1735 #if defined(__linux__) && defined(CONFIG_LIBDAXCTL)
1736 struct stat st;
1737
1738 if (fstat(fd, &st) < 0) {
1739 return -errno;
1740 }
1741
1742 /* Special handling for devdax character devices */
1743 if (S_ISCHR(st.st_mode)) {
1744 g_autofree char *path = NULL;
1745 g_autofree char *rpath = NULL;
1746 struct daxctl_ctx *ctx;
1747 struct daxctl_region *region;
1748 int rc = 0;
1749
1750 path = g_strdup_printf("/sys/dev/char/%d:%d",
1751 major(st.st_rdev), minor(st.st_rdev));
1752 rpath = realpath(path, NULL);
1753
1754 rc = daxctl_new(&ctx);
1755 if (rc) {
1756 return -1;
1757 }
1758
1759 daxctl_region_foreach(ctx, region) {
1760 if (strstr(rpath, daxctl_region_get_path(region))) {
1761 align = daxctl_region_get_align(region);
1762 break;
1763 }
1764 }
1765 daxctl_unref(ctx);
1766 }
1767 #endif /* defined(__linux__) && defined(CONFIG_LIBDAXCTL) */
1768
1769 return align;
1770 }
1771
1772 static int file_ram_open(const char *path,
1773 const char *region_name,
1774 bool *created,
1775 Error **errp)
1776 {
1777 char *filename;
1778 char *sanitized_name;
1779 char *c;
1780 int fd = -1;
1781
1782 *created = false;
1783 for (;;) {
1784 fd = open(path, O_RDWR);
1785 if (fd >= 0) {
1786 /* @path names an existing file, use it */
1787 break;
1788 }
1789 if (errno == ENOENT) {
1790 /* @path names a file that doesn't exist, create it */
1791 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1792 if (fd >= 0) {
1793 *created = true;
1794 break;
1795 }
1796 } else if (errno == EISDIR) {
1797 /* @path names a directory, create a file there */
1798 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1799 sanitized_name = g_strdup(region_name);
1800 for (c = sanitized_name; *c != '\0'; c++) {
1801 if (*c == '/') {
1802 *c = '_';
1803 }
1804 }
1805
1806 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1807 sanitized_name);
1808 g_free(sanitized_name);
1809
1810 fd = mkstemp(filename);
1811 if (fd >= 0) {
1812 unlink(filename);
1813 g_free(filename);
1814 break;
1815 }
1816 g_free(filename);
1817 }
1818 if (errno != EEXIST && errno != EINTR) {
1819 error_setg_errno(errp, errno,
1820 "can't open backing store %s for guest RAM",
1821 path);
1822 return -1;
1823 }
1824 /*
1825 * Try again on EINTR and EEXIST. The latter happens when
1826 * something else creates the file between our two open().
1827 */
1828 }
1829
1830 return fd;
1831 }
1832
1833 static void *file_ram_alloc(RAMBlock *block,
1834 ram_addr_t memory,
1835 int fd,
1836 bool truncate,
1837 Error **errp)
1838 {
1839 void *area;
1840
1841 block->page_size = qemu_fd_getpagesize(fd);
1842 if (block->mr->align % block->page_size) {
1843 error_setg(errp, "alignment 0x%" PRIx64
1844 " must be multiples of page size 0x%zx",
1845 block->mr->align, block->page_size);
1846 return NULL;
1847 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1848 error_setg(errp, "alignment 0x%" PRIx64
1849 " must be a power of two", block->mr->align);
1850 return NULL;
1851 }
1852 block->mr->align = MAX(block->page_size, block->mr->align);
1853 #if defined(__s390x__)
1854 if (kvm_enabled()) {
1855 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1856 }
1857 #endif
1858
1859 if (memory < block->page_size) {
1860 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1861 "or larger than page size 0x%zx",
1862 memory, block->page_size);
1863 return NULL;
1864 }
1865
1866 memory = ROUND_UP(memory, block->page_size);
1867
1868 /*
1869 * ftruncate is not supported by hugetlbfs in older
1870 * hosts, so don't bother bailing out on errors.
1871 * If anything goes wrong with it under other filesystems,
1872 * mmap will fail.
1873 *
1874 * Do not truncate the non-empty backend file to avoid corrupting
1875 * the existing data in the file. Disabling shrinking is not
1876 * enough. For example, the current vNVDIMM implementation stores
1877 * the guest NVDIMM labels at the end of the backend file. If the
1878 * backend file is later extended, QEMU will not be able to find
1879 * those labels. Therefore, extending the non-empty backend file
1880 * is disabled as well.
1881 */
1882 if (truncate && ftruncate(fd, memory)) {
1883 perror("ftruncate");
1884 }
1885
1886 area = qemu_ram_mmap(fd, memory, block->mr->align,
1887 block->flags & RAM_SHARED, block->flags & RAM_PMEM);
1888 if (area == MAP_FAILED) {
1889 error_setg_errno(errp, errno,
1890 "unable to map backing store for guest RAM");
1891 return NULL;
1892 }
1893
1894 block->fd = fd;
1895 return area;
1896 }
1897 #endif
1898
1899 /* Allocate space within the ram_addr_t space that governs the
1900 * dirty bitmaps.
1901 * Called with the ramlist lock held.
1902 */
1903 static ram_addr_t find_ram_offset(ram_addr_t size)
1904 {
1905 RAMBlock *block, *next_block;
1906 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1907
1908 assert(size != 0); /* it would hand out same offset multiple times */
1909
1910 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1911 return 0;
1912 }
1913
1914 RAMBLOCK_FOREACH(block) {
1915 ram_addr_t candidate, next = RAM_ADDR_MAX;
1916
1917 /* Align blocks to start on a 'long' in the bitmap
1918 * which makes the bitmap sync'ing take the fast path.
1919 */
1920 candidate = block->offset + block->max_length;
1921 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1922
1923 /* Search for the closest following block
1924 * and find the gap.
1925 */
1926 RAMBLOCK_FOREACH(next_block) {
1927 if (next_block->offset >= candidate) {
1928 next = MIN(next, next_block->offset);
1929 }
1930 }
1931
1932 /* If it fits remember our place and remember the size
1933 * of gap, but keep going so that we might find a smaller
1934 * gap to fill so avoiding fragmentation.
1935 */
1936 if (next - candidate >= size && next - candidate < mingap) {
1937 offset = candidate;
1938 mingap = next - candidate;
1939 }
1940
1941 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1942 }
1943
1944 if (offset == RAM_ADDR_MAX) {
1945 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1946 (uint64_t)size);
1947 abort();
1948 }
1949
1950 trace_find_ram_offset(size, offset);
1951
1952 return offset;
1953 }
1954
1955 static unsigned long last_ram_page(void)
1956 {
1957 RAMBlock *block;
1958 ram_addr_t last = 0;
1959
1960 RCU_READ_LOCK_GUARD();
1961 RAMBLOCK_FOREACH(block) {
1962 last = MAX(last, block->offset + block->max_length);
1963 }
1964 return last >> TARGET_PAGE_BITS;
1965 }
1966
1967 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1968 {
1969 int ret;
1970
1971 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1972 if (!machine_dump_guest_core(current_machine)) {
1973 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1974 if (ret) {
1975 perror("qemu_madvise");
1976 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1977 "but dump_guest_core=off specified\n");
1978 }
1979 }
1980 }
1981
1982 const char *qemu_ram_get_idstr(RAMBlock *rb)
1983 {
1984 return rb->idstr;
1985 }
1986
1987 void *qemu_ram_get_host_addr(RAMBlock *rb)
1988 {
1989 return rb->host;
1990 }
1991
1992 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
1993 {
1994 return rb->offset;
1995 }
1996
1997 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
1998 {
1999 return rb->used_length;
2000 }
2001
2002 bool qemu_ram_is_shared(RAMBlock *rb)
2003 {
2004 return rb->flags & RAM_SHARED;
2005 }
2006
2007 /* Note: Only set at the start of postcopy */
2008 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
2009 {
2010 return rb->flags & RAM_UF_ZEROPAGE;
2011 }
2012
2013 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
2014 {
2015 rb->flags |= RAM_UF_ZEROPAGE;
2016 }
2017
2018 bool qemu_ram_is_migratable(RAMBlock *rb)
2019 {
2020 return rb->flags & RAM_MIGRATABLE;
2021 }
2022
2023 void qemu_ram_set_migratable(RAMBlock *rb)
2024 {
2025 rb->flags |= RAM_MIGRATABLE;
2026 }
2027
2028 void qemu_ram_unset_migratable(RAMBlock *rb)
2029 {
2030 rb->flags &= ~RAM_MIGRATABLE;
2031 }
2032
2033 /* Called with iothread lock held. */
2034 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2035 {
2036 RAMBlock *block;
2037
2038 assert(new_block);
2039 assert(!new_block->idstr[0]);
2040
2041 if (dev) {
2042 char *id = qdev_get_dev_path(dev);
2043 if (id) {
2044 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2045 g_free(id);
2046 }
2047 }
2048 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2049
2050 RCU_READ_LOCK_GUARD();
2051 RAMBLOCK_FOREACH(block) {
2052 if (block != new_block &&
2053 !strcmp(block->idstr, new_block->idstr)) {
2054 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2055 new_block->idstr);
2056 abort();
2057 }
2058 }
2059 }
2060
2061 /* Called with iothread lock held. */
2062 void qemu_ram_unset_idstr(RAMBlock *block)
2063 {
2064 /* FIXME: arch_init.c assumes that this is not called throughout
2065 * migration. Ignore the problem since hot-unplug during migration
2066 * does not work anyway.
2067 */
2068 if (block) {
2069 memset(block->idstr, 0, sizeof(block->idstr));
2070 }
2071 }
2072
2073 size_t qemu_ram_pagesize(RAMBlock *rb)
2074 {
2075 return rb->page_size;
2076 }
2077
2078 /* Returns the largest size of page in use */
2079 size_t qemu_ram_pagesize_largest(void)
2080 {
2081 RAMBlock *block;
2082 size_t largest = 0;
2083
2084 RAMBLOCK_FOREACH(block) {
2085 largest = MAX(largest, qemu_ram_pagesize(block));
2086 }
2087
2088 return largest;
2089 }
2090
2091 static int memory_try_enable_merging(void *addr, size_t len)
2092 {
2093 if (!machine_mem_merge(current_machine)) {
2094 /* disabled by the user */
2095 return 0;
2096 }
2097
2098 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2099 }
2100
2101 /* Only legal before guest might have detected the memory size: e.g. on
2102 * incoming migration, or right after reset.
2103 *
2104 * As memory core doesn't know how is memory accessed, it is up to
2105 * resize callback to update device state and/or add assertions to detect
2106 * misuse, if necessary.
2107 */
2108 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2109 {
2110 const ram_addr_t unaligned_size = newsize;
2111
2112 assert(block);
2113
2114 newsize = HOST_PAGE_ALIGN(newsize);
2115
2116 if (block->used_length == newsize) {
2117 /*
2118 * We don't have to resize the ram block (which only knows aligned
2119 * sizes), however, we have to notify if the unaligned size changed.
2120 */
2121 if (unaligned_size != memory_region_size(block->mr)) {
2122 memory_region_set_size(block->mr, unaligned_size);
2123 if (block->resized) {
2124 block->resized(block->idstr, unaligned_size, block->host);
2125 }
2126 }
2127 return 0;
2128 }
2129
2130 if (!(block->flags & RAM_RESIZEABLE)) {
2131 error_setg_errno(errp, EINVAL,
2132 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2133 " in != 0x" RAM_ADDR_FMT, block->idstr,
2134 newsize, block->used_length);
2135 return -EINVAL;
2136 }
2137
2138 if (block->max_length < newsize) {
2139 error_setg_errno(errp, EINVAL,
2140 "Length too large: %s: 0x" RAM_ADDR_FMT
2141 " > 0x" RAM_ADDR_FMT, block->idstr,
2142 newsize, block->max_length);
2143 return -EINVAL;
2144 }
2145
2146 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2147 block->used_length = newsize;
2148 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2149 DIRTY_CLIENTS_ALL);
2150 memory_region_set_size(block->mr, unaligned_size);
2151 if (block->resized) {
2152 block->resized(block->idstr, unaligned_size, block->host);
2153 }
2154 return 0;
2155 }
2156
2157 /*
2158 * Trigger sync on the given ram block for range [start, start + length]
2159 * with the backing store if one is available.
2160 * Otherwise no-op.
2161 * @Note: this is supposed to be a synchronous op.
2162 */
2163 void qemu_ram_msync(RAMBlock *block, ram_addr_t start, ram_addr_t length)
2164 {
2165 /* The requested range should fit in within the block range */
2166 g_assert((start + length) <= block->used_length);
2167
2168 #ifdef CONFIG_LIBPMEM
2169 /* The lack of support for pmem should not block the sync */
2170 if (ramblock_is_pmem(block)) {
2171 void *addr = ramblock_ptr(block, start);
2172 pmem_persist(addr, length);
2173 return;
2174 }
2175 #endif
2176 if (block->fd >= 0) {
2177 /**
2178 * Case there is no support for PMEM or the memory has not been
2179 * specified as persistent (or is not one) - use the msync.
2180 * Less optimal but still achieves the same goal
2181 */
2182 void *addr = ramblock_ptr(block, start);
2183 if (qemu_msync(addr, length, block->fd)) {
2184 warn_report("%s: failed to sync memory range: start: "
2185 RAM_ADDR_FMT " length: " RAM_ADDR_FMT,
2186 __func__, start, length);
2187 }
2188 }
2189 }
2190
2191 /* Called with ram_list.mutex held */
2192 static void dirty_memory_extend(ram_addr_t old_ram_size,
2193 ram_addr_t new_ram_size)
2194 {
2195 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2196 DIRTY_MEMORY_BLOCK_SIZE);
2197 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2198 DIRTY_MEMORY_BLOCK_SIZE);
2199 int i;
2200
2201 /* Only need to extend if block count increased */
2202 if (new_num_blocks <= old_num_blocks) {
2203 return;
2204 }
2205
2206 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2207 DirtyMemoryBlocks *old_blocks;
2208 DirtyMemoryBlocks *new_blocks;
2209 int j;
2210
2211 old_blocks = qatomic_rcu_read(&ram_list.dirty_memory[i]);
2212 new_blocks = g_malloc(sizeof(*new_blocks) +
2213 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2214
2215 if (old_num_blocks) {
2216 memcpy(new_blocks->blocks, old_blocks->blocks,
2217 old_num_blocks * sizeof(old_blocks->blocks[0]));
2218 }
2219
2220 for (j = old_num_blocks; j < new_num_blocks; j++) {
2221 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2222 }
2223
2224 qatomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2225
2226 if (old_blocks) {
2227 g_free_rcu(old_blocks, rcu);
2228 }
2229 }
2230 }
2231
2232 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2233 {
2234 RAMBlock *block;
2235 RAMBlock *last_block = NULL;
2236 ram_addr_t old_ram_size, new_ram_size;
2237 Error *err = NULL;
2238
2239 old_ram_size = last_ram_page();
2240
2241 qemu_mutex_lock_ramlist();
2242 new_block->offset = find_ram_offset(new_block->max_length);
2243
2244 if (!new_block->host) {
2245 if (xen_enabled()) {
2246 xen_ram_alloc(new_block->offset, new_block->max_length,
2247 new_block->mr, &err);
2248 if (err) {
2249 error_propagate(errp, err);
2250 qemu_mutex_unlock_ramlist();
2251 return;
2252 }
2253 } else {
2254 new_block->host = phys_mem_alloc(new_block->max_length,
2255 &new_block->mr->align, shared);
2256 if (!new_block->host) {
2257 error_setg_errno(errp, errno,
2258 "cannot set up guest memory '%s'",
2259 memory_region_name(new_block->mr));
2260 qemu_mutex_unlock_ramlist();
2261 return;
2262 }
2263 memory_try_enable_merging(new_block->host, new_block->max_length);
2264 }
2265 }
2266
2267 new_ram_size = MAX(old_ram_size,
2268 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2269 if (new_ram_size > old_ram_size) {
2270 dirty_memory_extend(old_ram_size, new_ram_size);
2271 }
2272 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2273 * QLIST (which has an RCU-friendly variant) does not have insertion at
2274 * tail, so save the last element in last_block.
2275 */
2276 RAMBLOCK_FOREACH(block) {
2277 last_block = block;
2278 if (block->max_length < new_block->max_length) {
2279 break;
2280 }
2281 }
2282 if (block) {
2283 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2284 } else if (last_block) {
2285 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2286 } else { /* list is empty */
2287 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2288 }
2289 ram_list.mru_block = NULL;
2290
2291 /* Write list before version */
2292 smp_wmb();
2293 ram_list.version++;
2294 qemu_mutex_unlock_ramlist();
2295
2296 cpu_physical_memory_set_dirty_range(new_block->offset,
2297 new_block->used_length,
2298 DIRTY_CLIENTS_ALL);
2299
2300 if (new_block->host) {
2301 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2302 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2303 /*
2304 * MADV_DONTFORK is also needed by KVM in absence of synchronous MMU
2305 * Configure it unless the machine is a qtest server, in which case
2306 * KVM is not used and it may be forked (eg for fuzzing purposes).
2307 */
2308 if (!qtest_enabled()) {
2309 qemu_madvise(new_block->host, new_block->max_length,
2310 QEMU_MADV_DONTFORK);
2311 }
2312 ram_block_notify_add(new_block->host, new_block->max_length);
2313 }
2314 }
2315
2316 #ifdef CONFIG_POSIX
2317 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2318 uint32_t ram_flags, int fd,
2319 Error **errp)
2320 {
2321 RAMBlock *new_block;
2322 Error *local_err = NULL;
2323 int64_t file_size, file_align;
2324
2325 /* Just support these ram flags by now. */
2326 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2327
2328 if (xen_enabled()) {
2329 error_setg(errp, "-mem-path not supported with Xen");
2330 return NULL;
2331 }
2332
2333 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2334 error_setg(errp,
2335 "host lacks kvm mmu notifiers, -mem-path unsupported");
2336 return NULL;
2337 }
2338
2339 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2340 /*
2341 * file_ram_alloc() needs to allocate just like
2342 * phys_mem_alloc, but we haven't bothered to provide
2343 * a hook there.
2344 */
2345 error_setg(errp,
2346 "-mem-path not supported with this accelerator");
2347 return NULL;
2348 }
2349
2350 size = HOST_PAGE_ALIGN(size);
2351 file_size = get_file_size(fd);
2352 if (file_size > 0 && file_size < size) {
2353 error_setg(errp, "backing store size 0x%" PRIx64
2354 " does not match 'size' option 0x" RAM_ADDR_FMT,
2355 file_size, size);
2356 return NULL;
2357 }
2358
2359 file_align = get_file_align(fd);
2360 if (file_align > 0 && mr && file_align > mr->align) {
2361 error_setg(errp, "backing store align 0x%" PRIx64
2362 " is larger than 'align' option 0x%" PRIx64,
2363 file_align, mr->align);
2364 return NULL;
2365 }
2366
2367 new_block = g_malloc0(sizeof(*new_block));
2368 new_block->mr = mr;
2369 new_block->used_length = size;
2370 new_block->max_length = size;
2371 new_block->flags = ram_flags;
2372 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2373 if (!new_block->host) {
2374 g_free(new_block);
2375 return NULL;
2376 }
2377
2378 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2379 if (local_err) {
2380 g_free(new_block);
2381 error_propagate(errp, local_err);
2382 return NULL;
2383 }
2384 return new_block;
2385
2386 }
2387
2388
2389 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2390 uint32_t ram_flags, const char *mem_path,
2391 Error **errp)
2392 {
2393 int fd;
2394 bool created;
2395 RAMBlock *block;
2396
2397 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2398 if (fd < 0) {
2399 return NULL;
2400 }
2401
2402 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2403 if (!block) {
2404 if (created) {
2405 unlink(mem_path);
2406 }
2407 close(fd);
2408 return NULL;
2409 }
2410
2411 return block;
2412 }
2413 #endif
2414
2415 static
2416 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2417 void (*resized)(const char*,
2418 uint64_t length,
2419 void *host),
2420 void *host, bool resizeable, bool share,
2421 MemoryRegion *mr, Error **errp)
2422 {
2423 RAMBlock *new_block;
2424 Error *local_err = NULL;
2425
2426 size = HOST_PAGE_ALIGN(size);
2427 max_size = HOST_PAGE_ALIGN(max_size);
2428 new_block = g_malloc0(sizeof(*new_block));
2429 new_block->mr = mr;
2430 new_block->resized = resized;
2431 new_block->used_length = size;
2432 new_block->max_length = max_size;
2433 assert(max_size >= size);
2434 new_block->fd = -1;
2435 new_block->page_size = qemu_real_host_page_size;
2436 new_block->host = host;
2437 if (host) {
2438 new_block->flags |= RAM_PREALLOC;
2439 }
2440 if (resizeable) {
2441 new_block->flags |= RAM_RESIZEABLE;
2442 }
2443 ram_block_add(new_block, &local_err, share);
2444 if (local_err) {
2445 g_free(new_block);
2446 error_propagate(errp, local_err);
2447 return NULL;
2448 }
2449 return new_block;
2450 }
2451
2452 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2453 MemoryRegion *mr, Error **errp)
2454 {
2455 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2456 false, mr, errp);
2457 }
2458
2459 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2460 MemoryRegion *mr, Error **errp)
2461 {
2462 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2463 share, mr, errp);
2464 }
2465
2466 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2467 void (*resized)(const char*,
2468 uint64_t length,
2469 void *host),
2470 MemoryRegion *mr, Error **errp)
2471 {
2472 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2473 false, mr, errp);
2474 }
2475
2476 static void reclaim_ramblock(RAMBlock *block)
2477 {
2478 if (block->flags & RAM_PREALLOC) {
2479 ;
2480 } else if (xen_enabled()) {
2481 xen_invalidate_map_cache_entry(block->host);
2482 #ifndef _WIN32
2483 } else if (block->fd >= 0) {
2484 qemu_ram_munmap(block->fd, block->host, block->max_length);
2485 close(block->fd);
2486 #endif
2487 } else {
2488 qemu_anon_ram_free(block->host, block->max_length);
2489 }
2490 g_free(block);
2491 }
2492
2493 void qemu_ram_free(RAMBlock *block)
2494 {
2495 if (!block) {
2496 return;
2497 }
2498
2499 if (block->host) {
2500 ram_block_notify_remove(block->host, block->max_length);
2501 }
2502
2503 qemu_mutex_lock_ramlist();
2504 QLIST_REMOVE_RCU(block, next);
2505 ram_list.mru_block = NULL;
2506 /* Write list before version */
2507 smp_wmb();
2508 ram_list.version++;
2509 call_rcu(block, reclaim_ramblock, rcu);
2510 qemu_mutex_unlock_ramlist();
2511 }
2512
2513 #ifndef _WIN32
2514 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2515 {
2516 RAMBlock *block;
2517 ram_addr_t offset;
2518 int flags;
2519 void *area, *vaddr;
2520
2521 RAMBLOCK_FOREACH(block) {
2522 offset = addr - block->offset;
2523 if (offset < block->max_length) {
2524 vaddr = ramblock_ptr(block, offset);
2525 if (block->flags & RAM_PREALLOC) {
2526 ;
2527 } else if (xen_enabled()) {
2528 abort();
2529 } else {
2530 flags = MAP_FIXED;
2531 if (block->fd >= 0) {
2532 flags |= (block->flags & RAM_SHARED ?
2533 MAP_SHARED : MAP_PRIVATE);
2534 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2535 flags, block->fd, offset);
2536 } else {
2537 /*
2538 * Remap needs to match alloc. Accelerators that
2539 * set phys_mem_alloc never remap. If they did,
2540 * we'd need a remap hook here.
2541 */
2542 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2543
2544 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2545 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2546 flags, -1, 0);
2547 }
2548 if (area != vaddr) {
2549 error_report("Could not remap addr: "
2550 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2551 length, addr);
2552 exit(1);
2553 }
2554 memory_try_enable_merging(vaddr, length);
2555 qemu_ram_setup_dump(vaddr, length);
2556 }
2557 }
2558 }
2559 }
2560 #endif /* !_WIN32 */
2561
2562 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2563 * This should not be used for general purpose DMA. Use address_space_map
2564 * or address_space_rw instead. For local memory (e.g. video ram) that the
2565 * device owns, use memory_region_get_ram_ptr.
2566 *
2567 * Called within RCU critical section.
2568 */
2569 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2570 {
2571 RAMBlock *block = ram_block;
2572
2573 if (block == NULL) {
2574 block = qemu_get_ram_block(addr);
2575 addr -= block->offset;
2576 }
2577
2578 if (xen_enabled() && block->host == NULL) {
2579 /* We need to check if the requested address is in the RAM
2580 * because we don't want to map the entire memory in QEMU.
2581 * In that case just map until the end of the page.
2582 */
2583 if (block->offset == 0) {
2584 return xen_map_cache(addr, 0, 0, false);
2585 }
2586
2587 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2588 }
2589 return ramblock_ptr(block, addr);
2590 }
2591
2592 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2593 * but takes a size argument.
2594 *
2595 * Called within RCU critical section.
2596 */
2597 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2598 hwaddr *size, bool lock)
2599 {
2600 RAMBlock *block = ram_block;
2601 if (*size == 0) {
2602 return NULL;
2603 }
2604
2605 if (block == NULL) {
2606 block = qemu_get_ram_block(addr);
2607 addr -= block->offset;
2608 }
2609 *size = MIN(*size, block->max_length - addr);
2610
2611 if (xen_enabled() && block->host == NULL) {
2612 /* We need to check if the requested address is in the RAM
2613 * because we don't want to map the entire memory in QEMU.
2614 * In that case just map the requested area.
2615 */
2616 if (block->offset == 0) {
2617 return xen_map_cache(addr, *size, lock, lock);
2618 }
2619
2620 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2621 }
2622
2623 return ramblock_ptr(block, addr);
2624 }
2625
2626 /* Return the offset of a hostpointer within a ramblock */
2627 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2628 {
2629 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2630 assert((uintptr_t)host >= (uintptr_t)rb->host);
2631 assert(res < rb->max_length);
2632
2633 return res;
2634 }
2635
2636 /*
2637 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2638 * in that RAMBlock.
2639 *
2640 * ptr: Host pointer to look up
2641 * round_offset: If true round the result offset down to a page boundary
2642 * *ram_addr: set to result ram_addr
2643 * *offset: set to result offset within the RAMBlock
2644 *
2645 * Returns: RAMBlock (or NULL if not found)
2646 *
2647 * By the time this function returns, the returned pointer is not protected
2648 * by RCU anymore. If the caller is not within an RCU critical section and
2649 * does not hold the iothread lock, it must have other means of protecting the
2650 * pointer, such as a reference to the region that includes the incoming
2651 * ram_addr_t.
2652 */
2653 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2654 ram_addr_t *offset)
2655 {
2656 RAMBlock *block;
2657 uint8_t *host = ptr;
2658
2659 if (xen_enabled()) {
2660 ram_addr_t ram_addr;
2661 RCU_READ_LOCK_GUARD();
2662 ram_addr = xen_ram_addr_from_mapcache(ptr);
2663 block = qemu_get_ram_block(ram_addr);
2664 if (block) {
2665 *offset = ram_addr - block->offset;
2666 }
2667 return block;
2668 }
2669
2670 RCU_READ_LOCK_GUARD();
2671 block = qatomic_rcu_read(&ram_list.mru_block);
2672 if (block && block->host && host - block->host < block->max_length) {
2673 goto found;
2674 }
2675
2676 RAMBLOCK_FOREACH(block) {
2677 /* This case append when the block is not mapped. */
2678 if (block->host == NULL) {
2679 continue;
2680 }
2681 if (host - block->host < block->max_length) {
2682 goto found;
2683 }
2684 }
2685
2686 return NULL;
2687
2688 found:
2689 *offset = (host - block->host);
2690 if (round_offset) {
2691 *offset &= TARGET_PAGE_MASK;
2692 }
2693 return block;
2694 }
2695
2696 /*
2697 * Finds the named RAMBlock
2698 *
2699 * name: The name of RAMBlock to find
2700 *
2701 * Returns: RAMBlock (or NULL if not found)
2702 */
2703 RAMBlock *qemu_ram_block_by_name(const char *name)
2704 {
2705 RAMBlock *block;
2706
2707 RAMBLOCK_FOREACH(block) {
2708 if (!strcmp(name, block->idstr)) {
2709 return block;
2710 }
2711 }
2712
2713 return NULL;
2714 }
2715
2716 /* Some of the softmmu routines need to translate from a host pointer
2717 (typically a TLB entry) back to a ram offset. */
2718 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2719 {
2720 RAMBlock *block;
2721 ram_addr_t offset;
2722
2723 block = qemu_ram_block_from_host(ptr, false, &offset);
2724 if (!block) {
2725 return RAM_ADDR_INVALID;
2726 }
2727
2728 return block->offset + offset;
2729 }
2730
2731 /* Generate a debug exception if a watchpoint has been hit. */
2732 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
2733 MemTxAttrs attrs, int flags, uintptr_t ra)
2734 {
2735 CPUClass *cc = CPU_GET_CLASS(cpu);
2736 CPUWatchpoint *wp;
2737
2738 assert(tcg_enabled());
2739 if (cpu->watchpoint_hit) {
2740 /*
2741 * We re-entered the check after replacing the TB.
2742 * Now raise the debug interrupt so that it will
2743 * trigger after the current instruction.
2744 */
2745 qemu_mutex_lock_iothread();
2746 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2747 qemu_mutex_unlock_iothread();
2748 return;
2749 }
2750
2751 addr = cc->adjust_watchpoint_address(cpu, addr, len);
2752 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2753 if (watchpoint_address_matches(wp, addr, len)
2754 && (wp->flags & flags)) {
2755 if (flags == BP_MEM_READ) {
2756 wp->flags |= BP_WATCHPOINT_HIT_READ;
2757 } else {
2758 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2759 }
2760 wp->hitaddr = MAX(addr, wp->vaddr);
2761 wp->hitattrs = attrs;
2762 if (!cpu->watchpoint_hit) {
2763 if (wp->flags & BP_CPU &&
2764 !cc->debug_check_watchpoint(cpu, wp)) {
2765 wp->flags &= ~BP_WATCHPOINT_HIT;
2766 continue;
2767 }
2768 cpu->watchpoint_hit = wp;
2769
2770 mmap_lock();
2771 tb_check_watchpoint(cpu, ra);
2772 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2773 cpu->exception_index = EXCP_DEBUG;
2774 mmap_unlock();
2775 cpu_loop_exit_restore(cpu, ra);
2776 } else {
2777 /* Force execution of one insn next time. */
2778 cpu->cflags_next_tb = 1 | curr_cflags();
2779 mmap_unlock();
2780 if (ra) {
2781 cpu_restore_state(cpu, ra, true);
2782 }
2783 cpu_loop_exit_noexc(cpu);
2784 }
2785 }
2786 } else {
2787 wp->flags &= ~BP_WATCHPOINT_HIT;
2788 }
2789 }
2790 }
2791
2792 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2793 MemTxAttrs attrs, void *buf, hwaddr len);
2794 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2795 const void *buf, hwaddr len);
2796 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2797 bool is_write, MemTxAttrs attrs);
2798
2799 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2800 unsigned len, MemTxAttrs attrs)
2801 {
2802 subpage_t *subpage = opaque;
2803 uint8_t buf[8];
2804 MemTxResult res;
2805
2806 #if defined(DEBUG_SUBPAGE)
2807 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2808 subpage, len, addr);
2809 #endif
2810 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2811 if (res) {
2812 return res;
2813 }
2814 *data = ldn_p(buf, len);
2815 return MEMTX_OK;
2816 }
2817
2818 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2819 uint64_t value, unsigned len, MemTxAttrs attrs)
2820 {
2821 subpage_t *subpage = opaque;
2822 uint8_t buf[8];
2823
2824 #if defined(DEBUG_SUBPAGE)
2825 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2826 " value %"PRIx64"\n",
2827 __func__, subpage, len, addr, value);
2828 #endif
2829 stn_p(buf, len, value);
2830 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2831 }
2832
2833 static bool subpage_accepts(void *opaque, hwaddr addr,
2834 unsigned len, bool is_write,
2835 MemTxAttrs attrs)
2836 {
2837 subpage_t *subpage = opaque;
2838 #if defined(DEBUG_SUBPAGE)
2839 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2840 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2841 #endif
2842
2843 return flatview_access_valid(subpage->fv, addr + subpage->base,
2844 len, is_write, attrs);
2845 }
2846
2847 static const MemoryRegionOps subpage_ops = {
2848 .read_with_attrs = subpage_read,
2849 .write_with_attrs = subpage_write,
2850 .impl.min_access_size = 1,
2851 .impl.max_access_size = 8,
2852 .valid.min_access_size = 1,
2853 .valid.max_access_size = 8,
2854 .valid.accepts = subpage_accepts,
2855 .endianness = DEVICE_NATIVE_ENDIAN,
2856 };
2857
2858 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
2859 uint16_t section)
2860 {
2861 int idx, eidx;
2862
2863 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2864 return -1;
2865 idx = SUBPAGE_IDX(start);
2866 eidx = SUBPAGE_IDX(end);
2867 #if defined(DEBUG_SUBPAGE)
2868 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2869 __func__, mmio, start, end, idx, eidx, section);
2870 #endif
2871 for (; idx <= eidx; idx++) {
2872 mmio->sub_section[idx] = section;
2873 }
2874
2875 return 0;
2876 }
2877
2878 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2879 {
2880 subpage_t *mmio;
2881
2882 /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */
2883 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2884 mmio->fv = fv;
2885 mmio->base = base;
2886 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2887 NULL, TARGET_PAGE_SIZE);
2888 mmio->iomem.subpage = true;
2889 #if defined(DEBUG_SUBPAGE)
2890 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2891 mmio, base, TARGET_PAGE_SIZE);
2892 #endif
2893
2894 return mmio;
2895 }
2896
2897 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2898 {
2899 assert(fv);
2900 MemoryRegionSection section = {
2901 .fv = fv,
2902 .mr = mr,
2903 .offset_within_address_space = 0,
2904 .offset_within_region = 0,
2905 .size = int128_2_64(),
2906 };
2907
2908 return phys_section_add(map, &section);
2909 }
2910
2911 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
2912 hwaddr index, MemTxAttrs attrs)
2913 {
2914 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2915 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2916 AddressSpaceDispatch *d = qatomic_rcu_read(&cpuas->memory_dispatch);
2917 MemoryRegionSection *sections = d->map.sections;
2918
2919 return &sections[index & ~TARGET_PAGE_MASK];
2920 }
2921
2922 static void io_mem_init(void)
2923 {
2924 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2925 NULL, UINT64_MAX);
2926 }
2927
2928 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2929 {
2930 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2931 uint16_t n;
2932
2933 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2934 assert(n == PHYS_SECTION_UNASSIGNED);
2935
2936 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2937
2938 return d;
2939 }
2940
2941 void address_space_dispatch_free(AddressSpaceDispatch *d)
2942 {
2943 phys_sections_free(&d->map);
2944 g_free(d);
2945 }
2946
2947 static void do_nothing(CPUState *cpu, run_on_cpu_data d)
2948 {
2949 }
2950
2951 static void tcg_log_global_after_sync(MemoryListener *listener)
2952 {
2953 CPUAddressSpace *cpuas;
2954
2955 /* Wait for the CPU to end the current TB. This avoids the following
2956 * incorrect race:
2957 *
2958 * vCPU migration
2959 * ---------------------- -------------------------
2960 * TLB check -> slow path
2961 * notdirty_mem_write
2962 * write to RAM
2963 * mark dirty
2964 * clear dirty flag
2965 * TLB check -> fast path
2966 * read memory
2967 * write to RAM
2968 *
2969 * by pushing the migration thread's memory read after the vCPU thread has
2970 * written the memory.
2971 */
2972 if (replay_mode == REPLAY_MODE_NONE) {
2973 /*
2974 * VGA can make calls to this function while updating the screen.
2975 * In record/replay mode this causes a deadlock, because
2976 * run_on_cpu waits for rr mutex. Therefore no races are possible
2977 * in this case and no need for making run_on_cpu when
2978 * record/replay is not enabled.
2979 */
2980 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2981 run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL);
2982 }
2983 }
2984
2985 static void tcg_commit(MemoryListener *listener)
2986 {
2987 CPUAddressSpace *cpuas;
2988 AddressSpaceDispatch *d;
2989
2990 assert(tcg_enabled());
2991 /* since each CPU stores ram addresses in its TLB cache, we must
2992 reset the modified entries */
2993 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2994 cpu_reloading_memory_map();
2995 /* The CPU and TLB are protected by the iothread lock.
2996 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2997 * may have split the RCU critical section.
2998 */
2999 d = address_space_to_dispatch(cpuas->as);
3000 qatomic_rcu_set(&cpuas->memory_dispatch, d);
3001 tlb_flush(cpuas->cpu);
3002 }
3003
3004 static void memory_map_init(void)
3005 {
3006 system_memory = g_malloc(sizeof(*system_memory));
3007
3008 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
3009 address_space_init(&address_space_memory, system_memory, "memory");
3010
3011 system_io = g_malloc(sizeof(*system_io));
3012 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
3013 65536);
3014 address_space_init(&address_space_io, system_io, "I/O");
3015 }
3016
3017 MemoryRegion *get_system_memory(void)
3018 {
3019 return system_memory;
3020 }
3021
3022 MemoryRegion *get_system_io(void)
3023 {
3024 return system_io;
3025 }
3026
3027 #endif /* !defined(CONFIG_USER_ONLY) */
3028
3029 /* physical memory access (slow version, mainly for debug) */
3030 #if defined(CONFIG_USER_ONLY)
3031 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3032 void *ptr, target_ulong len, bool is_write)
3033 {
3034 int flags;
3035 target_ulong l, page;
3036 void * p;
3037 uint8_t *buf = ptr;
3038
3039 while (len > 0) {
3040 page = addr & TARGET_PAGE_MASK;
3041 l = (page + TARGET_PAGE_SIZE) - addr;
3042 if (l > len)
3043 l = len;
3044 flags = page_get_flags(page);
3045 if (!(flags & PAGE_VALID))
3046 return -1;
3047 if (is_write) {
3048 if (!(flags & PAGE_WRITE))
3049 return -1;
3050 /* XXX: this code should not depend on lock_user */
3051 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3052 return -1;
3053 memcpy(p, buf, l);
3054 unlock_user(p, addr, l);
3055 } else {
3056 if (!(flags & PAGE_READ))
3057 return -1;
3058 /* XXX: this code should not depend on lock_user */
3059 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3060 return -1;
3061 memcpy(buf, p, l);
3062 unlock_user(p, addr, 0);
3063 }
3064 len -= l;
3065 buf += l;
3066 addr += l;
3067 }
3068 return 0;
3069 }
3070
3071 #else
3072
3073 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3074 hwaddr length)
3075 {
3076 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3077 addr += memory_region_get_ram_addr(mr);
3078
3079 /* No early return if dirty_log_mask is or becomes 0, because
3080 * cpu_physical_memory_set_dirty_range will still call
3081 * xen_modified_memory.
3082 */
3083 if (dirty_log_mask) {
3084 dirty_log_mask =
3085 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3086 }
3087 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3088 assert(tcg_enabled());
3089 tb_invalidate_phys_range(addr, addr + length);
3090 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3091 }
3092 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3093 }
3094
3095 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3096 {
3097 /*
3098 * In principle this function would work on other memory region types too,
3099 * but the ROM device use case is the only one where this operation is
3100 * necessary. Other memory regions should use the
3101 * address_space_read/write() APIs.
3102 */
3103 assert(memory_region_is_romd(mr));
3104
3105 invalidate_and_set_dirty(mr, addr, size);
3106 }
3107
3108 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3109 {
3110 unsigned access_size_max = mr->ops->valid.max_access_size;
3111
3112 /* Regions are assumed to support 1-4 byte accesses unless
3113 otherwise specified. */
3114 if (access_size_max == 0) {
3115 access_size_max = 4;
3116 }
3117
3118 /* Bound the maximum access by the alignment of the address. */
3119 if (!mr->ops->impl.unaligned) {
3120 unsigned align_size_max = addr & -addr;
3121 if (align_size_max != 0 && align_size_max < access_size_max) {
3122 access_size_max = align_size_max;
3123 }
3124 }
3125
3126 /* Don't attempt accesses larger than the maximum. */
3127 if (l > access_size_max) {
3128 l = access_size_max;
3129 }
3130 l = pow2floor(l);
3131
3132 return l;
3133 }
3134
3135 static bool prepare_mmio_access(MemoryRegion *mr)
3136 {
3137 bool unlocked = !qemu_mutex_iothread_locked();
3138 bool release_lock = false;
3139
3140 if (unlocked) {
3141 qemu_mutex_lock_iothread();
3142 unlocked = false;
3143 release_lock = true;
3144 }
3145 if (mr->flush_coalesced_mmio) {
3146 if (unlocked) {
3147 qemu_mutex_lock_iothread();
3148 }
3149 qemu_flush_coalesced_mmio_buffer();
3150 if (unlocked) {
3151 qemu_mutex_unlock_iothread();
3152 }
3153 }
3154
3155 return release_lock;
3156 }
3157
3158 /* Called within RCU critical section. */
3159 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3160 MemTxAttrs attrs,
3161 const void *ptr,
3162 hwaddr len, hwaddr addr1,
3163 hwaddr l, MemoryRegion *mr)
3164 {
3165 uint8_t *ram_ptr;
3166 uint64_t val;
3167 MemTxResult result = MEMTX_OK;
3168 bool release_lock = false;
3169 const uint8_t *buf = ptr;
3170
3171 for (;;) {
3172 if (!memory_access_is_direct(mr, true)) {
3173 release_lock |= prepare_mmio_access(mr);
3174 l = memory_access_size(mr, l, addr1);
3175 /* XXX: could force current_cpu to NULL to avoid
3176 potential bugs */
3177 val = ldn_he_p(buf, l);
3178 result |= memory_region_dispatch_write(mr, addr1, val,
3179 size_memop(l), attrs);
3180 } else {
3181 /* RAM case */
3182 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3183 memcpy(ram_ptr, buf, l);
3184 invalidate_and_set_dirty(mr, addr1, l);
3185 }
3186
3187 if (release_lock) {
3188 qemu_mutex_unlock_iothread();
3189 release_lock = false;
3190 }
3191
3192 len -= l;
3193 buf += l;
3194 addr += l;
3195
3196 if (!len) {
3197 break;
3198 }
3199
3200 l = len;
3201 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3202 }
3203
3204 return result;
3205 }
3206
3207 /* Called from RCU critical section. */
3208 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3209 const void *buf, hwaddr len)
3210 {
3211 hwaddr l;
3212 hwaddr addr1;
3213 MemoryRegion *mr;
3214 MemTxResult result = MEMTX_OK;
3215
3216 l = len;
3217 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3218 result = flatview_write_continue(fv, addr, attrs, buf, len,
3219 addr1, l, mr);
3220
3221 return result;
3222 }
3223
3224 /* Called within RCU critical section. */
3225 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3226 MemTxAttrs attrs, void *ptr,
3227 hwaddr len, hwaddr addr1, hwaddr l,
3228 MemoryRegion *mr)
3229 {
3230 uint8_t *ram_ptr;
3231 uint64_t val;
3232 MemTxResult result = MEMTX_OK;
3233 bool release_lock = false;
3234 uint8_t *buf = ptr;
3235
3236 for (;;) {
3237 if (!memory_access_is_direct(mr, false)) {
3238 /* I/O case */
3239 release_lock |= prepare_mmio_access(mr);
3240 l = memory_access_size(mr, l, addr1);
3241 result |= memory_region_dispatch_read(mr, addr1, &val,
3242 size_memop(l), attrs);
3243 stn_he_p(buf, l, val);
3244 } else {
3245 /* RAM case */
3246 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3247 memcpy(buf, ram_ptr, l);
3248 }
3249
3250 if (release_lock) {
3251 qemu_mutex_unlock_iothread();
3252 release_lock = false;
3253 }
3254
3255 len -= l;
3256 buf += l;
3257 addr += l;
3258
3259 if (!len) {
3260 break;
3261 }
3262
3263 l = len;
3264 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3265 }
3266
3267 return result;
3268 }
3269
3270 /* Called from RCU critical section. */
3271 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3272 MemTxAttrs attrs, void *buf, hwaddr len)
3273 {
3274 hwaddr l;
3275 hwaddr addr1;
3276 MemoryRegion *mr;
3277
3278 l = len;
3279 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3280 return flatview_read_continue(fv, addr, attrs, buf, len,
3281 addr1, l, mr);
3282 }
3283
3284 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3285 MemTxAttrs attrs, void *buf, hwaddr len)
3286 {
3287 MemTxResult result = MEMTX_OK;
3288 FlatView *fv;
3289
3290 if (len > 0) {
3291 RCU_READ_LOCK_GUARD();
3292 fv = address_space_to_flatview(as);
3293 result = flatview_read(fv, addr, attrs, buf, len);
3294 }
3295
3296 return result;
3297 }
3298
3299 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3300 MemTxAttrs attrs,
3301 const void *buf, hwaddr len)
3302 {
3303 MemTxResult result = MEMTX_OK;
3304 FlatView *fv;
3305
3306 if (len > 0) {
3307 RCU_READ_LOCK_GUARD();
3308 fv = address_space_to_flatview(as);
3309 result = flatview_write(fv, addr, attrs, buf, len);
3310 }
3311
3312 return result;
3313 }
3314
3315 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3316 void *buf, hwaddr len, bool is_write)
3317 {
3318 if (is_write) {
3319 return address_space_write(as, addr, attrs, buf, len);
3320 } else {
3321 return address_space_read_full(as, addr, attrs, buf, len);
3322 }
3323 }
3324
3325 void cpu_physical_memory_rw(hwaddr addr, void *buf,
3326 hwaddr len, bool is_write)
3327 {
3328 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3329 buf, len, is_write);
3330 }
3331
3332 enum write_rom_type {
3333 WRITE_DATA,
3334 FLUSH_CACHE,
3335 };
3336
3337 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3338 hwaddr addr,
3339 MemTxAttrs attrs,
3340 const void *ptr,
3341 hwaddr len,
3342 enum write_rom_type type)
3343 {
3344 hwaddr l;
3345 uint8_t *ram_ptr;
3346 hwaddr addr1;
3347 MemoryRegion *mr;
3348 const uint8_t *buf = ptr;
3349
3350 RCU_READ_LOCK_GUARD();
3351 while (len > 0) {
3352 l = len;
3353 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3354
3355 if (!(memory_region_is_ram(mr) ||
3356 memory_region_is_romd(mr))) {
3357 l = memory_access_size(mr, l, addr1);
3358 } else {
3359 /* ROM/RAM case */
3360 ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3361 switch (type) {
3362 case WRITE_DATA:
3363 memcpy(ram_ptr, buf, l);
3364 invalidate_and_set_dirty(mr, addr1, l);
3365 break;
3366 case FLUSH_CACHE:
3367 flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l);
3368 break;
3369 }
3370 }
3371 len -= l;
3372 buf += l;
3373 addr += l;
3374 }
3375 return MEMTX_OK;
3376 }
3377
3378 /* used for ROM loading : can write in RAM and ROM */
3379 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3380 MemTxAttrs attrs,
3381 const void *buf, hwaddr len)
3382 {
3383 return address_space_write_rom_internal(as, addr, attrs,
3384 buf, len, WRITE_DATA);
3385 }
3386
3387 void cpu_flush_icache_range(hwaddr start, hwaddr len)
3388 {
3389 /*
3390 * This function should do the same thing as an icache flush that was
3391 * triggered from within the guest. For TCG we are always cache coherent,
3392 * so there is no need to flush anything. For KVM / Xen we need to flush
3393 * the host's instruction cache at least.
3394 */
3395 if (tcg_enabled()) {
3396 return;
3397 }
3398
3399 address_space_write_rom_internal(&address_space_memory,
3400 start, MEMTXATTRS_UNSPECIFIED,
3401 NULL, len, FLUSH_CACHE);
3402 }
3403
3404 typedef struct {
3405 MemoryRegion *mr;
3406 void *buffer;
3407 hwaddr addr;
3408 hwaddr len;
3409 bool in_use;
3410 } BounceBuffer;
3411
3412 static BounceBuffer bounce;
3413
3414 typedef struct MapClient {
3415 QEMUBH *bh;
3416 QLIST_ENTRY(MapClient) link;
3417 } MapClient;
3418
3419 QemuMutex map_client_list_lock;
3420 static QLIST_HEAD(, MapClient) map_client_list
3421 = QLIST_HEAD_INITIALIZER(map_client_list);
3422
3423 static void cpu_unregister_map_client_do(MapClient *client)
3424 {
3425 QLIST_REMOVE(client, link);
3426 g_free(client);
3427 }
3428
3429 static void cpu_notify_map_clients_locked(void)
3430 {
3431 MapClient *client;
3432
3433 while (!QLIST_EMPTY(&map_client_list)) {
3434 client = QLIST_FIRST(&map_client_list);
3435 qemu_bh_schedule(client->bh);
3436 cpu_unregister_map_client_do(client);
3437 }
3438 }
3439
3440 void cpu_register_map_client(QEMUBH *bh)
3441 {
3442 MapClient *client = g_malloc(sizeof(*client));
3443
3444 qemu_mutex_lock(&map_client_list_lock);
3445 client->bh = bh;
3446 QLIST_INSERT_HEAD(&map_client_list, client, link);
3447 if (!qatomic_read(&bounce.in_use)) {
3448 cpu_notify_map_clients_locked();
3449 }
3450 qemu_mutex_unlock(&map_client_list_lock);
3451 }
3452
3453 void cpu_exec_init_all(void)
3454 {
3455 qemu_mutex_init(&ram_list.mutex);
3456 /* The data structures we set up here depend on knowing the page size,
3457 * so no more changes can be made after this point.
3458 * In an ideal world, nothing we did before we had finished the
3459 * machine setup would care about the target page size, and we could
3460 * do this much later, rather than requiring board models to state
3461 * up front what their requirements are.
3462 */
3463 finalize_target_page_bits();
3464 io_mem_init();
3465 memory_map_init();
3466 qemu_mutex_init(&map_client_list_lock);
3467 }
3468
3469 void cpu_unregister_map_client(QEMUBH *bh)
3470 {
3471 MapClient *client;
3472
3473 qemu_mutex_lock(&map_client_list_lock);
3474 QLIST_FOREACH(client, &map_client_list, link) {
3475 if (client->bh == bh) {
3476 cpu_unregister_map_client_do(client);
3477 break;
3478 }
3479 }
3480 qemu_mutex_unlock(&map_client_list_lock);
3481 }
3482
3483 static void cpu_notify_map_clients(void)
3484 {
3485 qemu_mutex_lock(&map_client_list_lock);
3486 cpu_notify_map_clients_locked();
3487 qemu_mutex_unlock(&map_client_list_lock);
3488 }
3489
3490 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
3491 bool is_write, MemTxAttrs attrs)
3492 {
3493 MemoryRegion *mr;
3494 hwaddr l, xlat;
3495
3496 while (len > 0) {
3497 l = len;
3498 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3499 if (!memory_access_is_direct(mr, is_write)) {
3500 l = memory_access_size(mr, l, addr);
3501 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3502 return false;
3503 }
3504 }
3505
3506 len -= l;
3507 addr += l;
3508 }
3509 return true;
3510 }
3511
3512 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3513 hwaddr len, bool is_write,
3514 MemTxAttrs attrs)
3515 {
3516 FlatView *fv;
3517 bool result;
3518
3519 RCU_READ_LOCK_GUARD();
3520 fv = address_space_to_flatview(as);
3521 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3522 return result;
3523 }
3524
3525 static hwaddr
3526 flatview_extend_translation(FlatView *fv, hwaddr addr,
3527 hwaddr target_len,
3528 MemoryRegion *mr, hwaddr base, hwaddr len,
3529 bool is_write, MemTxAttrs attrs)
3530 {
3531 hwaddr done = 0;
3532 hwaddr xlat;
3533 MemoryRegion *this_mr;
3534
3535 for (;;) {
3536 target_len -= len;
3537 addr += len;
3538 done += len;
3539 if (target_len == 0) {
3540 return done;
3541 }
3542
3543 len = target_len;
3544 this_mr = flatview_translate(fv, addr, &xlat,
3545 &len, is_write, attrs);
3546 if (this_mr != mr || xlat != base + done) {
3547 return done;
3548 }
3549 }
3550 }
3551
3552 /* Map a physical memory region into a host virtual address.
3553 * May map a subset of the requested range, given by and returned in *plen.
3554 * May return NULL if resources needed to perform the mapping are exhausted.
3555 * Use only for reads OR writes - not for read-modify-write operations.
3556 * Use cpu_register_map_client() to know when retrying the map operation is
3557 * likely to succeed.
3558 */
3559 void *address_space_map(AddressSpace *as,
3560 hwaddr addr,
3561 hwaddr *plen,
3562 bool is_write,
3563 MemTxAttrs attrs)
3564 {
3565 hwaddr len = *plen;
3566 hwaddr l, xlat;
3567 MemoryRegion *mr;
3568 void *ptr;
3569 FlatView *fv;
3570
3571 if (len == 0) {
3572 return NULL;
3573 }
3574
3575 l = len;
3576 RCU_READ_LOCK_GUARD();
3577 fv = address_space_to_flatview(as);
3578 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3579
3580 if (!memory_access_is_direct(mr, is_write)) {