i386: Fix pkg_id offset for EPYC cpu models
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
28 #include "tcg/tcg.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
34 #endif
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/qtest.h"
39 #include "qemu/timer.h"
40 #include "qemu/config-file.h"
41 #include "qemu/error-report.h"
42 #include "qemu/qemu-print.h"
43 #if defined(CONFIG_USER_ONLY)
44 #include "qemu.h"
45 #else /* !CONFIG_USER_ONLY */
46 #include "exec/memory.h"
47 #include "exec/ioport.h"
48 #include "sysemu/dma.h"
49 #include "sysemu/hostmem.h"
50 #include "sysemu/hw_accel.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/xen-mapcache.h"
53 #include "trace-root.h"
54
55 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
56 #include <linux/falloc.h>
57 #endif
58
59 #endif
60 #include "qemu/rcu_queue.h"
61 #include "qemu/main-loop.h"
62 #include "translate-all.h"
63 #include "sysemu/replay.h"
64
65 #include "exec/memory-internal.h"
66 #include "exec/ram_addr.h"
67 #include "exec/log.h"
68
69 #include "qemu/pmem.h"
70
71 #include "migration/vmstate.h"
72
73 #include "qemu/range.h"
74 #ifndef _WIN32
75 #include "qemu/mmap-alloc.h"
76 #endif
77
78 #include "monitor/monitor.h"
79
80 //#define DEBUG_SUBPAGE
81
82 #if !defined(CONFIG_USER_ONLY)
83 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
84 * are protected by the ramlist lock.
85 */
86 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
87
88 static MemoryRegion *system_memory;
89 static MemoryRegion *system_io;
90
91 AddressSpace address_space_io;
92 AddressSpace address_space_memory;
93
94 static MemoryRegion io_mem_unassigned;
95 #endif
96
97 CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
98
99 /* current CPU in the current thread. It is only valid inside
100 cpu_exec() */
101 __thread CPUState *current_cpu;
102
103 uintptr_t qemu_host_page_size;
104 intptr_t qemu_host_page_mask;
105
106 #if !defined(CONFIG_USER_ONLY)
107 /* 0 = Do not count executed instructions.
108 1 = Precise instruction counting.
109 2 = Adaptive rate instruction counting. */
110 int use_icount;
111
112 typedef struct PhysPageEntry PhysPageEntry;
113
114 struct PhysPageEntry {
115 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
116 uint32_t skip : 6;
117 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
118 uint32_t ptr : 26;
119 };
120
121 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
122
123 /* Size of the L2 (and L3, etc) page tables. */
124 #define ADDR_SPACE_BITS 64
125
126 #define P_L2_BITS 9
127 #define P_L2_SIZE (1 << P_L2_BITS)
128
129 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
130
131 typedef PhysPageEntry Node[P_L2_SIZE];
132
133 typedef struct PhysPageMap {
134 struct rcu_head rcu;
135
136 unsigned sections_nb;
137 unsigned sections_nb_alloc;
138 unsigned nodes_nb;
139 unsigned nodes_nb_alloc;
140 Node *nodes;
141 MemoryRegionSection *sections;
142 } PhysPageMap;
143
144 struct AddressSpaceDispatch {
145 MemoryRegionSection *mru_section;
146 /* This is a multi-level map on the physical address space.
147 * The bottom level has pointers to MemoryRegionSections.
148 */
149 PhysPageEntry phys_map;
150 PhysPageMap map;
151 };
152
153 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
154 typedef struct subpage_t {
155 MemoryRegion iomem;
156 FlatView *fv;
157 hwaddr base;
158 uint16_t sub_section[];
159 } subpage_t;
160
161 #define PHYS_SECTION_UNASSIGNED 0
162
163 static void io_mem_init(void);
164 static void memory_map_init(void);
165 static void tcg_log_global_after_sync(MemoryListener *listener);
166 static void tcg_commit(MemoryListener *listener);
167
168 /**
169 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
170 * @cpu: the CPU whose AddressSpace this is
171 * @as: the AddressSpace itself
172 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
173 * @tcg_as_listener: listener for tracking changes to the AddressSpace
174 */
175 struct CPUAddressSpace {
176 CPUState *cpu;
177 AddressSpace *as;
178 struct AddressSpaceDispatch *memory_dispatch;
179 MemoryListener tcg_as_listener;
180 };
181
182 struct DirtyBitmapSnapshot {
183 ram_addr_t start;
184 ram_addr_t end;
185 unsigned long dirty[];
186 };
187
188 #endif
189
190 #if !defined(CONFIG_USER_ONLY)
191
192 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
193 {
194 static unsigned alloc_hint = 16;
195 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
196 map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes);
197 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
198 alloc_hint = map->nodes_nb_alloc;
199 }
200 }
201
202 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
203 {
204 unsigned i;
205 uint32_t ret;
206 PhysPageEntry e;
207 PhysPageEntry *p;
208
209 ret = map->nodes_nb++;
210 p = map->nodes[ret];
211 assert(ret != PHYS_MAP_NODE_NIL);
212 assert(ret != map->nodes_nb_alloc);
213
214 e.skip = leaf ? 0 : 1;
215 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
216 for (i = 0; i < P_L2_SIZE; ++i) {
217 memcpy(&p[i], &e, sizeof(e));
218 }
219 return ret;
220 }
221
222 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
223 hwaddr *index, uint64_t *nb, uint16_t leaf,
224 int level)
225 {
226 PhysPageEntry *p;
227 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
228
229 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
230 lp->ptr = phys_map_node_alloc(map, level == 0);
231 }
232 p = map->nodes[lp->ptr];
233 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
234
235 while (*nb && lp < &p[P_L2_SIZE]) {
236 if ((*index & (step - 1)) == 0 && *nb >= step) {
237 lp->skip = 0;
238 lp->ptr = leaf;
239 *index += step;
240 *nb -= step;
241 } else {
242 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
243 }
244 ++lp;
245 }
246 }
247
248 static void phys_page_set(AddressSpaceDispatch *d,
249 hwaddr index, uint64_t nb,
250 uint16_t leaf)
251 {
252 /* Wildly overreserve - it doesn't matter much. */
253 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
254
255 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
256 }
257
258 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
259 * and update our entry so we can skip it and go directly to the destination.
260 */
261 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
262 {
263 unsigned valid_ptr = P_L2_SIZE;
264 int valid = 0;
265 PhysPageEntry *p;
266 int i;
267
268 if (lp->ptr == PHYS_MAP_NODE_NIL) {
269 return;
270 }
271
272 p = nodes[lp->ptr];
273 for (i = 0; i < P_L2_SIZE; i++) {
274 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
275 continue;
276 }
277
278 valid_ptr = i;
279 valid++;
280 if (p[i].skip) {
281 phys_page_compact(&p[i], nodes);
282 }
283 }
284
285 /* We can only compress if there's only one child. */
286 if (valid != 1) {
287 return;
288 }
289
290 assert(valid_ptr < P_L2_SIZE);
291
292 /* Don't compress if it won't fit in the # of bits we have. */
293 if (P_L2_LEVELS >= (1 << 6) &&
294 lp->skip + p[valid_ptr].skip >= (1 << 6)) {
295 return;
296 }
297
298 lp->ptr = p[valid_ptr].ptr;
299 if (!p[valid_ptr].skip) {
300 /* If our only child is a leaf, make this a leaf. */
301 /* By design, we should have made this node a leaf to begin with so we
302 * should never reach here.
303 * But since it's so simple to handle this, let's do it just in case we
304 * change this rule.
305 */
306 lp->skip = 0;
307 } else {
308 lp->skip += p[valid_ptr].skip;
309 }
310 }
311
312 void address_space_dispatch_compact(AddressSpaceDispatch *d)
313 {
314 if (d->phys_map.skip) {
315 phys_page_compact(&d->phys_map, d->map.nodes);
316 }
317 }
318
319 static inline bool section_covers_addr(const MemoryRegionSection *section,
320 hwaddr addr)
321 {
322 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
323 * the section must cover the entire address space.
324 */
325 return int128_gethi(section->size) ||
326 range_covers_byte(section->offset_within_address_space,
327 int128_getlo(section->size), addr);
328 }
329
330 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
331 {
332 PhysPageEntry lp = d->phys_map, *p;
333 Node *nodes = d->map.nodes;
334 MemoryRegionSection *sections = d->map.sections;
335 hwaddr index = addr >> TARGET_PAGE_BITS;
336 int i;
337
338 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
339 if (lp.ptr == PHYS_MAP_NODE_NIL) {
340 return &sections[PHYS_SECTION_UNASSIGNED];
341 }
342 p = nodes[lp.ptr];
343 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
344 }
345
346 if (section_covers_addr(&sections[lp.ptr], addr)) {
347 return &sections[lp.ptr];
348 } else {
349 return &sections[PHYS_SECTION_UNASSIGNED];
350 }
351 }
352
353 /* Called from RCU critical section */
354 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
355 hwaddr addr,
356 bool resolve_subpage)
357 {
358 MemoryRegionSection *section = atomic_read(&d->mru_section);
359 subpage_t *subpage;
360
361 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
362 !section_covers_addr(section, addr)) {
363 section = phys_page_find(d, addr);
364 atomic_set(&d->mru_section, section);
365 }
366 if (resolve_subpage && section->mr->subpage) {
367 subpage = container_of(section->mr, subpage_t, iomem);
368 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
369 }
370 return section;
371 }
372
373 /* Called from RCU critical section */
374 static MemoryRegionSection *
375 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
376 hwaddr *plen, bool resolve_subpage)
377 {
378 MemoryRegionSection *section;
379 MemoryRegion *mr;
380 Int128 diff;
381
382 section = address_space_lookup_region(d, addr, resolve_subpage);
383 /* Compute offset within MemoryRegionSection */
384 addr -= section->offset_within_address_space;
385
386 /* Compute offset within MemoryRegion */
387 *xlat = addr + section->offset_within_region;
388
389 mr = section->mr;
390
391 /* MMIO registers can be expected to perform full-width accesses based only
392 * on their address, without considering adjacent registers that could
393 * decode to completely different MemoryRegions. When such registers
394 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
395 * regions overlap wildly. For this reason we cannot clamp the accesses
396 * here.
397 *
398 * If the length is small (as is the case for address_space_ldl/stl),
399 * everything works fine. If the incoming length is large, however,
400 * the caller really has to do the clamping through memory_access_size.
401 */
402 if (memory_region_is_ram(mr)) {
403 diff = int128_sub(section->size, int128_make64(addr));
404 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
405 }
406 return section;
407 }
408
409 /**
410 * address_space_translate_iommu - translate an address through an IOMMU
411 * memory region and then through the target address space.
412 *
413 * @iommu_mr: the IOMMU memory region that we start the translation from
414 * @addr: the address to be translated through the MMU
415 * @xlat: the translated address offset within the destination memory region.
416 * It cannot be %NULL.
417 * @plen_out: valid read/write length of the translated address. It
418 * cannot be %NULL.
419 * @page_mask_out: page mask for the translated address. This
420 * should only be meaningful for IOMMU translated
421 * addresses, since there may be huge pages that this bit
422 * would tell. It can be %NULL if we don't care about it.
423 * @is_write: whether the translation operation is for write
424 * @is_mmio: whether this can be MMIO, set true if it can
425 * @target_as: the address space targeted by the IOMMU
426 * @attrs: transaction attributes
427 *
428 * This function is called from RCU critical section. It is the common
429 * part of flatview_do_translate and address_space_translate_cached.
430 */
431 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
432 hwaddr *xlat,
433 hwaddr *plen_out,
434 hwaddr *page_mask_out,
435 bool is_write,
436 bool is_mmio,
437 AddressSpace **target_as,
438 MemTxAttrs attrs)
439 {
440 MemoryRegionSection *section;
441 hwaddr page_mask = (hwaddr)-1;
442
443 do {
444 hwaddr addr = *xlat;
445 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
446 int iommu_idx = 0;
447 IOMMUTLBEntry iotlb;
448
449 if (imrc->attrs_to_index) {
450 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
451 }
452
453 iotlb = imrc->translate(iommu_mr, addr, is_write ?
454 IOMMU_WO : IOMMU_RO, iommu_idx);
455
456 if (!(iotlb.perm & (1 << is_write))) {
457 goto unassigned;
458 }
459
460 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
461 | (addr & iotlb.addr_mask));
462 page_mask &= iotlb.addr_mask;
463 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
464 *target_as = iotlb.target_as;
465
466 section = address_space_translate_internal(
467 address_space_to_dispatch(iotlb.target_as), addr, xlat,
468 plen_out, is_mmio);
469
470 iommu_mr = memory_region_get_iommu(section->mr);
471 } while (unlikely(iommu_mr));
472
473 if (page_mask_out) {
474 *page_mask_out = page_mask;
475 }
476 return *section;
477
478 unassigned:
479 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
480 }
481
482 /**
483 * flatview_do_translate - translate an address in FlatView
484 *
485 * @fv: the flat view that we want to translate on
486 * @addr: the address to be translated in above address space
487 * @xlat: the translated address offset within memory region. It
488 * cannot be @NULL.
489 * @plen_out: valid read/write length of the translated address. It
490 * can be @NULL when we don't care about it.
491 * @page_mask_out: page mask for the translated address. This
492 * should only be meaningful for IOMMU translated
493 * addresses, since there may be huge pages that this bit
494 * would tell. It can be @NULL if we don't care about it.
495 * @is_write: whether the translation operation is for write
496 * @is_mmio: whether this can be MMIO, set true if it can
497 * @target_as: the address space targeted by the IOMMU
498 * @attrs: memory transaction attributes
499 *
500 * This function is called from RCU critical section
501 */
502 static MemoryRegionSection flatview_do_translate(FlatView *fv,
503 hwaddr addr,
504 hwaddr *xlat,
505 hwaddr *plen_out,
506 hwaddr *page_mask_out,
507 bool is_write,
508 bool is_mmio,
509 AddressSpace **target_as,
510 MemTxAttrs attrs)
511 {
512 MemoryRegionSection *section;
513 IOMMUMemoryRegion *iommu_mr;
514 hwaddr plen = (hwaddr)(-1);
515
516 if (!plen_out) {
517 plen_out = &plen;
518 }
519
520 section = address_space_translate_internal(
521 flatview_to_dispatch(fv), addr, xlat,
522 plen_out, is_mmio);
523
524 iommu_mr = memory_region_get_iommu(section->mr);
525 if (unlikely(iommu_mr)) {
526 return address_space_translate_iommu(iommu_mr, xlat,
527 plen_out, page_mask_out,
528 is_write, is_mmio,
529 target_as, attrs);
530 }
531 if (page_mask_out) {
532 /* Not behind an IOMMU, use default page size. */
533 *page_mask_out = ~TARGET_PAGE_MASK;
534 }
535
536 return *section;
537 }
538
539 /* Called from RCU critical section */
540 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
541 bool is_write, MemTxAttrs attrs)
542 {
543 MemoryRegionSection section;
544 hwaddr xlat, page_mask;
545
546 /*
547 * This can never be MMIO, and we don't really care about plen,
548 * but page mask.
549 */
550 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
551 NULL, &page_mask, is_write, false, &as,
552 attrs);
553
554 /* Illegal translation */
555 if (section.mr == &io_mem_unassigned) {
556 goto iotlb_fail;
557 }
558
559 /* Convert memory region offset into address space offset */
560 xlat += section.offset_within_address_space -
561 section.offset_within_region;
562
563 return (IOMMUTLBEntry) {
564 .target_as = as,
565 .iova = addr & ~page_mask,
566 .translated_addr = xlat & ~page_mask,
567 .addr_mask = page_mask,
568 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
569 .perm = IOMMU_RW,
570 };
571
572 iotlb_fail:
573 return (IOMMUTLBEntry) {0};
574 }
575
576 /* Called from RCU critical section */
577 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
578 hwaddr *plen, bool is_write,
579 MemTxAttrs attrs)
580 {
581 MemoryRegion *mr;
582 MemoryRegionSection section;
583 AddressSpace *as = NULL;
584
585 /* This can be MMIO, so setup MMIO bit. */
586 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
587 is_write, true, &as, attrs);
588 mr = section.mr;
589
590 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
591 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
592 *plen = MIN(page, *plen);
593 }
594
595 return mr;
596 }
597
598 typedef struct TCGIOMMUNotifier {
599 IOMMUNotifier n;
600 MemoryRegion *mr;
601 CPUState *cpu;
602 int iommu_idx;
603 bool active;
604 } TCGIOMMUNotifier;
605
606 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
607 {
608 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
609
610 if (!notifier->active) {
611 return;
612 }
613 tlb_flush(notifier->cpu);
614 notifier->active = false;
615 /* We leave the notifier struct on the list to avoid reallocating it later.
616 * Generally the number of IOMMUs a CPU deals with will be small.
617 * In any case we can't unregister the iommu notifier from a notify
618 * callback.
619 */
620 }
621
622 static void tcg_register_iommu_notifier(CPUState *cpu,
623 IOMMUMemoryRegion *iommu_mr,
624 int iommu_idx)
625 {
626 /* Make sure this CPU has an IOMMU notifier registered for this
627 * IOMMU/IOMMU index combination, so that we can flush its TLB
628 * when the IOMMU tells us the mappings we've cached have changed.
629 */
630 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
631 TCGIOMMUNotifier *notifier;
632 Error *err = NULL;
633 int i, ret;
634
635 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
636 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
637 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
638 break;
639 }
640 }
641 if (i == cpu->iommu_notifiers->len) {
642 /* Not found, add a new entry at the end of the array */
643 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
644 notifier = g_new0(TCGIOMMUNotifier, 1);
645 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
646
647 notifier->mr = mr;
648 notifier->iommu_idx = iommu_idx;
649 notifier->cpu = cpu;
650 /* Rather than trying to register interest in the specific part
651 * of the iommu's address space that we've accessed and then
652 * expand it later as subsequent accesses touch more of it, we
653 * just register interest in the whole thing, on the assumption
654 * that iommu reconfiguration will be rare.
655 */
656 iommu_notifier_init(&notifier->n,
657 tcg_iommu_unmap_notify,
658 IOMMU_NOTIFIER_UNMAP,
659 0,
660 HWADDR_MAX,
661 iommu_idx);
662 ret = memory_region_register_iommu_notifier(notifier->mr, &notifier->n,
663 &err);
664 if (ret) {
665 error_report_err(err);
666 exit(1);
667 }
668 }
669
670 if (!notifier->active) {
671 notifier->active = true;
672 }
673 }
674
675 static void tcg_iommu_free_notifier_list(CPUState *cpu)
676 {
677 /* Destroy the CPU's notifier list */
678 int i;
679 TCGIOMMUNotifier *notifier;
680
681 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
682 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
683 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
684 g_free(notifier);
685 }
686 g_array_free(cpu->iommu_notifiers, true);
687 }
688
689 /* Called from RCU critical section */
690 MemoryRegionSection *
691 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
692 hwaddr *xlat, hwaddr *plen,
693 MemTxAttrs attrs, int *prot)
694 {
695 MemoryRegionSection *section;
696 IOMMUMemoryRegion *iommu_mr;
697 IOMMUMemoryRegionClass *imrc;
698 IOMMUTLBEntry iotlb;
699 int iommu_idx;
700 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
701
702 for (;;) {
703 section = address_space_translate_internal(d, addr, &addr, plen, false);
704
705 iommu_mr = memory_region_get_iommu(section->mr);
706 if (!iommu_mr) {
707 break;
708 }
709
710 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
711
712 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
713 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
714 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
715 * doesn't short-cut its translation table walk.
716 */
717 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
718 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
719 | (addr & iotlb.addr_mask));
720 /* Update the caller's prot bits to remove permissions the IOMMU
721 * is giving us a failure response for. If we get down to no
722 * permissions left at all we can give up now.
723 */
724 if (!(iotlb.perm & IOMMU_RO)) {
725 *prot &= ~(PAGE_READ | PAGE_EXEC);
726 }
727 if (!(iotlb.perm & IOMMU_WO)) {
728 *prot &= ~PAGE_WRITE;
729 }
730
731 if (!*prot) {
732 goto translate_fail;
733 }
734
735 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
736 }
737
738 assert(!memory_region_is_iommu(section->mr));
739 *xlat = addr;
740 return section;
741
742 translate_fail:
743 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
744 }
745 #endif
746
747 #if !defined(CONFIG_USER_ONLY)
748
749 static int cpu_common_post_load(void *opaque, int version_id)
750 {
751 CPUState *cpu = opaque;
752
753 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
754 version_id is increased. */
755 cpu->interrupt_request &= ~0x01;
756 tlb_flush(cpu);
757
758 /* loadvm has just updated the content of RAM, bypassing the
759 * usual mechanisms that ensure we flush TBs for writes to
760 * memory we've translated code from. So we must flush all TBs,
761 * which will now be stale.
762 */
763 tb_flush(cpu);
764
765 return 0;
766 }
767
768 static int cpu_common_pre_load(void *opaque)
769 {
770 CPUState *cpu = opaque;
771
772 cpu->exception_index = -1;
773
774 return 0;
775 }
776
777 static bool cpu_common_exception_index_needed(void *opaque)
778 {
779 CPUState *cpu = opaque;
780
781 return tcg_enabled() && cpu->exception_index != -1;
782 }
783
784 static const VMStateDescription vmstate_cpu_common_exception_index = {
785 .name = "cpu_common/exception_index",
786 .version_id = 1,
787 .minimum_version_id = 1,
788 .needed = cpu_common_exception_index_needed,
789 .fields = (VMStateField[]) {
790 VMSTATE_INT32(exception_index, CPUState),
791 VMSTATE_END_OF_LIST()
792 }
793 };
794
795 static bool cpu_common_crash_occurred_needed(void *opaque)
796 {
797 CPUState *cpu = opaque;
798
799 return cpu->crash_occurred;
800 }
801
802 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
803 .name = "cpu_common/crash_occurred",
804 .version_id = 1,
805 .minimum_version_id = 1,
806 .needed = cpu_common_crash_occurred_needed,
807 .fields = (VMStateField[]) {
808 VMSTATE_BOOL(crash_occurred, CPUState),
809 VMSTATE_END_OF_LIST()
810 }
811 };
812
813 const VMStateDescription vmstate_cpu_common = {
814 .name = "cpu_common",
815 .version_id = 1,
816 .minimum_version_id = 1,
817 .pre_load = cpu_common_pre_load,
818 .post_load = cpu_common_post_load,
819 .fields = (VMStateField[]) {
820 VMSTATE_UINT32(halted, CPUState),
821 VMSTATE_UINT32(interrupt_request, CPUState),
822 VMSTATE_END_OF_LIST()
823 },
824 .subsections = (const VMStateDescription*[]) {
825 &vmstate_cpu_common_exception_index,
826 &vmstate_cpu_common_crash_occurred,
827 NULL
828 }
829 };
830
831 #endif
832
833 CPUState *qemu_get_cpu(int index)
834 {
835 CPUState *cpu;
836
837 CPU_FOREACH(cpu) {
838 if (cpu->cpu_index == index) {
839 return cpu;
840 }
841 }
842
843 return NULL;
844 }
845
846 #if !defined(CONFIG_USER_ONLY)
847 void cpu_address_space_init(CPUState *cpu, int asidx,
848 const char *prefix, MemoryRegion *mr)
849 {
850 CPUAddressSpace *newas;
851 AddressSpace *as = g_new0(AddressSpace, 1);
852 char *as_name;
853
854 assert(mr);
855 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
856 address_space_init(as, mr, as_name);
857 g_free(as_name);
858
859 /* Target code should have set num_ases before calling us */
860 assert(asidx < cpu->num_ases);
861
862 if (asidx == 0) {
863 /* address space 0 gets the convenience alias */
864 cpu->as = as;
865 }
866
867 /* KVM cannot currently support multiple address spaces. */
868 assert(asidx == 0 || !kvm_enabled());
869
870 if (!cpu->cpu_ases) {
871 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
872 }
873
874 newas = &cpu->cpu_ases[asidx];
875 newas->cpu = cpu;
876 newas->as = as;
877 if (tcg_enabled()) {
878 newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync;
879 newas->tcg_as_listener.commit = tcg_commit;
880 memory_listener_register(&newas->tcg_as_listener, as);
881 }
882 }
883
884 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
885 {
886 /* Return the AddressSpace corresponding to the specified index */
887 return cpu->cpu_ases[asidx].as;
888 }
889 #endif
890
891 void cpu_exec_unrealizefn(CPUState *cpu)
892 {
893 CPUClass *cc = CPU_GET_CLASS(cpu);
894
895 cpu_list_remove(cpu);
896
897 if (cc->vmsd != NULL) {
898 vmstate_unregister(NULL, cc->vmsd, cpu);
899 }
900 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
901 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
902 }
903 #ifndef CONFIG_USER_ONLY
904 tcg_iommu_free_notifier_list(cpu);
905 #endif
906 }
907
908 Property cpu_common_props[] = {
909 #ifndef CONFIG_USER_ONLY
910 /* Create a memory property for softmmu CPU object,
911 * so users can wire up its memory. (This can't go in hw/core/cpu.c
912 * because that file is compiled only once for both user-mode
913 * and system builds.) The default if no link is set up is to use
914 * the system address space.
915 */
916 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
917 MemoryRegion *),
918 #endif
919 DEFINE_PROP_END_OF_LIST(),
920 };
921
922 void cpu_exec_initfn(CPUState *cpu)
923 {
924 cpu->as = NULL;
925 cpu->num_ases = 0;
926
927 #ifndef CONFIG_USER_ONLY
928 cpu->thread_id = qemu_get_thread_id();
929 cpu->memory = system_memory;
930 object_ref(OBJECT(cpu->memory));
931 #endif
932 }
933
934 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
935 {
936 CPUClass *cc = CPU_GET_CLASS(cpu);
937 static bool tcg_target_initialized;
938
939 cpu_list_add(cpu);
940
941 if (tcg_enabled() && !tcg_target_initialized) {
942 tcg_target_initialized = true;
943 cc->tcg_initialize();
944 }
945 tlb_init(cpu);
946
947 qemu_plugin_vcpu_init_hook(cpu);
948
949 #ifndef CONFIG_USER_ONLY
950 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
951 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
952 }
953 if (cc->vmsd != NULL) {
954 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
955 }
956
957 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
958 #endif
959 }
960
961 const char *parse_cpu_option(const char *cpu_option)
962 {
963 ObjectClass *oc;
964 CPUClass *cc;
965 gchar **model_pieces;
966 const char *cpu_type;
967
968 model_pieces = g_strsplit(cpu_option, ",", 2);
969 if (!model_pieces[0]) {
970 error_report("-cpu option cannot be empty");
971 exit(1);
972 }
973
974 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
975 if (oc == NULL) {
976 error_report("unable to find CPU model '%s'", model_pieces[0]);
977 g_strfreev(model_pieces);
978 exit(EXIT_FAILURE);
979 }
980
981 cpu_type = object_class_get_name(oc);
982 cc = CPU_CLASS(oc);
983 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
984 g_strfreev(model_pieces);
985 return cpu_type;
986 }
987
988 #if defined(CONFIG_USER_ONLY)
989 void tb_invalidate_phys_addr(target_ulong addr)
990 {
991 mmap_lock();
992 tb_invalidate_phys_page_range(addr, addr + 1);
993 mmap_unlock();
994 }
995
996 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
997 {
998 tb_invalidate_phys_addr(pc);
999 }
1000 #else
1001 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
1002 {
1003 ram_addr_t ram_addr;
1004 MemoryRegion *mr;
1005 hwaddr l = 1;
1006
1007 if (!tcg_enabled()) {
1008 return;
1009 }
1010
1011 RCU_READ_LOCK_GUARD();
1012 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
1013 if (!(memory_region_is_ram(mr)
1014 || memory_region_is_romd(mr))) {
1015 return;
1016 }
1017 ram_addr = memory_region_get_ram_addr(mr) + addr;
1018 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
1019 }
1020
1021 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
1022 {
1023 /*
1024 * There may not be a virtual to physical translation for the pc
1025 * right now, but there may exist cached TB for this pc.
1026 * Flush the whole TB cache to force re-translation of such TBs.
1027 * This is heavyweight, but we're debugging anyway.
1028 */
1029 tb_flush(cpu);
1030 }
1031 #endif
1032
1033 #ifndef CONFIG_USER_ONLY
1034 /* Add a watchpoint. */
1035 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1036 int flags, CPUWatchpoint **watchpoint)
1037 {
1038 CPUWatchpoint *wp;
1039
1040 /* forbid ranges which are empty or run off the end of the address space */
1041 if (len == 0 || (addr + len - 1) < addr) {
1042 error_report("tried to set invalid watchpoint at %"
1043 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
1044 return -EINVAL;
1045 }
1046 wp = g_malloc(sizeof(*wp));
1047
1048 wp->vaddr = addr;
1049 wp->len = len;
1050 wp->flags = flags;
1051
1052 /* keep all GDB-injected watchpoints in front */
1053 if (flags & BP_GDB) {
1054 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
1055 } else {
1056 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
1057 }
1058
1059 tlb_flush_page(cpu, addr);
1060
1061 if (watchpoint)
1062 *watchpoint = wp;
1063 return 0;
1064 }
1065
1066 /* Remove a specific watchpoint. */
1067 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
1068 int flags)
1069 {
1070 CPUWatchpoint *wp;
1071
1072 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1073 if (addr == wp->vaddr && len == wp->len
1074 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
1075 cpu_watchpoint_remove_by_ref(cpu, wp);
1076 return 0;
1077 }
1078 }
1079 return -ENOENT;
1080 }
1081
1082 /* Remove a specific watchpoint by reference. */
1083 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
1084 {
1085 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
1086
1087 tlb_flush_page(cpu, watchpoint->vaddr);
1088
1089 g_free(watchpoint);
1090 }
1091
1092 /* Remove all matching watchpoints. */
1093 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1094 {
1095 CPUWatchpoint *wp, *next;
1096
1097 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
1098 if (wp->flags & mask) {
1099 cpu_watchpoint_remove_by_ref(cpu, wp);
1100 }
1101 }
1102 }
1103
1104 /* Return true if this watchpoint address matches the specified
1105 * access (ie the address range covered by the watchpoint overlaps
1106 * partially or completely with the address range covered by the
1107 * access).
1108 */
1109 static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
1110 vaddr addr, vaddr len)
1111 {
1112 /* We know the lengths are non-zero, but a little caution is
1113 * required to avoid errors in the case where the range ends
1114 * exactly at the top of the address space and so addr + len
1115 * wraps round to zero.
1116 */
1117 vaddr wpend = wp->vaddr + wp->len - 1;
1118 vaddr addrend = addr + len - 1;
1119
1120 return !(addr > wpend || wp->vaddr > addrend);
1121 }
1122
1123 /* Return flags for watchpoints that match addr + prot. */
1124 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
1125 {
1126 CPUWatchpoint *wp;
1127 int ret = 0;
1128
1129 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1130 if (watchpoint_address_matches(wp, addr, TARGET_PAGE_SIZE)) {
1131 ret |= wp->flags;
1132 }
1133 }
1134 return ret;
1135 }
1136 #endif /* !CONFIG_USER_ONLY */
1137
1138 /* Add a breakpoint. */
1139 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1140 CPUBreakpoint **breakpoint)
1141 {
1142 CPUBreakpoint *bp;
1143
1144 bp = g_malloc(sizeof(*bp));
1145
1146 bp->pc = pc;
1147 bp->flags = flags;
1148
1149 /* keep all GDB-injected breakpoints in front */
1150 if (flags & BP_GDB) {
1151 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
1152 } else {
1153 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
1154 }
1155
1156 breakpoint_invalidate(cpu, pc);
1157
1158 if (breakpoint) {
1159 *breakpoint = bp;
1160 }
1161 return 0;
1162 }
1163
1164 /* Remove a specific breakpoint. */
1165 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
1166 {
1167 CPUBreakpoint *bp;
1168
1169 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1170 if (bp->pc == pc && bp->flags == flags) {
1171 cpu_breakpoint_remove_by_ref(cpu, bp);
1172 return 0;
1173 }
1174 }
1175 return -ENOENT;
1176 }
1177
1178 /* Remove a specific breakpoint by reference. */
1179 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1180 {
1181 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1182
1183 breakpoint_invalidate(cpu, breakpoint->pc);
1184
1185 g_free(breakpoint);
1186 }
1187
1188 /* Remove all matching breakpoints. */
1189 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1190 {
1191 CPUBreakpoint *bp, *next;
1192
1193 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1194 if (bp->flags & mask) {
1195 cpu_breakpoint_remove_by_ref(cpu, bp);
1196 }
1197 }
1198 }
1199
1200 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1201 CPU loop after each instruction */
1202 void cpu_single_step(CPUState *cpu, int enabled)
1203 {
1204 if (cpu->singlestep_enabled != enabled) {
1205 cpu->singlestep_enabled = enabled;
1206 if (kvm_enabled()) {
1207 kvm_update_guest_debug(cpu, 0);
1208 } else {
1209 /* must flush all the translated code to avoid inconsistencies */
1210 /* XXX: only flush what is necessary */
1211 tb_flush(cpu);
1212 }
1213 }
1214 }
1215
1216 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1217 {
1218 va_list ap;
1219 va_list ap2;
1220
1221 va_start(ap, fmt);
1222 va_copy(ap2, ap);
1223 fprintf(stderr, "qemu: fatal: ");
1224 vfprintf(stderr, fmt, ap);
1225 fprintf(stderr, "\n");
1226 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1227 if (qemu_log_separate()) {
1228 FILE *logfile = qemu_log_lock();
1229 qemu_log("qemu: fatal: ");
1230 qemu_log_vprintf(fmt, ap2);
1231 qemu_log("\n");
1232 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1233 qemu_log_flush();
1234 qemu_log_unlock(logfile);
1235 qemu_log_close();
1236 }
1237 va_end(ap2);
1238 va_end(ap);
1239 replay_finish();
1240 #if defined(CONFIG_USER_ONLY)
1241 {
1242 struct sigaction act;
1243 sigfillset(&act.sa_mask);
1244 act.sa_handler = SIG_DFL;
1245 act.sa_flags = 0;
1246 sigaction(SIGABRT, &act, NULL);
1247 }
1248 #endif
1249 abort();
1250 }
1251
1252 #if !defined(CONFIG_USER_ONLY)
1253 /* Called from RCU critical section */
1254 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1255 {
1256 RAMBlock *block;
1257
1258 block = atomic_rcu_read(&ram_list.mru_block);
1259 if (block && addr - block->offset < block->max_length) {
1260 return block;
1261 }
1262 RAMBLOCK_FOREACH(block) {
1263 if (addr - block->offset < block->max_length) {
1264 goto found;
1265 }
1266 }
1267
1268 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1269 abort();
1270
1271 found:
1272 /* It is safe to write mru_block outside the iothread lock. This
1273 * is what happens:
1274 *
1275 * mru_block = xxx
1276 * rcu_read_unlock()
1277 * xxx removed from list
1278 * rcu_read_lock()
1279 * read mru_block
1280 * mru_block = NULL;
1281 * call_rcu(reclaim_ramblock, xxx);
1282 * rcu_read_unlock()
1283 *
1284 * atomic_rcu_set is not needed here. The block was already published
1285 * when it was placed into the list. Here we're just making an extra
1286 * copy of the pointer.
1287 */
1288 ram_list.mru_block = block;
1289 return block;
1290 }
1291
1292 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1293 {
1294 CPUState *cpu;
1295 ram_addr_t start1;
1296 RAMBlock *block;
1297 ram_addr_t end;
1298
1299 assert(tcg_enabled());
1300 end = TARGET_PAGE_ALIGN(start + length);
1301 start &= TARGET_PAGE_MASK;
1302
1303 RCU_READ_LOCK_GUARD();
1304 block = qemu_get_ram_block(start);
1305 assert(block == qemu_get_ram_block(end - 1));
1306 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1307 CPU_FOREACH(cpu) {
1308 tlb_reset_dirty(cpu, start1, length);
1309 }
1310 }
1311
1312 /* Note: start and end must be within the same ram block. */
1313 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1314 ram_addr_t length,
1315 unsigned client)
1316 {
1317 DirtyMemoryBlocks *blocks;
1318 unsigned long end, page, start_page;
1319 bool dirty = false;
1320 RAMBlock *ramblock;
1321 uint64_t mr_offset, mr_size;
1322
1323 if (length == 0) {
1324 return false;
1325 }
1326
1327 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1328 start_page = start >> TARGET_PAGE_BITS;
1329 page = start_page;
1330
1331 WITH_RCU_READ_LOCK_GUARD() {
1332 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1333 ramblock = qemu_get_ram_block(start);
1334 /* Range sanity check on the ramblock */
1335 assert(start >= ramblock->offset &&
1336 start + length <= ramblock->offset + ramblock->used_length);
1337
1338 while (page < end) {
1339 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1340 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1341 unsigned long num = MIN(end - page,
1342 DIRTY_MEMORY_BLOCK_SIZE - offset);
1343
1344 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1345 offset, num);
1346 page += num;
1347 }
1348
1349 mr_offset = (ram_addr_t)(start_page << TARGET_PAGE_BITS) - ramblock->offset;
1350 mr_size = (end - start_page) << TARGET_PAGE_BITS;
1351 memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
1352 }
1353
1354 if (dirty && tcg_enabled()) {
1355 tlb_reset_dirty_range_all(start, length);
1356 }
1357
1358 return dirty;
1359 }
1360
1361 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1362 (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client)
1363 {
1364 DirtyMemoryBlocks *blocks;
1365 ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
1366 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1367 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1368 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1369 DirtyBitmapSnapshot *snap;
1370 unsigned long page, end, dest;
1371
1372 snap = g_malloc0(sizeof(*snap) +
1373 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1374 snap->start = first;
1375 snap->end = last;
1376
1377 page = first >> TARGET_PAGE_BITS;
1378 end = last >> TARGET_PAGE_BITS;
1379 dest = 0;
1380
1381 WITH_RCU_READ_LOCK_GUARD() {
1382 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1383
1384 while (page < end) {
1385 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1386 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1387 unsigned long num = MIN(end - page,
1388 DIRTY_MEMORY_BLOCK_SIZE - offset);
1389
1390 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1391 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1392 offset >>= BITS_PER_LEVEL;
1393
1394 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1395 blocks->blocks[idx] + offset,
1396 num);
1397 page += num;
1398 dest += num >> BITS_PER_LEVEL;
1399 }
1400 }
1401
1402 if (tcg_enabled()) {
1403 tlb_reset_dirty_range_all(start, length);
1404 }
1405
1406 memory_region_clear_dirty_bitmap(mr, offset, length);
1407
1408 return snap;
1409 }
1410
1411 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1412 ram_addr_t start,
1413 ram_addr_t length)
1414 {
1415 unsigned long page, end;
1416
1417 assert(start >= snap->start);
1418 assert(start + length <= snap->end);
1419
1420 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1421 page = (start - snap->start) >> TARGET_PAGE_BITS;
1422
1423 while (page < end) {
1424 if (test_bit(page, snap->dirty)) {
1425 return true;
1426 }
1427 page++;
1428 }
1429 return false;
1430 }
1431
1432 /* Called from RCU critical section */
1433 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1434 MemoryRegionSection *section)
1435 {
1436 AddressSpaceDispatch *d = flatview_to_dispatch(section->fv);
1437 return section - d->map.sections;
1438 }
1439 #endif /* defined(CONFIG_USER_ONLY) */
1440
1441 #if !defined(CONFIG_USER_ONLY)
1442
1443 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
1444 uint16_t section);
1445 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1446
1447 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1448 qemu_anon_ram_alloc;
1449
1450 /*
1451 * Set a custom physical guest memory alloator.
1452 * Accelerators with unusual needs may need this. Hopefully, we can
1453 * get rid of it eventually.
1454 */
1455 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1456 {
1457 phys_mem_alloc = alloc;
1458 }
1459
1460 static uint16_t phys_section_add(PhysPageMap *map,
1461 MemoryRegionSection *section)
1462 {
1463 /* The physical section number is ORed with a page-aligned
1464 * pointer to produce the iotlb entries. Thus it should
1465 * never overflow into the page-aligned value.
1466 */
1467 assert(map->sections_nb < TARGET_PAGE_SIZE);
1468
1469 if (map->sections_nb == map->sections_nb_alloc) {
1470 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1471 map->sections = g_renew(MemoryRegionSection, map->sections,
1472 map->sections_nb_alloc);
1473 }
1474 map->sections[map->sections_nb] = *section;
1475 memory_region_ref(section->mr);
1476 return map->sections_nb++;
1477 }
1478
1479 static void phys_section_destroy(MemoryRegion *mr)
1480 {
1481 bool have_sub_page = mr->subpage;
1482
1483 memory_region_unref(mr);
1484
1485 if (have_sub_page) {
1486 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1487 object_unref(OBJECT(&subpage->iomem));
1488 g_free(subpage);
1489 }
1490 }
1491
1492 static void phys_sections_free(PhysPageMap *map)
1493 {
1494 while (map->sections_nb > 0) {
1495 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1496 phys_section_destroy(section->mr);
1497 }
1498 g_free(map->sections);
1499 g_free(map->nodes);
1500 }
1501
1502 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1503 {
1504 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1505 subpage_t *subpage;
1506 hwaddr base = section->offset_within_address_space
1507 & TARGET_PAGE_MASK;
1508 MemoryRegionSection *existing = phys_page_find(d, base);
1509 MemoryRegionSection subsection = {
1510 .offset_within_address_space = base,
1511 .size = int128_make64(TARGET_PAGE_SIZE),
1512 };
1513 hwaddr start, end;
1514
1515 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1516
1517 if (!(existing->mr->subpage)) {
1518 subpage = subpage_init(fv, base);
1519 subsection.fv = fv;
1520 subsection.mr = &subpage->iomem;
1521 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1522 phys_section_add(&d->map, &subsection));
1523 } else {
1524 subpage = container_of(existing->mr, subpage_t, iomem);
1525 }
1526 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1527 end = start + int128_get64(section->size) - 1;
1528 subpage_register(subpage, start, end,
1529 phys_section_add(&d->map, section));
1530 }
1531
1532
1533 static void register_multipage(FlatView *fv,
1534 MemoryRegionSection *section)
1535 {
1536 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1537 hwaddr start_addr = section->offset_within_address_space;
1538 uint16_t section_index = phys_section_add(&d->map, section);
1539 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1540 TARGET_PAGE_BITS));
1541
1542 assert(num_pages);
1543 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1544 }
1545
1546 /*
1547 * The range in *section* may look like this:
1548 *
1549 * |s|PPPPPPP|s|
1550 *
1551 * where s stands for subpage and P for page.
1552 */
1553 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1554 {
1555 MemoryRegionSection remain = *section;
1556 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1557
1558 /* register first subpage */
1559 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1560 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1561 - remain.offset_within_address_space;
1562
1563 MemoryRegionSection now = remain;
1564 now.size = int128_min(int128_make64(left), now.size);
1565 register_subpage(fv, &now);
1566 if (int128_eq(remain.size, now.size)) {
1567 return;
1568 }
1569 remain.size = int128_sub(remain.size, now.size);
1570 remain.offset_within_address_space += int128_get64(now.size);
1571 remain.offset_within_region += int128_get64(now.size);
1572 }
1573
1574 /* register whole pages */
1575 if (int128_ge(remain.size, page_size)) {
1576 MemoryRegionSection now = remain;
1577 now.size = int128_and(now.size, int128_neg(page_size));
1578 register_multipage(fv, &now);
1579 if (int128_eq(remain.size, now.size)) {
1580 return;
1581 }
1582 remain.size = int128_sub(remain.size, now.size);
1583 remain.offset_within_address_space += int128_get64(now.size);
1584 remain.offset_within_region += int128_get64(now.size);
1585 }
1586
1587 /* register last subpage */
1588 register_subpage(fv, &remain);
1589 }
1590
1591 void qemu_flush_coalesced_mmio_buffer(void)
1592 {
1593 if (kvm_enabled())
1594 kvm_flush_coalesced_mmio_buffer();
1595 }
1596
1597 void qemu_mutex_lock_ramlist(void)
1598 {
1599 qemu_mutex_lock(&ram_list.mutex);
1600 }
1601
1602 void qemu_mutex_unlock_ramlist(void)
1603 {
1604 qemu_mutex_unlock(&ram_list.mutex);
1605 }
1606
1607 void ram_block_dump(Monitor *mon)
1608 {
1609 RAMBlock *block;
1610 char *psize;
1611
1612 RCU_READ_LOCK_GUARD();
1613 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1614 "Block Name", "PSize", "Offset", "Used", "Total");
1615 RAMBLOCK_FOREACH(block) {
1616 psize = size_to_str(block->page_size);
1617 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1618 " 0x%016" PRIx64 "\n", block->idstr, psize,
1619 (uint64_t)block->offset,
1620 (uint64_t)block->used_length,
1621 (uint64_t)block->max_length);
1622 g_free(psize);
1623 }
1624 }
1625
1626 #ifdef __linux__
1627 /*
1628 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1629 * may or may not name the same files / on the same filesystem now as
1630 * when we actually open and map them. Iterate over the file
1631 * descriptors instead, and use qemu_fd_getpagesize().
1632 */
1633 static int find_min_backend_pagesize(Object *obj, void *opaque)
1634 {
1635 long *hpsize_min = opaque;
1636
1637 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1638 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1639 long hpsize = host_memory_backend_pagesize(backend);
1640
1641 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1642 *hpsize_min = hpsize;
1643 }
1644 }
1645
1646 return 0;
1647 }
1648
1649 static int find_max_backend_pagesize(Object *obj, void *opaque)
1650 {
1651 long *hpsize_max = opaque;
1652
1653 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1654 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1655 long hpsize = host_memory_backend_pagesize(backend);
1656
1657 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1658 *hpsize_max = hpsize;
1659 }
1660 }
1661
1662 return 0;
1663 }
1664
1665 /*
1666 * TODO: We assume right now that all mapped host memory backends are
1667 * used as RAM, however some might be used for different purposes.
1668 */
1669 long qemu_minrampagesize(void)
1670 {
1671 long hpsize = LONG_MAX;
1672 Object *memdev_root = object_resolve_path("/objects", NULL);
1673
1674 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1675 return hpsize;
1676 }
1677
1678 long qemu_maxrampagesize(void)
1679 {
1680 long pagesize = 0;
1681 Object *memdev_root = object_resolve_path("/objects", NULL);
1682
1683 object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize);
1684 return pagesize;
1685 }
1686 #else
1687 long qemu_minrampagesize(void)
1688 {
1689 return qemu_real_host_page_size;
1690 }
1691 long qemu_maxrampagesize(void)
1692 {
1693 return qemu_real_host_page_size;
1694 }
1695 #endif
1696
1697 #ifdef CONFIG_POSIX
1698 static int64_t get_file_size(int fd)
1699 {
1700 int64_t size;
1701 #if defined(__linux__)
1702 struct stat st;
1703
1704 if (fstat(fd, &st) < 0) {
1705 return -errno;
1706 }
1707
1708 /* Special handling for devdax character devices */
1709 if (S_ISCHR(st.st_mode)) {
1710 g_autofree char *subsystem_path = NULL;
1711 g_autofree char *subsystem = NULL;
1712
1713 subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem",
1714 major(st.st_rdev), minor(st.st_rdev));
1715 subsystem = g_file_read_link(subsystem_path, NULL);
1716
1717 if (subsystem && g_str_has_suffix(subsystem, "/dax")) {
1718 g_autofree char *size_path = NULL;
1719 g_autofree char *size_str = NULL;
1720
1721 size_path = g_strdup_printf("/sys/dev/char/%d:%d/size",
1722 major(st.st_rdev), minor(st.st_rdev));
1723
1724 if (g_file_get_contents(size_path, &size_str, NULL, NULL)) {
1725 return g_ascii_strtoll(size_str, NULL, 0);
1726 }
1727 }
1728 }
1729 #endif /* defined(__linux__) */
1730
1731 /* st.st_size may be zero for special files yet lseek(2) works */
1732 size = lseek(fd, 0, SEEK_END);
1733 if (size < 0) {
1734 return -errno;
1735 }
1736 return size;
1737 }
1738
1739 static int file_ram_open(const char *path,
1740 const char *region_name,
1741 bool *created,
1742 Error **errp)
1743 {
1744 char *filename;
1745 char *sanitized_name;
1746 char *c;
1747 int fd = -1;
1748
1749 *created = false;
1750 for (;;) {
1751 fd = open(path, O_RDWR);
1752 if (fd >= 0) {
1753 /* @path names an existing file, use it */
1754 break;
1755 }
1756 if (errno == ENOENT) {
1757 /* @path names a file that doesn't exist, create it */
1758 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1759 if (fd >= 0) {
1760 *created = true;
1761 break;
1762 }
1763 } else if (errno == EISDIR) {
1764 /* @path names a directory, create a file there */
1765 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1766 sanitized_name = g_strdup(region_name);
1767 for (c = sanitized_name; *c != '\0'; c++) {
1768 if (*c == '/') {
1769 *c = '_';
1770 }
1771 }
1772
1773 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1774 sanitized_name);
1775 g_free(sanitized_name);
1776
1777 fd = mkstemp(filename);
1778 if (fd >= 0) {
1779 unlink(filename);
1780 g_free(filename);
1781 break;
1782 }
1783 g_free(filename);
1784 }
1785 if (errno != EEXIST && errno != EINTR) {
1786 error_setg_errno(errp, errno,
1787 "can't open backing store %s for guest RAM",
1788 path);
1789 return -1;
1790 }
1791 /*
1792 * Try again on EINTR and EEXIST. The latter happens when
1793 * something else creates the file between our two open().
1794 */
1795 }
1796
1797 return fd;
1798 }
1799
1800 static void *file_ram_alloc(RAMBlock *block,
1801 ram_addr_t memory,
1802 int fd,
1803 bool truncate,
1804 Error **errp)
1805 {
1806 void *area;
1807
1808 block->page_size = qemu_fd_getpagesize(fd);
1809 if (block->mr->align % block->page_size) {
1810 error_setg(errp, "alignment 0x%" PRIx64
1811 " must be multiples of page size 0x%zx",
1812 block->mr->align, block->page_size);
1813 return NULL;
1814 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1815 error_setg(errp, "alignment 0x%" PRIx64
1816 " must be a power of two", block->mr->align);
1817 return NULL;
1818 }
1819 block->mr->align = MAX(block->page_size, block->mr->align);
1820 #if defined(__s390x__)
1821 if (kvm_enabled()) {
1822 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1823 }
1824 #endif
1825
1826 if (memory < block->page_size) {
1827 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1828 "or larger than page size 0x%zx",
1829 memory, block->page_size);
1830 return NULL;
1831 }
1832
1833 memory = ROUND_UP(memory, block->page_size);
1834
1835 /*
1836 * ftruncate is not supported by hugetlbfs in older
1837 * hosts, so don't bother bailing out on errors.
1838 * If anything goes wrong with it under other filesystems,
1839 * mmap will fail.
1840 *
1841 * Do not truncate the non-empty backend file to avoid corrupting
1842 * the existing data in the file. Disabling shrinking is not
1843 * enough. For example, the current vNVDIMM implementation stores
1844 * the guest NVDIMM labels at the end of the backend file. If the
1845 * backend file is later extended, QEMU will not be able to find
1846 * those labels. Therefore, extending the non-empty backend file
1847 * is disabled as well.
1848 */
1849 if (truncate && ftruncate(fd, memory)) {
1850 perror("ftruncate");
1851 }
1852
1853 area = qemu_ram_mmap(fd, memory, block->mr->align,
1854 block->flags & RAM_SHARED, block->flags & RAM_PMEM);
1855 if (area == MAP_FAILED) {
1856 error_setg_errno(errp, errno,
1857 "unable to map backing store for guest RAM");
1858 return NULL;
1859 }
1860
1861 block->fd = fd;
1862 return area;
1863 }
1864 #endif
1865
1866 /* Allocate space within the ram_addr_t space that governs the
1867 * dirty bitmaps.
1868 * Called with the ramlist lock held.
1869 */
1870 static ram_addr_t find_ram_offset(ram_addr_t size)
1871 {
1872 RAMBlock *block, *next_block;
1873 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1874
1875 assert(size != 0); /* it would hand out same offset multiple times */
1876
1877 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1878 return 0;
1879 }
1880
1881 RAMBLOCK_FOREACH(block) {
1882 ram_addr_t candidate, next = RAM_ADDR_MAX;
1883
1884 /* Align blocks to start on a 'long' in the bitmap
1885 * which makes the bitmap sync'ing take the fast path.
1886 */
1887 candidate = block->offset + block->max_length;
1888 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1889
1890 /* Search for the closest following block
1891 * and find the gap.
1892 */
1893 RAMBLOCK_FOREACH(next_block) {
1894 if (next_block->offset >= candidate) {
1895 next = MIN(next, next_block->offset);
1896 }
1897 }
1898
1899 /* If it fits remember our place and remember the size
1900 * of gap, but keep going so that we might find a smaller
1901 * gap to fill so avoiding fragmentation.
1902 */
1903 if (next - candidate >= size && next - candidate < mingap) {
1904 offset = candidate;
1905 mingap = next - candidate;
1906 }
1907
1908 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1909 }
1910
1911 if (offset == RAM_ADDR_MAX) {
1912 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1913 (uint64_t)size);
1914 abort();
1915 }
1916
1917 trace_find_ram_offset(size, offset);
1918
1919 return offset;
1920 }
1921
1922 static unsigned long last_ram_page(void)
1923 {
1924 RAMBlock *block;
1925 ram_addr_t last = 0;
1926
1927 RCU_READ_LOCK_GUARD();
1928 RAMBLOCK_FOREACH(block) {
1929 last = MAX(last, block->offset + block->max_length);
1930 }
1931 return last >> TARGET_PAGE_BITS;
1932 }
1933
1934 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1935 {
1936 int ret;
1937
1938 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1939 if (!machine_dump_guest_core(current_machine)) {
1940 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1941 if (ret) {
1942 perror("qemu_madvise");
1943 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1944 "but dump_guest_core=off specified\n");
1945 }
1946 }
1947 }
1948
1949 const char *qemu_ram_get_idstr(RAMBlock *rb)
1950 {
1951 return rb->idstr;
1952 }
1953
1954 void *qemu_ram_get_host_addr(RAMBlock *rb)
1955 {
1956 return rb->host;
1957 }
1958
1959 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
1960 {
1961 return rb->offset;
1962 }
1963
1964 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
1965 {
1966 return rb->used_length;
1967 }
1968
1969 bool qemu_ram_is_shared(RAMBlock *rb)
1970 {
1971 return rb->flags & RAM_SHARED;
1972 }
1973
1974 /* Note: Only set at the start of postcopy */
1975 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
1976 {
1977 return rb->flags & RAM_UF_ZEROPAGE;
1978 }
1979
1980 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
1981 {
1982 rb->flags |= RAM_UF_ZEROPAGE;
1983 }
1984
1985 bool qemu_ram_is_migratable(RAMBlock *rb)
1986 {
1987 return rb->flags & RAM_MIGRATABLE;
1988 }
1989
1990 void qemu_ram_set_migratable(RAMBlock *rb)
1991 {
1992 rb->flags |= RAM_MIGRATABLE;
1993 }
1994
1995 void qemu_ram_unset_migratable(RAMBlock *rb)
1996 {
1997 rb->flags &= ~RAM_MIGRATABLE;
1998 }
1999
2000 /* Called with iothread lock held. */
2001 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
2002 {
2003 RAMBlock *block;
2004
2005 assert(new_block);
2006 assert(!new_block->idstr[0]);
2007
2008 if (dev) {
2009 char *id = qdev_get_dev_path(dev);
2010 if (id) {
2011 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2012 g_free(id);
2013 }
2014 }
2015 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2016
2017 RCU_READ_LOCK_GUARD();
2018 RAMBLOCK_FOREACH(block) {
2019 if (block != new_block &&
2020 !strcmp(block->idstr, new_block->idstr)) {
2021 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2022 new_block->idstr);
2023 abort();
2024 }
2025 }
2026 }
2027
2028 /* Called with iothread lock held. */
2029 void qemu_ram_unset_idstr(RAMBlock *block)
2030 {
2031 /* FIXME: arch_init.c assumes that this is not called throughout
2032 * migration. Ignore the problem since hot-unplug during migration
2033 * does not work anyway.
2034 */
2035 if (block) {
2036 memset(block->idstr, 0, sizeof(block->idstr));
2037 }
2038 }
2039
2040 size_t qemu_ram_pagesize(RAMBlock *rb)
2041 {
2042 return rb->page_size;
2043 }
2044
2045 /* Returns the largest size of page in use */
2046 size_t qemu_ram_pagesize_largest(void)
2047 {
2048 RAMBlock *block;
2049 size_t largest = 0;
2050
2051 RAMBLOCK_FOREACH(block) {
2052 largest = MAX(largest, qemu_ram_pagesize(block));
2053 }
2054
2055 return largest;
2056 }
2057
2058 static int memory_try_enable_merging(void *addr, size_t len)
2059 {
2060 if (!machine_mem_merge(current_machine)) {
2061 /* disabled by the user */
2062 return 0;
2063 }
2064
2065 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
2066 }
2067
2068 /* Only legal before guest might have detected the memory size: e.g. on
2069 * incoming migration, or right after reset.
2070 *
2071 * As memory core doesn't know how is memory accessed, it is up to
2072 * resize callback to update device state and/or add assertions to detect
2073 * misuse, if necessary.
2074 */
2075 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
2076 {
2077 assert(block);
2078
2079 newsize = HOST_PAGE_ALIGN(newsize);
2080
2081 if (block->used_length == newsize) {
2082 return 0;
2083 }
2084
2085 if (!(block->flags & RAM_RESIZEABLE)) {
2086 error_setg_errno(errp, EINVAL,
2087 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2088 " in != 0x" RAM_ADDR_FMT, block->idstr,
2089 newsize, block->used_length);
2090 return -EINVAL;
2091 }
2092
2093 if (block->max_length < newsize) {
2094 error_setg_errno(errp, EINVAL,
2095 "Length too large: %s: 0x" RAM_ADDR_FMT
2096 " > 0x" RAM_ADDR_FMT, block->idstr,
2097 newsize, block->max_length);
2098 return -EINVAL;
2099 }
2100
2101 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
2102 block->used_length = newsize;
2103 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
2104 DIRTY_CLIENTS_ALL);
2105 memory_region_set_size(block->mr, newsize);
2106 if (block->resized) {
2107 block->resized(block->idstr, newsize, block->host);
2108 }
2109 return 0;
2110 }
2111
2112 /*
2113 * Trigger sync on the given ram block for range [start, start + length]
2114 * with the backing store if one is available.
2115 * Otherwise no-op.
2116 * @Note: this is supposed to be a synchronous op.
2117 */
2118 void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length)
2119 {
2120 /* The requested range should fit in within the block range */
2121 g_assert((start + length) <= block->used_length);
2122
2123 #ifdef CONFIG_LIBPMEM
2124 /* The lack of support for pmem should not block the sync */
2125 if (ramblock_is_pmem(block)) {
2126 void *addr = ramblock_ptr(block, start);
2127 pmem_persist(addr, length);
2128 return;
2129 }
2130 #endif
2131 if (block->fd >= 0) {
2132 /**
2133 * Case there is no support for PMEM or the memory has not been
2134 * specified as persistent (or is not one) - use the msync.
2135 * Less optimal but still achieves the same goal
2136 */
2137 void *addr = ramblock_ptr(block, start);
2138 if (qemu_msync(addr, length, block->fd)) {
2139 warn_report("%s: failed to sync memory range: start: "
2140 RAM_ADDR_FMT " length: " RAM_ADDR_FMT,
2141 __func__, start, length);
2142 }
2143 }
2144 }
2145
2146 /* Called with ram_list.mutex held */
2147 static void dirty_memory_extend(ram_addr_t old_ram_size,
2148 ram_addr_t new_ram_size)
2149 {
2150 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
2151 DIRTY_MEMORY_BLOCK_SIZE);
2152 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
2153 DIRTY_MEMORY_BLOCK_SIZE);
2154 int i;
2155
2156 /* Only need to extend if block count increased */
2157 if (new_num_blocks <= old_num_blocks) {
2158 return;
2159 }
2160
2161 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
2162 DirtyMemoryBlocks *old_blocks;
2163 DirtyMemoryBlocks *new_blocks;
2164 int j;
2165
2166 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
2167 new_blocks = g_malloc(sizeof(*new_blocks) +
2168 sizeof(new_blocks->blocks[0]) * new_num_blocks);
2169
2170 if (old_num_blocks) {
2171 memcpy(new_blocks->blocks, old_blocks->blocks,
2172 old_num_blocks * sizeof(old_blocks->blocks[0]));
2173 }
2174
2175 for (j = old_num_blocks; j < new_num_blocks; j++) {
2176 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
2177 }
2178
2179 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
2180
2181 if (old_blocks) {
2182 g_free_rcu(old_blocks, rcu);
2183 }
2184 }
2185 }
2186
2187 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
2188 {
2189 RAMBlock *block;
2190 RAMBlock *last_block = NULL;
2191 ram_addr_t old_ram_size, new_ram_size;
2192 Error *err = NULL;
2193
2194 old_ram_size = last_ram_page();
2195
2196 qemu_mutex_lock_ramlist();
2197 new_block->offset = find_ram_offset(new_block->max_length);
2198
2199 if (!new_block->host) {
2200 if (xen_enabled()) {
2201 xen_ram_alloc(new_block->offset, new_block->max_length,
2202 new_block->mr, &err);
2203 if (err) {
2204 error_propagate(errp, err);
2205 qemu_mutex_unlock_ramlist();
2206 return;
2207 }
2208 } else {
2209 new_block->host = phys_mem_alloc(new_block->max_length,
2210 &new_block->mr->align, shared);
2211 if (!new_block->host) {
2212 error_setg_errno(errp, errno,
2213 "cannot set up guest memory '%s'",
2214 memory_region_name(new_block->mr));
2215 qemu_mutex_unlock_ramlist();
2216 return;
2217 }
2218 memory_try_enable_merging(new_block->host, new_block->max_length);
2219 }
2220 }
2221
2222 new_ram_size = MAX(old_ram_size,
2223 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
2224 if (new_ram_size > old_ram_size) {
2225 dirty_memory_extend(old_ram_size, new_ram_size);
2226 }
2227 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2228 * QLIST (which has an RCU-friendly variant) does not have insertion at
2229 * tail, so save the last element in last_block.
2230 */
2231 RAMBLOCK_FOREACH(block) {
2232 last_block = block;
2233 if (block->max_length < new_block->max_length) {
2234 break;
2235 }
2236 }
2237 if (block) {
2238 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2239 } else if (last_block) {
2240 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2241 } else { /* list is empty */
2242 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2243 }
2244 ram_list.mru_block = NULL;
2245
2246 /* Write list before version */
2247 smp_wmb();
2248 ram_list.version++;
2249 qemu_mutex_unlock_ramlist();
2250
2251 cpu_physical_memory_set_dirty_range(new_block->offset,
2252 new_block->used_length,
2253 DIRTY_CLIENTS_ALL);
2254
2255 if (new_block->host) {
2256 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2257 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2258 /*
2259 * MADV_DONTFORK is also needed by KVM in absence of synchronous MMU
2260 * Configure it unless the machine is a qtest server, in which case
2261 * KVM is not used and it may be forked (eg for fuzzing purposes).
2262 */
2263 if (!qtest_enabled()) {
2264 qemu_madvise(new_block->host, new_block->max_length,
2265 QEMU_MADV_DONTFORK);
2266 }
2267 ram_block_notify_add(new_block->host, new_block->max_length);
2268 }
2269 }
2270
2271 #ifdef CONFIG_POSIX
2272 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2273 uint32_t ram_flags, int fd,
2274 Error **errp)
2275 {
2276 RAMBlock *new_block;
2277 Error *local_err = NULL;
2278 int64_t file_size;
2279
2280 /* Just support these ram flags by now. */
2281 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM)) == 0);
2282
2283 if (xen_enabled()) {
2284 error_setg(errp, "-mem-path not supported with Xen");
2285 return NULL;
2286 }
2287
2288 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2289 error_setg(errp,
2290 "host lacks kvm mmu notifiers, -mem-path unsupported");
2291 return NULL;
2292 }
2293
2294 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2295 /*
2296 * file_ram_alloc() needs to allocate just like
2297 * phys_mem_alloc, but we haven't bothered to provide
2298 * a hook there.
2299 */
2300 error_setg(errp,
2301 "-mem-path not supported with this accelerator");
2302 return NULL;
2303 }
2304
2305 size = HOST_PAGE_ALIGN(size);
2306 file_size = get_file_size(fd);
2307 if (file_size > 0 && file_size < size) {
2308 error_setg(errp, "backing store size 0x%" PRIx64
2309 " does not match 'size' option 0x" RAM_ADDR_FMT,
2310 file_size, size);
2311 return NULL;
2312 }
2313
2314 new_block = g_malloc0(sizeof(*new_block));
2315 new_block->mr = mr;
2316 new_block->used_length = size;
2317 new_block->max_length = size;
2318 new_block->flags = ram_flags;
2319 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2320 if (!new_block->host) {
2321 g_free(new_block);
2322 return NULL;
2323 }
2324
2325 ram_block_add(new_block, &local_err, ram_flags & RAM_SHARED);
2326 if (local_err) {
2327 g_free(new_block);
2328 error_propagate(errp, local_err);
2329 return NULL;
2330 }
2331 return new_block;
2332
2333 }
2334
2335
2336 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2337 uint32_t ram_flags, const char *mem_path,
2338 Error **errp)
2339 {
2340 int fd;
2341 bool created;
2342 RAMBlock *block;
2343
2344 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2345 if (fd < 0) {
2346 return NULL;
2347 }
2348
2349 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, errp);
2350 if (!block) {
2351 if (created) {
2352 unlink(mem_path);
2353 }
2354 close(fd);
2355 return NULL;
2356 }
2357
2358 return block;
2359 }
2360 #endif
2361
2362 static
2363 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2364 void (*resized)(const char*,
2365 uint64_t length,
2366 void *host),
2367 void *host, bool resizeable, bool share,
2368 MemoryRegion *mr, Error **errp)
2369 {
2370 RAMBlock *new_block;
2371 Error *local_err = NULL;
2372
2373 size = HOST_PAGE_ALIGN(size);
2374 max_size = HOST_PAGE_ALIGN(max_size);
2375 new_block = g_malloc0(sizeof(*new_block));
2376 new_block->mr = mr;
2377 new_block->resized = resized;
2378 new_block->used_length = size;
2379 new_block->max_length = max_size;
2380 assert(max_size >= size);
2381 new_block->fd = -1;
2382 new_block->page_size = qemu_real_host_page_size;
2383 new_block->host = host;
2384 if (host) {
2385 new_block->flags |= RAM_PREALLOC;
2386 }
2387 if (resizeable) {
2388 new_block->flags |= RAM_RESIZEABLE;
2389 }
2390 ram_block_add(new_block, &local_err, share);
2391 if (local_err) {
2392 g_free(new_block);
2393 error_propagate(errp, local_err);
2394 return NULL;
2395 }
2396 return new_block;
2397 }
2398
2399 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2400 MemoryRegion *mr, Error **errp)
2401 {
2402 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2403 false, mr, errp);
2404 }
2405
2406 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2407 MemoryRegion *mr, Error **errp)
2408 {
2409 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2410 share, mr, errp);
2411 }
2412
2413 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2414 void (*resized)(const char*,
2415 uint64_t length,
2416 void *host),
2417 MemoryRegion *mr, Error **errp)
2418 {
2419 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2420 false, mr, errp);
2421 }
2422
2423 static void reclaim_ramblock(RAMBlock *block)
2424 {
2425 if (block->flags & RAM_PREALLOC) {
2426 ;
2427 } else if (xen_enabled()) {
2428 xen_invalidate_map_cache_entry(block->host);
2429 #ifndef _WIN32
2430 } else if (block->fd >= 0) {
2431 qemu_ram_munmap(block->fd, block->host, block->max_length);
2432 close(block->fd);
2433 #endif
2434 } else {
2435 qemu_anon_ram_free(block->host, block->max_length);
2436 }
2437 g_free(block);
2438 }
2439
2440 void qemu_ram_free(RAMBlock *block)
2441 {
2442 if (!block) {
2443 return;
2444 }
2445
2446 if (block->host) {
2447 ram_block_notify_remove(block->host, block->max_length);
2448 }
2449
2450 qemu_mutex_lock_ramlist();
2451 QLIST_REMOVE_RCU(block, next);
2452 ram_list.mru_block = NULL;
2453 /* Write list before version */
2454 smp_wmb();
2455 ram_list.version++;
2456 call_rcu(block, reclaim_ramblock, rcu);
2457 qemu_mutex_unlock_ramlist();
2458 }
2459
2460 #ifndef _WIN32
2461 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2462 {
2463 RAMBlock *block;
2464 ram_addr_t offset;
2465 int flags;
2466 void *area, *vaddr;
2467
2468 RAMBLOCK_FOREACH(block) {
2469 offset = addr - block->offset;
2470 if (offset < block->max_length) {
2471 vaddr = ramblock_ptr(block, offset);
2472 if (block->flags & RAM_PREALLOC) {
2473 ;
2474 } else if (xen_enabled()) {
2475 abort();
2476 } else {
2477 flags = MAP_FIXED;
2478 if (block->fd >= 0) {
2479 flags |= (block->flags & RAM_SHARED ?
2480 MAP_SHARED : MAP_PRIVATE);
2481 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2482 flags, block->fd, offset);
2483 } else {
2484 /*
2485 * Remap needs to match alloc. Accelerators that
2486 * set phys_mem_alloc never remap. If they did,
2487 * we'd need a remap hook here.
2488 */
2489 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2490
2491 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2492 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2493 flags, -1, 0);
2494 }
2495 if (area != vaddr) {
2496 error_report("Could not remap addr: "
2497 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2498 length, addr);
2499 exit(1);
2500 }
2501 memory_try_enable_merging(vaddr, length);
2502 qemu_ram_setup_dump(vaddr, length);
2503 }
2504 }
2505 }
2506 }
2507 #endif /* !_WIN32 */
2508
2509 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2510 * This should not be used for general purpose DMA. Use address_space_map
2511 * or address_space_rw instead. For local memory (e.g. video ram) that the
2512 * device owns, use memory_region_get_ram_ptr.
2513 *
2514 * Called within RCU critical section.
2515 */
2516 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2517 {
2518 RAMBlock *block = ram_block;
2519
2520 if (block == NULL) {
2521 block = qemu_get_ram_block(addr);
2522 addr -= block->offset;
2523 }
2524
2525 if (xen_enabled() && block->host == NULL) {
2526 /* We need to check if the requested address is in the RAM
2527 * because we don't want to map the entire memory in QEMU.
2528 * In that case just map until the end of the page.
2529 */
2530 if (block->offset == 0) {
2531 return xen_map_cache(addr, 0, 0, false);
2532 }
2533
2534 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2535 }
2536 return ramblock_ptr(block, addr);
2537 }
2538
2539 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2540 * but takes a size argument.
2541 *
2542 * Called within RCU critical section.
2543 */
2544 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2545 hwaddr *size, bool lock)
2546 {
2547 RAMBlock *block = ram_block;
2548 if (*size == 0) {
2549 return NULL;
2550 }
2551
2552 if (block == NULL) {
2553 block = qemu_get_ram_block(addr);
2554 addr -= block->offset;
2555 }
2556 *size = MIN(*size, block->max_length - addr);
2557
2558 if (xen_enabled() && block->host == NULL) {
2559 /* We need to check if the requested address is in the RAM
2560 * because we don't want to map the entire memory in QEMU.
2561 * In that case just map the requested area.
2562 */
2563 if (block->offset == 0) {
2564 return xen_map_cache(addr, *size, lock, lock);
2565 }
2566
2567 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2568 }
2569
2570 return ramblock_ptr(block, addr);
2571 }
2572
2573 /* Return the offset of a hostpointer within a ramblock */
2574 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2575 {
2576 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2577 assert((uintptr_t)host >= (uintptr_t)rb->host);
2578 assert(res < rb->max_length);
2579
2580 return res;
2581 }
2582
2583 /*
2584 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2585 * in that RAMBlock.
2586 *
2587 * ptr: Host pointer to look up
2588 * round_offset: If true round the result offset down to a page boundary
2589 * *ram_addr: set to result ram_addr
2590 * *offset: set to result offset within the RAMBlock
2591 *
2592 * Returns: RAMBlock (or NULL if not found)
2593 *
2594 * By the time this function returns, the returned pointer is not protected
2595 * by RCU anymore. If the caller is not within an RCU critical section and
2596 * does not hold the iothread lock, it must have other means of protecting the
2597 * pointer, such as a reference to the region that includes the incoming
2598 * ram_addr_t.
2599 */
2600 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2601 ram_addr_t *offset)
2602 {
2603 RAMBlock *block;
2604 uint8_t *host = ptr;
2605
2606 if (xen_enabled()) {
2607 ram_addr_t ram_addr;
2608 RCU_READ_LOCK_GUARD();
2609 ram_addr = xen_ram_addr_from_mapcache(ptr);
2610 block = qemu_get_ram_block(ram_addr);
2611 if (block) {
2612 *offset = ram_addr - block->offset;
2613 }
2614 return block;
2615 }
2616
2617 RCU_READ_LOCK_GUARD();
2618 block = atomic_rcu_read(&ram_list.mru_block);
2619 if (block && block->host && host - block->host < block->max_length) {
2620 goto found;
2621 }
2622
2623 RAMBLOCK_FOREACH(block) {
2624 /* This case append when the block is not mapped. */
2625 if (block->host == NULL) {
2626 continue;
2627 }
2628 if (host - block->host < block->max_length) {
2629 goto found;
2630 }
2631 }
2632
2633 return NULL;
2634
2635 found:
2636 *offset = (host - block->host);
2637 if (round_offset) {
2638 *offset &= TARGET_PAGE_MASK;
2639 }
2640 return block;
2641 }
2642
2643 /*
2644 * Finds the named RAMBlock
2645 *
2646 * name: The name of RAMBlock to find
2647 *
2648 * Returns: RAMBlock (or NULL if not found)
2649 */
2650 RAMBlock *qemu_ram_block_by_name(const char *name)
2651 {
2652 RAMBlock *block;
2653
2654 RAMBLOCK_FOREACH(block) {
2655 if (!strcmp(name, block->idstr)) {
2656 return block;
2657 }
2658 }
2659
2660 return NULL;
2661 }
2662
2663 /* Some of the softmmu routines need to translate from a host pointer
2664 (typically a TLB entry) back to a ram offset. */
2665 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2666 {
2667 RAMBlock *block;
2668 ram_addr_t offset;
2669
2670 block = qemu_ram_block_from_host(ptr, false, &offset);
2671 if (!block) {
2672 return RAM_ADDR_INVALID;
2673 }
2674
2675 return block->offset + offset;
2676 }
2677
2678 /* Generate a debug exception if a watchpoint has been hit. */
2679 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
2680 MemTxAttrs attrs, int flags, uintptr_t ra)
2681 {
2682 CPUClass *cc = CPU_GET_CLASS(cpu);
2683 CPUWatchpoint *wp;
2684
2685 assert(tcg_enabled());
2686 if (cpu->watchpoint_hit) {
2687 /*
2688 * We re-entered the check after replacing the TB.
2689 * Now raise the debug interrupt so that it will
2690 * trigger after the current instruction.
2691 */
2692 qemu_mutex_lock_iothread();
2693 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2694 qemu_mutex_unlock_iothread();
2695 return;
2696 }
2697
2698 addr = cc->adjust_watchpoint_address(cpu, addr, len);
2699 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2700 if (watchpoint_address_matches(wp, addr, len)
2701 && (wp->flags & flags)) {
2702 if (flags == BP_MEM_READ) {
2703 wp->flags |= BP_WATCHPOINT_HIT_READ;
2704 } else {
2705 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2706 }
2707 wp->hitaddr = MAX(addr, wp->vaddr);
2708 wp->hitattrs = attrs;
2709 if (!cpu->watchpoint_hit) {
2710 if (wp->flags & BP_CPU &&
2711 !cc->debug_check_watchpoint(cpu, wp)) {
2712 wp->flags &= ~BP_WATCHPOINT_HIT;
2713 continue;
2714 }
2715 cpu->watchpoint_hit = wp;
2716
2717 mmap_lock();
2718 tb_check_watchpoint(cpu, ra);
2719 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2720 cpu->exception_index = EXCP_DEBUG;
2721 mmap_unlock();
2722 cpu_loop_exit_restore(cpu, ra);
2723 } else {
2724 /* Force execution of one insn next time. */
2725 cpu->cflags_next_tb = 1 | curr_cflags();
2726 mmap_unlock();
2727 if (ra) {
2728 cpu_restore_state(cpu, ra, true);
2729 }
2730 cpu_loop_exit_noexc(cpu);
2731 }
2732 }
2733 } else {
2734 wp->flags &= ~BP_WATCHPOINT_HIT;
2735 }
2736 }
2737 }
2738
2739 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2740 MemTxAttrs attrs, void *buf, hwaddr len);
2741 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2742 const void *buf, hwaddr len);
2743 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2744 bool is_write, MemTxAttrs attrs);
2745
2746 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2747 unsigned len, MemTxAttrs attrs)
2748 {
2749 subpage_t *subpage = opaque;
2750 uint8_t buf[8];
2751 MemTxResult res;
2752
2753 #if defined(DEBUG_SUBPAGE)
2754 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2755 subpage, len, addr);
2756 #endif
2757 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2758 if (res) {
2759 return res;
2760 }
2761 *data = ldn_p(buf, len);
2762 return MEMTX_OK;
2763 }
2764
2765 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2766 uint64_t value, unsigned len, MemTxAttrs attrs)
2767 {
2768 subpage_t *subpage = opaque;
2769 uint8_t buf[8];
2770
2771 #if defined(DEBUG_SUBPAGE)
2772 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2773 " value %"PRIx64"\n",
2774 __func__, subpage, len, addr, value);
2775 #endif
2776 stn_p(buf, len, value);
2777 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2778 }
2779
2780 static bool subpage_accepts(void *opaque, hwaddr addr,
2781 unsigned len, bool is_write,
2782 MemTxAttrs attrs)
2783 {
2784 subpage_t *subpage = opaque;
2785 #if defined(DEBUG_SUBPAGE)
2786 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2787 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2788 #endif
2789
2790 return flatview_access_valid(subpage->fv, addr + subpage->base,
2791 len, is_write, attrs);
2792 }
2793
2794 static const MemoryRegionOps subpage_ops = {
2795 .read_with_attrs = subpage_read,
2796 .write_with_attrs = subpage_write,
2797 .impl.min_access_size = 1,
2798 .impl.max_access_size = 8,
2799 .valid.min_access_size = 1,
2800 .valid.max_access_size = 8,
2801 .valid.accepts = subpage_accepts,
2802 .endianness = DEVICE_NATIVE_ENDIAN,
2803 };
2804
2805 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
2806 uint16_t section)
2807 {
2808 int idx, eidx;
2809
2810 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2811 return -1;
2812 idx = SUBPAGE_IDX(start);
2813 eidx = SUBPAGE_IDX(end);
2814 #if defined(DEBUG_SUBPAGE)
2815 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2816 __func__, mmio, start, end, idx, eidx, section);
2817 #endif
2818 for (; idx <= eidx; idx++) {
2819 mmio->sub_section[idx] = section;
2820 }
2821
2822 return 0;
2823 }
2824
2825 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2826 {
2827 subpage_t *mmio;
2828
2829 /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */
2830 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2831 mmio->fv = fv;
2832 mmio->base = base;
2833 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2834 NULL, TARGET_PAGE_SIZE);
2835 mmio->iomem.subpage = true;
2836 #if defined(DEBUG_SUBPAGE)
2837 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2838 mmio, base, TARGET_PAGE_SIZE);
2839 #endif
2840
2841 return mmio;
2842 }
2843
2844 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2845 {
2846 assert(fv);
2847 MemoryRegionSection section = {
2848 .fv = fv,
2849 .mr = mr,
2850 .offset_within_address_space = 0,
2851 .offset_within_region = 0,
2852 .size = int128_2_64(),
2853 };
2854
2855 return phys_section_add(map, &section);
2856 }
2857
2858 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
2859 hwaddr index, MemTxAttrs attrs)
2860 {
2861 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2862 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2863 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2864 MemoryRegionSection *sections = d->map.sections;
2865
2866 return &sections[index & ~TARGET_PAGE_MASK];
2867 }
2868
2869 static void io_mem_init(void)
2870 {
2871 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2872 NULL, UINT64_MAX);
2873 }
2874
2875 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2876 {
2877 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2878 uint16_t n;
2879
2880 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2881 assert(n == PHYS_SECTION_UNASSIGNED);
2882
2883 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2884
2885 return d;
2886 }
2887
2888 void address_space_dispatch_free(AddressSpaceDispatch *d)
2889 {
2890 phys_sections_free(&d->map);
2891 g_free(d);
2892 }
2893
2894 static void do_nothing(CPUState *cpu, run_on_cpu_data d)
2895 {
2896 }
2897
2898 static void tcg_log_global_after_sync(MemoryListener *listener)
2899 {
2900 CPUAddressSpace *cpuas;
2901
2902 /* Wait for the CPU to end the current TB. This avoids the following
2903 * incorrect race:
2904 *
2905 * vCPU migration
2906 * ---------------------- -------------------------
2907 * TLB check -> slow path
2908 * notdirty_mem_write
2909 * write to RAM
2910 * mark dirty
2911 * clear dirty flag
2912 * TLB check -> fast path
2913 * read memory
2914 * write to RAM
2915 *
2916 * by pushing the migration thread's memory read after the vCPU thread has
2917 * written the memory.
2918 */
2919 if (replay_mode == REPLAY_MODE_NONE) {
2920 /*
2921 * VGA can make calls to this function while updating the screen.
2922 * In record/replay mode this causes a deadlock, because
2923 * run_on_cpu waits for rr mutex. Therefore no races are possible
2924 * in this case and no need for making run_on_cpu when
2925 * record/replay is not enabled.
2926 */
2927 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2928 run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL);
2929 }
2930 }
2931
2932 static void tcg_commit(MemoryListener *listener)
2933 {
2934 CPUAddressSpace *cpuas;
2935 AddressSpaceDispatch *d;
2936
2937 assert(tcg_enabled());
2938 /* since each CPU stores ram addresses in its TLB cache, we must
2939 reset the modified entries */
2940 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2941 cpu_reloading_memory_map();
2942 /* The CPU and TLB are protected by the iothread lock.
2943 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2944 * may have split the RCU critical section.
2945 */
2946 d = address_space_to_dispatch(cpuas->as);
2947 atomic_rcu_set(&cpuas->memory_dispatch, d);
2948 tlb_flush(cpuas->cpu);
2949 }
2950
2951 static void memory_map_init(void)
2952 {
2953 system_memory = g_malloc(sizeof(*system_memory));
2954
2955 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2956 address_space_init(&address_space_memory, system_memory, "memory");
2957
2958 system_io = g_malloc(sizeof(*system_io));
2959 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2960 65536);
2961 address_space_init(&address_space_io, system_io, "I/O");
2962 }
2963
2964 MemoryRegion *get_system_memory(void)
2965 {
2966 return system_memory;
2967 }
2968
2969 MemoryRegion *get_system_io(void)
2970 {
2971 return system_io;
2972 }
2973
2974 #endif /* !defined(CONFIG_USER_ONLY) */
2975
2976 /* physical memory access (slow version, mainly for debug) */
2977 #if defined(CONFIG_USER_ONLY)
2978 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2979 void *ptr, target_ulong len, bool is_write)
2980 {
2981 int flags;
2982 target_ulong l, page;
2983 void * p;
2984 uint8_t *buf = ptr;
2985
2986 while (len > 0) {
2987 page = addr & TARGET_PAGE_MASK;
2988 l = (page + TARGET_PAGE_SIZE) - addr;
2989 if (l > len)
2990 l = len;
2991 flags = page_get_flags(page);
2992 if (!(flags & PAGE_VALID))
2993 return -1;
2994 if (is_write) {
2995 if (!(flags & PAGE_WRITE))
2996 return -1;
2997 /* XXX: this code should not depend on lock_user */
2998 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2999 return -1;
3000 memcpy(p, buf, l);
3001 unlock_user(p, addr, l);
3002 } else {
3003 if (!(flags & PAGE_READ))
3004 return -1;
3005 /* XXX: this code should not depend on lock_user */
3006 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3007 return -1;
3008 memcpy(buf, p, l);
3009 unlock_user(p, addr, 0);
3010 }
3011 len -= l;
3012 buf += l;
3013 addr += l;
3014 }
3015 return 0;
3016 }
3017
3018 #else
3019
3020 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
3021 hwaddr length)
3022 {
3023 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
3024 addr += memory_region_get_ram_addr(mr);
3025
3026 /* No early return if dirty_log_mask is or becomes 0, because
3027 * cpu_physical_memory_set_dirty_range will still call
3028 * xen_modified_memory.
3029 */
3030 if (dirty_log_mask) {
3031 dirty_log_mask =
3032 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
3033 }
3034 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
3035 assert(tcg_enabled());
3036 tb_invalidate_phys_range(addr, addr + length);
3037 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
3038 }
3039 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
3040 }
3041
3042 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
3043 {
3044 /*
3045 * In principle this function would work on other memory region types too,
3046 * but the ROM device use case is the only one where this operation is
3047 * necessary. Other memory regions should use the
3048 * address_space_read/write() APIs.
3049 */
3050 assert(memory_region_is_romd(mr));
3051
3052 invalidate_and_set_dirty(mr, addr, size);
3053 }
3054
3055 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
3056 {
3057 unsigned access_size_max = mr->ops->valid.max_access_size;
3058
3059 /* Regions are assumed to support 1-4 byte accesses unless
3060 otherwise specified. */
3061 if (access_size_max == 0) {
3062 access_size_max = 4;
3063 }
3064
3065 /* Bound the maximum access by the alignment of the address. */
3066 if (!mr->ops->impl.unaligned) {
3067 unsigned align_size_max = addr & -addr;
3068 if (align_size_max != 0 && align_size_max < access_size_max) {
3069 access_size_max = align_size_max;
3070 }
3071 }
3072
3073 /* Don't attempt accesses larger than the maximum. */
3074 if (l > access_size_max) {
3075 l = access_size_max;
3076 }
3077 l = pow2floor(l);
3078
3079 return l;
3080 }
3081
3082 static bool prepare_mmio_access(MemoryRegion *mr)
3083 {
3084 bool unlocked = !qemu_mutex_iothread_locked();
3085 bool release_lock = false;
3086
3087 if (unlocked && mr->global_locking) {
3088 qemu_mutex_lock_iothread();
3089 unlocked = false;
3090 release_lock = true;
3091 }
3092 if (mr->flush_coalesced_mmio) {
3093 if (unlocked) {
3094 qemu_mutex_lock_iothread();
3095 }
3096 qemu_flush_coalesced_mmio_buffer();
3097 if (unlocked) {
3098 qemu_mutex_unlock_iothread();
3099 }
3100 }
3101
3102 return release_lock;
3103 }
3104
3105 /* Called within RCU critical section. */
3106 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3107 MemTxAttrs attrs,
3108 const void *ptr,
3109 hwaddr len, hwaddr addr1,
3110 hwaddr l, MemoryRegion *mr)
3111 {
3112 uint8_t *ram_ptr;
3113 uint64_t val;
3114 MemTxResult result = MEMTX_OK;
3115 bool release_lock = false;
3116 const uint8_t *buf = ptr;
3117
3118 for (;;) {
3119 if (!memory_access_is_direct(mr, true)) {
3120 release_lock |= prepare_mmio_access(mr);
3121 l = memory_access_size(mr, l, addr1);
3122 /* XXX: could force current_cpu to NULL to avoid
3123 potential bugs */
3124 val = ldn_he_p(buf, l);
3125 result |= memory_region_dispatch_write(mr, addr1, val,
3126 size_memop(l), attrs);
3127 } else {
3128 /* RAM case */
3129 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3130 memcpy(ram_ptr, buf, l);
3131 invalidate_and_set_dirty(mr, addr1, l);
3132 }
3133
3134 if (release_lock) {
3135 qemu_mutex_unlock_iothread();
3136 release_lock = false;
3137 }
3138
3139 len -= l;
3140 buf += l;
3141 addr += l;
3142
3143 if (!len) {
3144 break;
3145 }
3146
3147 l = len;
3148 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3149 }
3150
3151 return result;
3152 }
3153
3154 /* Called from RCU critical section. */
3155 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3156 const void *buf, hwaddr len)
3157 {
3158 hwaddr l;
3159 hwaddr addr1;
3160 MemoryRegion *mr;
3161 MemTxResult result = MEMTX_OK;
3162
3163 l = len;
3164 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
3165 result = flatview_write_continue(fv, addr, attrs, buf, len,
3166 addr1, l, mr);
3167
3168 return result;
3169 }
3170
3171 /* Called within RCU critical section. */
3172 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3173 MemTxAttrs attrs, void *ptr,
3174 hwaddr len, hwaddr addr1, hwaddr l,
3175 MemoryRegion *mr)
3176 {
3177 uint8_t *ram_ptr;
3178 uint64_t val;
3179 MemTxResult result = MEMTX_OK;
3180 bool release_lock = false;
3181 uint8_t *buf = ptr;
3182
3183 for (;;) {
3184 if (!memory_access_is_direct(mr, false)) {
3185 /* I/O case */
3186 release_lock |= prepare_mmio_access(mr);
3187 l = memory_access_size(mr, l, addr1);
3188 result |= memory_region_dispatch_read(mr, addr1, &val,
3189 size_memop(l), attrs);
3190 stn_he_p(buf, l, val);
3191 } else {
3192 /* RAM case */
3193 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3194 memcpy(buf, ram_ptr, l);
3195 }
3196
3197 if (release_lock) {
3198 qemu_mutex_unlock_iothread();
3199 release_lock = false;
3200 }
3201
3202 len -= l;
3203 buf += l;
3204 addr += l;
3205
3206 if (!len) {
3207 break;
3208 }
3209
3210 l = len;
3211 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3212 }
3213
3214 return result;
3215 }
3216
3217 /* Called from RCU critical section. */
3218 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3219 MemTxAttrs attrs, void *buf, hwaddr len)
3220 {
3221 hwaddr l;
3222 hwaddr addr1;
3223 MemoryRegion *mr;
3224
3225 l = len;
3226 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
3227 return flatview_read_continue(fv, addr, attrs, buf, len,
3228 addr1, l, mr);
3229 }
3230
3231 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3232 MemTxAttrs attrs, void *buf, hwaddr len)
3233 {
3234 MemTxResult result = MEMTX_OK;
3235 FlatView *fv;
3236
3237 if (len > 0) {
3238 RCU_READ_LOCK_GUARD();
3239 fv = address_space_to_flatview(as);
3240 result = flatview_read(fv, addr, attrs, buf, len);
3241 }
3242
3243 return result;
3244 }
3245
3246 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3247 MemTxAttrs attrs,
3248 const void *buf, hwaddr len)
3249 {
3250 MemTxResult result = MEMTX_OK;
3251 FlatView *fv;
3252
3253 if (len > 0) {
3254 RCU_READ_LOCK_GUARD();
3255 fv = address_space_to_flatview(as);
3256 result = flatview_write(fv, addr, attrs, buf, len);
3257 }
3258
3259 return result;
3260 }
3261
3262 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3263 void *buf, hwaddr len, bool is_write)
3264 {
3265 if (is_write) {
3266 return address_space_write(as, addr, attrs, buf, len);
3267 } else {
3268 return address_space_read_full(as, addr, attrs, buf, len);
3269 }
3270 }
3271
3272 void cpu_physical_memory_rw(hwaddr addr, void *buf,
3273 hwaddr len, bool is_write)
3274 {
3275 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3276 buf, len, is_write);
3277 }
3278
3279 enum write_rom_type {
3280 WRITE_DATA,
3281 FLUSH_CACHE,
3282 };
3283
3284 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
3285 hwaddr addr,
3286 MemTxAttrs attrs,
3287 const void *ptr,
3288 hwaddr len,
3289 enum write_rom_type type)
3290 {
3291 hwaddr l;
3292 uint8_t *ram_ptr;
3293 hwaddr addr1;
3294 MemoryRegion *mr;
3295 const uint8_t *buf = ptr;
3296
3297 RCU_READ_LOCK_GUARD();
3298 while (len > 0) {
3299 l = len;
3300 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
3301
3302 if (!(memory_region_is_ram(mr) ||
3303 memory_region_is_romd(mr))) {
3304 l = memory_access_size(mr, l, addr1);
3305 } else {
3306 /* ROM/RAM case */
3307 ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3308 switch (type) {
3309 case WRITE_DATA:
3310 memcpy(ram_ptr, buf, l);
3311 invalidate_and_set_dirty(mr, addr1, l);
3312 break;
3313 case FLUSH_CACHE:
3314 flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l);
3315 break;
3316 }
3317 }
3318 len -= l;
3319 buf += l;
3320 addr += l;
3321 }
3322 return MEMTX_OK;
3323 }
3324
3325 /* used for ROM loading : can write in RAM and ROM */
3326 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
3327 MemTxAttrs attrs,
3328 const void *buf, hwaddr len)
3329 {
3330 return address_space_write_rom_internal(as, addr, attrs,
3331 buf, len, WRITE_DATA);
3332 }
3333
3334 void cpu_flush_icache_range(hwaddr start, hwaddr len)
3335 {
3336 /*
3337 * This function should do the same thing as an icache flush that was
3338 * triggered from within the guest. For TCG we are always cache coherent,
3339 * so there is no need to flush anything. For KVM / Xen we need to flush
3340 * the host's instruction cache at least.
3341 */
3342 if (tcg_enabled()) {
3343 return;
3344 }
3345
3346 address_space_write_rom_internal(&address_space_memory,
3347 start, MEMTXATTRS_UNSPECIFIED,
3348 NULL, len, FLUSH_CACHE);
3349 }
3350
3351 typedef struct {
3352 MemoryRegion *mr;
3353 void *buffer;
3354 hwaddr addr;
3355 hwaddr len;
3356 bool in_use;
3357 } BounceBuffer;
3358
3359 static BounceBuffer bounce;
3360
3361 typedef struct MapClient {
3362 QEMUBH *bh;
3363 QLIST_ENTRY(MapClient) link;
3364 } MapClient;
3365
3366 QemuMutex map_client_list_lock;
3367 static QLIST_HEAD(, MapClient) map_client_list
3368 = QLIST_HEAD_INITIALIZER(map_client_list);
3369
3370 static void cpu_unregister_map_client_do(MapClient *client)
3371 {
3372 QLIST_REMOVE(client, link);
3373 g_free(client);
3374 }
3375
3376 static void cpu_notify_map_clients_locked(void)
3377 {
3378 MapClient *client;
3379
3380 while (!QLIST_EMPTY(&map_client_list)) {
3381 client = QLIST_FIRST(&map_client_list);
3382 qemu_bh_schedule(client->bh);
3383 cpu_unregister_map_client_do(client);
3384 }
3385 }
3386
3387 void cpu_register_map_client(QEMUBH *bh)
3388 {
3389 MapClient *client = g_malloc(sizeof(*client));
3390
3391 qemu_mutex_lock(&map_client_list_lock);
3392 client->bh = bh;
3393 QLIST_INSERT_HEAD(&map_client_list, client, link);
3394 if (!atomic_read(&bounce.in_use)) {
3395 cpu_notify_map_clients_locked();
3396 }
3397 qemu_mutex_unlock(&map_client_list_lock);
3398 }
3399
3400 void cpu_exec_init_all(void)
3401 {
3402 qemu_mutex_init(&ram_list.mutex);
3403 /* The data structures we set up here depend on knowing the page size,
3404 * so no more changes can be made after this point.
3405 * In an ideal world, nothing we did before we had finished the
3406 * machine setup would care about the target page size, and we could
3407 * do this much later, rather than requiring board models to state
3408 * up front what their requirements are.
3409 */
3410 finalize_target_page_bits();
3411 io_mem_init();
3412 memory_map_init();
3413 qemu_mutex_init(&map_client_list_lock);
3414 }
3415
3416 void cpu_unregister_map_client(QEMUBH *bh)
3417 {
3418 MapClient *client;
3419
3420 qemu_mutex_lock(&map_client_list_lock);
3421 QLIST_FOREACH(client, &map_client_list, link) {
3422 if (client->bh == bh) {
3423 cpu_unregister_map_client_do(client);
3424 break;
3425 }
3426 }
3427 qemu_mutex_unlock(&map_client_list_lock);
3428 }
3429
3430 static void cpu_notify_map_clients(void)
3431 {
3432 qemu_mutex_lock(&map_client_list_lock);
3433 cpu_notify_map_clients_locked();
3434 qemu_mutex_unlock(&map_client_list_lock);
3435 }
3436
3437 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
3438 bool is_write, MemTxAttrs attrs)
3439 {
3440 MemoryRegion *mr;
3441 hwaddr l, xlat;
3442
3443 while (len > 0) {
3444 l = len;
3445 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3446 if (!memory_access_is_direct(mr, is_write)) {
3447 l = memory_access_size(mr, l, addr);
3448 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3449 return false;
3450 }
3451 }
3452
3453 len -= l;
3454 addr += l;
3455 }
3456 return true;
3457 }
3458
3459 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3460 hwaddr len, bool is_write,
3461 MemTxAttrs attrs)
3462 {
3463 FlatView *fv;
3464 bool result;
3465
3466 RCU_READ_LOCK_GUARD();
3467 fv = address_space_to_flatview(as);
3468 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3469 return result;
3470 }
3471
3472 static hwaddr
3473 flatview_extend_translation(FlatView *fv, hwaddr addr,
3474 hwaddr target_len,
3475 MemoryRegion *mr, hwaddr base, hwaddr len,
3476 bool is_write, MemTxAttrs attrs)
3477 {
3478 hwaddr done = 0;
3479 hwaddr xlat;
3480 MemoryRegion *this_mr;
3481
3482 for (;;) {
3483 target_len -= len;
3484 addr += len;
3485 done += len;
3486 if (target_len == 0) {
3487 return done;
3488 }
3489
3490 len = target_len;
3491 this_mr = flatview_translate(fv, addr, &xlat,
3492 &len, is_write, attrs);
3493 if (this_mr != mr || xlat != base + done) {
3494 return done;
3495 }
3496 }
3497 }
3498
3499 /* Map a physical memory region into a host virtual address.
3500 * May map a subset of the requested range, given by and returned in *plen.
3501 * May return NULL if resources needed to perform the mapping are exhausted.
3502 * Use only for reads OR writes - not for read-modify-write operations.
3503 * Use cpu_register_map_client() to know when retrying the map operation is
3504 * likely to succeed.
3505 */
3506 void *address_space_map(AddressSpace *as,
3507 hwaddr addr,
3508 hwaddr *plen,
3509 bool is_write,
3510 MemTxAttrs attrs)
3511 {
3512 hwaddr len = *plen;
3513 hwaddr l, xlat;
3514 MemoryRegion *mr;
3515 void *ptr;
3516 FlatView *fv;
3517
3518 if (len == 0) {
3519 return NULL;
3520 }
3521
3522 l = len;
3523 RCU_READ_LOCK_GUARD();
3524 fv = address_space_to_flatview(as);
3525 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3526
3527 if (!memory_access_is_direct(mr, is_write)) {
3528 if (atomic_xchg(&bounce.in_use, true)) {
3529 return NULL;
3530 }
3531 /* Avoid unbounded allocations */
3532 l = MIN(l, TARGET_PAGE_SIZE);
3533 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3534 bounce.addr = addr;
3535 bounce.len = l;
3536
3537 memory_region_ref(mr);
3538 bounce.mr = mr;
3539 if (!is_write) {
3540 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3541 bounce.buffer, l);
3542 }
3543
3544 *plen = l;
3545 return bounce.buffer;
3546 }
3547
3548
3549 memory_region_ref(mr);
3550 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3551 l, is_write, attrs);
3552 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3553
3554 return ptr;
3555 }
3556
3557 /* Unmaps a memory region previously mapped by address_space_map().
3558 * Will also mark the memory as dirty if is_write is true. access_len gives
3559 * the amount of memory that was actually read or written by the caller.
3560 */
3561 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3562 bool is_write, hwaddr access_len)
3563 {
3564 if (buffer != bounce.buffer) {
3565 MemoryRegion *mr;
3566 ram_addr_t addr1;
3567
3568 mr = memory_region_from_host(buffer, &addr1);
3569 assert(mr != NULL);
3570 if (is_write) {
3571 invalidate_and_set_dirty(mr, addr1, access_len);
3572 }
3573 if (xen_enabled()) {
3574 xen_invalidate_map_cache_entry(buffer);
3575 }
3576 memory_region_unref(mr);
3577 return;
3578 }
3579 if (is_write) {
3580 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3581 bounce.buffer, access_len);
3582 }
3583 qemu_vfree(bounce.buffer);