cirrus: fix off-by-one in cirrus_bitblt_rop_bkwd_transp_*_16
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "tcg.h"
28 #include "hw/qdev-core.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
50
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <fcntl.h>
53 #include <linux/falloc.h>
54 #endif
55
56 #endif
57 #include "exec/cpu-all.h"
58 #include "qemu/rcu_queue.h"
59 #include "qemu/main-loop.h"
60 #include "translate-all.h"
61 #include "sysemu/replay.h"
62
63 #include "exec/memory-internal.h"
64 #include "exec/ram_addr.h"
65 #include "exec/log.h"
66
67 #include "migration/vmstate.h"
68
69 #include "qemu/range.h"
70 #ifndef _WIN32
71 #include "qemu/mmap-alloc.h"
72 #endif
73
74 //#define DEBUG_SUBPAGE
75
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
79 */
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
81
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
84
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
87
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
90
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
93
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
96
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
99 */
100 #define RAM_RESIZEABLE (1 << 2)
101
102 #endif
103
104 #ifdef TARGET_PAGE_BITS_VARY
105 int target_page_bits;
106 bool target_page_bits_decided;
107 #endif
108
109 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
110 /* current CPU in the current thread. It is only valid inside
111 cpu_exec() */
112 __thread CPUState *current_cpu;
113 /* 0 = Do not count executed instructions.
114 1 = Precise instruction counting.
115 2 = Adaptive rate instruction counting. */
116 int use_icount;
117
118 bool set_preferred_target_page_bits(int bits)
119 {
120 /* The target page size is the lowest common denominator for all
121 * the CPUs in the system, so we can only make it smaller, never
122 * larger. And we can't make it smaller once we've committed to
123 * a particular size.
124 */
125 #ifdef TARGET_PAGE_BITS_VARY
126 assert(bits >= TARGET_PAGE_BITS_MIN);
127 if (target_page_bits == 0 || target_page_bits > bits) {
128 if (target_page_bits_decided) {
129 return false;
130 }
131 target_page_bits = bits;
132 }
133 #endif
134 return true;
135 }
136
137 #if !defined(CONFIG_USER_ONLY)
138
139 static void finalize_target_page_bits(void)
140 {
141 #ifdef TARGET_PAGE_BITS_VARY
142 if (target_page_bits == 0) {
143 target_page_bits = TARGET_PAGE_BITS_MIN;
144 }
145 target_page_bits_decided = true;
146 #endif
147 }
148
149 typedef struct PhysPageEntry PhysPageEntry;
150
151 struct PhysPageEntry {
152 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
153 uint32_t skip : 6;
154 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
155 uint32_t ptr : 26;
156 };
157
158 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
159
160 /* Size of the L2 (and L3, etc) page tables. */
161 #define ADDR_SPACE_BITS 64
162
163 #define P_L2_BITS 9
164 #define P_L2_SIZE (1 << P_L2_BITS)
165
166 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
167
168 typedef PhysPageEntry Node[P_L2_SIZE];
169
170 typedef struct PhysPageMap {
171 struct rcu_head rcu;
172
173 unsigned sections_nb;
174 unsigned sections_nb_alloc;
175 unsigned nodes_nb;
176 unsigned nodes_nb_alloc;
177 Node *nodes;
178 MemoryRegionSection *sections;
179 } PhysPageMap;
180
181 struct AddressSpaceDispatch {
182 struct rcu_head rcu;
183
184 MemoryRegionSection *mru_section;
185 /* This is a multi-level map on the physical address space.
186 * The bottom level has pointers to MemoryRegionSections.
187 */
188 PhysPageEntry phys_map;
189 PhysPageMap map;
190 AddressSpace *as;
191 };
192
193 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
194 typedef struct subpage_t {
195 MemoryRegion iomem;
196 AddressSpace *as;
197 hwaddr base;
198 uint16_t sub_section[];
199 } subpage_t;
200
201 #define PHYS_SECTION_UNASSIGNED 0
202 #define PHYS_SECTION_NOTDIRTY 1
203 #define PHYS_SECTION_ROM 2
204 #define PHYS_SECTION_WATCH 3
205
206 static void io_mem_init(void);
207 static void memory_map_init(void);
208 static void tcg_commit(MemoryListener *listener);
209
210 static MemoryRegion io_mem_watch;
211
212 /**
213 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
214 * @cpu: the CPU whose AddressSpace this is
215 * @as: the AddressSpace itself
216 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
217 * @tcg_as_listener: listener for tracking changes to the AddressSpace
218 */
219 struct CPUAddressSpace {
220 CPUState *cpu;
221 AddressSpace *as;
222 struct AddressSpaceDispatch *memory_dispatch;
223 MemoryListener tcg_as_listener;
224 };
225
226 #endif
227
228 #if !defined(CONFIG_USER_ONLY)
229
230 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
231 {
232 static unsigned alloc_hint = 16;
233 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
234 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
235 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
236 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
237 alloc_hint = map->nodes_nb_alloc;
238 }
239 }
240
241 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
242 {
243 unsigned i;
244 uint32_t ret;
245 PhysPageEntry e;
246 PhysPageEntry *p;
247
248 ret = map->nodes_nb++;
249 p = map->nodes[ret];
250 assert(ret != PHYS_MAP_NODE_NIL);
251 assert(ret != map->nodes_nb_alloc);
252
253 e.skip = leaf ? 0 : 1;
254 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
255 for (i = 0; i < P_L2_SIZE; ++i) {
256 memcpy(&p[i], &e, sizeof(e));
257 }
258 return ret;
259 }
260
261 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
262 hwaddr *index, hwaddr *nb, uint16_t leaf,
263 int level)
264 {
265 PhysPageEntry *p;
266 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
267
268 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
269 lp->ptr = phys_map_node_alloc(map, level == 0);
270 }
271 p = map->nodes[lp->ptr];
272 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
273
274 while (*nb && lp < &p[P_L2_SIZE]) {
275 if ((*index & (step - 1)) == 0 && *nb >= step) {
276 lp->skip = 0;
277 lp->ptr = leaf;
278 *index += step;
279 *nb -= step;
280 } else {
281 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
282 }
283 ++lp;
284 }
285 }
286
287 static void phys_page_set(AddressSpaceDispatch *d,
288 hwaddr index, hwaddr nb,
289 uint16_t leaf)
290 {
291 /* Wildly overreserve - it doesn't matter much. */
292 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
293
294 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
295 }
296
297 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
298 * and update our entry so we can skip it and go directly to the destination.
299 */
300 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
301 {
302 unsigned valid_ptr = P_L2_SIZE;
303 int valid = 0;
304 PhysPageEntry *p;
305 int i;
306
307 if (lp->ptr == PHYS_MAP_NODE_NIL) {
308 return;
309 }
310
311 p = nodes[lp->ptr];
312 for (i = 0; i < P_L2_SIZE; i++) {
313 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
314 continue;
315 }
316
317 valid_ptr = i;
318 valid++;
319 if (p[i].skip) {
320 phys_page_compact(&p[i], nodes);
321 }
322 }
323
324 /* We can only compress if there's only one child. */
325 if (valid != 1) {
326 return;
327 }
328
329 assert(valid_ptr < P_L2_SIZE);
330
331 /* Don't compress if it won't fit in the # of bits we have. */
332 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
333 return;
334 }
335
336 lp->ptr = p[valid_ptr].ptr;
337 if (!p[valid_ptr].skip) {
338 /* If our only child is a leaf, make this a leaf. */
339 /* By design, we should have made this node a leaf to begin with so we
340 * should never reach here.
341 * But since it's so simple to handle this, let's do it just in case we
342 * change this rule.
343 */
344 lp->skip = 0;
345 } else {
346 lp->skip += p[valid_ptr].skip;
347 }
348 }
349
350 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
351 {
352 if (d->phys_map.skip) {
353 phys_page_compact(&d->phys_map, d->map.nodes);
354 }
355 }
356
357 static inline bool section_covers_addr(const MemoryRegionSection *section,
358 hwaddr addr)
359 {
360 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
361 * the section must cover the entire address space.
362 */
363 return int128_gethi(section->size) ||
364 range_covers_byte(section->offset_within_address_space,
365 int128_getlo(section->size), addr);
366 }
367
368 static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr,
369 Node *nodes, MemoryRegionSection *sections)
370 {
371 PhysPageEntry *p;
372 hwaddr index = addr >> TARGET_PAGE_BITS;
373 int i;
374
375 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
376 if (lp.ptr == PHYS_MAP_NODE_NIL) {
377 return &sections[PHYS_SECTION_UNASSIGNED];
378 }
379 p = nodes[lp.ptr];
380 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
381 }
382
383 if (section_covers_addr(&sections[lp.ptr], addr)) {
384 return &sections[lp.ptr];
385 } else {
386 return &sections[PHYS_SECTION_UNASSIGNED];
387 }
388 }
389
390 bool memory_region_is_unassigned(MemoryRegion *mr)
391 {
392 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
393 && mr != &io_mem_watch;
394 }
395
396 /* Called from RCU critical section */
397 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
398 hwaddr addr,
399 bool resolve_subpage)
400 {
401 MemoryRegionSection *section = atomic_read(&d->mru_section);
402 subpage_t *subpage;
403 bool update;
404
405 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
406 section_covers_addr(section, addr)) {
407 update = false;
408 } else {
409 section = phys_page_find(d->phys_map, addr, d->map.nodes,
410 d->map.sections);
411 update = true;
412 }
413 if (resolve_subpage && section->mr->subpage) {
414 subpage = container_of(section->mr, subpage_t, iomem);
415 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
416 }
417 if (update) {
418 atomic_set(&d->mru_section, section);
419 }
420 return section;
421 }
422
423 /* Called from RCU critical section */
424 static MemoryRegionSection *
425 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
426 hwaddr *plen, bool resolve_subpage)
427 {
428 MemoryRegionSection *section;
429 MemoryRegion *mr;
430 Int128 diff;
431
432 section = address_space_lookup_region(d, addr, resolve_subpage);
433 /* Compute offset within MemoryRegionSection */
434 addr -= section->offset_within_address_space;
435
436 /* Compute offset within MemoryRegion */
437 *xlat = addr + section->offset_within_region;
438
439 mr = section->mr;
440
441 /* MMIO registers can be expected to perform full-width accesses based only
442 * on their address, without considering adjacent registers that could
443 * decode to completely different MemoryRegions. When such registers
444 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
445 * regions overlap wildly. For this reason we cannot clamp the accesses
446 * here.
447 *
448 * If the length is small (as is the case for address_space_ldl/stl),
449 * everything works fine. If the incoming length is large, however,
450 * the caller really has to do the clamping through memory_access_size.
451 */
452 if (memory_region_is_ram(mr)) {
453 diff = int128_sub(section->size, int128_make64(addr));
454 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
455 }
456 return section;
457 }
458
459 /* Called from RCU critical section */
460 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
461 bool is_write)
462 {
463 IOMMUTLBEntry iotlb = {0};
464 MemoryRegionSection *section;
465 MemoryRegion *mr;
466
467 for (;;) {
468 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
469 section = address_space_lookup_region(d, addr, false);
470 addr = addr - section->offset_within_address_space
471 + section->offset_within_region;
472 mr = section->mr;
473
474 if (!mr->iommu_ops) {
475 break;
476 }
477
478 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
479 if (!(iotlb.perm & (1 << is_write))) {
480 iotlb.target_as = NULL;
481 break;
482 }
483
484 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
485 | (addr & iotlb.addr_mask));
486 as = iotlb.target_as;
487 }
488
489 return iotlb;
490 }
491
492 /* Called from RCU critical section */
493 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
494 hwaddr *xlat, hwaddr *plen,
495 bool is_write)
496 {
497 IOMMUTLBEntry iotlb;
498 MemoryRegionSection *section;
499 MemoryRegion *mr;
500
501 for (;;) {
502 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
503 section = address_space_translate_internal(d, addr, &addr, plen, true);
504 mr = section->mr;
505
506 if (!mr->iommu_ops) {
507 break;
508 }
509
510 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
511 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
512 | (addr & iotlb.addr_mask));
513 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
514 if (!(iotlb.perm & (1 << is_write))) {
515 mr = &io_mem_unassigned;
516 break;
517 }
518
519 as = iotlb.target_as;
520 }
521
522 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
523 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
524 *plen = MIN(page, *plen);
525 }
526
527 *xlat = addr;
528 return mr;
529 }
530
531 /* Called from RCU critical section */
532 MemoryRegionSection *
533 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
534 hwaddr *xlat, hwaddr *plen)
535 {
536 MemoryRegionSection *section;
537 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
538
539 section = address_space_translate_internal(d, addr, xlat, plen, false);
540
541 assert(!section->mr->iommu_ops);
542 return section;
543 }
544 #endif
545
546 #if !defined(CONFIG_USER_ONLY)
547
548 static int cpu_common_post_load(void *opaque, int version_id)
549 {
550 CPUState *cpu = opaque;
551
552 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
553 version_id is increased. */
554 cpu->interrupt_request &= ~0x01;
555 tlb_flush(cpu);
556
557 return 0;
558 }
559
560 static int cpu_common_pre_load(void *opaque)
561 {
562 CPUState *cpu = opaque;
563
564 cpu->exception_index = -1;
565
566 return 0;
567 }
568
569 static bool cpu_common_exception_index_needed(void *opaque)
570 {
571 CPUState *cpu = opaque;
572
573 return tcg_enabled() && cpu->exception_index != -1;
574 }
575
576 static const VMStateDescription vmstate_cpu_common_exception_index = {
577 .name = "cpu_common/exception_index",
578 .version_id = 1,
579 .minimum_version_id = 1,
580 .needed = cpu_common_exception_index_needed,
581 .fields = (VMStateField[]) {
582 VMSTATE_INT32(exception_index, CPUState),
583 VMSTATE_END_OF_LIST()
584 }
585 };
586
587 static bool cpu_common_crash_occurred_needed(void *opaque)
588 {
589 CPUState *cpu = opaque;
590
591 return cpu->crash_occurred;
592 }
593
594 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
595 .name = "cpu_common/crash_occurred",
596 .version_id = 1,
597 .minimum_version_id = 1,
598 .needed = cpu_common_crash_occurred_needed,
599 .fields = (VMStateField[]) {
600 VMSTATE_BOOL(crash_occurred, CPUState),
601 VMSTATE_END_OF_LIST()
602 }
603 };
604
605 const VMStateDescription vmstate_cpu_common = {
606 .name = "cpu_common",
607 .version_id = 1,
608 .minimum_version_id = 1,
609 .pre_load = cpu_common_pre_load,
610 .post_load = cpu_common_post_load,
611 .fields = (VMStateField[]) {
612 VMSTATE_UINT32(halted, CPUState),
613 VMSTATE_UINT32(interrupt_request, CPUState),
614 VMSTATE_END_OF_LIST()
615 },
616 .subsections = (const VMStateDescription*[]) {
617 &vmstate_cpu_common_exception_index,
618 &vmstate_cpu_common_crash_occurred,
619 NULL
620 }
621 };
622
623 #endif
624
625 CPUState *qemu_get_cpu(int index)
626 {
627 CPUState *cpu;
628
629 CPU_FOREACH(cpu) {
630 if (cpu->cpu_index == index) {
631 return cpu;
632 }
633 }
634
635 return NULL;
636 }
637
638 #if !defined(CONFIG_USER_ONLY)
639 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
640 {
641 CPUAddressSpace *newas;
642
643 /* Target code should have set num_ases before calling us */
644 assert(asidx < cpu->num_ases);
645
646 if (asidx == 0) {
647 /* address space 0 gets the convenience alias */
648 cpu->as = as;
649 }
650
651 /* KVM cannot currently support multiple address spaces. */
652 assert(asidx == 0 || !kvm_enabled());
653
654 if (!cpu->cpu_ases) {
655 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
656 }
657
658 newas = &cpu->cpu_ases[asidx];
659 newas->cpu = cpu;
660 newas->as = as;
661 if (tcg_enabled()) {
662 newas->tcg_as_listener.commit = tcg_commit;
663 memory_listener_register(&newas->tcg_as_listener, as);
664 }
665 }
666
667 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
668 {
669 /* Return the AddressSpace corresponding to the specified index */
670 return cpu->cpu_ases[asidx].as;
671 }
672 #endif
673
674 void cpu_exec_unrealizefn(CPUState *cpu)
675 {
676 CPUClass *cc = CPU_GET_CLASS(cpu);
677
678 cpu_list_remove(cpu);
679
680 if (cc->vmsd != NULL) {
681 vmstate_unregister(NULL, cc->vmsd, cpu);
682 }
683 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
684 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
685 }
686 }
687
688 void cpu_exec_initfn(CPUState *cpu)
689 {
690 cpu->as = NULL;
691 cpu->num_ases = 0;
692
693 #ifndef CONFIG_USER_ONLY
694 cpu->thread_id = qemu_get_thread_id();
695
696 /* This is a softmmu CPU object, so create a property for it
697 * so users can wire up its memory. (This can't go in qom/cpu.c
698 * because that file is compiled only once for both user-mode
699 * and system builds.) The default if no link is set up is to use
700 * the system address space.
701 */
702 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
703 (Object **)&cpu->memory,
704 qdev_prop_allow_set_link_before_realize,
705 OBJ_PROP_LINK_UNREF_ON_RELEASE,
706 &error_abort);
707 cpu->memory = system_memory;
708 object_ref(OBJECT(cpu->memory));
709 #endif
710 }
711
712 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
713 {
714 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
715
716 cpu_list_add(cpu);
717
718 #ifndef CONFIG_USER_ONLY
719 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
720 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
721 }
722 if (cc->vmsd != NULL) {
723 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
724 }
725 #endif
726 }
727
728 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
729 {
730 /* Flush the whole TB as this will not have race conditions
731 * even if we don't have proper locking yet.
732 * Ideally we would just invalidate the TBs for the
733 * specified PC.
734 */
735 tb_flush(cpu);
736 }
737
738 #if defined(CONFIG_USER_ONLY)
739 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
740
741 {
742 }
743
744 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
745 int flags)
746 {
747 return -ENOSYS;
748 }
749
750 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
751 {
752 }
753
754 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
755 int flags, CPUWatchpoint **watchpoint)
756 {
757 return -ENOSYS;
758 }
759 #else
760 /* Add a watchpoint. */
761 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
762 int flags, CPUWatchpoint **watchpoint)
763 {
764 CPUWatchpoint *wp;
765
766 /* forbid ranges which are empty or run off the end of the address space */
767 if (len == 0 || (addr + len - 1) < addr) {
768 error_report("tried to set invalid watchpoint at %"
769 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
770 return -EINVAL;
771 }
772 wp = g_malloc(sizeof(*wp));
773
774 wp->vaddr = addr;
775 wp->len = len;
776 wp->flags = flags;
777
778 /* keep all GDB-injected watchpoints in front */
779 if (flags & BP_GDB) {
780 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
781 } else {
782 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
783 }
784
785 tlb_flush_page(cpu, addr);
786
787 if (watchpoint)
788 *watchpoint = wp;
789 return 0;
790 }
791
792 /* Remove a specific watchpoint. */
793 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
794 int flags)
795 {
796 CPUWatchpoint *wp;
797
798 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
799 if (addr == wp->vaddr && len == wp->len
800 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
801 cpu_watchpoint_remove_by_ref(cpu, wp);
802 return 0;
803 }
804 }
805 return -ENOENT;
806 }
807
808 /* Remove a specific watchpoint by reference. */
809 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
810 {
811 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
812
813 tlb_flush_page(cpu, watchpoint->vaddr);
814
815 g_free(watchpoint);
816 }
817
818 /* Remove all matching watchpoints. */
819 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
820 {
821 CPUWatchpoint *wp, *next;
822
823 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
824 if (wp->flags & mask) {
825 cpu_watchpoint_remove_by_ref(cpu, wp);
826 }
827 }
828 }
829
830 /* Return true if this watchpoint address matches the specified
831 * access (ie the address range covered by the watchpoint overlaps
832 * partially or completely with the address range covered by the
833 * access).
834 */
835 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
836 vaddr addr,
837 vaddr len)
838 {
839 /* We know the lengths are non-zero, but a little caution is
840 * required to avoid errors in the case where the range ends
841 * exactly at the top of the address space and so addr + len
842 * wraps round to zero.
843 */
844 vaddr wpend = wp->vaddr + wp->len - 1;
845 vaddr addrend = addr + len - 1;
846
847 return !(addr > wpend || wp->vaddr > addrend);
848 }
849
850 #endif
851
852 /* Add a breakpoint. */
853 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
854 CPUBreakpoint **breakpoint)
855 {
856 CPUBreakpoint *bp;
857
858 bp = g_malloc(sizeof(*bp));
859
860 bp->pc = pc;
861 bp->flags = flags;
862
863 /* keep all GDB-injected breakpoints in front */
864 if (flags & BP_GDB) {
865 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
866 } else {
867 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
868 }
869
870 breakpoint_invalidate(cpu, pc);
871
872 if (breakpoint) {
873 *breakpoint = bp;
874 }
875 return 0;
876 }
877
878 /* Remove a specific breakpoint. */
879 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
880 {
881 CPUBreakpoint *bp;
882
883 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
884 if (bp->pc == pc && bp->flags == flags) {
885 cpu_breakpoint_remove_by_ref(cpu, bp);
886 return 0;
887 }
888 }
889 return -ENOENT;
890 }
891
892 /* Remove a specific breakpoint by reference. */
893 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
894 {
895 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
896
897 breakpoint_invalidate(cpu, breakpoint->pc);
898
899 g_free(breakpoint);
900 }
901
902 /* Remove all matching breakpoints. */
903 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
904 {
905 CPUBreakpoint *bp, *next;
906
907 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
908 if (bp->flags & mask) {
909 cpu_breakpoint_remove_by_ref(cpu, bp);
910 }
911 }
912 }
913
914 /* enable or disable single step mode. EXCP_DEBUG is returned by the
915 CPU loop after each instruction */
916 void cpu_single_step(CPUState *cpu, int enabled)
917 {
918 if (cpu->singlestep_enabled != enabled) {
919 cpu->singlestep_enabled = enabled;
920 if (kvm_enabled()) {
921 kvm_update_guest_debug(cpu, 0);
922 } else {
923 /* must flush all the translated code to avoid inconsistencies */
924 /* XXX: only flush what is necessary */
925 tb_flush(cpu);
926 }
927 }
928 }
929
930 void cpu_abort(CPUState *cpu, const char *fmt, ...)
931 {
932 va_list ap;
933 va_list ap2;
934
935 va_start(ap, fmt);
936 va_copy(ap2, ap);
937 fprintf(stderr, "qemu: fatal: ");
938 vfprintf(stderr, fmt, ap);
939 fprintf(stderr, "\n");
940 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
941 if (qemu_log_separate()) {
942 qemu_log_lock();
943 qemu_log("qemu: fatal: ");
944 qemu_log_vprintf(fmt, ap2);
945 qemu_log("\n");
946 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
947 qemu_log_flush();
948 qemu_log_unlock();
949 qemu_log_close();
950 }
951 va_end(ap2);
952 va_end(ap);
953 replay_finish();
954 #if defined(CONFIG_USER_ONLY)
955 {
956 struct sigaction act;
957 sigfillset(&act.sa_mask);
958 act.sa_handler = SIG_DFL;
959 sigaction(SIGABRT, &act, NULL);
960 }
961 #endif
962 abort();
963 }
964
965 #if !defined(CONFIG_USER_ONLY)
966 /* Called from RCU critical section */
967 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
968 {
969 RAMBlock *block;
970
971 block = atomic_rcu_read(&ram_list.mru_block);
972 if (block && addr - block->offset < block->max_length) {
973 return block;
974 }
975 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
976 if (addr - block->offset < block->max_length) {
977 goto found;
978 }
979 }
980
981 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
982 abort();
983
984 found:
985 /* It is safe to write mru_block outside the iothread lock. This
986 * is what happens:
987 *
988 * mru_block = xxx
989 * rcu_read_unlock()
990 * xxx removed from list
991 * rcu_read_lock()
992 * read mru_block
993 * mru_block = NULL;
994 * call_rcu(reclaim_ramblock, xxx);
995 * rcu_read_unlock()
996 *
997 * atomic_rcu_set is not needed here. The block was already published
998 * when it was placed into the list. Here we're just making an extra
999 * copy of the pointer.
1000 */
1001 ram_list.mru_block = block;
1002 return block;
1003 }
1004
1005 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1006 {
1007 CPUState *cpu;
1008 ram_addr_t start1;
1009 RAMBlock *block;
1010 ram_addr_t end;
1011
1012 end = TARGET_PAGE_ALIGN(start + length);
1013 start &= TARGET_PAGE_MASK;
1014
1015 rcu_read_lock();
1016 block = qemu_get_ram_block(start);
1017 assert(block == qemu_get_ram_block(end - 1));
1018 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1019 CPU_FOREACH(cpu) {
1020 tlb_reset_dirty(cpu, start1, length);
1021 }
1022 rcu_read_unlock();
1023 }
1024
1025 /* Note: start and end must be within the same ram block. */
1026 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1027 ram_addr_t length,
1028 unsigned client)
1029 {
1030 DirtyMemoryBlocks *blocks;
1031 unsigned long end, page;
1032 bool dirty = false;
1033
1034 if (length == 0) {
1035 return false;
1036 }
1037
1038 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1039 page = start >> TARGET_PAGE_BITS;
1040
1041 rcu_read_lock();
1042
1043 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1044
1045 while (page < end) {
1046 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1047 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1048 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1049
1050 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1051 offset, num);
1052 page += num;
1053 }
1054
1055 rcu_read_unlock();
1056
1057 if (dirty && tcg_enabled()) {
1058 tlb_reset_dirty_range_all(start, length);
1059 }
1060
1061 return dirty;
1062 }
1063
1064 /* Called from RCU critical section */
1065 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1066 MemoryRegionSection *section,
1067 target_ulong vaddr,
1068 hwaddr paddr, hwaddr xlat,
1069 int prot,
1070 target_ulong *address)
1071 {
1072 hwaddr iotlb;
1073 CPUWatchpoint *wp;
1074
1075 if (memory_region_is_ram(section->mr)) {
1076 /* Normal RAM. */
1077 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1078 if (!section->readonly) {
1079 iotlb |= PHYS_SECTION_NOTDIRTY;
1080 } else {
1081 iotlb |= PHYS_SECTION_ROM;
1082 }
1083 } else {
1084 AddressSpaceDispatch *d;
1085
1086 d = atomic_rcu_read(&section->address_space->dispatch);
1087 iotlb = section - d->map.sections;
1088 iotlb += xlat;
1089 }
1090
1091 /* Make accesses to pages with watchpoints go via the
1092 watchpoint trap routines. */
1093 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1094 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1095 /* Avoid trapping reads of pages with a write breakpoint. */
1096 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1097 iotlb = PHYS_SECTION_WATCH + paddr;
1098 *address |= TLB_MMIO;
1099 break;
1100 }
1101 }
1102 }
1103
1104 return iotlb;
1105 }
1106 #endif /* defined(CONFIG_USER_ONLY) */
1107
1108 #if !defined(CONFIG_USER_ONLY)
1109
1110 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1111 uint16_t section);
1112 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1113
1114 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1115 qemu_anon_ram_alloc;
1116
1117 /*
1118 * Set a custom physical guest memory alloator.
1119 * Accelerators with unusual needs may need this. Hopefully, we can
1120 * get rid of it eventually.
1121 */
1122 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1123 {
1124 phys_mem_alloc = alloc;
1125 }
1126
1127 static uint16_t phys_section_add(PhysPageMap *map,
1128 MemoryRegionSection *section)
1129 {
1130 /* The physical section number is ORed with a page-aligned
1131 * pointer to produce the iotlb entries. Thus it should
1132 * never overflow into the page-aligned value.
1133 */
1134 assert(map->sections_nb < TARGET_PAGE_SIZE);
1135
1136 if (map->sections_nb == map->sections_nb_alloc) {
1137 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1138 map->sections = g_renew(MemoryRegionSection, map->sections,
1139 map->sections_nb_alloc);
1140 }
1141 map->sections[map->sections_nb] = *section;
1142 memory_region_ref(section->mr);
1143 return map->sections_nb++;
1144 }
1145
1146 static void phys_section_destroy(MemoryRegion *mr)
1147 {
1148 bool have_sub_page = mr->subpage;
1149
1150 memory_region_unref(mr);
1151
1152 if (have_sub_page) {
1153 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1154 object_unref(OBJECT(&subpage->iomem));
1155 g_free(subpage);
1156 }
1157 }
1158
1159 static void phys_sections_free(PhysPageMap *map)
1160 {
1161 while (map->sections_nb > 0) {
1162 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1163 phys_section_destroy(section->mr);
1164 }
1165 g_free(map->sections);
1166 g_free(map->nodes);
1167 }
1168
1169 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1170 {
1171 subpage_t *subpage;
1172 hwaddr base = section->offset_within_address_space
1173 & TARGET_PAGE_MASK;
1174 MemoryRegionSection *existing = phys_page_find(d->phys_map, base,
1175 d->map.nodes, d->map.sections);
1176 MemoryRegionSection subsection = {
1177 .offset_within_address_space = base,
1178 .size = int128_make64(TARGET_PAGE_SIZE),
1179 };
1180 hwaddr start, end;
1181
1182 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1183
1184 if (!(existing->mr->subpage)) {
1185 subpage = subpage_init(d->as, base);
1186 subsection.address_space = d->as;
1187 subsection.mr = &subpage->iomem;
1188 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1189 phys_section_add(&d->map, &subsection));
1190 } else {
1191 subpage = container_of(existing->mr, subpage_t, iomem);
1192 }
1193 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1194 end = start + int128_get64(section->size) - 1;
1195 subpage_register(subpage, start, end,
1196 phys_section_add(&d->map, section));
1197 }
1198
1199
1200 static void register_multipage(AddressSpaceDispatch *d,
1201 MemoryRegionSection *section)
1202 {
1203 hwaddr start_addr = section->offset_within_address_space;
1204 uint16_t section_index = phys_section_add(&d->map, section);
1205 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1206 TARGET_PAGE_BITS));
1207
1208 assert(num_pages);
1209 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1210 }
1211
1212 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1213 {
1214 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1215 AddressSpaceDispatch *d = as->next_dispatch;
1216 MemoryRegionSection now = *section, remain = *section;
1217 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1218
1219 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1220 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1221 - now.offset_within_address_space;
1222
1223 now.size = int128_min(int128_make64(left), now.size);
1224 register_subpage(d, &now);
1225 } else {
1226 now.size = int128_zero();
1227 }
1228 while (int128_ne(remain.size, now.size)) {
1229 remain.size = int128_sub(remain.size, now.size);
1230 remain.offset_within_address_space += int128_get64(now.size);
1231 remain.offset_within_region += int128_get64(now.size);
1232 now = remain;
1233 if (int128_lt(remain.size, page_size)) {
1234 register_subpage(d, &now);
1235 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1236 now.size = page_size;
1237 register_subpage(d, &now);
1238 } else {
1239 now.size = int128_and(now.size, int128_neg(page_size));
1240 register_multipage(d, &now);
1241 }
1242 }
1243 }
1244
1245 void qemu_flush_coalesced_mmio_buffer(void)
1246 {
1247 if (kvm_enabled())
1248 kvm_flush_coalesced_mmio_buffer();
1249 }
1250
1251 void qemu_mutex_lock_ramlist(void)
1252 {
1253 qemu_mutex_lock(&ram_list.mutex);
1254 }
1255
1256 void qemu_mutex_unlock_ramlist(void)
1257 {
1258 qemu_mutex_unlock(&ram_list.mutex);
1259 }
1260
1261 #ifdef __linux__
1262 /*
1263 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1264 * may or may not name the same files / on the same filesystem now as
1265 * when we actually open and map them. Iterate over the file
1266 * descriptors instead, and use qemu_fd_getpagesize().
1267 */
1268 static int find_max_supported_pagesize(Object *obj, void *opaque)
1269 {
1270 char *mem_path;
1271 long *hpsize_min = opaque;
1272
1273 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1274 mem_path = object_property_get_str(obj, "mem-path", NULL);
1275 if (mem_path) {
1276 long hpsize = qemu_mempath_getpagesize(mem_path);
1277 if (hpsize < *hpsize_min) {
1278 *hpsize_min = hpsize;
1279 }
1280 } else {
1281 *hpsize_min = getpagesize();
1282 }
1283 }
1284
1285 return 0;
1286 }
1287
1288 long qemu_getrampagesize(void)
1289 {
1290 long hpsize = LONG_MAX;
1291 long mainrampagesize;
1292 Object *memdev_root;
1293
1294 if (mem_path) {
1295 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1296 } else {
1297 mainrampagesize = getpagesize();
1298 }
1299
1300 /* it's possible we have memory-backend objects with
1301 * hugepage-backed RAM. these may get mapped into system
1302 * address space via -numa parameters or memory hotplug
1303 * hooks. we want to take these into account, but we
1304 * also want to make sure these supported hugepage
1305 * sizes are applicable across the entire range of memory
1306 * we may boot from, so we take the min across all
1307 * backends, and assume normal pages in cases where a
1308 * backend isn't backed by hugepages.
1309 */
1310 memdev_root = object_resolve_path("/objects", NULL);
1311 if (memdev_root) {
1312 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1313 }
1314 if (hpsize == LONG_MAX) {
1315 /* No additional memory regions found ==> Report main RAM page size */
1316 return mainrampagesize;
1317 }
1318
1319 /* If NUMA is disabled or the NUMA nodes are not backed with a
1320 * memory-backend, then there is at least one node using "normal" RAM,
1321 * so if its page size is smaller we have got to report that size instead.
1322 */
1323 if (hpsize > mainrampagesize &&
1324 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1325 static bool warned;
1326 if (!warned) {
1327 error_report("Huge page support disabled (n/a for main memory).");
1328 warned = true;
1329 }
1330 return mainrampagesize;
1331 }
1332
1333 return hpsize;
1334 }
1335 #else
1336 long qemu_getrampagesize(void)
1337 {
1338 return getpagesize();
1339 }
1340 #endif
1341
1342 #ifdef __linux__
1343 static int64_t get_file_size(int fd)
1344 {
1345 int64_t size = lseek(fd, 0, SEEK_END);
1346 if (size < 0) {
1347 return -errno;
1348 }
1349 return size;
1350 }
1351
1352 static void *file_ram_alloc(RAMBlock *block,
1353 ram_addr_t memory,
1354 const char *path,
1355 Error **errp)
1356 {
1357 bool unlink_on_error = false;
1358 char *filename;
1359 char *sanitized_name;
1360 char *c;
1361 void *area = MAP_FAILED;
1362 int fd = -1;
1363 int64_t file_size;
1364
1365 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1366 error_setg(errp,
1367 "host lacks kvm mmu notifiers, -mem-path unsupported");
1368 return NULL;
1369 }
1370
1371 for (;;) {
1372 fd = open(path, O_RDWR);
1373 if (fd >= 0) {
1374 /* @path names an existing file, use it */
1375 break;
1376 }
1377 if (errno == ENOENT) {
1378 /* @path names a file that doesn't exist, create it */
1379 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1380 if (fd >= 0) {
1381 unlink_on_error = true;
1382 break;
1383 }
1384 } else if (errno == EISDIR) {
1385 /* @path names a directory, create a file there */
1386 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1387 sanitized_name = g_strdup(memory_region_name(block->mr));
1388 for (c = sanitized_name; *c != '\0'; c++) {
1389 if (*c == '/') {
1390 *c = '_';
1391 }
1392 }
1393
1394 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1395 sanitized_name);
1396 g_free(sanitized_name);
1397
1398 fd = mkstemp(filename);
1399 if (fd >= 0) {
1400 unlink(filename);
1401 g_free(filename);
1402 break;
1403 }
1404 g_free(filename);
1405 }
1406 if (errno != EEXIST && errno != EINTR) {
1407 error_setg_errno(errp, errno,
1408 "can't open backing store %s for guest RAM",
1409 path);
1410 goto error;
1411 }
1412 /*
1413 * Try again on EINTR and EEXIST. The latter happens when
1414 * something else creates the file between our two open().
1415 */
1416 }
1417
1418 block->page_size = qemu_fd_getpagesize(fd);
1419 block->mr->align = block->page_size;
1420 #if defined(__s390x__)
1421 if (kvm_enabled()) {
1422 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1423 }
1424 #endif
1425
1426 file_size = get_file_size(fd);
1427
1428 if (memory < block->page_size) {
1429 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1430 "or larger than page size 0x%zx",
1431 memory, block->page_size);
1432 goto error;
1433 }
1434
1435 if (file_size > 0 && file_size < memory) {
1436 error_setg(errp, "backing store %s size 0x%" PRIx64
1437 " does not match 'size' option 0x" RAM_ADDR_FMT,
1438 path, file_size, memory);
1439 goto error;
1440 }
1441
1442 memory = ROUND_UP(memory, block->page_size);
1443
1444 /*
1445 * ftruncate is not supported by hugetlbfs in older
1446 * hosts, so don't bother bailing out on errors.
1447 * If anything goes wrong with it under other filesystems,
1448 * mmap will fail.
1449 *
1450 * Do not truncate the non-empty backend file to avoid corrupting
1451 * the existing data in the file. Disabling shrinking is not
1452 * enough. For example, the current vNVDIMM implementation stores
1453 * the guest NVDIMM labels at the end of the backend file. If the
1454 * backend file is later extended, QEMU will not be able to find
1455 * those labels. Therefore, extending the non-empty backend file
1456 * is disabled as well.
1457 */
1458 if (!file_size && ftruncate(fd, memory)) {
1459 perror("ftruncate");
1460 }
1461
1462 area = qemu_ram_mmap(fd, memory, block->mr->align,
1463 block->flags & RAM_SHARED);
1464 if (area == MAP_FAILED) {
1465 error_setg_errno(errp, errno,
1466 "unable to map backing store for guest RAM");
1467 goto error;
1468 }
1469
1470 if (mem_prealloc) {
1471 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1472 if (errp && *errp) {
1473 goto error;
1474 }
1475 }
1476
1477 block->fd = fd;
1478 return area;
1479
1480 error:
1481 if (area != MAP_FAILED) {
1482 qemu_ram_munmap(area, memory);
1483 }
1484 if (unlink_on_error) {
1485 unlink(path);
1486 }
1487 if (fd != -1) {
1488 close(fd);
1489 }
1490 return NULL;
1491 }
1492 #endif
1493
1494 /* Called with the ramlist lock held. */
1495 static ram_addr_t find_ram_offset(ram_addr_t size)
1496 {
1497 RAMBlock *block, *next_block;
1498 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1499
1500 assert(size != 0); /* it would hand out same offset multiple times */
1501
1502 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1503 return 0;
1504 }
1505
1506 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1507 ram_addr_t end, next = RAM_ADDR_MAX;
1508
1509 end = block->offset + block->max_length;
1510
1511 QLIST_FOREACH_RCU(next_block, &ram_list.blocks, next) {
1512 if (next_block->offset >= end) {
1513 next = MIN(next, next_block->offset);
1514 }
1515 }
1516 if (next - end >= size && next - end < mingap) {
1517 offset = end;
1518 mingap = next - end;
1519 }
1520 }
1521
1522 if (offset == RAM_ADDR_MAX) {
1523 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1524 (uint64_t)size);
1525 abort();
1526 }
1527
1528 return offset;
1529 }
1530
1531 ram_addr_t last_ram_offset(void)
1532 {
1533 RAMBlock *block;
1534 ram_addr_t last = 0;
1535
1536 rcu_read_lock();
1537 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1538 last = MAX(last, block->offset + block->max_length);
1539 }
1540 rcu_read_unlock();
1541 return last;
1542 }
1543
1544 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1545 {
1546 int ret;
1547
1548 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1549 if (!machine_dump_guest_core(current_machine)) {
1550 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1551 if (ret) {
1552 perror("qemu_madvise");
1553 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1554 "but dump_guest_core=off specified\n");
1555 }
1556 }
1557 }
1558
1559 const char *qemu_ram_get_idstr(RAMBlock *rb)
1560 {
1561 return rb->idstr;
1562 }
1563
1564 bool qemu_ram_is_shared(RAMBlock *rb)
1565 {
1566 return rb->flags & RAM_SHARED;
1567 }
1568
1569 /* Called with iothread lock held. */
1570 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1571 {
1572 RAMBlock *block;
1573
1574 assert(new_block);
1575 assert(!new_block->idstr[0]);
1576
1577 if (dev) {
1578 char *id = qdev_get_dev_path(dev);
1579 if (id) {
1580 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1581 g_free(id);
1582 }
1583 }
1584 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1585
1586 rcu_read_lock();
1587 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1588 if (block != new_block &&
1589 !strcmp(block->idstr, new_block->idstr)) {
1590 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1591 new_block->idstr);
1592 abort();
1593 }
1594 }
1595 rcu_read_unlock();
1596 }
1597
1598 /* Called with iothread lock held. */
1599 void qemu_ram_unset_idstr(RAMBlock *block)
1600 {
1601 /* FIXME: arch_init.c assumes that this is not called throughout
1602 * migration. Ignore the problem since hot-unplug during migration
1603 * does not work anyway.
1604 */
1605 if (block) {
1606 memset(block->idstr, 0, sizeof(block->idstr));
1607 }
1608 }
1609
1610 size_t qemu_ram_pagesize(RAMBlock *rb)
1611 {
1612 return rb->page_size;
1613 }
1614
1615 /* Returns the largest size of page in use */
1616 size_t qemu_ram_pagesize_largest(void)
1617 {
1618 RAMBlock *block;
1619 size_t largest = 0;
1620
1621 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1622 largest = MAX(largest, qemu_ram_pagesize(block));
1623 }
1624
1625 return largest;
1626 }
1627
1628 static int memory_try_enable_merging(void *addr, size_t len)
1629 {
1630 if (!machine_mem_merge(current_machine)) {
1631 /* disabled by the user */
1632 return 0;
1633 }
1634
1635 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1636 }
1637
1638 /* Only legal before guest might have detected the memory size: e.g. on
1639 * incoming migration, or right after reset.
1640 *
1641 * As memory core doesn't know how is memory accessed, it is up to
1642 * resize callback to update device state and/or add assertions to detect
1643 * misuse, if necessary.
1644 */
1645 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1646 {
1647 assert(block);
1648
1649 newsize = HOST_PAGE_ALIGN(newsize);
1650
1651 if (block->used_length == newsize) {
1652 return 0;
1653 }
1654
1655 if (!(block->flags & RAM_RESIZEABLE)) {
1656 error_setg_errno(errp, EINVAL,
1657 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1658 " in != 0x" RAM_ADDR_FMT, block->idstr,
1659 newsize, block->used_length);
1660 return -EINVAL;
1661 }
1662
1663 if (block->max_length < newsize) {
1664 error_setg_errno(errp, EINVAL,
1665 "Length too large: %s: 0x" RAM_ADDR_FMT
1666 " > 0x" RAM_ADDR_FMT, block->idstr,
1667 newsize, block->max_length);
1668 return -EINVAL;
1669 }
1670
1671 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1672 block->used_length = newsize;
1673 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1674 DIRTY_CLIENTS_ALL);
1675 memory_region_set_size(block->mr, newsize);
1676 if (block->resized) {
1677 block->resized(block->idstr, newsize, block->host);
1678 }
1679 return 0;
1680 }
1681
1682 /* Called with ram_list.mutex held */
1683 static void dirty_memory_extend(ram_addr_t old_ram_size,
1684 ram_addr_t new_ram_size)
1685 {
1686 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1687 DIRTY_MEMORY_BLOCK_SIZE);
1688 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1689 DIRTY_MEMORY_BLOCK_SIZE);
1690 int i;
1691
1692 /* Only need to extend if block count increased */
1693 if (new_num_blocks <= old_num_blocks) {
1694 return;
1695 }
1696
1697 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1698 DirtyMemoryBlocks *old_blocks;
1699 DirtyMemoryBlocks *new_blocks;
1700 int j;
1701
1702 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1703 new_blocks = g_malloc(sizeof(*new_blocks) +
1704 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1705
1706 if (old_num_blocks) {
1707 memcpy(new_blocks->blocks, old_blocks->blocks,
1708 old_num_blocks * sizeof(old_blocks->blocks[0]));
1709 }
1710
1711 for (j = old_num_blocks; j < new_num_blocks; j++) {
1712 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1713 }
1714
1715 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1716
1717 if (old_blocks) {
1718 g_free_rcu(old_blocks, rcu);
1719 }
1720 }
1721 }
1722
1723 static void ram_block_add(RAMBlock *new_block, Error **errp)
1724 {
1725 RAMBlock *block;
1726 RAMBlock *last_block = NULL;
1727 ram_addr_t old_ram_size, new_ram_size;
1728 Error *err = NULL;
1729
1730 old_ram_size = last_ram_offset() >> TARGET_PAGE_BITS;
1731
1732 qemu_mutex_lock_ramlist();
1733 new_block->offset = find_ram_offset(new_block->max_length);
1734
1735 if (!new_block->host) {
1736 if (xen_enabled()) {
1737 xen_ram_alloc(new_block->offset, new_block->max_length,
1738 new_block->mr, &err);
1739 if (err) {
1740 error_propagate(errp, err);
1741 qemu_mutex_unlock_ramlist();
1742 return;
1743 }
1744 } else {
1745 new_block->host = phys_mem_alloc(new_block->max_length,
1746 &new_block->mr->align);
1747 if (!new_block->host) {
1748 error_setg_errno(errp, errno,
1749 "cannot set up guest memory '%s'",
1750 memory_region_name(new_block->mr));
1751 qemu_mutex_unlock_ramlist();
1752 return;
1753 }
1754 memory_try_enable_merging(new_block->host, new_block->max_length);
1755 }
1756 }
1757
1758 new_ram_size = MAX(old_ram_size,
1759 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1760 if (new_ram_size > old_ram_size) {
1761 migration_bitmap_extend(old_ram_size, new_ram_size);
1762 dirty_memory_extend(old_ram_size, new_ram_size);
1763 }
1764 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1765 * QLIST (which has an RCU-friendly variant) does not have insertion at
1766 * tail, so save the last element in last_block.
1767 */
1768 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1769 last_block = block;
1770 if (block->max_length < new_block->max_length) {
1771 break;
1772 }
1773 }
1774 if (block) {
1775 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1776 } else if (last_block) {
1777 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1778 } else { /* list is empty */
1779 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1780 }
1781 ram_list.mru_block = NULL;
1782
1783 /* Write list before version */
1784 smp_wmb();
1785 ram_list.version++;
1786 qemu_mutex_unlock_ramlist();
1787
1788 cpu_physical_memory_set_dirty_range(new_block->offset,
1789 new_block->used_length,
1790 DIRTY_CLIENTS_ALL);
1791
1792 if (new_block->host) {
1793 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1794 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1795 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1796 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1797 ram_block_notify_add(new_block->host, new_block->max_length);
1798 }
1799 }
1800
1801 #ifdef __linux__
1802 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1803 bool share, const char *mem_path,
1804 Error **errp)
1805 {
1806 RAMBlock *new_block;
1807 Error *local_err = NULL;
1808
1809 if (xen_enabled()) {
1810 error_setg(errp, "-mem-path not supported with Xen");
1811 return NULL;
1812 }
1813
1814 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1815 /*
1816 * file_ram_alloc() needs to allocate just like
1817 * phys_mem_alloc, but we haven't bothered to provide
1818 * a hook there.
1819 */
1820 error_setg(errp,
1821 "-mem-path not supported with this accelerator");
1822 return NULL;
1823 }
1824
1825 size = HOST_PAGE_ALIGN(size);
1826 new_block = g_malloc0(sizeof(*new_block));
1827 new_block->mr = mr;
1828 new_block->used_length = size;
1829 new_block->max_length = size;
1830 new_block->flags = share ? RAM_SHARED : 0;
1831 new_block->host = file_ram_alloc(new_block, size,
1832 mem_path, errp);
1833 if (!new_block->host) {
1834 g_free(new_block);
1835 return NULL;
1836 }
1837
1838 ram_block_add(new_block, &local_err);
1839 if (local_err) {
1840 g_free(new_block);
1841 error_propagate(errp, local_err);
1842 return NULL;
1843 }
1844 return new_block;
1845 }
1846 #endif
1847
1848 static
1849 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
1850 void (*resized)(const char*,
1851 uint64_t length,
1852 void *host),
1853 void *host, bool resizeable,
1854 MemoryRegion *mr, Error **errp)
1855 {
1856 RAMBlock *new_block;
1857 Error *local_err = NULL;
1858
1859 size = HOST_PAGE_ALIGN(size);
1860 max_size = HOST_PAGE_ALIGN(max_size);
1861 new_block = g_malloc0(sizeof(*new_block));
1862 new_block->mr = mr;
1863 new_block->resized = resized;
1864 new_block->used_length = size;
1865 new_block->max_length = max_size;
1866 assert(max_size >= size);
1867 new_block->fd = -1;
1868 new_block->page_size = getpagesize();
1869 new_block->host = host;
1870 if (host) {
1871 new_block->flags |= RAM_PREALLOC;
1872 }
1873 if (resizeable) {
1874 new_block->flags |= RAM_RESIZEABLE;
1875 }
1876 ram_block_add(new_block, &local_err);
1877 if (local_err) {
1878 g_free(new_block);
1879 error_propagate(errp, local_err);
1880 return NULL;
1881 }
1882 return new_block;
1883 }
1884
1885 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
1886 MemoryRegion *mr, Error **errp)
1887 {
1888 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
1889 }
1890
1891 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
1892 {
1893 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
1894 }
1895
1896 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
1897 void (*resized)(const char*,
1898 uint64_t length,
1899 void *host),
1900 MemoryRegion *mr, Error **errp)
1901 {
1902 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
1903 }
1904
1905 static void reclaim_ramblock(RAMBlock *block)
1906 {
1907 if (block->flags & RAM_PREALLOC) {
1908 ;
1909 } else if (xen_enabled()) {
1910 xen_invalidate_map_cache_entry(block->host);
1911 #ifndef _WIN32
1912 } else if (block->fd >= 0) {
1913 qemu_ram_munmap(block->host, block->max_length);
1914 close(block->fd);
1915 #endif
1916 } else {
1917 qemu_anon_ram_free(block->host, block->max_length);
1918 }
1919 g_free(block);
1920 }
1921
1922 void qemu_ram_free(RAMBlock *block)
1923 {
1924 if (!block) {
1925 return;
1926 }
1927
1928 if (block->host) {
1929 ram_block_notify_remove(block->host, block->max_length);
1930 }
1931
1932 qemu_mutex_lock_ramlist();
1933 QLIST_REMOVE_RCU(block, next);
1934 ram_list.mru_block = NULL;
1935 /* Write list before version */
1936 smp_wmb();
1937 ram_list.version++;
1938 call_rcu(block, reclaim_ramblock, rcu);
1939 qemu_mutex_unlock_ramlist();
1940 }
1941
1942 #ifndef _WIN32
1943 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
1944 {
1945 RAMBlock *block;
1946 ram_addr_t offset;
1947 int flags;
1948 void *area, *vaddr;
1949
1950 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1951 offset = addr - block->offset;
1952 if (offset < block->max_length) {
1953 vaddr = ramblock_ptr(block, offset);
1954 if (block->flags & RAM_PREALLOC) {
1955 ;
1956 } else if (xen_enabled()) {
1957 abort();
1958 } else {
1959 flags = MAP_FIXED;
1960 if (block->fd >= 0) {
1961 flags |= (block->flags & RAM_SHARED ?
1962 MAP_SHARED : MAP_PRIVATE);
1963 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1964 flags, block->fd, offset);
1965 } else {
1966 /*
1967 * Remap needs to match alloc. Accelerators that
1968 * set phys_mem_alloc never remap. If they did,
1969 * we'd need a remap hook here.
1970 */
1971 assert(phys_mem_alloc == qemu_anon_ram_alloc);
1972
1973 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1974 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1975 flags, -1, 0);
1976 }
1977 if (area != vaddr) {
1978 fprintf(stderr, "Could not remap addr: "
1979 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
1980 length, addr);
1981 exit(1);
1982 }
1983 memory_try_enable_merging(vaddr, length);
1984 qemu_ram_setup_dump(vaddr, length);
1985 }
1986 }
1987 }
1988 }
1989 #endif /* !_WIN32 */
1990
1991 /* Return a host pointer to ram allocated with qemu_ram_alloc.
1992 * This should not be used for general purpose DMA. Use address_space_map
1993 * or address_space_rw instead. For local memory (e.g. video ram) that the
1994 * device owns, use memory_region_get_ram_ptr.
1995 *
1996 * Called within RCU critical section.
1997 */
1998 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
1999 {
2000 RAMBlock *block = ram_block;
2001
2002 if (block == NULL) {
2003 block = qemu_get_ram_block(addr);
2004 addr -= block->offset;
2005 }
2006
2007 if (xen_enabled() && block->host == NULL) {
2008 /* We need to check if the requested address is in the RAM
2009 * because we don't want to map the entire memory in QEMU.
2010 * In that case just map until the end of the page.
2011 */
2012 if (block->offset == 0) {
2013 return xen_map_cache(addr, 0, 0);
2014 }
2015
2016 block->host = xen_map_cache(block->offset, block->max_length, 1);
2017 }
2018 return ramblock_ptr(block, addr);
2019 }
2020
2021 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2022 * but takes a size argument.
2023 *
2024 * Called within RCU critical section.
2025 */
2026 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2027 hwaddr *size)
2028 {
2029 RAMBlock *block = ram_block;
2030 if (*size == 0) {
2031 return NULL;
2032 }
2033
2034 if (block == NULL) {
2035 block = qemu_get_ram_block(addr);
2036 addr -= block->offset;
2037 }
2038 *size = MIN(*size, block->max_length - addr);
2039
2040 if (xen_enabled() && block->host == NULL) {
2041 /* We need to check if the requested address is in the RAM
2042 * because we don't want to map the entire memory in QEMU.
2043 * In that case just map the requested area.
2044 */
2045 if (block->offset == 0) {
2046 return xen_map_cache(addr, *size, 1);
2047 }
2048
2049 block->host = xen_map_cache(block->offset, block->max_length, 1);
2050 }
2051
2052 return ramblock_ptr(block, addr);
2053 }
2054
2055 /*
2056 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2057 * in that RAMBlock.
2058 *
2059 * ptr: Host pointer to look up
2060 * round_offset: If true round the result offset down to a page boundary
2061 * *ram_addr: set to result ram_addr
2062 * *offset: set to result offset within the RAMBlock
2063 *
2064 * Returns: RAMBlock (or NULL if not found)
2065 *
2066 * By the time this function returns, the returned pointer is not protected
2067 * by RCU anymore. If the caller is not within an RCU critical section and
2068 * does not hold the iothread lock, it must have other means of protecting the
2069 * pointer, such as a reference to the region that includes the incoming
2070 * ram_addr_t.
2071 */
2072 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2073 ram_addr_t *offset)
2074 {
2075 RAMBlock *block;
2076 uint8_t *host = ptr;
2077
2078 if (xen_enabled()) {
2079 ram_addr_t ram_addr;
2080 rcu_read_lock();
2081 ram_addr = xen_ram_addr_from_mapcache(ptr);
2082 block = qemu_get_ram_block(ram_addr);
2083 if (block) {
2084 *offset = ram_addr - block->offset;
2085 }
2086 rcu_read_unlock();
2087 return block;
2088 }
2089
2090 rcu_read_lock();
2091 block = atomic_rcu_read(&ram_list.mru_block);
2092 if (block && block->host && host - block->host < block->max_length) {
2093 goto found;
2094 }
2095
2096 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
2097 /* This case append when the block is not mapped. */
2098 if (block->host == NULL) {
2099 continue;
2100 }
2101 if (host - block->host < block->max_length) {
2102 goto found;
2103 }
2104 }
2105
2106 rcu_read_unlock();
2107 return NULL;
2108
2109 found:
2110 *offset = (host - block->host);
2111 if (round_offset) {
2112 *offset &= TARGET_PAGE_MASK;
2113 }
2114 rcu_read_unlock();
2115 return block;
2116 }
2117
2118 /*
2119 * Finds the named RAMBlock
2120 *
2121 * name: The name of RAMBlock to find
2122 *
2123 * Returns: RAMBlock (or NULL if not found)
2124 */
2125 RAMBlock *qemu_ram_block_by_name(const char *name)
2126 {
2127 RAMBlock *block;
2128
2129 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
2130 if (!strcmp(name, block->idstr)) {
2131 return block;
2132 }
2133 }
2134
2135 return NULL;
2136 }
2137
2138 /* Some of the softmmu routines need to translate from a host pointer
2139 (typically a TLB entry) back to a ram offset. */
2140 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2141 {
2142 RAMBlock *block;
2143 ram_addr_t offset;
2144
2145 block = qemu_ram_block_from_host(ptr, false, &offset);
2146 if (!block) {
2147 return RAM_ADDR_INVALID;
2148 }
2149
2150 return block->offset + offset;
2151 }
2152
2153 /* Called within RCU critical section. */
2154 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2155 uint64_t val, unsigned size)
2156 {
2157 bool locked = false;
2158
2159 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2160 locked = true;
2161 tb_lock();
2162 tb_invalidate_phys_page_fast(ram_addr, size);
2163 }
2164 switch (size) {
2165 case 1:
2166 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2167 break;
2168 case 2:
2169 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2170 break;
2171 case 4:
2172 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2173 break;
2174 default:
2175 abort();
2176 }
2177
2178 if (locked) {
2179 tb_unlock();
2180 }
2181
2182 /* Set both VGA and migration bits for simplicity and to remove
2183 * the notdirty callback faster.
2184 */
2185 cpu_physical_memory_set_dirty_range(ram_addr, size,
2186 DIRTY_CLIENTS_NOCODE);
2187 /* we remove the notdirty callback only if the code has been
2188 flushed */
2189 if (!cpu_physical_memory_is_clean(ram_addr)) {
2190 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2191 }
2192 }
2193
2194 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2195 unsigned size, bool is_write)
2196 {
2197 return is_write;
2198 }
2199
2200 static const MemoryRegionOps notdirty_mem_ops = {
2201 .write = notdirty_mem_write,
2202 .valid.accepts = notdirty_mem_accepts,
2203 .endianness = DEVICE_NATIVE_ENDIAN,
2204 };
2205
2206 /* Generate a debug exception if a watchpoint has been hit. */
2207 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2208 {
2209 CPUState *cpu = current_cpu;
2210 CPUClass *cc = CPU_GET_CLASS(cpu);
2211 CPUArchState *env = cpu->env_ptr;
2212 target_ulong pc, cs_base;
2213 target_ulong vaddr;
2214 CPUWatchpoint *wp;
2215 uint32_t cpu_flags;
2216
2217 if (cpu->watchpoint_hit) {
2218 /* We re-entered the check after replacing the TB. Now raise
2219 * the debug interrupt so that is will trigger after the
2220 * current instruction. */
2221 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2222 return;
2223 }
2224 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2225 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2226 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2227 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2228 && (wp->flags & flags)) {
2229 if (flags == BP_MEM_READ) {
2230 wp->flags |= BP_WATCHPOINT_HIT_READ;
2231 } else {
2232 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2233 }
2234 wp->hitaddr = vaddr;
2235 wp->hitattrs = attrs;
2236 if (!cpu->watchpoint_hit) {
2237 if (wp->flags & BP_CPU &&
2238 !cc->debug_check_watchpoint(cpu, wp)) {
2239 wp->flags &= ~BP_WATCHPOINT_HIT;
2240 continue;
2241 }
2242 cpu->watchpoint_hit = wp;
2243
2244 /* Both tb_lock and iothread_mutex will be reset when
2245 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2246 * back into the cpu_exec main loop.
2247 */
2248 tb_lock();
2249 tb_check_watchpoint(cpu);
2250 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2251 cpu->exception_index = EXCP_DEBUG;
2252 cpu_loop_exit(cpu);
2253 } else {
2254 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2255 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2256 cpu_loop_exit_noexc(cpu);
2257 }
2258 }
2259 } else {
2260 wp->flags &= ~BP_WATCHPOINT_HIT;
2261 }
2262 }
2263 }
2264
2265 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2266 so these check for a hit then pass through to the normal out-of-line
2267 phys routines. */
2268 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2269 unsigned size, MemTxAttrs attrs)
2270 {
2271 MemTxResult res;
2272 uint64_t data;
2273 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2274 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2275
2276 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2277 switch (size) {
2278 case 1:
2279 data = address_space_ldub(as, addr, attrs, &res);
2280 break;
2281 case 2:
2282 data = address_space_lduw(as, addr, attrs, &res);
2283 break;
2284 case 4:
2285 data = address_space_ldl(as, addr, attrs, &res);
2286 break;
2287 default: abort();
2288 }
2289 *pdata = data;
2290 return res;
2291 }
2292
2293 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2294 uint64_t val, unsigned size,
2295 MemTxAttrs attrs)
2296 {
2297 MemTxResult res;
2298 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2299 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2300
2301 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2302 switch (size) {
2303 case 1:
2304 address_space_stb(as, addr, val, attrs, &res);
2305 break;
2306 case 2:
2307 address_space_stw(as, addr, val, attrs, &res);
2308 break;
2309 case 4:
2310 address_space_stl(as, addr, val, attrs, &res);
2311 break;
2312 default: abort();
2313 }
2314 return res;
2315 }
2316
2317 static const MemoryRegionOps watch_mem_ops = {
2318 .read_with_attrs = watch_mem_read,
2319 .write_with_attrs = watch_mem_write,
2320 .endianness = DEVICE_NATIVE_ENDIAN,
2321 };
2322
2323 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2324 unsigned len, MemTxAttrs attrs)
2325 {
2326 subpage_t *subpage = opaque;
2327 uint8_t buf[8];
2328 MemTxResult res;
2329
2330 #if defined(DEBUG_SUBPAGE)
2331 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2332 subpage, len, addr);
2333 #endif
2334 res = address_space_read(subpage->as, addr + subpage->base,
2335 attrs, buf, len);
2336 if (res) {
2337 return res;
2338 }
2339 switch (len) {
2340 case 1:
2341 *data = ldub_p(buf);
2342 return MEMTX_OK;
2343 case 2:
2344 *data = lduw_p(buf);
2345 return MEMTX_OK;
2346 case 4:
2347 *data = ldl_p(buf);
2348 return MEMTX_OK;
2349 case 8:
2350 *data = ldq_p(buf);
2351 return MEMTX_OK;
2352 default:
2353 abort();
2354 }
2355 }
2356
2357 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2358 uint64_t value, unsigned len, MemTxAttrs attrs)
2359 {
2360 subpage_t *subpage = opaque;
2361 uint8_t buf[8];
2362
2363 #if defined(DEBUG_SUBPAGE)
2364 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2365 " value %"PRIx64"\n",
2366 __func__, subpage, len, addr, value);
2367 #endif
2368 switch (len) {
2369 case 1:
2370 stb_p(buf, value);
2371 break;
2372 case 2:
2373 stw_p(buf, value);
2374 break;
2375 case 4:
2376 stl_p(buf, value);
2377 break;
2378 case 8:
2379 stq_p(buf, value);
2380 break;
2381 default:
2382 abort();
2383 }
2384 return address_space_write(subpage->as, addr + subpage->base,
2385 attrs, buf, len);
2386 }
2387
2388 static bool subpage_accepts(void *opaque, hwaddr addr,
2389 unsigned len, bool is_write)
2390 {
2391 subpage_t *subpage = opaque;
2392 #if defined(DEBUG_SUBPAGE)
2393 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2394 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2395 #endif
2396
2397 return address_space_access_valid(subpage->as, addr + subpage->base,
2398 len, is_write);
2399 }
2400
2401 static const MemoryRegionOps subpage_ops = {
2402 .read_with_attrs = subpage_read,
2403 .write_with_attrs = subpage_write,
2404 .impl.min_access_size = 1,
2405 .impl.max_access_size = 8,
2406 .valid.min_access_size = 1,
2407 .valid.max_access_size = 8,
2408 .valid.accepts = subpage_accepts,
2409 .endianness = DEVICE_NATIVE_ENDIAN,
2410 };
2411
2412 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2413 uint16_t section)
2414 {
2415 int idx, eidx;
2416
2417 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2418 return -1;
2419 idx = SUBPAGE_IDX(start);
2420 eidx = SUBPAGE_IDX(end);
2421 #if defined(DEBUG_SUBPAGE)
2422 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2423 __func__, mmio, start, end, idx, eidx, section);
2424 #endif
2425 for (; idx <= eidx; idx++) {
2426 mmio->sub_section[idx] = section;
2427 }
2428
2429 return 0;
2430 }
2431
2432 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2433 {
2434 subpage_t *mmio;
2435
2436 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2437 mmio->as = as;
2438 mmio->base = base;
2439 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2440 NULL, TARGET_PAGE_SIZE);
2441 mmio->iomem.subpage = true;
2442 #if defined(DEBUG_SUBPAGE)
2443 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2444 mmio, base, TARGET_PAGE_SIZE);
2445 #endif
2446 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2447
2448 return mmio;
2449 }
2450
2451 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2452 MemoryRegion *mr)
2453 {
2454 assert(as);
2455 MemoryRegionSection section = {
2456 .address_space = as,
2457 .mr = mr,
2458 .offset_within_address_space = 0,
2459 .offset_within_region = 0,
2460 .size = int128_2_64(),
2461 };
2462
2463 return phys_section_add(map, &section);
2464 }
2465
2466 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2467 {
2468 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2469 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2470 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2471 MemoryRegionSection *sections = d->map.sections;
2472
2473 return sections[index & ~TARGET_PAGE_MASK].mr;
2474 }
2475
2476 static void io_mem_init(void)
2477 {
2478 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2479 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2480 NULL, UINT64_MAX);
2481
2482 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2483 * which can be called without the iothread mutex.
2484 */
2485 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2486 NULL, UINT64_MAX);
2487 memory_region_clear_global_locking(&io_mem_notdirty);
2488
2489 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2490 NULL, UINT64_MAX);
2491 }
2492
2493 static void mem_begin(MemoryListener *listener)
2494 {
2495 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2496 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2497 uint16_t n;
2498
2499 n = dummy_section(&d->map, as, &io_mem_unassigned);
2500 assert(n == PHYS_SECTION_UNASSIGNED);
2501 n = dummy_section(&d->map, as, &io_mem_notdirty);
2502 assert(n == PHYS_SECTION_NOTDIRTY);
2503 n = dummy_section(&d->map, as, &io_mem_rom);
2504 assert(n == PHYS_SECTION_ROM);
2505 n = dummy_section(&d->map, as, &io_mem_watch);
2506 assert(n == PHYS_SECTION_WATCH);
2507
2508 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2509 d->as = as;
2510 as->next_dispatch = d;
2511 }
2512
2513 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2514 {
2515 phys_sections_free(&d->map);
2516 g_free(d);
2517 }
2518
2519 static void mem_commit(MemoryListener *listener)
2520 {
2521 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2522 AddressSpaceDispatch *cur = as->dispatch;
2523 AddressSpaceDispatch *next = as->next_dispatch;
2524
2525 phys_page_compact_all(next, next->map.nodes_nb);
2526
2527 atomic_rcu_set(&as->dispatch, next);
2528 if (cur) {
2529 call_rcu(cur, address_space_dispatch_free, rcu);
2530 }
2531 }
2532
2533 static void tcg_commit(MemoryListener *listener)
2534 {
2535 CPUAddressSpace *cpuas;
2536 AddressSpaceDispatch *d;
2537
2538 /* since each CPU stores ram addresses in its TLB cache, we must
2539 reset the modified entries */
2540 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2541 cpu_reloading_memory_map();
2542 /* The CPU and TLB are protected by the iothread lock.
2543 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2544 * may have split the RCU critical section.
2545 */
2546 d = atomic_rcu_read(&cpuas->as->dispatch);
2547 atomic_rcu_set(&cpuas->memory_dispatch, d);
2548 tlb_flush(cpuas->cpu);
2549 }
2550
2551 void address_space_init_dispatch(AddressSpace *as)
2552 {
2553 as->dispatch = NULL;
2554 as->dispatch_listener = (MemoryListener) {
2555 .begin = mem_begin,
2556 .commit = mem_commit,
2557 .region_add = mem_add,
2558 .region_nop = mem_add,
2559 .priority = 0,
2560 };
2561 memory_listener_register(&as->dispatch_listener, as);
2562 }
2563
2564 void address_space_unregister(AddressSpace *as)
2565 {
2566 memory_listener_unregister(&as->dispatch_listener);
2567 }
2568
2569 void address_space_destroy_dispatch(AddressSpace *as)
2570 {
2571 AddressSpaceDispatch *d = as->dispatch;
2572
2573 atomic_rcu_set(&as->dispatch, NULL);
2574 if (d) {
2575 call_rcu(d, address_space_dispatch_free, rcu);
2576 }
2577 }
2578
2579 static void memory_map_init(void)
2580 {
2581 system_memory = g_malloc(sizeof(*system_memory));
2582
2583 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2584 address_space_init(&address_space_memory, system_memory, "memory");
2585
2586 system_io = g_malloc(sizeof(*system_io));
2587 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2588 65536);
2589 address_space_init(&address_space_io, system_io, "I/O");
2590 }
2591
2592 MemoryRegion *get_system_memory(void)
2593 {
2594 return system_memory;
2595 }
2596
2597 MemoryRegion *get_system_io(void)
2598 {
2599 return system_io;
2600 }
2601
2602 #endif /* !defined(CONFIG_USER_ONLY) */
2603
2604 /* physical memory access (slow version, mainly for debug) */
2605 #if defined(CONFIG_USER_ONLY)
2606 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2607 uint8_t *buf, int len, int is_write)
2608 {
2609 int l, flags;
2610 target_ulong page;
2611 void * p;
2612
2613 while (len > 0) {
2614 page = addr & TARGET_PAGE_MASK;
2615 l = (page + TARGET_PAGE_SIZE) - addr;
2616 if (l > len)
2617 l = len;
2618 flags = page_get_flags(page);
2619 if (!(flags & PAGE_VALID))
2620 return -1;
2621 if (is_write) {
2622 if (!(flags & PAGE_WRITE))
2623 return -1;
2624 /* XXX: this code should not depend on lock_user */
2625 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2626 return -1;
2627 memcpy(p, buf, l);
2628 unlock_user(p, addr, l);
2629 } else {
2630 if (!(flags & PAGE_READ))
2631 return -1;
2632 /* XXX: this code should not depend on lock_user */
2633 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2634 return -1;
2635 memcpy(buf, p, l);
2636 unlock_user(p, addr, 0);
2637 }
2638 len -= l;
2639 buf += l;
2640 addr += l;
2641 }
2642 return 0;
2643 }
2644
2645 #else
2646
2647 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2648 hwaddr length)
2649 {
2650 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2651 addr += memory_region_get_ram_addr(mr);
2652
2653 /* No early return if dirty_log_mask is or becomes 0, because
2654 * cpu_physical_memory_set_dirty_range will still call
2655 * xen_modified_memory.
2656 */
2657 if (dirty_log_mask) {
2658 dirty_log_mask =
2659 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2660 }
2661 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2662 tb_lock();
2663 tb_invalidate_phys_range(addr, addr + length);
2664 tb_unlock();
2665 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2666 }
2667 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2668 }
2669
2670 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2671 {
2672 unsigned access_size_max = mr->ops->valid.max_access_size;
2673
2674 /* Regions are assumed to support 1-4 byte accesses unless
2675 otherwise specified. */
2676 if (access_size_max == 0) {
2677 access_size_max = 4;
2678 }
2679
2680 /* Bound the maximum access by the alignment of the address. */
2681 if (!mr->ops->impl.unaligned) {
2682 unsigned align_size_max = addr & -addr;
2683 if (align_size_max != 0 && align_size_max < access_size_max) {
2684 access_size_max = align_size_max;
2685 }
2686 }
2687
2688 /* Don't attempt accesses larger than the maximum. */
2689 if (l > access_size_max) {
2690 l = access_size_max;
2691 }
2692 l = pow2floor(l);
2693
2694 return l;
2695 }
2696
2697 static bool prepare_mmio_access(MemoryRegion *mr)
2698 {
2699 bool unlocked = !qemu_mutex_iothread_locked();
2700 bool release_lock = false;
2701
2702 if (unlocked && mr->global_locking) {
2703 qemu_mutex_lock_iothread();
2704 unlocked = false;
2705 release_lock = true;
2706 }
2707 if (mr->flush_coalesced_mmio) {
2708 if (unlocked) {
2709 qemu_mutex_lock_iothread();
2710 }
2711 qemu_flush_coalesced_mmio_buffer();
2712 if (unlocked) {
2713 qemu_mutex_unlock_iothread();
2714 }
2715 }
2716
2717 return release_lock;
2718 }
2719
2720 /* Called within RCU critical section. */
2721 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2722 MemTxAttrs attrs,
2723 const uint8_t *buf,
2724 int len, hwaddr addr1,
2725 hwaddr l, MemoryRegion *mr)
2726 {
2727 uint8_t *ptr;
2728 uint64_t val;
2729 MemTxResult result = MEMTX_OK;
2730 bool release_lock = false;
2731
2732 for (;;) {
2733 if (!memory_access_is_direct(mr, true)) {
2734 release_lock |= prepare_mmio_access(mr);
2735 l = memory_access_size(mr, l, addr1);
2736 /* XXX: could force current_cpu to NULL to avoid
2737 potential bugs */
2738 switch (l) {
2739 case 8:
2740 /* 64 bit write access */
2741 val = ldq_p(buf);
2742 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2743 attrs);
2744 break;
2745 case 4:
2746 /* 32 bit write access */
2747 val = (uint32_t)ldl_p(buf);
2748 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2749 attrs);
2750 break;
2751 case 2:
2752 /* 16 bit write access */
2753 val = lduw_p(buf);
2754 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2755 attrs);
2756 break;
2757 case 1:
2758 /* 8 bit write access */
2759 val = ldub_p(buf);
2760 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2761 attrs);
2762 break;
2763 default:
2764 abort();
2765 }
2766 } else {
2767 /* RAM case */
2768 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2769 memcpy(ptr, buf, l);
2770 invalidate_and_set_dirty(mr, addr1, l);
2771 }
2772
2773 if (release_lock) {
2774 qemu_mutex_unlock_iothread();
2775 release_lock = false;
2776 }
2777
2778 len -= l;
2779 buf += l;
2780 addr += l;
2781
2782 if (!len) {
2783 break;
2784 }
2785
2786 l = len;
2787 mr = address_space_translate(as, addr, &addr1, &l, true);
2788 }
2789
2790 return result;
2791 }
2792
2793 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2794 const uint8_t *buf, int len)
2795 {
2796 hwaddr l;
2797 hwaddr addr1;
2798 MemoryRegion *mr;
2799 MemTxResult result = MEMTX_OK;
2800
2801 if (len > 0) {
2802 rcu_read_lock();
2803 l = len;
2804 mr = address_space_translate(as, addr, &addr1, &l, true);
2805 result = address_space_write_continue(as, addr, attrs, buf, len,
2806 addr1, l, mr);
2807 rcu_read_unlock();
2808 }
2809
2810 return result;
2811 }
2812
2813 /* Called within RCU critical section. */
2814 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2815 MemTxAttrs attrs, uint8_t *buf,
2816 int len, hwaddr addr1, hwaddr l,
2817 MemoryRegion *mr)
2818 {
2819 uint8_t *ptr;
2820 uint64_t val;
2821 MemTxResult result = MEMTX_OK;
2822 bool release_lock = false;
2823
2824 for (;;) {
2825 if (!memory_access_is_direct(mr, false)) {
2826 /* I/O case */
2827 release_lock |= prepare_mmio_access(mr);
2828 l = memory_access_size(mr, l, addr1);
2829 switch (l) {
2830 case 8:
2831 /* 64 bit read access */
2832 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2833 attrs);
2834 stq_p(buf, val);
2835 break;
2836 case 4:
2837 /* 32 bit read access */
2838 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
2839 attrs);
2840 stl_p(buf, val);
2841 break;
2842 case 2:
2843 /* 16 bit read access */
2844 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
2845 attrs);
2846 stw_p(buf, val);
2847 break;
2848 case 1:
2849 /* 8 bit read access */
2850 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
2851 attrs);
2852 stb_p(buf, val);
2853 break;
2854 default:
2855 abort();
2856 }
2857 } else {
2858 /* RAM case */
2859 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2860 memcpy(buf, ptr, l);
2861 }
2862
2863 if (release_lock) {
2864 qemu_mutex_unlock_iothread();
2865 release_lock = false;
2866 }
2867
2868 len -= l;
2869 buf += l;
2870 addr += l;
2871
2872 if (!len) {
2873 break;
2874 }
2875
2876 l = len;
2877 mr = address_space_translate(as, addr, &addr1, &l, false);
2878 }
2879
2880 return result;
2881 }
2882
2883 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
2884 MemTxAttrs attrs, uint8_t *buf, int len)
2885 {
2886 hwaddr l;
2887 hwaddr addr1;
2888 MemoryRegion *mr;
2889 MemTxResult result = MEMTX_OK;
2890
2891 if (len > 0) {
2892 rcu_read_lock();
2893 l = len;
2894 mr = address_space_translate(as, addr, &addr1, &l, false);
2895 result = address_space_read_continue(as, addr, attrs, buf, len,
2896 addr1, l, mr);
2897 rcu_read_unlock();
2898 }
2899
2900 return result;
2901 }
2902
2903 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2904 uint8_t *buf, int len, bool is_write)
2905 {
2906 if (is_write) {
2907 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
2908 } else {
2909 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
2910 }
2911 }
2912
2913 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
2914 int len, int is_write)
2915 {
2916 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
2917 buf, len, is_write);
2918 }
2919
2920 enum write_rom_type {
2921 WRITE_DATA,
2922 FLUSH_CACHE,
2923 };
2924
2925 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
2926 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
2927 {
2928 hwaddr l;
2929 uint8_t *ptr;
2930 hwaddr addr1;
2931 MemoryRegion *mr;
2932
2933 rcu_read_lock();
2934 while (len > 0) {
2935 l = len;
2936 mr = address_space_translate(as, addr, &addr1, &l, true);
2937
2938 if (!(memory_region_is_ram(mr) ||
2939 memory_region_is_romd(mr))) {
2940 l = memory_access_size(mr, l, addr1);
2941 } else {
2942 /* ROM/RAM case */
2943 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2944 switch (type) {
2945 case WRITE_DATA:
2946 memcpy(ptr, buf, l);
2947 invalidate_and_set_dirty(mr, addr1, l);
2948 break;
2949 case FLUSH_CACHE:
2950 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
2951 break;
2952 }
2953 }
2954 len -= l;
2955 buf += l;
2956 addr += l;
2957 }
2958 rcu_read_unlock();
2959 }
2960
2961 /* used for ROM loading : can write in RAM and ROM */
2962 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
2963 const uint8_t *buf, int len)
2964 {
2965 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
2966 }
2967
2968 void cpu_flush_icache_range(hwaddr start, int len)
2969 {
2970 /*
2971 * This function should do the same thing as an icache flush that was
2972 * triggered from within the guest. For TCG we are always cache coherent,
2973 * so there is no need to flush anything. For KVM / Xen we need to flush
2974 * the host's instruction cache at least.
2975 */
2976 if (tcg_enabled()) {
2977 return;
2978 }
2979
2980 cpu_physical_memory_write_rom_internal(&address_space_memory,
2981 start, NULL, len, FLUSH_CACHE);
2982 }
2983
2984 typedef struct {
2985 MemoryRegion *mr;
2986 void *buffer;
2987 hwaddr addr;
2988 hwaddr len;
2989 bool in_use;
2990 } BounceBuffer;
2991
2992 static BounceBuffer bounce;
2993
2994 typedef struct MapClient {
2995 QEMUBH *bh;
2996 QLIST_ENTRY(MapClient) link;
2997 } MapClient;
2998
2999 QemuMutex map_client_list_lock;
3000 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3001 = QLIST_HEAD_INITIALIZER(map_client_list);
3002
3003 static void cpu_unregister_map_client_do(MapClient *client)
3004 {
3005 QLIST_REMOVE(client, link);
3006 g_free(client);
3007 }
3008
3009 static void cpu_notify_map_clients_locked(void)
3010 {
3011 MapClient *client;
3012
3013 while (!QLIST_EMPTY(&map_client_list)) {
3014 client = QLIST_FIRST(&map_client_list);
3015 qemu_bh_schedule(client->bh);
3016 cpu_unregister_map_client_do(client);
3017 }
3018 }
3019
3020 void cpu_register_map_client(QEMUBH *bh)
3021 {
3022 MapClient *client = g_malloc(sizeof(*client));
3023
3024 qemu_mutex_lock(&map_client_list_lock);
3025 client->bh = bh;
3026 QLIST_INSERT_HEAD(&map_client_list, client, link);
3027 if (!atomic_read(&bounce.in_use)) {
3028 cpu_notify_map_clients_locked();
3029 }
3030 qemu_mutex_unlock(&map_client_list_lock);
3031 }
3032
3033 void cpu_exec_init_all(void)
3034 {
3035 qemu_mutex_init(&ram_list.mutex);
3036 /* The data structures we set up here depend on knowing the page size,
3037 * so no more changes can be made after this point.
3038 * In an ideal world, nothing we did before we had finished the
3039 * machine setup would care about the target page size, and we could
3040 * do this much later, rather than requiring board models to state
3041 * up front what their requirements are.
3042 */
3043 finalize_target_page_bits();
3044 io_mem_init();
3045 memory_map_init();
3046 qemu_mutex_init(&map_client_list_lock);
3047 }
3048
3049 void cpu_unregister_map_client(QEMUBH *bh)
3050 {
3051 MapClient *client;
3052
3053 qemu_mutex_lock(&map_client_list_lock);
3054 QLIST_FOREACH(client, &map_client_list, link) {
3055 if (client->bh == bh) {
3056 cpu_unregister_map_client_do(client);
3057 break;
3058 }
3059 }
3060 qemu_mutex_unlock(&map_client_list_lock);
3061 }
3062
3063 static void cpu_notify_map_clients(void)
3064 {
3065 qemu_mutex_lock(&map_client_list_lock);
3066 cpu_notify_map_clients_locked();
3067 qemu_mutex_unlock(&map_client_list_lock);
3068 }
3069
3070 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
3071 {
3072 MemoryRegion *mr;
3073 hwaddr l, xlat;
3074
3075 rcu_read_lock();
3076 while (len > 0) {
3077 l = len;
3078 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3079 if (!memory_access_is_direct(mr, is_write)) {
3080 l = memory_access_size(mr, l, addr);
3081 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3082 rcu_read_unlock();
3083 return false;
3084 }
3085 }
3086
3087 len -= l;
3088 addr += l;
3089 }
3090 rcu_read_unlock();
3091 return true;
3092 }
3093
3094 static hwaddr
3095 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
3096 MemoryRegion *mr, hwaddr base, hwaddr len,
3097 bool is_write)
3098 {
3099 hwaddr done = 0;
3100 hwaddr xlat;
3101 MemoryRegion *this_mr;
3102
3103 for (;;) {
3104 target_len -= len;
3105 addr += len;
3106 done += len;
3107 if (target_len == 0) {
3108 return done;
3109 }
3110
3111 len = target_len;
3112 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
3113 if (this_mr != mr || xlat != base + done) {
3114 return done;
3115 }
3116 }
3117 }
3118
3119 /* Map a physical memory region into a host virtual address.
3120 * May map a subset of the requested range, given by and returned in *plen.
3121 * May return NULL if resources needed to perform the mapping are exhausted.
3122 * Use only for reads OR writes - not for read-modify-write operations.
3123 * Use cpu_register_map_client() to know when retrying the map operation is
3124 * likely to succeed.
3125 */
3126 void *address_space_map(AddressSpace *as,
3127 hwaddr addr,
3128 hwaddr *plen,
3129 bool is_write)
3130 {
3131 hwaddr len = *plen;
3132 hwaddr l, xlat;
3133 MemoryRegion *mr;
3134 void *ptr;
3135
3136 if (len == 0) {
3137 return NULL;
3138 }
3139
3140 l = len;
3141 rcu_read_lock();
3142 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3143
3144 if (!memory_access_is_direct(mr, is_write)) {
3145 if (atomic_xchg(&bounce.in_use, true)) {
3146 rcu_read_unlock();
3147 return NULL;
3148 }
3149 /* Avoid unbounded allocations */
3150 l = MIN(l, TARGET_PAGE_SIZE);
3151 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3152 bounce.addr = addr;
3153 bounce.len = l;
3154
3155 memory_region_ref(mr);
3156 bounce.mr = mr;
3157 if (!is_write) {
3158 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3159 bounce.buffer, l);
3160 }
3161
3162 rcu_read_unlock();
3163 *plen = l;
3164 return bounce.buffer;
3165 }
3166
3167
3168 memory_region_ref(mr);
3169 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3170 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3171 rcu_read_unlock();
3172
3173 return ptr;
3174 }
3175
3176 /* Unmaps a memory region previously mapped by address_space_map().
3177 * Will also mark the memory as dirty if is_write == 1. access_len gives
3178 * the amount of memory that was actually read or written by the caller.
3179 */
3180 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3181 int is_write, hwaddr access_len)
3182 {
3183 if (buffer != bounce.buffer) {
3184 MemoryRegion *mr;
3185 ram_addr_t addr1;
3186
3187 mr = memory_region_from_host(buffer, &addr1);
3188 assert(mr != NULL);
3189 if (is_write) {
3190 invalidate_and_set_dirty(mr, addr1, access_len);
3191 }
3192 if (xen_enabled()) {
3193 xen_invalidate_map_cache_entry(buffer);
3194 }
3195 memory_region_unref(mr);
3196 return;
3197 }
3198 if (is_write) {
3199 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3200 bounce.buffer, access_len);
3201 }
3202 qemu_vfree(bounce.buffer);
3203 bounce.buffer = NULL;
3204 memory_region_unref(bounce.mr);
3205 atomic_mb_set(&bounce.in_use, false);
3206 cpu_notify_map_clients();
3207 }
3208
3209 void *cpu_physical_memory_map(hwaddr addr,
3210 hwaddr *plen,
3211 int is_write)
3212 {
3213 return address_space_map(&address_space_memory, addr, plen, is_write);
3214 }
3215
3216 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3217 int is_write, hwaddr access_len)
3218 {
3219 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3220 }
3221
3222 #define ARG1_DECL AddressSpace *as
3223 #define ARG1 as
3224 #define SUFFIX
3225 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3226 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3227 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3228 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3229 #define RCU_READ_LOCK(...) rcu_read_lock()
3230 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3231 #include "memory_ldst.inc.c"
3232
3233 int64_t address_space_cache_init(MemoryRegionCache *cache,
3234 AddressSpace *as,
3235 hwaddr addr,
3236 hwaddr len,
3237 bool is_write)
3238 {
3239 hwaddr l, xlat;
3240 MemoryRegion *mr;
3241 void *ptr;
3242
3243 assert(len > 0);
3244
3245 l = len;
3246 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3247 if (!memory_access_is_direct(mr, is_write)) {
3248 return -EINVAL;
3249 }
3250
3251 l = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3252 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, &l);
3253
3254 cache->xlat = xlat;
3255 cache->is_write = is_write;
3256 cache->mr = mr;
3257 cache->ptr = ptr;
3258 cache->len = l;
3259 memory_region_ref(cache->mr);
3260
3261 return l;
3262 }
3263
3264 void address_space_cache_invalidate(MemoryRegionCache *cache,
3265 hwaddr addr,
3266 hwaddr access_len)
3267 {
3268 assert(cache->is_write);
3269 invalidate_and_set_dirty(cache->mr, addr + cache->xlat, access_len);
3270 }
3271
3272 void address_space_cache_destroy(MemoryRegionCache *cache)
3273 {
3274 if (!cache->mr) {
3275 return;
3276 }
3277
3278 if (xen_enabled()) {
3279 xen_invalidate_map_cache_entry(cache->ptr);
3280 }
3281 memory_region_unref(cache->mr);
3282 cache->mr = NULL;
3283 }
3284
3285 /* Called from RCU critical section. This function has the same
3286 * semantics as address_space_translate, but it only works on a
3287 * predefined range of a MemoryRegion that was mapped with
3288 * address_space_cache_init.
3289 */
3290 static inline MemoryRegion *address_space_translate_cached(
3291 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3292 hwaddr *plen, bool is_write)
3293 {
3294 assert(addr < cache->len && *plen <= cache->len - addr);
3295 *xlat = addr + cache->xlat;
3296 return cache->mr;
3297 }
3298
3299 #define ARG1_DECL MemoryRegionCache *cache
3300 #define ARG1 cache
3301 #define SUFFIX _cached
3302 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3303 #define IS_DIRECT(mr, is_write) true
3304 #define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat))
3305 #define INVALIDATE(mr, ofs, len) ((void)0)
3306 #define RCU_READ_LOCK() ((void)0)
3307 #define RCU_READ_UNLOCK() ((void)0)
3308 #include "memory_ldst.inc.c"
3309
3310 /* virtual memory access for debug (includes writing to ROM) */
3311 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3312 uint8_t *buf, int len, int is_write)
3313 {
3314 int l;
3315 hwaddr phys_addr;
3316 target_ulong page;
3317
3318 cpu_synchronize_state(cpu);
3319 while (len > 0) {
3320 int asidx;
3321 MemTxAttrs attrs;
3322
3323 page = addr & TARGET_PAGE_MASK;
3324 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3325 asidx = cpu_asidx_from_attrs(cpu, attrs);
3326 /* if no physical page mapped, return an error */
3327 if (phys_addr == -1)
3328 return -1;
3329 l = (page + TARGET_PAGE_SIZE) - addr;
3330 if (l > len)
3331 l = len;
3332 phys_addr += (addr & ~TARGET_PAGE_MASK);
3333 if (is_write) {
3334 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3335 phys_addr, buf, l);
3336 } else {
3337 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3338 MEMTXATTRS_UNSPECIFIED,
3339 buf, l, 0);
3340 }
3341 len -= l;
3342 buf += l;
3343 addr += l;
3344 }
3345 return 0;
3346 }
3347
3348 /*
3349 * Allows code that needs to deal with migration bitmaps etc to still be built
3350 * target independent.
3351 */
3352 size_t qemu_target_page_bits(void)
3353 {
3354 return TARGET_PAGE_BITS;
3355 }
3356
3357 #endif
3358
3359 /*
3360 * A helper function for the _utterly broken_ virtio device model to find out if
3361 * it's running on a big endian machine. Don't do this at home kids!
3362 */
3363 bool target_words_bigendian(void);
3364 bool target_words_bigendian(void)
3365 {
3366 #if defined(TARGET_WORDS_BIGENDIAN)
3367 return true;
3368 #else
3369 return false;
3370 #endif
3371 }
3372
3373 #ifndef CONFIG_USER_ONLY
3374 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3375 {
3376 MemoryRegion*mr;
3377 hwaddr l = 1;
3378 bool res;
3379
3380 rcu_read_lock();
3381 mr = address_space_translate(&address_space_memory,
3382 phys_addr, &phys_addr, &l, false);
3383
3384 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3385 rcu_read_unlock();
3386 return res;
3387 }
3388
3389 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3390 {
3391 RAMBlock *block;
3392 int ret = 0;
3393
3394 rcu_read_lock();
3395 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
3396 ret = func(block->idstr, block->host, block->offset,
3397 block->used_length, opaque);
3398 if (ret) {
3399 break;
3400 }
3401 }
3402 rcu_read_unlock();
3403 return ret;
3404 }
3405
3406 /*
3407 * Unmap pages of memory from start to start+length such that
3408 * they a) read as 0, b) Trigger whatever fault mechanism
3409 * the OS provides for postcopy.
3410 * The pages must be unmapped by the end of the function.
3411 * Returns: 0 on success, none-0 on failure
3412 *
3413 */
3414 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3415 {
3416 int ret = -1;
3417
3418 uint8_t *host_startaddr = rb->host + start;
3419
3420 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3421 error_report("ram_block_discard_range: Unaligned start address: %p",
3422 host_startaddr);
3423 goto err;
3424 }
3425
3426 if ((start + length) <= rb->used_length) {
3427 uint8_t *host_endaddr = host_startaddr + length;
3428 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3429 error_report("ram_block_discard_range: Unaligned end address: %p",
3430 host_endaddr);
3431 goto err;
3432 }
3433
3434 errno = ENOTSUP; /* If we are missing MADVISE etc */
3435
3436 if (rb->page_size == qemu_host_page_size) {
3437 #if defined(CONFIG_MADVISE)
3438 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3439 * freeing the page.
3440 */
3441 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3442 #endif
3443 } else {
3444 /* Huge page case - unfortunately it can't do DONTNEED, but
3445 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3446 * huge page file.
3447 */
3448 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3449 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3450 start, length);
3451 #endif
3452 }
3453 if (ret) {
3454 ret = -errno;
3455 error_report("ram_block_discard_range: Failed to discard range "
3456 "%s:%" PRIx64 " +%zx (%d)",
3457 rb->idstr, start, length, ret);
3458 }
3459 } else {
3460 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3461 "/%zx/" RAM_ADDR_FMT")",
3462 rb->idstr, start, length, rb->used_length);
3463 }
3464
3465 err:
3466 return ret;
3467 }
3468
3469 #endif