tests: Add a tester for HMP commands
[qemu.git] / exec.c
1 /*
2 * Virtual page mapping
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #ifndef _WIN32
22 #endif
23
24 #include "qemu/cutils.h"
25 #include "cpu.h"
26 #include "exec/exec-all.h"
27 #include "tcg.h"
28 #include "hw/qdev-core.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
50
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <fcntl.h>
53 #include <linux/falloc.h>
54 #endif
55
56 #endif
57 #include "exec/cpu-all.h"
58 #include "qemu/rcu_queue.h"
59 #include "qemu/main-loop.h"
60 #include "translate-all.h"
61 #include "sysemu/replay.h"
62
63 #include "exec/memory-internal.h"
64 #include "exec/ram_addr.h"
65 #include "exec/log.h"
66
67 #include "migration/vmstate.h"
68
69 #include "qemu/range.h"
70 #ifndef _WIN32
71 #include "qemu/mmap-alloc.h"
72 #endif
73
74 //#define DEBUG_SUBPAGE
75
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
79 */
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
81
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
84
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
87
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
90
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
93
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
96
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
99 */
100 #define RAM_RESIZEABLE (1 << 2)
101
102 #endif
103
104 #ifdef TARGET_PAGE_BITS_VARY
105 int target_page_bits;
106 bool target_page_bits_decided;
107 #endif
108
109 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
110 /* current CPU in the current thread. It is only valid inside
111 cpu_exec() */
112 __thread CPUState *current_cpu;
113 /* 0 = Do not count executed instructions.
114 1 = Precise instruction counting.
115 2 = Adaptive rate instruction counting. */
116 int use_icount;
117
118 bool set_preferred_target_page_bits(int bits)
119 {
120 /* The target page size is the lowest common denominator for all
121 * the CPUs in the system, so we can only make it smaller, never
122 * larger. And we can't make it smaller once we've committed to
123 * a particular size.
124 */
125 #ifdef TARGET_PAGE_BITS_VARY
126 assert(bits >= TARGET_PAGE_BITS_MIN);
127 if (target_page_bits == 0 || target_page_bits > bits) {
128 if (target_page_bits_decided) {
129 return false;
130 }
131 target_page_bits = bits;
132 }
133 #endif
134 return true;
135 }
136
137 #if !defined(CONFIG_USER_ONLY)
138
139 static void finalize_target_page_bits(void)
140 {
141 #ifdef TARGET_PAGE_BITS_VARY
142 if (target_page_bits == 0) {
143 target_page_bits = TARGET_PAGE_BITS_MIN;
144 }
145 target_page_bits_decided = true;
146 #endif
147 }
148
149 typedef struct PhysPageEntry PhysPageEntry;
150
151 struct PhysPageEntry {
152 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
153 uint32_t skip : 6;
154 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
155 uint32_t ptr : 26;
156 };
157
158 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
159
160 /* Size of the L2 (and L3, etc) page tables. */
161 #define ADDR_SPACE_BITS 64
162
163 #define P_L2_BITS 9
164 #define P_L2_SIZE (1 << P_L2_BITS)
165
166 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
167
168 typedef PhysPageEntry Node[P_L2_SIZE];
169
170 typedef struct PhysPageMap {
171 struct rcu_head rcu;
172
173 unsigned sections_nb;
174 unsigned sections_nb_alloc;
175 unsigned nodes_nb;
176 unsigned nodes_nb_alloc;
177 Node *nodes;
178 MemoryRegionSection *sections;
179 } PhysPageMap;
180
181 struct AddressSpaceDispatch {
182 struct rcu_head rcu;
183
184 MemoryRegionSection *mru_section;
185 /* This is a multi-level map on the physical address space.
186 * The bottom level has pointers to MemoryRegionSections.
187 */
188 PhysPageEntry phys_map;
189 PhysPageMap map;
190 AddressSpace *as;
191 };
192
193 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
194 typedef struct subpage_t {
195 MemoryRegion iomem;
196 AddressSpace *as;
197 hwaddr base;
198 uint16_t sub_section[];
199 } subpage_t;
200
201 #define PHYS_SECTION_UNASSIGNED 0
202 #define PHYS_SECTION_NOTDIRTY 1
203 #define PHYS_SECTION_ROM 2
204 #define PHYS_SECTION_WATCH 3
205
206 static void io_mem_init(void);
207 static void memory_map_init(void);
208 static void tcg_commit(MemoryListener *listener);
209
210 static MemoryRegion io_mem_watch;
211
212 /**
213 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
214 * @cpu: the CPU whose AddressSpace this is
215 * @as: the AddressSpace itself
216 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
217 * @tcg_as_listener: listener for tracking changes to the AddressSpace
218 */
219 struct CPUAddressSpace {
220 CPUState *cpu;
221 AddressSpace *as;
222 struct AddressSpaceDispatch *memory_dispatch;
223 MemoryListener tcg_as_listener;
224 };
225
226 struct DirtyBitmapSnapshot {
227 ram_addr_t start;
228 ram_addr_t end;
229 unsigned long dirty[];
230 };
231
232 #endif
233
234 #if !defined(CONFIG_USER_ONLY)
235
236 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
237 {
238 static unsigned alloc_hint = 16;
239 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
240 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
241 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
242 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
243 alloc_hint = map->nodes_nb_alloc;
244 }
245 }
246
247 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
248 {
249 unsigned i;
250 uint32_t ret;
251 PhysPageEntry e;
252 PhysPageEntry *p;
253
254 ret = map->nodes_nb++;
255 p = map->nodes[ret];
256 assert(ret != PHYS_MAP_NODE_NIL);
257 assert(ret != map->nodes_nb_alloc);
258
259 e.skip = leaf ? 0 : 1;
260 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
261 for (i = 0; i < P_L2_SIZE; ++i) {
262 memcpy(&p[i], &e, sizeof(e));
263 }
264 return ret;
265 }
266
267 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
268 hwaddr *index, hwaddr *nb, uint16_t leaf,
269 int level)
270 {
271 PhysPageEntry *p;
272 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
273
274 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
275 lp->ptr = phys_map_node_alloc(map, level == 0);
276 }
277 p = map->nodes[lp->ptr];
278 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
279
280 while (*nb && lp < &p[P_L2_SIZE]) {
281 if ((*index & (step - 1)) == 0 && *nb >= step) {
282 lp->skip = 0;
283 lp->ptr = leaf;
284 *index += step;
285 *nb -= step;
286 } else {
287 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
288 }
289 ++lp;
290 }
291 }
292
293 static void phys_page_set(AddressSpaceDispatch *d,
294 hwaddr index, hwaddr nb,
295 uint16_t leaf)
296 {
297 /* Wildly overreserve - it doesn't matter much. */
298 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
299
300 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
301 }
302
303 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
304 * and update our entry so we can skip it and go directly to the destination.
305 */
306 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
307 {
308 unsigned valid_ptr = P_L2_SIZE;
309 int valid = 0;
310 PhysPageEntry *p;
311 int i;
312
313 if (lp->ptr == PHYS_MAP_NODE_NIL) {
314 return;
315 }
316
317 p = nodes[lp->ptr];
318 for (i = 0; i < P_L2_SIZE; i++) {
319 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
320 continue;
321 }
322
323 valid_ptr = i;
324 valid++;
325 if (p[i].skip) {
326 phys_page_compact(&p[i], nodes);
327 }
328 }
329
330 /* We can only compress if there's only one child. */
331 if (valid != 1) {
332 return;
333 }
334
335 assert(valid_ptr < P_L2_SIZE);
336
337 /* Don't compress if it won't fit in the # of bits we have. */
338 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
339 return;
340 }
341
342 lp->ptr = p[valid_ptr].ptr;
343 if (!p[valid_ptr].skip) {
344 /* If our only child is a leaf, make this a leaf. */
345 /* By design, we should have made this node a leaf to begin with so we
346 * should never reach here.
347 * But since it's so simple to handle this, let's do it just in case we
348 * change this rule.
349 */
350 lp->skip = 0;
351 } else {
352 lp->skip += p[valid_ptr].skip;
353 }
354 }
355
356 static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb)
357 {
358 if (d->phys_map.skip) {
359 phys_page_compact(&d->phys_map, d->map.nodes);
360 }
361 }
362
363 static inline bool section_covers_addr(const MemoryRegionSection *section,
364 hwaddr addr)
365 {
366 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
367 * the section must cover the entire address space.
368 */
369 return int128_gethi(section->size) ||
370 range_covers_byte(section->offset_within_address_space,
371 int128_getlo(section->size), addr);
372 }
373
374 static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr addr,
375 Node *nodes, MemoryRegionSection *sections)
376 {
377 PhysPageEntry *p;
378 hwaddr index = addr >> TARGET_PAGE_BITS;
379 int i;
380
381 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
382 if (lp.ptr == PHYS_MAP_NODE_NIL) {
383 return &sections[PHYS_SECTION_UNASSIGNED];
384 }
385 p = nodes[lp.ptr];
386 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
387 }
388
389 if (section_covers_addr(&sections[lp.ptr], addr)) {
390 return &sections[lp.ptr];
391 } else {
392 return &sections[PHYS_SECTION_UNASSIGNED];
393 }
394 }
395
396 bool memory_region_is_unassigned(MemoryRegion *mr)
397 {
398 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
399 && mr != &io_mem_watch;
400 }
401
402 /* Called from RCU critical section */
403 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
404 hwaddr addr,
405 bool resolve_subpage)
406 {
407 MemoryRegionSection *section = atomic_read(&d->mru_section);
408 subpage_t *subpage;
409 bool update;
410
411 if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
412 section_covers_addr(section, addr)) {
413 update = false;
414 } else {
415 section = phys_page_find(d->phys_map, addr, d->map.nodes,
416 d->map.sections);
417 update = true;
418 }
419 if (resolve_subpage && section->mr->subpage) {
420 subpage = container_of(section->mr, subpage_t, iomem);
421 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
422 }
423 if (update) {
424 atomic_set(&d->mru_section, section);
425 }
426 return section;
427 }
428
429 /* Called from RCU critical section */
430 static MemoryRegionSection *
431 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
432 hwaddr *plen, bool resolve_subpage)
433 {
434 MemoryRegionSection *section;
435 MemoryRegion *mr;
436 Int128 diff;
437
438 section = address_space_lookup_region(d, addr, resolve_subpage);
439 /* Compute offset within MemoryRegionSection */
440 addr -= section->offset_within_address_space;
441
442 /* Compute offset within MemoryRegion */
443 *xlat = addr + section->offset_within_region;
444
445 mr = section->mr;
446
447 /* MMIO registers can be expected to perform full-width accesses based only
448 * on their address, without considering adjacent registers that could
449 * decode to completely different MemoryRegions. When such registers
450 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
451 * regions overlap wildly. For this reason we cannot clamp the accesses
452 * here.
453 *
454 * If the length is small (as is the case for address_space_ldl/stl),
455 * everything works fine. If the incoming length is large, however,
456 * the caller really has to do the clamping through memory_access_size.
457 */
458 if (memory_region_is_ram(mr)) {
459 diff = int128_sub(section->size, int128_make64(addr));
460 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
461 }
462 return section;
463 }
464
465 /* Called from RCU critical section */
466 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
467 bool is_write)
468 {
469 IOMMUTLBEntry iotlb = {0};
470 MemoryRegionSection *section;
471 MemoryRegion *mr;
472
473 for (;;) {
474 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
475 section = address_space_lookup_region(d, addr, false);
476 addr = addr - section->offset_within_address_space
477 + section->offset_within_region;
478 mr = section->mr;
479
480 if (!mr->iommu_ops) {
481 break;
482 }
483
484 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
485 if (!(iotlb.perm & (1 << is_write))) {
486 iotlb.target_as = NULL;
487 break;
488 }
489
490 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
491 | (addr & iotlb.addr_mask));
492 as = iotlb.target_as;
493 }
494
495 return iotlb;
496 }
497
498 /* Called from RCU critical section */
499 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
500 hwaddr *xlat, hwaddr *plen,
501 bool is_write)
502 {
503 IOMMUTLBEntry iotlb;
504 MemoryRegionSection *section;
505 MemoryRegion *mr;
506
507 for (;;) {
508 AddressSpaceDispatch *d = atomic_rcu_read(&as->dispatch);
509 section = address_space_translate_internal(d, addr, &addr, plen, true);
510 mr = section->mr;
511
512 if (!mr->iommu_ops) {
513 break;
514 }
515
516 iotlb = mr->iommu_ops->translate(mr, addr, is_write);
517 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
518 | (addr & iotlb.addr_mask));
519 *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1);
520 if (!(iotlb.perm & (1 << is_write))) {
521 mr = &io_mem_unassigned;
522 break;
523 }
524
525 as = iotlb.target_as;
526 }
527
528 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
529 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
530 *plen = MIN(page, *plen);
531 }
532
533 *xlat = addr;
534 return mr;
535 }
536
537 /* Called from RCU critical section */
538 MemoryRegionSection *
539 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
540 hwaddr *xlat, hwaddr *plen)
541 {
542 MemoryRegionSection *section;
543 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
544
545 section = address_space_translate_internal(d, addr, xlat, plen, false);
546
547 assert(!section->mr->iommu_ops);
548 return section;
549 }
550 #endif
551
552 #if !defined(CONFIG_USER_ONLY)
553
554 static int cpu_common_post_load(void *opaque, int version_id)
555 {
556 CPUState *cpu = opaque;
557
558 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
559 version_id is increased. */
560 cpu->interrupt_request &= ~0x01;
561 tlb_flush(cpu);
562
563 return 0;
564 }
565
566 static int cpu_common_pre_load(void *opaque)
567 {
568 CPUState *cpu = opaque;
569
570 cpu->exception_index = -1;
571
572 return 0;
573 }
574
575 static bool cpu_common_exception_index_needed(void *opaque)
576 {
577 CPUState *cpu = opaque;
578
579 return tcg_enabled() && cpu->exception_index != -1;
580 }
581
582 static const VMStateDescription vmstate_cpu_common_exception_index = {
583 .name = "cpu_common/exception_index",
584 .version_id = 1,
585 .minimum_version_id = 1,
586 .needed = cpu_common_exception_index_needed,
587 .fields = (VMStateField[]) {
588 VMSTATE_INT32(exception_index, CPUState),
589 VMSTATE_END_OF_LIST()
590 }
591 };
592
593 static bool cpu_common_crash_occurred_needed(void *opaque)
594 {
595 CPUState *cpu = opaque;
596
597 return cpu->crash_occurred;
598 }
599
600 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
601 .name = "cpu_common/crash_occurred",
602 .version_id = 1,
603 .minimum_version_id = 1,
604 .needed = cpu_common_crash_occurred_needed,
605 .fields = (VMStateField[]) {
606 VMSTATE_BOOL(crash_occurred, CPUState),
607 VMSTATE_END_OF_LIST()
608 }
609 };
610
611 const VMStateDescription vmstate_cpu_common = {
612 .name = "cpu_common",
613 .version_id = 1,
614 .minimum_version_id = 1,
615 .pre_load = cpu_common_pre_load,
616 .post_load = cpu_common_post_load,
617 .fields = (VMStateField[]) {
618 VMSTATE_UINT32(halted, CPUState),
619 VMSTATE_UINT32(interrupt_request, CPUState),
620 VMSTATE_END_OF_LIST()
621 },
622 .subsections = (const VMStateDescription*[]) {
623 &vmstate_cpu_common_exception_index,
624 &vmstate_cpu_common_crash_occurred,
625 NULL
626 }
627 };
628
629 #endif
630
631 CPUState *qemu_get_cpu(int index)
632 {
633 CPUState *cpu;
634
635 CPU_FOREACH(cpu) {
636 if (cpu->cpu_index == index) {
637 return cpu;
638 }
639 }
640
641 return NULL;
642 }
643
644 #if !defined(CONFIG_USER_ONLY)
645 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx)
646 {
647 CPUAddressSpace *newas;
648
649 /* Target code should have set num_ases before calling us */
650 assert(asidx < cpu->num_ases);
651
652 if (asidx == 0) {
653 /* address space 0 gets the convenience alias */
654 cpu->as = as;
655 }
656
657 /* KVM cannot currently support multiple address spaces. */
658 assert(asidx == 0 || !kvm_enabled());
659
660 if (!cpu->cpu_ases) {
661 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
662 }
663
664 newas = &cpu->cpu_ases[asidx];
665 newas->cpu = cpu;
666 newas->as = as;
667 if (tcg_enabled()) {
668 newas->tcg_as_listener.commit = tcg_commit;
669 memory_listener_register(&newas->tcg_as_listener, as);
670 }
671 }
672
673 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
674 {
675 /* Return the AddressSpace corresponding to the specified index */
676 return cpu->cpu_ases[asidx].as;
677 }
678 #endif
679
680 void cpu_exec_unrealizefn(CPUState *cpu)
681 {
682 CPUClass *cc = CPU_GET_CLASS(cpu);
683
684 cpu_list_remove(cpu);
685
686 if (cc->vmsd != NULL) {
687 vmstate_unregister(NULL, cc->vmsd, cpu);
688 }
689 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
690 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
691 }
692 }
693
694 void cpu_exec_initfn(CPUState *cpu)
695 {
696 cpu->as = NULL;
697 cpu->num_ases = 0;
698
699 #ifndef CONFIG_USER_ONLY
700 cpu->thread_id = qemu_get_thread_id();
701
702 /* This is a softmmu CPU object, so create a property for it
703 * so users can wire up its memory. (This can't go in qom/cpu.c
704 * because that file is compiled only once for both user-mode
705 * and system builds.) The default if no link is set up is to use
706 * the system address space.
707 */
708 object_property_add_link(OBJECT(cpu), "memory", TYPE_MEMORY_REGION,
709 (Object **)&cpu->memory,
710 qdev_prop_allow_set_link_before_realize,
711 OBJ_PROP_LINK_UNREF_ON_RELEASE,
712 &error_abort);
713 cpu->memory = system_memory;
714 object_ref(OBJECT(cpu->memory));
715 #endif
716 }
717
718 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
719 {
720 CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu);
721
722 cpu_list_add(cpu);
723
724 #ifndef CONFIG_USER_ONLY
725 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
726 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
727 }
728 if (cc->vmsd != NULL) {
729 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
730 }
731 #endif
732 }
733
734 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
735 {
736 /* Flush the whole TB as this will not have race conditions
737 * even if we don't have proper locking yet.
738 * Ideally we would just invalidate the TBs for the
739 * specified PC.
740 */
741 tb_flush(cpu);
742 }
743
744 #if defined(CONFIG_USER_ONLY)
745 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
746
747 {
748 }
749
750 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
751 int flags)
752 {
753 return -ENOSYS;
754 }
755
756 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
757 {
758 }
759
760 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
761 int flags, CPUWatchpoint **watchpoint)
762 {
763 return -ENOSYS;
764 }
765 #else
766 /* Add a watchpoint. */
767 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
768 int flags, CPUWatchpoint **watchpoint)
769 {
770 CPUWatchpoint *wp;
771
772 /* forbid ranges which are empty or run off the end of the address space */
773 if (len == 0 || (addr + len - 1) < addr) {
774 error_report("tried to set invalid watchpoint at %"
775 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
776 return -EINVAL;
777 }
778 wp = g_malloc(sizeof(*wp));
779
780 wp->vaddr = addr;
781 wp->len = len;
782 wp->flags = flags;
783
784 /* keep all GDB-injected watchpoints in front */
785 if (flags & BP_GDB) {
786 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
787 } else {
788 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
789 }
790
791 tlb_flush_page(cpu, addr);
792
793 if (watchpoint)
794 *watchpoint = wp;
795 return 0;
796 }
797
798 /* Remove a specific watchpoint. */
799 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
800 int flags)
801 {
802 CPUWatchpoint *wp;
803
804 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
805 if (addr == wp->vaddr && len == wp->len
806 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
807 cpu_watchpoint_remove_by_ref(cpu, wp);
808 return 0;
809 }
810 }
811 return -ENOENT;
812 }
813
814 /* Remove a specific watchpoint by reference. */
815 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
816 {
817 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
818
819 tlb_flush_page(cpu, watchpoint->vaddr);
820
821 g_free(watchpoint);
822 }
823
824 /* Remove all matching watchpoints. */
825 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
826 {
827 CPUWatchpoint *wp, *next;
828
829 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
830 if (wp->flags & mask) {
831 cpu_watchpoint_remove_by_ref(cpu, wp);
832 }
833 }
834 }
835
836 /* Return true if this watchpoint address matches the specified
837 * access (ie the address range covered by the watchpoint overlaps
838 * partially or completely with the address range covered by the
839 * access).
840 */
841 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
842 vaddr addr,
843 vaddr len)
844 {
845 /* We know the lengths are non-zero, but a little caution is
846 * required to avoid errors in the case where the range ends
847 * exactly at the top of the address space and so addr + len
848 * wraps round to zero.
849 */
850 vaddr wpend = wp->vaddr + wp->len - 1;
851 vaddr addrend = addr + len - 1;
852
853 return !(addr > wpend || wp->vaddr > addrend);
854 }
855
856 #endif
857
858 /* Add a breakpoint. */
859 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
860 CPUBreakpoint **breakpoint)
861 {
862 CPUBreakpoint *bp;
863
864 bp = g_malloc(sizeof(*bp));
865
866 bp->pc = pc;
867 bp->flags = flags;
868
869 /* keep all GDB-injected breakpoints in front */
870 if (flags & BP_GDB) {
871 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
872 } else {
873 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
874 }
875
876 breakpoint_invalidate(cpu, pc);
877
878 if (breakpoint) {
879 *breakpoint = bp;
880 }
881 return 0;
882 }
883
884 /* Remove a specific breakpoint. */
885 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
886 {
887 CPUBreakpoint *bp;
888
889 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
890 if (bp->pc == pc && bp->flags == flags) {
891 cpu_breakpoint_remove_by_ref(cpu, bp);
892 return 0;
893 }
894 }
895 return -ENOENT;
896 }
897
898 /* Remove a specific breakpoint by reference. */
899 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
900 {
901 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
902
903 breakpoint_invalidate(cpu, breakpoint->pc);
904
905 g_free(breakpoint);
906 }
907
908 /* Remove all matching breakpoints. */
909 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
910 {
911 CPUBreakpoint *bp, *next;
912
913 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
914 if (bp->flags & mask) {
915 cpu_breakpoint_remove_by_ref(cpu, bp);
916 }
917 }
918 }
919
920 /* enable or disable single step mode. EXCP_DEBUG is returned by the
921 CPU loop after each instruction */
922 void cpu_single_step(CPUState *cpu, int enabled)
923 {
924 if (cpu->singlestep_enabled != enabled) {
925 cpu->singlestep_enabled = enabled;
926 if (kvm_enabled()) {
927 kvm_update_guest_debug(cpu, 0);
928 } else {
929 /* must flush all the translated code to avoid inconsistencies */
930 /* XXX: only flush what is necessary */
931 tb_flush(cpu);
932 }
933 }
934 }
935
936 void cpu_abort(CPUState *cpu, const char *fmt, ...)
937 {
938 va_list ap;
939 va_list ap2;
940
941 va_start(ap, fmt);
942 va_copy(ap2, ap);
943 fprintf(stderr, "qemu: fatal: ");
944 vfprintf(stderr, fmt, ap);
945 fprintf(stderr, "\n");
946 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
947 if (qemu_log_separate()) {
948 qemu_log_lock();
949 qemu_log("qemu: fatal: ");
950 qemu_log_vprintf(fmt, ap2);
951 qemu_log("\n");
952 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
953 qemu_log_flush();
954 qemu_log_unlock();
955 qemu_log_close();
956 }
957 va_end(ap2);
958 va_end(ap);
959 replay_finish();
960 #if defined(CONFIG_USER_ONLY)
961 {
962 struct sigaction act;
963 sigfillset(&act.sa_mask);
964 act.sa_handler = SIG_DFL;
965 sigaction(SIGABRT, &act, NULL);
966 }
967 #endif
968 abort();
969 }
970
971 #if !defined(CONFIG_USER_ONLY)
972 /* Called from RCU critical section */
973 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
974 {
975 RAMBlock *block;
976
977 block = atomic_rcu_read(&ram_list.mru_block);
978 if (block && addr - block->offset < block->max_length) {
979 return block;
980 }
981 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
982 if (addr - block->offset < block->max_length) {
983 goto found;
984 }
985 }
986
987 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
988 abort();
989
990 found:
991 /* It is safe to write mru_block outside the iothread lock. This
992 * is what happens:
993 *
994 * mru_block = xxx
995 * rcu_read_unlock()
996 * xxx removed from list
997 * rcu_read_lock()
998 * read mru_block
999 * mru_block = NULL;
1000 * call_rcu(reclaim_ramblock, xxx);
1001 * rcu_read_unlock()
1002 *
1003 * atomic_rcu_set is not needed here. The block was already published
1004 * when it was placed into the list. Here we're just making an extra
1005 * copy of the pointer.
1006 */
1007 ram_list.mru_block = block;
1008 return block;
1009 }
1010
1011 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1012 {
1013 CPUState *cpu;
1014 ram_addr_t start1;
1015 RAMBlock *block;
1016 ram_addr_t end;
1017
1018 end = TARGET_PAGE_ALIGN(start + length);
1019 start &= TARGET_PAGE_MASK;
1020
1021 rcu_read_lock();
1022 block = qemu_get_ram_block(start);
1023 assert(block == qemu_get_ram_block(end - 1));
1024 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1025 CPU_FOREACH(cpu) {
1026 tlb_reset_dirty(cpu, start1, length);
1027 }
1028 rcu_read_unlock();
1029 }
1030
1031 /* Note: start and end must be within the same ram block. */
1032 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1033 ram_addr_t length,
1034 unsigned client)
1035 {
1036 DirtyMemoryBlocks *blocks;
1037 unsigned long end, page;
1038 bool dirty = false;
1039
1040 if (length == 0) {
1041 return false;
1042 }
1043
1044 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1045 page = start >> TARGET_PAGE_BITS;
1046
1047 rcu_read_lock();
1048
1049 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1050
1051 while (page < end) {
1052 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1053 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1054 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1055
1056 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1057 offset, num);
1058 page += num;
1059 }
1060
1061 rcu_read_unlock();
1062
1063 if (dirty && tcg_enabled()) {
1064 tlb_reset_dirty_range_all(start, length);
1065 }
1066
1067 return dirty;
1068 }
1069
1070 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1071 (ram_addr_t start, ram_addr_t length, unsigned client)
1072 {
1073 DirtyMemoryBlocks *blocks;
1074 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1075 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1076 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1077 DirtyBitmapSnapshot *snap;
1078 unsigned long page, end, dest;
1079
1080 snap = g_malloc0(sizeof(*snap) +
1081 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1082 snap->start = first;
1083 snap->end = last;
1084
1085 page = first >> TARGET_PAGE_BITS;
1086 end = last >> TARGET_PAGE_BITS;
1087 dest = 0;
1088
1089 rcu_read_lock();
1090
1091 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1092
1093 while (page < end) {
1094 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1095 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1096 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1097
1098 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1099 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1100 offset >>= BITS_PER_LEVEL;
1101
1102 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1103 blocks->blocks[idx] + offset,
1104 num);
1105 page += num;
1106 dest += num >> BITS_PER_LEVEL;
1107 }
1108
1109 rcu_read_unlock();
1110
1111 if (tcg_enabled()) {
1112 tlb_reset_dirty_range_all(start, length);
1113 }
1114
1115 return snap;
1116 }
1117
1118 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1119 ram_addr_t start,
1120 ram_addr_t length)
1121 {
1122 unsigned long page, end;
1123
1124 assert(start >= snap->start);
1125 assert(start + length <= snap->end);
1126
1127 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1128 page = (start - snap->start) >> TARGET_PAGE_BITS;
1129
1130 while (page < end) {
1131 if (test_bit(page, snap->dirty)) {
1132 return true;
1133 }
1134 page++;
1135 }
1136 return false;
1137 }
1138
1139 /* Called from RCU critical section */
1140 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1141 MemoryRegionSection *section,
1142 target_ulong vaddr,
1143 hwaddr paddr, hwaddr xlat,
1144 int prot,
1145 target_ulong *address)
1146 {
1147 hwaddr iotlb;
1148 CPUWatchpoint *wp;
1149
1150 if (memory_region_is_ram(section->mr)) {
1151 /* Normal RAM. */
1152 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1153 if (!section->readonly) {
1154 iotlb |= PHYS_SECTION_NOTDIRTY;
1155 } else {
1156 iotlb |= PHYS_SECTION_ROM;
1157 }
1158 } else {
1159 AddressSpaceDispatch *d;
1160
1161 d = atomic_rcu_read(&section->address_space->dispatch);
1162 iotlb = section - d->map.sections;
1163 iotlb += xlat;
1164 }
1165
1166 /* Make accesses to pages with watchpoints go via the
1167 watchpoint trap routines. */
1168 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1169 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1170 /* Avoid trapping reads of pages with a write breakpoint. */
1171 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1172 iotlb = PHYS_SECTION_WATCH + paddr;
1173 *address |= TLB_MMIO;
1174 break;
1175 }
1176 }
1177 }
1178
1179 return iotlb;
1180 }
1181 #endif /* defined(CONFIG_USER_ONLY) */
1182
1183 #if !defined(CONFIG_USER_ONLY)
1184
1185 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1186 uint16_t section);
1187 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
1188
1189 static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
1190 qemu_anon_ram_alloc;
1191
1192 /*
1193 * Set a custom physical guest memory alloator.
1194 * Accelerators with unusual needs may need this. Hopefully, we can
1195 * get rid of it eventually.
1196 */
1197 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
1198 {
1199 phys_mem_alloc = alloc;
1200 }
1201
1202 static uint16_t phys_section_add(PhysPageMap *map,
1203 MemoryRegionSection *section)
1204 {
1205 /* The physical section number is ORed with a page-aligned
1206 * pointer to produce the iotlb entries. Thus it should
1207 * never overflow into the page-aligned value.
1208 */
1209 assert(map->sections_nb < TARGET_PAGE_SIZE);
1210
1211 if (map->sections_nb == map->sections_nb_alloc) {
1212 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1213 map->sections = g_renew(MemoryRegionSection, map->sections,
1214 map->sections_nb_alloc);
1215 }
1216 map->sections[map->sections_nb] = *section;
1217 memory_region_ref(section->mr);
1218 return map->sections_nb++;
1219 }
1220
1221 static void phys_section_destroy(MemoryRegion *mr)
1222 {
1223 bool have_sub_page = mr->subpage;
1224
1225 memory_region_unref(mr);
1226
1227 if (have_sub_page) {
1228 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1229 object_unref(OBJECT(&subpage->iomem));
1230 g_free(subpage);
1231 }
1232 }
1233
1234 static void phys_sections_free(PhysPageMap *map)
1235 {
1236 while (map->sections_nb > 0) {
1237 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1238 phys_section_destroy(section->mr);
1239 }
1240 g_free(map->sections);
1241 g_free(map->nodes);
1242 }
1243
1244 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
1245 {
1246 subpage_t *subpage;
1247 hwaddr base = section->offset_within_address_space
1248 & TARGET_PAGE_MASK;
1249 MemoryRegionSection *existing = phys_page_find(d->phys_map, base,
1250 d->map.nodes, d->map.sections);
1251 MemoryRegionSection subsection = {
1252 .offset_within_address_space = base,
1253 .size = int128_make64(TARGET_PAGE_SIZE),
1254 };
1255 hwaddr start, end;
1256
1257 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1258
1259 if (!(existing->mr->subpage)) {
1260 subpage = subpage_init(d->as, base);
1261 subsection.address_space = d->as;
1262 subsection.mr = &subpage->iomem;
1263 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1264 phys_section_add(&d->map, &subsection));
1265 } else {
1266 subpage = container_of(existing->mr, subpage_t, iomem);
1267 }
1268 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1269 end = start + int128_get64(section->size) - 1;
1270 subpage_register(subpage, start, end,
1271 phys_section_add(&d->map, section));
1272 }
1273
1274
1275 static void register_multipage(AddressSpaceDispatch *d,
1276 MemoryRegionSection *section)
1277 {
1278 hwaddr start_addr = section->offset_within_address_space;
1279 uint16_t section_index = phys_section_add(&d->map, section);
1280 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1281 TARGET_PAGE_BITS));
1282
1283 assert(num_pages);
1284 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1285 }
1286
1287 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
1288 {
1289 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1290 AddressSpaceDispatch *d = as->next_dispatch;
1291 MemoryRegionSection now = *section, remain = *section;
1292 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1293
1294 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1295 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1296 - now.offset_within_address_space;
1297
1298 now.size = int128_min(int128_make64(left), now.size);
1299 register_subpage(d, &now);
1300 } else {
1301 now.size = int128_zero();
1302 }
1303 while (int128_ne(remain.size, now.size)) {
1304 remain.size = int128_sub(remain.size, now.size);
1305 remain.offset_within_address_space += int128_get64(now.size);
1306 remain.offset_within_region += int128_get64(now.size);
1307 now = remain;
1308 if (int128_lt(remain.size, page_size)) {
1309 register_subpage(d, &now);
1310 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1311 now.size = page_size;
1312 register_subpage(d, &now);
1313 } else {
1314 now.size = int128_and(now.size, int128_neg(page_size));
1315 register_multipage(d, &now);
1316 }
1317 }
1318 }
1319
1320 void qemu_flush_coalesced_mmio_buffer(void)
1321 {
1322 if (kvm_enabled())
1323 kvm_flush_coalesced_mmio_buffer();
1324 }
1325
1326 void qemu_mutex_lock_ramlist(void)
1327 {
1328 qemu_mutex_lock(&ram_list.mutex);
1329 }
1330
1331 void qemu_mutex_unlock_ramlist(void)
1332 {
1333 qemu_mutex_unlock(&ram_list.mutex);
1334 }
1335
1336 #ifdef __linux__
1337 /*
1338 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1339 * may or may not name the same files / on the same filesystem now as
1340 * when we actually open and map them. Iterate over the file
1341 * descriptors instead, and use qemu_fd_getpagesize().
1342 */
1343 static int find_max_supported_pagesize(Object *obj, void *opaque)
1344 {
1345 char *mem_path;
1346 long *hpsize_min = opaque;
1347
1348 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1349 mem_path = object_property_get_str(obj, "mem-path", NULL);
1350 if (mem_path) {
1351 long hpsize = qemu_mempath_getpagesize(mem_path);
1352 if (hpsize < *hpsize_min) {
1353 *hpsize_min = hpsize;
1354 }
1355 } else {
1356 *hpsize_min = getpagesize();
1357 }
1358 }
1359
1360 return 0;
1361 }
1362
1363 long qemu_getrampagesize(void)
1364 {
1365 long hpsize = LONG_MAX;
1366 long mainrampagesize;
1367 Object *memdev_root;
1368
1369 if (mem_path) {
1370 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1371 } else {
1372 mainrampagesize = getpagesize();
1373 }
1374
1375 /* it's possible we have memory-backend objects with
1376 * hugepage-backed RAM. these may get mapped into system
1377 * address space via -numa parameters or memory hotplug
1378 * hooks. we want to take these into account, but we
1379 * also want to make sure these supported hugepage
1380 * sizes are applicable across the entire range of memory
1381 * we may boot from, so we take the min across all
1382 * backends, and assume normal pages in cases where a
1383 * backend isn't backed by hugepages.
1384 */
1385 memdev_root = object_resolve_path("/objects", NULL);
1386 if (memdev_root) {
1387 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1388 }
1389 if (hpsize == LONG_MAX) {
1390 /* No additional memory regions found ==> Report main RAM page size */
1391 return mainrampagesize;
1392 }
1393
1394 /* If NUMA is disabled or the NUMA nodes are not backed with a
1395 * memory-backend, then there is at least one node using "normal" RAM,
1396 * so if its page size is smaller we have got to report that size instead.
1397 */
1398 if (hpsize > mainrampagesize &&
1399 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1400 static bool warned;
1401 if (!warned) {
1402 error_report("Huge page support disabled (n/a for main memory).");
1403 warned = true;
1404 }
1405 return mainrampagesize;
1406 }
1407
1408 return hpsize;
1409 }
1410 #else
1411 long qemu_getrampagesize(void)
1412 {
1413 return getpagesize();
1414 }
1415 #endif
1416
1417 #ifdef __linux__
1418 static int64_t get_file_size(int fd)
1419 {
1420 int64_t size = lseek(fd, 0, SEEK_END);
1421 if (size < 0) {
1422 return -errno;
1423 }
1424 return size;
1425 }
1426
1427 static void *file_ram_alloc(RAMBlock *block,
1428 ram_addr_t memory,
1429 const char *path,
1430 Error **errp)
1431 {
1432 bool unlink_on_error = false;
1433 char *filename;
1434 char *sanitized_name;
1435 char *c;
1436 void *area = MAP_FAILED;
1437 int fd = -1;
1438 int64_t file_size;
1439
1440 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1441 error_setg(errp,
1442 "host lacks kvm mmu notifiers, -mem-path unsupported");
1443 return NULL;
1444 }
1445
1446 for (;;) {
1447 fd = open(path, O_RDWR);
1448 if (fd >= 0) {
1449 /* @path names an existing file, use it */
1450 break;
1451 }
1452 if (errno == ENOENT) {
1453 /* @path names a file that doesn't exist, create it */
1454 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1455 if (fd >= 0) {
1456 unlink_on_error = true;
1457 break;
1458 }
1459 } else if (errno == EISDIR) {
1460 /* @path names a directory, create a file there */
1461 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1462 sanitized_name = g_strdup(memory_region_name(block->mr));
1463 for (c = sanitized_name; *c != '\0'; c++) {
1464 if (*c == '/') {
1465 *c = '_';
1466 }
1467 }
1468
1469 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1470 sanitized_name);
1471 g_free(sanitized_name);
1472
1473 fd = mkstemp(filename);
1474 if (fd >= 0) {
1475 unlink(filename);
1476 g_free(filename);
1477 break;
1478 }
1479 g_free(filename);
1480 }
1481 if (errno != EEXIST && errno != EINTR) {
1482 error_setg_errno(errp, errno,
1483 "can't open backing store %s for guest RAM",
1484 path);
1485 goto error;
1486 }
1487 /*
1488 * Try again on EINTR and EEXIST. The latter happens when
1489 * something else creates the file between our two open().
1490 */
1491 }
1492
1493 block->page_size = qemu_fd_getpagesize(fd);
1494 block->mr->align = block->page_size;
1495 #if defined(__s390x__)
1496 if (kvm_enabled()) {
1497 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1498 }
1499 #endif
1500
1501 file_size = get_file_size(fd);
1502
1503 if (memory < block->page_size) {
1504 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1505 "or larger than page size 0x%zx",
1506 memory, block->page_size);
1507 goto error;
1508 }
1509
1510 if (file_size > 0 && file_size < memory) {
1511 error_setg(errp, "backing store %s size 0x%" PRIx64
1512 " does not match 'size' option 0x" RAM_ADDR_FMT,
1513 path, file_size, memory);
1514 goto error;
1515 }
1516
1517 memory = ROUND_UP(memory, block->page_size);
1518
1519 /*
1520 * ftruncate is not supported by hugetlbfs in older
1521 * hosts, so don't bother bailing out on errors.
1522 * If anything goes wrong with it under other filesystems,
1523 * mmap will fail.
1524 *
1525 * Do not truncate the non-empty backend file to avoid corrupting
1526 * the existing data in the file. Disabling shrinking is not
1527 * enough. For example, the current vNVDIMM implementation stores
1528 * the guest NVDIMM labels at the end of the backend file. If the
1529 * backend file is later extended, QEMU will not be able to find
1530 * those labels. Therefore, extending the non-empty backend file
1531 * is disabled as well.
1532 */
1533 if (!file_size && ftruncate(fd, memory)) {
1534 perror("ftruncate");
1535 }
1536
1537 area = qemu_ram_mmap(fd, memory, block->mr->align,
1538 block->flags & RAM_SHARED);
1539 if (area == MAP_FAILED) {
1540 error_setg_errno(errp, errno,
1541 "unable to map backing store for guest RAM");
1542 goto error;
1543 }
1544
1545 if (mem_prealloc) {
1546 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1547 if (errp && *errp) {
1548 goto error;
1549 }
1550 }
1551
1552 block->fd = fd;
1553 return area;
1554
1555 error:
1556 if (area != MAP_FAILED) {
1557 qemu_ram_munmap(area, memory);
1558 }
1559 if (unlink_on_error) {
1560 unlink(path);
1561 }
1562 if (fd != -1) {
1563 close(fd);
1564 }
1565 return NULL;
1566 }
1567 #endif
1568
1569 /* Called with the ramlist lock held. */
1570 static ram_addr_t find_ram_offset(ram_addr_t size)
1571 {
1572 RAMBlock *block, *next_block;
1573 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1574
1575 assert(size != 0); /* it would hand out same offset multiple times */
1576
1577 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1578 return 0;
1579 }
1580
1581 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1582 ram_addr_t end, next = RAM_ADDR_MAX;
1583
1584 end = block->offset + block->max_length;
1585
1586 QLIST_FOREACH_RCU(next_block, &ram_list.blocks, next) {
1587 if (next_block->offset >= end) {
1588 next = MIN(next, next_block->offset);
1589 }
1590 }
1591 if (next - end >= size && next - end < mingap) {
1592 offset = end;
1593 mingap = next - end;
1594 }
1595 }
1596
1597 if (offset == RAM_ADDR_MAX) {
1598 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1599 (uint64_t)size);
1600 abort();
1601 }
1602
1603 return offset;
1604 }
1605
1606 unsigned long last_ram_page(void)
1607 {
1608 RAMBlock *block;
1609 ram_addr_t last = 0;
1610
1611 rcu_read_lock();
1612 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1613 last = MAX(last, block->offset + block->max_length);
1614 }
1615 rcu_read_unlock();
1616 return last >> TARGET_PAGE_BITS;
1617 }
1618
1619 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1620 {
1621 int ret;
1622
1623 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1624 if (!machine_dump_guest_core(current_machine)) {
1625 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1626 if (ret) {
1627 perror("qemu_madvise");
1628 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1629 "but dump_guest_core=off specified\n");
1630 }
1631 }
1632 }
1633
1634 const char *qemu_ram_get_idstr(RAMBlock *rb)
1635 {
1636 return rb->idstr;
1637 }
1638
1639 bool qemu_ram_is_shared(RAMBlock *rb)
1640 {
1641 return rb->flags & RAM_SHARED;
1642 }
1643
1644 /* Called with iothread lock held. */
1645 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1646 {
1647 RAMBlock *block;
1648
1649 assert(new_block);
1650 assert(!new_block->idstr[0]);
1651
1652 if (dev) {
1653 char *id = qdev_get_dev_path(dev);
1654 if (id) {
1655 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1656 g_free(id);
1657 }
1658 }
1659 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1660
1661 rcu_read_lock();
1662 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1663 if (block != new_block &&
1664 !strcmp(block->idstr, new_block->idstr)) {
1665 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1666 new_block->idstr);
1667 abort();
1668 }
1669 }
1670 rcu_read_unlock();
1671 }
1672
1673 /* Called with iothread lock held. */
1674 void qemu_ram_unset_idstr(RAMBlock *block)
1675 {
1676 /* FIXME: arch_init.c assumes that this is not called throughout
1677 * migration. Ignore the problem since hot-unplug during migration
1678 * does not work anyway.
1679 */
1680 if (block) {
1681 memset(block->idstr, 0, sizeof(block->idstr));
1682 }
1683 }
1684
1685 size_t qemu_ram_pagesize(RAMBlock *rb)
1686 {
1687 return rb->page_size;
1688 }
1689
1690 /* Returns the largest size of page in use */
1691 size_t qemu_ram_pagesize_largest(void)
1692 {
1693 RAMBlock *block;
1694 size_t largest = 0;
1695
1696 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1697 largest = MAX(largest, qemu_ram_pagesize(block));
1698 }
1699
1700 return largest;
1701 }
1702
1703 static int memory_try_enable_merging(void *addr, size_t len)
1704 {
1705 if (!machine_mem_merge(current_machine)) {
1706 /* disabled by the user */
1707 return 0;
1708 }
1709
1710 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1711 }
1712
1713 /* Only legal before guest might have detected the memory size: e.g. on
1714 * incoming migration, or right after reset.
1715 *
1716 * As memory core doesn't know how is memory accessed, it is up to
1717 * resize callback to update device state and/or add assertions to detect
1718 * misuse, if necessary.
1719 */
1720 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1721 {
1722 assert(block);
1723
1724 newsize = HOST_PAGE_ALIGN(newsize);
1725
1726 if (block->used_length == newsize) {
1727 return 0;
1728 }
1729
1730 if (!(block->flags & RAM_RESIZEABLE)) {
1731 error_setg_errno(errp, EINVAL,
1732 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1733 " in != 0x" RAM_ADDR_FMT, block->idstr,
1734 newsize, block->used_length);
1735 return -EINVAL;
1736 }
1737
1738 if (block->max_length < newsize) {
1739 error_setg_errno(errp, EINVAL,
1740 "Length too large: %s: 0x" RAM_ADDR_FMT
1741 " > 0x" RAM_ADDR_FMT, block->idstr,
1742 newsize, block->max_length);
1743 return -EINVAL;
1744 }
1745
1746 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1747 block->used_length = newsize;
1748 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1749 DIRTY_CLIENTS_ALL);
1750 memory_region_set_size(block->mr, newsize);
1751 if (block->resized) {
1752 block->resized(block->idstr, newsize, block->host);
1753 }
1754 return 0;
1755 }
1756
1757 /* Called with ram_list.mutex held */
1758 static void dirty_memory_extend(ram_addr_t old_ram_size,
1759 ram_addr_t new_ram_size)
1760 {
1761 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1762 DIRTY_MEMORY_BLOCK_SIZE);
1763 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1764 DIRTY_MEMORY_BLOCK_SIZE);
1765 int i;
1766
1767 /* Only need to extend if block count increased */
1768 if (new_num_blocks <= old_num_blocks) {
1769 return;
1770 }
1771
1772 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1773 DirtyMemoryBlocks *old_blocks;
1774 DirtyMemoryBlocks *new_blocks;
1775 int j;
1776
1777 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1778 new_blocks = g_malloc(sizeof(*new_blocks) +
1779 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1780
1781 if (old_num_blocks) {
1782 memcpy(new_blocks->blocks, old_blocks->blocks,
1783 old_num_blocks * sizeof(old_blocks->blocks[0]));
1784 }
1785
1786 for (j = old_num_blocks; j < new_num_blocks; j++) {
1787 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1788 }
1789
1790 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1791
1792 if (old_blocks) {
1793 g_free_rcu(old_blocks, rcu);
1794 }
1795 }
1796 }
1797
1798 static void ram_block_add(RAMBlock *new_block, Error **errp)
1799 {
1800 RAMBlock *block;
1801 RAMBlock *last_block = NULL;
1802 ram_addr_t old_ram_size, new_ram_size;
1803 Error *err = NULL;
1804
1805 old_ram_size = last_ram_page();
1806
1807 qemu_mutex_lock_ramlist();
1808 new_block->offset = find_ram_offset(new_block->max_length);
1809
1810 if (!new_block->host) {
1811 if (xen_enabled()) {
1812 xen_ram_alloc(new_block->offset, new_block->max_length,
1813 new_block->mr, &err);
1814 if (err) {
1815 error_propagate(errp, err);
1816 qemu_mutex_unlock_ramlist();
1817 return;
1818 }
1819 } else {
1820 new_block->host = phys_mem_alloc(new_block->max_length,
1821 &new_block->mr->align);
1822 if (!new_block->host) {
1823 error_setg_errno(errp, errno,
1824 "cannot set up guest memory '%s'",
1825 memory_region_name(new_block->mr));
1826 qemu_mutex_unlock_ramlist();
1827 return;
1828 }
1829 memory_try_enable_merging(new_block->host, new_block->max_length);
1830 }
1831 }
1832
1833 new_ram_size = MAX(old_ram_size,
1834 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1835 if (new_ram_size > old_ram_size) {
1836 dirty_memory_extend(old_ram_size, new_ram_size);
1837 }
1838 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1839 * QLIST (which has an RCU-friendly variant) does not have insertion at
1840 * tail, so save the last element in last_block.
1841 */
1842 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
1843 last_block = block;
1844 if (block->max_length < new_block->max_length) {
1845 break;
1846 }
1847 }
1848 if (block) {
1849 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1850 } else if (last_block) {
1851 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1852 } else { /* list is empty */
1853 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1854 }
1855 ram_list.mru_block = NULL;
1856
1857 /* Write list before version */
1858 smp_wmb();
1859 ram_list.version++;
1860 qemu_mutex_unlock_ramlist();
1861
1862 cpu_physical_memory_set_dirty_range(new_block->offset,
1863 new_block->used_length,
1864 DIRTY_CLIENTS_ALL);
1865
1866 if (new_block->host) {
1867 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1868 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1869 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1870 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1871 ram_block_notify_add(new_block->host, new_block->max_length);
1872 }
1873 }
1874
1875 #ifdef __linux__
1876 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
1877 bool share, const char *mem_path,
1878 Error **errp)
1879 {
1880 RAMBlock *new_block;
1881 Error *local_err = NULL;
1882
1883 if (xen_enabled()) {
1884 error_setg(errp, "-mem-path not supported with Xen");
1885 return NULL;
1886 }
1887
1888 if (phys_mem_alloc != qemu_anon_ram_alloc) {
1889 /*
1890 * file_ram_alloc() needs to allocate just like
1891 * phys_mem_alloc, but we haven't bothered to provide
1892 * a hook there.
1893 */
1894 error_setg(errp,
1895 "-mem-path not supported with this accelerator");
1896 return NULL;
1897 }
1898
1899 size = HOST_PAGE_ALIGN(size);
1900 new_block = g_malloc0(sizeof(*new_block));
1901 new_block->mr = mr;
1902 new_block->used_length = size;
1903 new_block->max_length = size;
1904 new_block->flags = share ? RAM_SHARED : 0;
1905 new_block->host = file_ram_alloc(new_block, size,
1906 mem_path, errp);
1907 if (!new_block->host) {
1908 g_free(new_block);
1909 return NULL;
1910 }
1911
1912 ram_block_add(new_block, &local_err);
1913 if (local_err) {
1914 g_free(new_block);
1915 error_propagate(errp, local_err);
1916 return NULL;
1917 }
1918 return new_block;
1919 }
1920 #endif
1921
1922 static
1923 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
1924 void (*resized)(const char*,
1925 uint64_t length,
1926 void *host),
1927 void *host, bool resizeable,
1928 MemoryRegion *mr, Error **errp)
1929 {
1930 RAMBlock *new_block;
1931 Error *local_err = NULL;
1932
1933 size = HOST_PAGE_ALIGN(size);
1934 max_size = HOST_PAGE_ALIGN(max_size);
1935 new_block = g_malloc0(sizeof(*new_block));
1936 new_block->mr = mr;
1937 new_block->resized = resized;
1938 new_block->used_length = size;
1939 new_block->max_length = max_size;
1940 assert(max_size >= size);
1941 new_block->fd = -1;
1942 new_block->page_size = getpagesize();
1943 new_block->host = host;
1944 if (host) {
1945 new_block->flags |= RAM_PREALLOC;
1946 }
1947 if (resizeable) {
1948 new_block->flags |= RAM_RESIZEABLE;
1949 }
1950 ram_block_add(new_block, &local_err);
1951 if (local_err) {
1952 g_free(new_block);
1953 error_propagate(errp, local_err);
1954 return NULL;
1955 }
1956 return new_block;
1957 }
1958
1959 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
1960 MemoryRegion *mr, Error **errp)
1961 {
1962 return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp);
1963 }
1964
1965 RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp)
1966 {
1967 return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp);
1968 }
1969
1970 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
1971 void (*resized)(const char*,
1972 uint64_t length,
1973 void *host),
1974 MemoryRegion *mr, Error **errp)
1975 {
1976 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp);
1977 }
1978
1979 static void reclaim_ramblock(RAMBlock *block)
1980 {
1981 if (block->flags & RAM_PREALLOC) {
1982 ;
1983 } else if (xen_enabled()) {
1984 xen_invalidate_map_cache_entry(block->host);
1985 #ifndef _WIN32
1986 } else if (block->fd >= 0) {
1987 qemu_ram_munmap(block->host, block->max_length);
1988 close(block->fd);
1989 #endif
1990 } else {
1991 qemu_anon_ram_free(block->host, block->max_length);
1992 }
1993 g_free(block);
1994 }
1995
1996 void qemu_ram_free(RAMBlock *block)
1997 {
1998 if (!block) {
1999 return;
2000 }
2001
2002 if (block->host) {
2003 ram_block_notify_remove(block->host, block->max_length);
2004 }
2005
2006 qemu_mutex_lock_ramlist();
2007 QLIST_REMOVE_RCU(block, next);
2008 ram_list.mru_block = NULL;
2009 /* Write list before version */
2010 smp_wmb();
2011 ram_list.version++;
2012 call_rcu(block, reclaim_ramblock, rcu);
2013 qemu_mutex_unlock_ramlist();
2014 }
2015
2016 #ifndef _WIN32
2017 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2018 {
2019 RAMBlock *block;
2020 ram_addr_t offset;
2021 int flags;
2022 void *area, *vaddr;
2023
2024 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
2025 offset = addr - block->offset;
2026 if (offset < block->max_length) {
2027 vaddr = ramblock_ptr(block, offset);
2028 if (block->flags & RAM_PREALLOC) {
2029 ;
2030 } else if (xen_enabled()) {
2031 abort();
2032 } else {
2033 flags = MAP_FIXED;
2034 if (block->fd >= 0) {
2035 flags |= (block->flags & RAM_SHARED ?
2036 MAP_SHARED : MAP_PRIVATE);
2037 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2038 flags, block->fd, offset);
2039 } else {
2040 /*
2041 * Remap needs to match alloc. Accelerators that
2042 * set phys_mem_alloc never remap. If they did,
2043 * we'd need a remap hook here.
2044 */
2045 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2046
2047 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2048 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2049 flags, -1, 0);
2050 }
2051 if (area != vaddr) {
2052 fprintf(stderr, "Could not remap addr: "
2053 RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
2054 length, addr);
2055 exit(1);
2056 }
2057 memory_try_enable_merging(vaddr, length);
2058 qemu_ram_setup_dump(vaddr, length);
2059 }
2060 }
2061 }
2062 }
2063 #endif /* !_WIN32 */
2064
2065 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2066 * This should not be used for general purpose DMA. Use address_space_map
2067 * or address_space_rw instead. For local memory (e.g. video ram) that the
2068 * device owns, use memory_region_get_ram_ptr.
2069 *
2070 * Called within RCU critical section.
2071 */
2072 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2073 {
2074 RAMBlock *block = ram_block;
2075
2076 if (block == NULL) {
2077 block = qemu_get_ram_block(addr);
2078 addr -= block->offset;
2079 }
2080
2081 if (xen_enabled() && block->host == NULL) {
2082 /* We need to check if the requested address is in the RAM
2083 * because we don't want to map the entire memory in QEMU.
2084 * In that case just map until the end of the page.
2085 */
2086 if (block->offset == 0) {
2087 return xen_map_cache(addr, 0, 0);
2088 }
2089
2090 block->host = xen_map_cache(block->offset, block->max_length, 1);
2091 }
2092 return ramblock_ptr(block, addr);
2093 }
2094
2095 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2096 * but takes a size argument.
2097 *
2098 * Called within RCU critical section.
2099 */
2100 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2101 hwaddr *size)
2102 {
2103 RAMBlock *block = ram_block;
2104 if (*size == 0) {
2105 return NULL;
2106 }
2107
2108 if (block == NULL) {
2109 block = qemu_get_ram_block(addr);
2110 addr -= block->offset;
2111 }
2112 *size = MIN(*size, block->max_length - addr);
2113
2114 if (xen_enabled() && block->host == NULL) {
2115 /* We need to check if the requested address is in the RAM
2116 * because we don't want to map the entire memory in QEMU.
2117 * In that case just map the requested area.
2118 */
2119 if (block->offset == 0) {
2120 return xen_map_cache(addr, *size, 1);
2121 }
2122
2123 block->host = xen_map_cache(block->offset, block->max_length, 1);
2124 }
2125
2126 return ramblock_ptr(block, addr);
2127 }
2128
2129 /*
2130 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2131 * in that RAMBlock.
2132 *
2133 * ptr: Host pointer to look up
2134 * round_offset: If true round the result offset down to a page boundary
2135 * *ram_addr: set to result ram_addr
2136 * *offset: set to result offset within the RAMBlock
2137 *
2138 * Returns: RAMBlock (or NULL if not found)
2139 *
2140 * By the time this function returns, the returned pointer is not protected
2141 * by RCU anymore. If the caller is not within an RCU critical section and
2142 * does not hold the iothread lock, it must have other means of protecting the
2143 * pointer, such as a reference to the region that includes the incoming
2144 * ram_addr_t.
2145 */
2146 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2147 ram_addr_t *offset)
2148 {
2149 RAMBlock *block;
2150 uint8_t *host = ptr;
2151
2152 if (xen_enabled()) {
2153 ram_addr_t ram_addr;
2154 rcu_read_lock();
2155 ram_addr = xen_ram_addr_from_mapcache(ptr);
2156 block = qemu_get_ram_block(ram_addr);
2157 if (block) {
2158 *offset = ram_addr - block->offset;
2159 }
2160 rcu_read_unlock();
2161 return block;
2162 }
2163
2164 rcu_read_lock();
2165 block = atomic_rcu_read(&ram_list.mru_block);
2166 if (block && block->host && host - block->host < block->max_length) {
2167 goto found;
2168 }
2169
2170 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
2171 /* This case append when the block is not mapped. */
2172 if (block->host == NULL) {
2173 continue;
2174 }
2175 if (host - block->host < block->max_length) {
2176 goto found;
2177 }
2178 }
2179
2180 rcu_read_unlock();
2181 return NULL;
2182
2183 found:
2184 *offset = (host - block->host);
2185 if (round_offset) {
2186 *offset &= TARGET_PAGE_MASK;
2187 }
2188 rcu_read_unlock();
2189 return block;
2190 }
2191
2192 /*
2193 * Finds the named RAMBlock
2194 *
2195 * name: The name of RAMBlock to find
2196 *
2197 * Returns: RAMBlock (or NULL if not found)
2198 */
2199 RAMBlock *qemu_ram_block_by_name(const char *name)
2200 {
2201 RAMBlock *block;
2202
2203 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
2204 if (!strcmp(name, block->idstr)) {
2205 return block;
2206 }
2207 }
2208
2209 return NULL;
2210 }
2211
2212 /* Some of the softmmu routines need to translate from a host pointer
2213 (typically a TLB entry) back to a ram offset. */
2214 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2215 {
2216 RAMBlock *block;
2217 ram_addr_t offset;
2218
2219 block = qemu_ram_block_from_host(ptr, false, &offset);
2220 if (!block) {
2221 return RAM_ADDR_INVALID;
2222 }
2223
2224 return block->offset + offset;
2225 }
2226
2227 /* Called within RCU critical section. */
2228 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2229 uint64_t val, unsigned size)
2230 {
2231 bool locked = false;
2232
2233 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2234 locked = true;
2235 tb_lock();
2236 tb_invalidate_phys_page_fast(ram_addr, size);
2237 }
2238 switch (size) {
2239 case 1:
2240 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2241 break;
2242 case 2:
2243 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2244 break;
2245 case 4:
2246 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2247 break;
2248 default:
2249 abort();
2250 }
2251
2252 if (locked) {
2253 tb_unlock();
2254 }
2255
2256 /* Set both VGA and migration bits for simplicity and to remove
2257 * the notdirty callback faster.
2258 */
2259 cpu_physical_memory_set_dirty_range(ram_addr, size,
2260 DIRTY_CLIENTS_NOCODE);
2261 /* we remove the notdirty callback only if the code has been
2262 flushed */
2263 if (!cpu_physical_memory_is_clean(ram_addr)) {
2264 tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr);
2265 }
2266 }
2267
2268 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2269 unsigned size, bool is_write)
2270 {
2271 return is_write;
2272 }
2273
2274 static const MemoryRegionOps notdirty_mem_ops = {
2275 .write = notdirty_mem_write,
2276 .valid.accepts = notdirty_mem_accepts,
2277 .endianness = DEVICE_NATIVE_ENDIAN,
2278 };
2279
2280 /* Generate a debug exception if a watchpoint has been hit. */
2281 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2282 {
2283 CPUState *cpu = current_cpu;
2284 CPUClass *cc = CPU_GET_CLASS(cpu);
2285 CPUArchState *env = cpu->env_ptr;
2286 target_ulong pc, cs_base;
2287 target_ulong vaddr;
2288 CPUWatchpoint *wp;
2289 uint32_t cpu_flags;
2290
2291 if (cpu->watchpoint_hit) {
2292 /* We re-entered the check after replacing the TB. Now raise
2293 * the debug interrupt so that is will trigger after the
2294 * current instruction. */
2295 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2296 return;
2297 }
2298 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2299 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2300 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2301 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2302 && (wp->flags & flags)) {
2303 if (flags == BP_MEM_READ) {
2304 wp->flags |= BP_WATCHPOINT_HIT_READ;
2305 } else {
2306 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2307 }
2308 wp->hitaddr = vaddr;
2309 wp->hitattrs = attrs;
2310 if (!cpu->watchpoint_hit) {
2311 if (wp->flags & BP_CPU &&
2312 !cc->debug_check_watchpoint(cpu, wp)) {
2313 wp->flags &= ~BP_WATCHPOINT_HIT;
2314 continue;
2315 }
2316 cpu->watchpoint_hit = wp;
2317
2318 /* Both tb_lock and iothread_mutex will be reset when
2319 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2320 * back into the cpu_exec main loop.
2321 */
2322 tb_lock();
2323 tb_check_watchpoint(cpu);
2324 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2325 cpu->exception_index = EXCP_DEBUG;
2326 cpu_loop_exit(cpu);
2327 } else {
2328 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2329 tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
2330 cpu_loop_exit_noexc(cpu);
2331 }
2332 }
2333 } else {
2334 wp->flags &= ~BP_WATCHPOINT_HIT;
2335 }
2336 }
2337 }
2338
2339 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2340 so these check for a hit then pass through to the normal out-of-line
2341 phys routines. */
2342 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2343 unsigned size, MemTxAttrs attrs)
2344 {
2345 MemTxResult res;
2346 uint64_t data;
2347 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2348 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2349
2350 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2351 switch (size) {
2352 case 1:
2353 data = address_space_ldub(as, addr, attrs, &res);
2354 break;
2355 case 2:
2356 data = address_space_lduw(as, addr, attrs, &res);
2357 break;
2358 case 4:
2359 data = address_space_ldl(as, addr, attrs, &res);
2360 break;
2361 default: abort();
2362 }
2363 *pdata = data;
2364 return res;
2365 }
2366
2367 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2368 uint64_t val, unsigned size,
2369 MemTxAttrs attrs)
2370 {
2371 MemTxResult res;
2372 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2373 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2374
2375 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2376 switch (size) {
2377 case 1:
2378 address_space_stb(as, addr, val, attrs, &res);
2379 break;
2380 case 2:
2381 address_space_stw(as, addr, val, attrs, &res);
2382 break;
2383 case 4:
2384 address_space_stl(as, addr, val, attrs, &res);
2385 break;
2386 default: abort();
2387 }
2388 return res;
2389 }
2390
2391 static const MemoryRegionOps watch_mem_ops = {
2392 .read_with_attrs = watch_mem_read,
2393 .write_with_attrs = watch_mem_write,
2394 .endianness = DEVICE_NATIVE_ENDIAN,
2395 };
2396
2397 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2398 unsigned len, MemTxAttrs attrs)
2399 {
2400 subpage_t *subpage = opaque;
2401 uint8_t buf[8];
2402 MemTxResult res;
2403
2404 #if defined(DEBUG_SUBPAGE)
2405 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2406 subpage, len, addr);
2407 #endif
2408 res = address_space_read(subpage->as, addr + subpage->base,
2409 attrs, buf, len);
2410 if (res) {
2411 return res;
2412 }
2413 switch (len) {
2414 case 1:
2415 *data = ldub_p(buf);
2416 return MEMTX_OK;
2417 case 2:
2418 *data = lduw_p(buf);
2419 return MEMTX_OK;
2420 case 4:
2421 *data = ldl_p(buf);
2422 return MEMTX_OK;
2423 case 8:
2424 *data = ldq_p(buf);
2425 return MEMTX_OK;
2426 default:
2427 abort();
2428 }
2429 }
2430
2431 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2432 uint64_t value, unsigned len, MemTxAttrs attrs)
2433 {
2434 subpage_t *subpage = opaque;
2435 uint8_t buf[8];
2436
2437 #if defined(DEBUG_SUBPAGE)
2438 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2439 " value %"PRIx64"\n",
2440 __func__, subpage, len, addr, value);
2441 #endif
2442 switch (len) {
2443 case 1:
2444 stb_p(buf, value);
2445 break;
2446 case 2:
2447 stw_p(buf, value);
2448 break;
2449 case 4:
2450 stl_p(buf, value);
2451 break;
2452 case 8:
2453 stq_p(buf, value);
2454 break;
2455 default:
2456 abort();
2457 }
2458 return address_space_write(subpage->as, addr + subpage->base,
2459 attrs, buf, len);
2460 }
2461
2462 static bool subpage_accepts(void *opaque, hwaddr addr,
2463 unsigned len, bool is_write)
2464 {
2465 subpage_t *subpage = opaque;
2466 #if defined(DEBUG_SUBPAGE)
2467 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2468 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2469 #endif
2470
2471 return address_space_access_valid(subpage->as, addr + subpage->base,
2472 len, is_write);
2473 }
2474
2475 static const MemoryRegionOps subpage_ops = {
2476 .read_with_attrs = subpage_read,
2477 .write_with_attrs = subpage_write,
2478 .impl.min_access_size = 1,
2479 .impl.max_access_size = 8,
2480 .valid.min_access_size = 1,
2481 .valid.max_access_size = 8,
2482 .valid.accepts = subpage_accepts,
2483 .endianness = DEVICE_NATIVE_ENDIAN,
2484 };
2485
2486 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2487 uint16_t section)
2488 {
2489 int idx, eidx;
2490
2491 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2492 return -1;
2493 idx = SUBPAGE_IDX(start);
2494 eidx = SUBPAGE_IDX(end);
2495 #if defined(DEBUG_SUBPAGE)
2496 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2497 __func__, mmio, start, end, idx, eidx, section);
2498 #endif
2499 for (; idx <= eidx; idx++) {
2500 mmio->sub_section[idx] = section;
2501 }
2502
2503 return 0;
2504 }
2505
2506 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
2507 {
2508 subpage_t *mmio;
2509
2510 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2511 mmio->as = as;
2512 mmio->base = base;
2513 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2514 NULL, TARGET_PAGE_SIZE);
2515 mmio->iomem.subpage = true;
2516 #if defined(DEBUG_SUBPAGE)
2517 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2518 mmio, base, TARGET_PAGE_SIZE);
2519 #endif
2520 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2521
2522 return mmio;
2523 }
2524
2525 static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
2526 MemoryRegion *mr)
2527 {
2528 assert(as);
2529 MemoryRegionSection section = {
2530 .address_space = as,
2531 .mr = mr,
2532 .offset_within_address_space = 0,
2533 .offset_within_region = 0,
2534 .size = int128_2_64(),
2535 };
2536
2537 return phys_section_add(map, &section);
2538 }
2539
2540 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2541 {
2542 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2543 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2544 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2545 MemoryRegionSection *sections = d->map.sections;
2546
2547 return sections[index & ~TARGET_PAGE_MASK].mr;
2548 }
2549
2550 static void io_mem_init(void)
2551 {
2552 memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
2553 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2554 NULL, UINT64_MAX);
2555
2556 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2557 * which can be called without the iothread mutex.
2558 */
2559 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2560 NULL, UINT64_MAX);
2561 memory_region_clear_global_locking(&io_mem_notdirty);
2562
2563 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2564 NULL, UINT64_MAX);
2565 }
2566
2567 static void mem_begin(MemoryListener *listener)
2568 {
2569 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2570 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2571 uint16_t n;
2572
2573 n = dummy_section(&d->map, as, &io_mem_unassigned);
2574 assert(n == PHYS_SECTION_UNASSIGNED);
2575 n = dummy_section(&d->map, as, &io_mem_notdirty);
2576 assert(n == PHYS_SECTION_NOTDIRTY);
2577 n = dummy_section(&d->map, as, &io_mem_rom);
2578 assert(n == PHYS_SECTION_ROM);
2579 n = dummy_section(&d->map, as, &io_mem_watch);
2580 assert(n == PHYS_SECTION_WATCH);
2581
2582 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2583 d->as = as;
2584 as->next_dispatch = d;
2585 }
2586
2587 static void address_space_dispatch_free(AddressSpaceDispatch *d)
2588 {
2589 phys_sections_free(&d->map);
2590 g_free(d);
2591 }
2592
2593 static void mem_commit(MemoryListener *listener)
2594 {
2595 AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
2596 AddressSpaceDispatch *cur = as->dispatch;
2597 AddressSpaceDispatch *next = as->next_dispatch;
2598
2599 phys_page_compact_all(next, next->map.nodes_nb);
2600
2601 atomic_rcu_set(&as->dispatch, next);
2602 if (cur) {
2603 call_rcu(cur, address_space_dispatch_free, rcu);
2604 }
2605 }
2606
2607 static void tcg_commit(MemoryListener *listener)
2608 {
2609 CPUAddressSpace *cpuas;
2610 AddressSpaceDispatch *d;
2611
2612 /* since each CPU stores ram addresses in its TLB cache, we must
2613 reset the modified entries */
2614 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2615 cpu_reloading_memory_map();
2616 /* The CPU and TLB are protected by the iothread lock.
2617 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2618 * may have split the RCU critical section.
2619 */
2620 d = atomic_rcu_read(&cpuas->as->dispatch);
2621 atomic_rcu_set(&cpuas->memory_dispatch, d);
2622 tlb_flush(cpuas->cpu);
2623 }
2624
2625 void address_space_init_dispatch(AddressSpace *as)
2626 {
2627 as->dispatch = NULL;
2628 as->dispatch_listener = (MemoryListener) {
2629 .begin = mem_begin,
2630 .commit = mem_commit,
2631 .region_add = mem_add,
2632 .region_nop = mem_add,
2633 .priority = 0,
2634 };
2635 memory_listener_register(&as->dispatch_listener, as);
2636 }
2637
2638 void address_space_unregister(AddressSpace *as)
2639 {
2640 memory_listener_unregister(&as->dispatch_listener);
2641 }
2642
2643 void address_space_destroy_dispatch(AddressSpace *as)
2644 {
2645 AddressSpaceDispatch *d = as->dispatch;
2646
2647 atomic_rcu_set(&as->dispatch, NULL);
2648 if (d) {
2649 call_rcu(d, address_space_dispatch_free, rcu);
2650 }
2651 }
2652
2653 static void memory_map_init(void)
2654 {
2655 system_memory = g_malloc(sizeof(*system_memory));
2656
2657 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2658 address_space_init(&address_space_memory, system_memory, "memory");
2659
2660 system_io = g_malloc(sizeof(*system_io));
2661 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2662 65536);
2663 address_space_init(&address_space_io, system_io, "I/O");
2664 }
2665
2666 MemoryRegion *get_system_memory(void)
2667 {
2668 return system_memory;
2669 }
2670
2671 MemoryRegion *get_system_io(void)
2672 {
2673 return system_io;
2674 }
2675
2676 #endif /* !defined(CONFIG_USER_ONLY) */
2677
2678 /* physical memory access (slow version, mainly for debug) */
2679 #if defined(CONFIG_USER_ONLY)
2680 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2681 uint8_t *buf, int len, int is_write)
2682 {
2683 int l, flags;
2684 target_ulong page;
2685 void * p;
2686
2687 while (len > 0) {
2688 page = addr & TARGET_PAGE_MASK;
2689 l = (page + TARGET_PAGE_SIZE) - addr;
2690 if (l > len)
2691 l = len;
2692 flags = page_get_flags(page);
2693 if (!(flags & PAGE_VALID))
2694 return -1;
2695 if (is_write) {
2696 if (!(flags & PAGE_WRITE))
2697 return -1;
2698 /* XXX: this code should not depend on lock_user */
2699 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2700 return -1;
2701 memcpy(p, buf, l);
2702 unlock_user(p, addr, l);
2703 } else {
2704 if (!(flags & PAGE_READ))
2705 return -1;
2706 /* XXX: this code should not depend on lock_user */
2707 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2708 return -1;
2709 memcpy(buf, p, l);
2710 unlock_user(p, addr, 0);
2711 }
2712 len -= l;
2713 buf += l;
2714 addr += l;
2715 }
2716 return 0;
2717 }
2718
2719 #else
2720
2721 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2722 hwaddr length)
2723 {
2724 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2725 addr += memory_region_get_ram_addr(mr);
2726
2727 /* No early return if dirty_log_mask is or becomes 0, because
2728 * cpu_physical_memory_set_dirty_range will still call
2729 * xen_modified_memory.
2730 */
2731 if (dirty_log_mask) {
2732 dirty_log_mask =
2733 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2734 }
2735 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2736 tb_lock();
2737 tb_invalidate_phys_range(addr, addr + length);
2738 tb_unlock();
2739 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2740 }
2741 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2742 }
2743
2744 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2745 {
2746 unsigned access_size_max = mr->ops->valid.max_access_size;
2747
2748 /* Regions are assumed to support 1-4 byte accesses unless
2749 otherwise specified. */
2750 if (access_size_max == 0) {
2751 access_size_max = 4;
2752 }
2753
2754 /* Bound the maximum access by the alignment of the address. */
2755 if (!mr->ops->impl.unaligned) {
2756 unsigned align_size_max = addr & -addr;
2757 if (align_size_max != 0 && align_size_max < access_size_max) {
2758 access_size_max = align_size_max;
2759 }
2760 }
2761
2762 /* Don't attempt accesses larger than the maximum. */
2763 if (l > access_size_max) {
2764 l = access_size_max;
2765 }
2766 l = pow2floor(l);
2767
2768 return l;
2769 }
2770
2771 static bool prepare_mmio_access(MemoryRegion *mr)
2772 {
2773 bool unlocked = !qemu_mutex_iothread_locked();
2774 bool release_lock = false;
2775
2776 if (unlocked && mr->global_locking) {
2777 qemu_mutex_lock_iothread();
2778 unlocked = false;
2779 release_lock = true;
2780 }
2781 if (mr->flush_coalesced_mmio) {
2782 if (unlocked) {
2783 qemu_mutex_lock_iothread();
2784 }
2785 qemu_flush_coalesced_mmio_buffer();
2786 if (unlocked) {
2787 qemu_mutex_unlock_iothread();
2788 }
2789 }
2790
2791 return release_lock;
2792 }
2793
2794 /* Called within RCU critical section. */
2795 static MemTxResult address_space_write_continue(AddressSpace *as, hwaddr addr,
2796 MemTxAttrs attrs,
2797 const uint8_t *buf,
2798 int len, hwaddr addr1,
2799 hwaddr l, MemoryRegion *mr)
2800 {
2801 uint8_t *ptr;
2802 uint64_t val;
2803 MemTxResult result = MEMTX_OK;
2804 bool release_lock = false;
2805
2806 for (;;) {
2807 if (!memory_access_is_direct(mr, true)) {
2808 release_lock |= prepare_mmio_access(mr);
2809 l = memory_access_size(mr, l, addr1);
2810 /* XXX: could force current_cpu to NULL to avoid
2811 potential bugs */
2812 switch (l) {
2813 case 8:
2814 /* 64 bit write access */
2815 val = ldq_p(buf);
2816 result |= memory_region_dispatch_write(mr, addr1, val, 8,
2817 attrs);
2818 break;
2819 case 4:
2820 /* 32 bit write access */
2821 val = (uint32_t)ldl_p(buf);
2822 result |= memory_region_dispatch_write(mr, addr1, val, 4,
2823 attrs);
2824 break;
2825 case 2:
2826 /* 16 bit write access */
2827 val = lduw_p(buf);
2828 result |= memory_region_dispatch_write(mr, addr1, val, 2,
2829 attrs);
2830 break;
2831 case 1:
2832 /* 8 bit write access */
2833 val = ldub_p(buf);
2834 result |= memory_region_dispatch_write(mr, addr1, val, 1,
2835 attrs);
2836 break;
2837 default:
2838 abort();
2839 }
2840 } else {
2841 /* RAM case */
2842 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2843 memcpy(ptr, buf, l);
2844 invalidate_and_set_dirty(mr, addr1, l);
2845 }
2846
2847 if (release_lock) {
2848 qemu_mutex_unlock_iothread();
2849 release_lock = false;
2850 }
2851
2852 len -= l;
2853 buf += l;
2854 addr += l;
2855
2856 if (!len) {
2857 break;
2858 }
2859
2860 l = len;
2861 mr = address_space_translate(as, addr, &addr1, &l, true);
2862 }
2863
2864 return result;
2865 }
2866
2867 MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2868 const uint8_t *buf, int len)
2869 {
2870 hwaddr l;
2871 hwaddr addr1;
2872 MemoryRegion *mr;
2873 MemTxResult result = MEMTX_OK;
2874
2875 if (len > 0) {
2876 rcu_read_lock();
2877 l = len;
2878 mr = address_space_translate(as, addr, &addr1, &l, true);
2879 result = address_space_write_continue(as, addr, attrs, buf, len,
2880 addr1, l, mr);
2881 rcu_read_unlock();
2882 }
2883
2884 return result;
2885 }
2886
2887 /* Called within RCU critical section. */
2888 MemTxResult address_space_read_continue(AddressSpace *as, hwaddr addr,
2889 MemTxAttrs attrs, uint8_t *buf,
2890 int len, hwaddr addr1, hwaddr l,
2891 MemoryRegion *mr)
2892 {
2893 uint8_t *ptr;
2894 uint64_t val;
2895 MemTxResult result = MEMTX_OK;
2896 bool release_lock = false;
2897
2898 for (;;) {
2899 if (!memory_access_is_direct(mr, false)) {
2900 /* I/O case */
2901 release_lock |= prepare_mmio_access(mr);
2902 l = memory_access_size(mr, l, addr1);
2903 switch (l) {
2904 case 8:
2905 /* 64 bit read access */
2906 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
2907 attrs);
2908 stq_p(buf, val);
2909 break;
2910 case 4:
2911 /* 32 bit read access */
2912 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
2913 attrs);
2914 stl_p(buf, val);
2915 break;
2916 case 2:
2917 /* 16 bit read access */
2918 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
2919 attrs);
2920 stw_p(buf, val);
2921 break;
2922 case 1:
2923 /* 8 bit read access */
2924 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
2925 attrs);
2926 stb_p(buf, val);
2927 break;
2928 default:
2929 abort();
2930 }
2931 } else {
2932 /* RAM case */
2933 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2934 memcpy(buf, ptr, l);
2935 }
2936
2937 if (release_lock) {
2938 qemu_mutex_unlock_iothread();
2939 release_lock = false;
2940 }
2941
2942 len -= l;
2943 buf += l;
2944 addr += l;
2945
2946 if (!len) {
2947 break;
2948 }
2949
2950 l = len;
2951 mr = address_space_translate(as, addr, &addr1, &l, false);
2952 }
2953
2954 return result;
2955 }
2956
2957 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
2958 MemTxAttrs attrs, uint8_t *buf, int len)
2959 {
2960 hwaddr l;
2961 hwaddr addr1;
2962 MemoryRegion *mr;
2963 MemTxResult result = MEMTX_OK;
2964
2965 if (len > 0) {
2966 rcu_read_lock();
2967 l = len;
2968 mr = address_space_translate(as, addr, &addr1, &l, false);
2969 result = address_space_read_continue(as, addr, attrs, buf, len,
2970 addr1, l, mr);
2971 rcu_read_unlock();
2972 }
2973
2974 return result;
2975 }
2976
2977 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2978 uint8_t *buf, int len, bool is_write)
2979 {
2980 if (is_write) {
2981 return address_space_write(as, addr, attrs, (uint8_t *)buf, len);
2982 } else {
2983 return address_space_read(as, addr, attrs, (uint8_t *)buf, len);
2984 }
2985 }
2986
2987 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
2988 int len, int is_write)
2989 {
2990 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
2991 buf, len, is_write);
2992 }
2993
2994 enum write_rom_type {
2995 WRITE_DATA,
2996 FLUSH_CACHE,
2997 };
2998
2999 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3000 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3001 {
3002 hwaddr l;
3003 uint8_t *ptr;
3004 hwaddr addr1;
3005 MemoryRegion *mr;
3006
3007 rcu_read_lock();
3008 while (len > 0) {
3009 l = len;
3010 mr = address_space_translate(as, addr, &addr1, &l, true);
3011
3012 if (!(memory_region_is_ram(mr) ||
3013 memory_region_is_romd(mr))) {
3014 l = memory_access_size(mr, l, addr1);
3015 } else {
3016 /* ROM/RAM case */
3017 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3018 switch (type) {
3019 case WRITE_DATA:
3020 memcpy(ptr, buf, l);
3021 invalidate_and_set_dirty(mr, addr1, l);
3022 break;
3023 case FLUSH_CACHE:
3024 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3025 break;
3026 }
3027 }
3028 len -= l;
3029 buf += l;
3030 addr += l;
3031 }
3032 rcu_read_unlock();
3033 }
3034
3035 /* used for ROM loading : can write in RAM and ROM */
3036 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3037 const uint8_t *buf, int len)
3038 {
3039 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3040 }
3041
3042 void cpu_flush_icache_range(hwaddr start, int len)
3043 {
3044 /*
3045 * This function should do the same thing as an icache flush that was
3046 * triggered from within the guest. For TCG we are always cache coherent,
3047 * so there is no need to flush anything. For KVM / Xen we need to flush
3048 * the host's instruction cache at least.
3049 */
3050 if (tcg_enabled()) {
3051 return;
3052 }
3053
3054 cpu_physical_memory_write_rom_internal(&address_space_memory,
3055 start, NULL, len, FLUSH_CACHE);
3056 }
3057
3058 typedef struct {
3059 MemoryRegion *mr;
3060 void *buffer;
3061 hwaddr addr;
3062 hwaddr len;
3063 bool in_use;
3064 } BounceBuffer;
3065
3066 static BounceBuffer bounce;
3067
3068 typedef struct MapClient {
3069 QEMUBH *bh;
3070 QLIST_ENTRY(MapClient) link;
3071 } MapClient;
3072
3073 QemuMutex map_client_list_lock;
3074 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3075 = QLIST_HEAD_INITIALIZER(map_client_list);
3076
3077 static void cpu_unregister_map_client_do(MapClient *client)
3078 {
3079 QLIST_REMOVE(client, link);
3080 g_free(client);
3081 }
3082
3083 static void cpu_notify_map_clients_locked(void)
3084 {
3085 MapClient *client;
3086
3087 while (!QLIST_EMPTY(&map_client_list)) {
3088 client = QLIST_FIRST(&map_client_list);
3089 qemu_bh_schedule(client->bh);
3090 cpu_unregister_map_client_do(client);
3091 }
3092 }
3093
3094 void cpu_register_map_client(QEMUBH *bh)
3095 {
3096 MapClient *client = g_malloc(sizeof(*client));
3097
3098 qemu_mutex_lock(&map_client_list_lock);
3099 client->bh = bh;
3100 QLIST_INSERT_HEAD(&map_client_list, client, link);
3101 if (!atomic_read(&bounce.in_use)) {
3102 cpu_notify_map_clients_locked();
3103 }
3104 qemu_mutex_unlock(&map_client_list_lock);
3105 }
3106
3107 void cpu_exec_init_all(void)
3108 {
3109 qemu_mutex_init(&ram_list.mutex);
3110 /* The data structures we set up here depend on knowing the page size,
3111 * so no more changes can be made after this point.
3112 * In an ideal world, nothing we did before we had finished the
3113 * machine setup would care about the target page size, and we could
3114 * do this much later, rather than requiring board models to state
3115 * up front what their requirements are.
3116 */
3117 finalize_target_page_bits();
3118 io_mem_init();
3119 memory_map_init();
3120 qemu_mutex_init(&map_client_list_lock);
3121 }
3122
3123 void cpu_unregister_map_client(QEMUBH *bh)
3124 {
3125 MapClient *client;
3126
3127 qemu_mutex_lock(&map_client_list_lock);
3128 QLIST_FOREACH(client, &map_client_list, link) {
3129 if (client->bh == bh) {
3130 cpu_unregister_map_client_do(client);
3131 break;
3132 }
3133 }
3134 qemu_mutex_unlock(&map_client_list_lock);
3135 }
3136
3137 static void cpu_notify_map_clients(void)
3138 {
3139 qemu_mutex_lock(&map_client_list_lock);
3140 cpu_notify_map_clients_locked();
3141 qemu_mutex_unlock(&map_client_list_lock);
3142 }
3143
3144 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
3145 {
3146 MemoryRegion *mr;
3147 hwaddr l, xlat;
3148
3149 rcu_read_lock();
3150 while (len > 0) {
3151 l = len;
3152 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3153 if (!memory_access_is_direct(mr, is_write)) {
3154 l = memory_access_size(mr, l, addr);
3155 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3156 rcu_read_unlock();
3157 return false;
3158 }
3159 }
3160
3161 len -= l;
3162 addr += l;
3163 }
3164 rcu_read_unlock();
3165 return true;
3166 }
3167
3168 static hwaddr
3169 address_space_extend_translation(AddressSpace *as, hwaddr addr, hwaddr target_len,
3170 MemoryRegion *mr, hwaddr base, hwaddr len,
3171 bool is_write)
3172 {
3173 hwaddr done = 0;
3174 hwaddr xlat;
3175 MemoryRegion *this_mr;
3176
3177 for (;;) {
3178 target_len -= len;
3179 addr += len;
3180 done += len;
3181 if (target_len == 0) {
3182 return done;
3183 }
3184
3185 len = target_len;
3186 this_mr = address_space_translate(as, addr, &xlat, &len, is_write);
3187 if (this_mr != mr || xlat != base + done) {
3188 return done;
3189 }
3190 }
3191 }
3192
3193 /* Map a physical memory region into a host virtual address.
3194 * May map a subset of the requested range, given by and returned in *plen.
3195 * May return NULL if resources needed to perform the mapping are exhausted.
3196 * Use only for reads OR writes - not for read-modify-write operations.
3197 * Use cpu_register_map_client() to know when retrying the map operation is
3198 * likely to succeed.
3199 */
3200 void *address_space_map(AddressSpace *as,
3201 hwaddr addr,
3202 hwaddr *plen,
3203 bool is_write)
3204 {
3205 hwaddr len = *plen;
3206 hwaddr l, xlat;
3207 MemoryRegion *mr;
3208 void *ptr;
3209
3210 if (len == 0) {
3211 return NULL;
3212 }
3213
3214 l = len;
3215 rcu_read_lock();
3216 mr = address_space_translate(as, addr, &xlat, &l, is_write);
3217
3218 if (!memory_access_is_direct(mr, is_write)) {
3219 if (atomic_xchg(&bounce.in_use, true)) {
3220 rcu_read_unlock();
3221 return NULL;
3222 }
3223 /* Avoid unbounded allocations */
3224 l = MIN(l, TARGET_PAGE_SIZE);
3225 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3226 bounce.addr = addr;
3227 bounce.len = l;
3228
3229 memory_region_ref(mr);
3230 bounce.mr = mr;
3231 if (!is_write) {
3232 address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
3233 bounce.buffer, l);
3234 }
3235
3236 rcu_read_unlock();
3237 *plen = l;
3238 return bounce.buffer;
3239 }
3240
3241
3242 memory_region_ref(mr);
3243 *plen = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
3244 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen);
3245 rcu_read_unlock();
3246
3247 return ptr;
3248 }
3249
3250 /* Unmaps a memory region previously mapped by address_space_map().
3251 * Will also mark the memory as dirty if is_write == 1. access_len gives
3252 * the amount of memory that was actually read or written by the caller.
3253 */
3254 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3255 int is_write, hwaddr access_len)
3256 {
3257 if (buffer != bounce.buffer) {
3258 MemoryRegion *mr;
3259 ram_addr_t addr1;
3260
3261 mr = memory_region_from_host(buffer, &addr1);
3262 assert(mr != NULL);
3263 if (is_write) {
3264 invalidate_and_set_dirty(mr, addr1, access_len);
3265 }
3266 if (xen_enabled()) {
3267 xen_invalidate_map_cache_entry(buffer);
3268 }
3269 memory_region_unref(mr);
3270 return;
3271 }
3272 if (is_write) {
3273 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3274 bounce.buffer, access_len);
3275 }
3276 qemu_vfree(bounce.buffer);
3277 bounce.buffer = NULL;
3278 memory_region_unref(bounce.mr);
3279 atomic_mb_set(&bounce.in_use, false);
3280 cpu_notify_map_clients();
3281 }
3282
3283 void *cpu_physical_memory_map(hwaddr addr,
3284 hwaddr *plen,
3285 int is_write)
3286 {
3287 return address_space_map(&address_space_memory, addr, plen, is_write);
3288 }
3289
3290 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3291 int is_write, hwaddr access_len)
3292 {
3293 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3294 }
3295
3296 #define ARG1_DECL AddressSpace *as
3297 #define ARG1 as
3298 #define SUFFIX
3299 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3300 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3301 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3302 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3303 #define RCU_READ_LOCK(...) rcu_read_lock()
3304 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3305 #include "memory_ldst.inc.c"
3306
3307 int64_t address_space_cache_init(MemoryRegionCache *cache,
3308 AddressSpace *as,
3309 hwaddr addr,
3310 hwaddr len,
3311 bool is_write)
3312 {
3313 cache->len = len;
3314 cache->as = as;
3315 cache->xlat = addr;
3316 return len;
3317 }
3318
3319 void address_space_cache_invalidate(MemoryRegionCache *cache,
3320 hwaddr addr,
3321 hwaddr access_len)
3322 {
3323 }
3324
3325 void address_space_cache_destroy(MemoryRegionCache *cache)
3326 {
3327 cache->as = NULL;
3328 }
3329
3330 #define ARG1_DECL MemoryRegionCache *cache
3331 #define ARG1 cache
3332 #define SUFFIX _cached
3333 #define TRANSLATE(addr, ...) \
3334 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3335 #define IS_DIRECT(mr, is_write) true
3336 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3337 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3338 #define RCU_READ_LOCK() rcu_read_lock()
3339 #define RCU_READ_UNLOCK() rcu_read_unlock()
3340 #include "memory_ldst.inc.c"
3341
3342 /* virtual memory access for debug (includes writing to ROM) */
3343 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3344 uint8_t *buf, int len, int is_write)
3345 {
3346 int l;
3347 hwaddr phys_addr;
3348 target_ulong page;
3349
3350 cpu_synchronize_state(cpu);
3351 while (len > 0) {
3352 int asidx;
3353 MemTxAttrs attrs;
3354
3355 page = addr & TARGET_PAGE_MASK;
3356 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3357 asidx = cpu_asidx_from_attrs(cpu, attrs);
3358 /* if no physical page mapped, return an error */
3359 if (phys_addr == -1)
3360 return -1;
3361 l = (page + TARGET_PAGE_SIZE) - addr;
3362 if (l > len)
3363 l = len;
3364 phys_addr += (addr & ~TARGET_PAGE_MASK);
3365 if (is_write) {
3366 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3367 phys_addr, buf, l);
3368 } else {
3369 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3370 MEMTXATTRS_UNSPECIFIED,
3371 buf, l, 0);
3372 }
3373 len -= l;
3374 buf += l;
3375 addr += l;
3376 }
3377 return 0;
3378 }
3379
3380 /*
3381 * Allows code that needs to deal with migration bitmaps etc to still be built
3382 * target independent.
3383 */
3384 size_t qemu_target_page_size(void)
3385 {
3386 return TARGET_PAGE_SIZE;
3387 }
3388
3389 #endif
3390
3391 /*
3392 * A helper function for the _utterly broken_ virtio device model to find out if
3393 * it's running on a big endian machine. Don't do this at home kids!
3394 */
3395 bool target_words_bigendian(void);
3396 bool target_words_bigendian(void)
3397 {
3398 #if defined(TARGET_WORDS_BIGENDIAN)
3399 return true;
3400 #else
3401 return false;
3402 #endif
3403 }
3404
3405 #ifndef CONFIG_USER_ONLY
3406 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3407 {
3408 MemoryRegion*mr;
3409 hwaddr l = 1;
3410 bool res;
3411
3412 rcu_read_lock();
3413 mr = address_space_translate(&address_space_memory,
3414 phys_addr, &phys_addr, &l, false);
3415
3416 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3417 rcu_read_unlock();
3418 return res;
3419 }
3420
3421 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3422 {
3423 RAMBlock *block;
3424 int ret = 0;
3425
3426 rcu_read_lock();
3427 QLIST_FOREACH_RCU(block, &ram_list.blocks, next) {
3428 ret = func(block->idstr, block->host, block->offset,
3429 block->used_length, opaque);
3430 if (ret) {
3431 break;
3432 }
3433 }
3434 rcu_read_unlock();
3435 return ret;
3436 }
3437
3438 /*
3439 * Unmap pages of memory from start to start+length such that
3440 * they a) read as 0, b) Trigger whatever fault mechanism
3441 * the OS provides for postcopy.
3442 * The pages must be unmapped by the end of the function.
3443 * Returns: 0 on success, none-0 on failure
3444 *
3445 */
3446 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3447 {
3448 int ret = -1;
3449
3450 uint8_t *host_startaddr = rb->host + start;
3451
3452 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3453 error_report("ram_block_discard_range: Unaligned start address: %p",
3454 host_startaddr);
3455 goto err;
3456 }
3457
3458 if ((start + length) <= rb->used_length) {
3459 uint8_t *host_endaddr = host_startaddr + length;
3460 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3461 error_report("ram_block_discard_range: Unaligned end address: %p",
3462 host_endaddr);
3463 goto err;
3464 }
3465
3466 errno = ENOTSUP; /* If we are missing MADVISE etc */
3467
3468 if (rb->page_size == qemu_host_page_size) {
3469 #if defined(CONFIG_MADVISE)
3470 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3471 * freeing the page.
3472 */
3473 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3474 #endif
3475 } else {
3476 /* Huge page case - unfortunately it can't do DONTNEED, but
3477 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3478 * huge page file.
3479 */
3480 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3481 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3482 start, length);
3483 #endif
3484 }
3485 if (ret) {
3486 ret = -errno;
3487 error_report("ram_block_discard_range: Failed to discard range "
3488 "%s:%" PRIx64 " +%zx (%d)",
3489 rb->idstr, start, length, ret);
3490 }
3491 } else {
3492 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3493 "/%zx/" RAM_ADDR_FMT")",
3494 rb->idstr, start, length, rb->used_length);
3495 }
3496
3497 err:
3498 return ret;
3499 }
3500
3501 #endif