qxl: check release info object
[qemu.git] / fpu / softfloat-specialize.h
1 /*
2 * QEMU float support
3 *
4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 * the SoftFloat-2a license
10 * the BSD license
11 * GPL-v2-or-later
12 *
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
16 */
17
18 /*
19 ===============================================================================
20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
21 Arithmetic Package, Release 2a.
22
23 Written by John R. Hauser. This work was made possible in part by the
24 International Computer Science Institute, located at Suite 600, 1947 Center
25 Street, Berkeley, California 94704. Funding was partially provided by the
26 National Science Foundation under grant MIP-9311980. The original version
27 of this code was written as part of a project to build a fixed-point vector
28 processor in collaboration with the University of California at Berkeley,
29 overseen by Profs. Nelson Morgan and John Wawrzynek. More information
30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
31 arithmetic/SoftFloat.html'.
32
33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35 TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
38
39 Derivative works are acceptable, even for commercial purposes, so long as
40 (1) they include prominent notice that the work is derivative, and (2) they
41 include prominent notice akin to these four paragraphs for those parts of
42 this code that are retained.
43
44 ===============================================================================
45 */
46
47 /* BSD licensing:
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
53 *
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
56 *
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 *
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
76 */
77
78 /* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
80 */
81
82 /* Define for architectures which deviate from IEEE in not supporting
83 * signaling NaNs (so all NaNs are treated as quiet).
84 */
85 #if defined(TARGET_XTENSA)
86 #define NO_SIGNALING_NANS 1
87 #endif
88
89 /* Define how the architecture discriminates signaling NaNs.
90 * This done with the most significant bit of the fraction.
91 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
92 * the msb must be zero. MIPS is (so far) unique in supporting both the
93 * 2008 revision and backward compatibility with their original choice.
94 * Thus for MIPS we must make the choice at runtime.
95 */
96 static inline flag snan_bit_is_one(float_status *status)
97 {
98 #if defined(TARGET_MIPS)
99 return status->snan_bit_is_one;
100 #elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4)
101 return 1;
102 #else
103 return 0;
104 #endif
105 }
106
107 /*----------------------------------------------------------------------------
108 | For the deconstructed floating-point with fraction FRAC, return true
109 | if the fraction represents a signalling NaN; otherwise false.
110 *----------------------------------------------------------------------------*/
111
112 static bool parts_is_snan_frac(uint64_t frac, float_status *status)
113 {
114 #ifdef NO_SIGNALING_NANS
115 return false;
116 #else
117 flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
118 return msb == snan_bit_is_one(status);
119 #endif
120 }
121
122 /*----------------------------------------------------------------------------
123 | The pattern for a default generated deconstructed floating-point NaN.
124 *----------------------------------------------------------------------------*/
125
126 static FloatParts parts_default_nan(float_status *status)
127 {
128 bool sign = 0;
129 uint64_t frac;
130
131 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
132 /* !snan_bit_is_one, set all bits */
133 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
134 #elif defined(TARGET_I386) || defined(TARGET_X86_64) \
135 || defined(TARGET_MICROBLAZE)
136 /* !snan_bit_is_one, set sign and msb */
137 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
138 sign = 1;
139 #elif defined(TARGET_HPPA)
140 /* snan_bit_is_one, set msb-1. */
141 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
142 #else
143 /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
144 * S390, SH4, TriCore, and Xtensa. I cannot find documentation
145 * for Unicore32; the choice from the original commit is unchanged.
146 * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
147 * do not have floating-point.
148 */
149 if (snan_bit_is_one(status)) {
150 /* set all bits other than msb */
151 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
152 } else {
153 /* set msb */
154 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
155 }
156 #endif
157
158 return (FloatParts) {
159 .cls = float_class_qnan,
160 .sign = sign,
161 .exp = INT_MAX,
162 .frac = frac
163 };
164 }
165
166 /*----------------------------------------------------------------------------
167 | Returns a quiet NaN from a signalling NaN for the deconstructed
168 | floating-point parts.
169 *----------------------------------------------------------------------------*/
170
171 static FloatParts parts_silence_nan(FloatParts a, float_status *status)
172 {
173 #ifdef NO_SIGNALING_NANS
174 g_assert_not_reached();
175 #elif defined(TARGET_HPPA)
176 a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
177 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
178 #else
179 if (snan_bit_is_one(status)) {
180 return parts_default_nan(status);
181 } else {
182 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
183 }
184 #endif
185 a.cls = float_class_qnan;
186 return a;
187 }
188
189 /*----------------------------------------------------------------------------
190 | The pattern for a default generated extended double-precision NaN.
191 *----------------------------------------------------------------------------*/
192 floatx80 floatx80_default_nan(float_status *status)
193 {
194 floatx80 r;
195
196 /* None of the targets that have snan_bit_is_one use floatx80. */
197 assert(!snan_bit_is_one(status));
198 #if defined(TARGET_M68K)
199 r.low = LIT64(0xFFFFFFFFFFFFFFFF);
200 r.high = 0x7FFF;
201 #else
202 /* X86 */
203 r.low = LIT64(0xC000000000000000);
204 r.high = 0xFFFF;
205 #endif
206 return r;
207 }
208
209 /*----------------------------------------------------------------------------
210 | The pattern for a default generated extended double-precision inf.
211 *----------------------------------------------------------------------------*/
212
213 #define floatx80_infinity_high 0x7FFF
214 #if defined(TARGET_M68K)
215 #define floatx80_infinity_low LIT64(0x0000000000000000)
216 #else
217 #define floatx80_infinity_low LIT64(0x8000000000000000)
218 #endif
219
220 const floatx80 floatx80_infinity
221 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
222
223 /*----------------------------------------------------------------------------
224 | Raises the exceptions specified by `flags'. Floating-point traps can be
225 | defined here if desired. It is currently not possible for such a trap
226 | to substitute a result value. If traps are not implemented, this routine
227 | should be simply `float_exception_flags |= flags;'.
228 *----------------------------------------------------------------------------*/
229
230 void float_raise(uint8_t flags, float_status *status)
231 {
232 status->float_exception_flags |= flags;
233 }
234
235 /*----------------------------------------------------------------------------
236 | Internal canonical NaN format.
237 *----------------------------------------------------------------------------*/
238 typedef struct {
239 flag sign;
240 uint64_t high, low;
241 } commonNaNT;
242
243 /*----------------------------------------------------------------------------
244 | Returns 1 if the half-precision floating-point value `a' is a quiet
245 | NaN; otherwise returns 0.
246 *----------------------------------------------------------------------------*/
247
248 int float16_is_quiet_nan(float16 a_, float_status *status)
249 {
250 #ifdef NO_SIGNALING_NANS
251 return float16_is_any_nan(a_);
252 #else
253 uint16_t a = float16_val(a_);
254 if (snan_bit_is_one(status)) {
255 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
256 } else {
257 return ((a & ~0x8000) >= 0x7C80);
258 }
259 #endif
260 }
261
262 /*----------------------------------------------------------------------------
263 | Returns 1 if the half-precision floating-point value `a' is a signaling
264 | NaN; otherwise returns 0.
265 *----------------------------------------------------------------------------*/
266
267 int float16_is_signaling_nan(float16 a_, float_status *status)
268 {
269 #ifdef NO_SIGNALING_NANS
270 return 0;
271 #else
272 uint16_t a = float16_val(a_);
273 if (snan_bit_is_one(status)) {
274 return ((a & ~0x8000) >= 0x7C80);
275 } else {
276 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
277 }
278 #endif
279 }
280
281 /*----------------------------------------------------------------------------
282 | Returns 1 if the single-precision floating-point value `a' is a quiet
283 | NaN; otherwise returns 0.
284 *----------------------------------------------------------------------------*/
285
286 int float32_is_quiet_nan(float32 a_, float_status *status)
287 {
288 #ifdef NO_SIGNALING_NANS
289 return float32_is_any_nan(a_);
290 #else
291 uint32_t a = float32_val(a_);
292 if (snan_bit_is_one(status)) {
293 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
294 } else {
295 return ((uint32_t)(a << 1) >= 0xFF800000);
296 }
297 #endif
298 }
299
300 /*----------------------------------------------------------------------------
301 | Returns 1 if the single-precision floating-point value `a' is a signaling
302 | NaN; otherwise returns 0.
303 *----------------------------------------------------------------------------*/
304
305 int float32_is_signaling_nan(float32 a_, float_status *status)
306 {
307 #ifdef NO_SIGNALING_NANS
308 return 0;
309 #else
310 uint32_t a = float32_val(a_);
311 if (snan_bit_is_one(status)) {
312 return ((uint32_t)(a << 1) >= 0xFF800000);
313 } else {
314 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
315 }
316 #endif
317 }
318
319 /*----------------------------------------------------------------------------
320 | Returns the result of converting the single-precision floating-point NaN
321 | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
322 | exception is raised.
323 *----------------------------------------------------------------------------*/
324
325 static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
326 {
327 commonNaNT z;
328
329 if (float32_is_signaling_nan(a, status)) {
330 float_raise(float_flag_invalid, status);
331 }
332 z.sign = float32_val(a) >> 31;
333 z.low = 0;
334 z.high = ((uint64_t)float32_val(a)) << 41;
335 return z;
336 }
337
338 /*----------------------------------------------------------------------------
339 | Returns the result of converting the canonical NaN `a' to the single-
340 | precision floating-point format.
341 *----------------------------------------------------------------------------*/
342
343 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
344 {
345 uint32_t mantissa = a.high >> 41;
346
347 if (status->default_nan_mode) {
348 return float32_default_nan(status);
349 }
350
351 if (mantissa) {
352 return make_float32(
353 (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
354 } else {
355 return float32_default_nan(status);
356 }
357 }
358
359 /*----------------------------------------------------------------------------
360 | Select which NaN to propagate for a two-input operation.
361 | IEEE754 doesn't specify all the details of this, so the
362 | algorithm is target-specific.
363 | The routine is passed various bits of information about the
364 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
365 | Note that signalling NaNs are always squashed to quiet NaNs
366 | by the caller, by calling floatXX_silence_nan() before
367 | returning them.
368 |
369 | aIsLargerSignificand is only valid if both a and b are NaNs
370 | of some kind, and is true if a has the larger significand,
371 | or if both a and b have the same significand but a is
372 | positive but b is negative. It is only needed for the x87
373 | tie-break rule.
374 *----------------------------------------------------------------------------*/
375
376 static int pickNaN(FloatClass a_cls, FloatClass b_cls,
377 flag aIsLargerSignificand)
378 {
379 #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
380 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
381 * the first of:
382 * 1. A if it is signaling
383 * 2. B if it is signaling
384 * 3. A (quiet)
385 * 4. B (quiet)
386 * A signaling NaN is always quietened before returning it.
387 */
388 /* According to MIPS specifications, if one of the two operands is
389 * a sNaN, a new qNaN has to be generated. This is done in
390 * floatXX_silence_nan(). For qNaN inputs the specifications
391 * says: "When possible, this QNaN result is one of the operand QNaN
392 * values." In practice it seems that most implementations choose
393 * the first operand if both operands are qNaN. In short this gives
394 * the following rules:
395 * 1. A if it is signaling
396 * 2. B if it is signaling
397 * 3. A (quiet)
398 * 4. B (quiet)
399 * A signaling NaN is always silenced before returning it.
400 */
401 if (is_snan(a_cls)) {
402 return 0;
403 } else if (is_snan(b_cls)) {
404 return 1;
405 } else if (is_qnan(a_cls)) {
406 return 0;
407 } else {
408 return 1;
409 }
410 #elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K)
411 /* PowerPC propagation rules:
412 * 1. A if it sNaN or qNaN
413 * 2. B if it sNaN or qNaN
414 * A signaling NaN is always silenced before returning it.
415 */
416 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
417 * 3.4 FLOATING-POINT INSTRUCTION DETAILS
418 * If either operand, but not both operands, of an operation is a
419 * nonsignaling NaN, then that NaN is returned as the result. If both
420 * operands are nonsignaling NaNs, then the destination operand
421 * nonsignaling NaN is returned as the result.
422 * If either operand to an operation is a signaling NaN (SNaN), then the
423 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
424 * is set in the FPCR ENABLE byte, then the exception is taken and the
425 * destination is not modified. If the SNaN exception enable bit is not
426 * set, setting the SNaN bit in the operand to a one converts the SNaN to
427 * a nonsignaling NaN. The operation then continues as described in the
428 * preceding paragraph for nonsignaling NaNs.
429 */
430 if (is_nan(a_cls)) {
431 return 0;
432 } else {
433 return 1;
434 }
435 #else
436 /* This implements x87 NaN propagation rules:
437 * SNaN + QNaN => return the QNaN
438 * two SNaNs => return the one with the larger significand, silenced
439 * two QNaNs => return the one with the larger significand
440 * SNaN and a non-NaN => return the SNaN, silenced
441 * QNaN and a non-NaN => return the QNaN
442 *
443 * If we get down to comparing significands and they are the same,
444 * return the NaN with the positive sign bit (if any).
445 */
446 if (is_snan(a_cls)) {
447 if (is_snan(b_cls)) {
448 return aIsLargerSignificand ? 0 : 1;
449 }
450 return is_qnan(b_cls) ? 1 : 0;
451 } else if (is_qnan(a_cls)) {
452 if (is_snan(b_cls) || !is_qnan(b_cls)) {
453 return 0;
454 } else {
455 return aIsLargerSignificand ? 0 : 1;
456 }
457 } else {
458 return 1;
459 }
460 #endif
461 }
462
463 /*----------------------------------------------------------------------------
464 | Select which NaN to propagate for a three-input operation.
465 | For the moment we assume that no CPU needs the 'larger significand'
466 | information.
467 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
468 *----------------------------------------------------------------------------*/
469 static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
470 bool infzero, float_status *status)
471 {
472 #if defined(TARGET_ARM)
473 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
474 * the default NaN
475 */
476 if (infzero && is_qnan(c_cls)) {
477 float_raise(float_flag_invalid, status);
478 return 3;
479 }
480
481 /* This looks different from the ARM ARM pseudocode, because the ARM ARM
482 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
483 */
484 if (is_snan(c_cls)) {
485 return 2;
486 } else if (is_snan(a_cls)) {
487 return 0;
488 } else if (is_snan(b_cls)) {
489 return 1;
490 } else if (is_qnan(c_cls)) {
491 return 2;
492 } else if (is_qnan(a_cls)) {
493 return 0;
494 } else {
495 return 1;
496 }
497 #elif defined(TARGET_MIPS)
498 if (snan_bit_is_one(status)) {
499 /*
500 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
501 * case sets InvalidOp and returns the default NaN
502 */
503 if (infzero) {
504 float_raise(float_flag_invalid, status);
505 return 3;
506 }
507 /* Prefer sNaN over qNaN, in the a, b, c order. */
508 if (is_snan(a_cls)) {
509 return 0;
510 } else if (is_snan(b_cls)) {
511 return 1;
512 } else if (is_snan(c_cls)) {
513 return 2;
514 } else if (is_qnan(a_cls)) {
515 return 0;
516 } else if (is_qnan(b_cls)) {
517 return 1;
518 } else {
519 return 2;
520 }
521 } else {
522 /*
523 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
524 * case sets InvalidOp and returns the input value 'c'
525 */
526 if (infzero) {
527 float_raise(float_flag_invalid, status);
528 return 2;
529 }
530 /* Prefer sNaN over qNaN, in the c, a, b order. */
531 if (is_snan(c_cls)) {
532 return 2;
533 } else if (is_snan(a_cls)) {
534 return 0;
535 } else if (is_snan(b_cls)) {
536 return 1;
537 } else if (is_qnan(c_cls)) {
538 return 2;
539 } else if (is_qnan(a_cls)) {
540 return 0;
541 } else {
542 return 1;
543 }
544 }
545 #elif defined(TARGET_PPC)
546 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
547 * to return an input NaN if we have one (ie c) rather than generating
548 * a default NaN
549 */
550 if (infzero) {
551 float_raise(float_flag_invalid, status);
552 return 2;
553 }
554
555 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
556 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
557 */
558 if (is_nan(a_cls)) {
559 return 0;
560 } else if (is_nan(c_cls)) {
561 return 2;
562 } else {
563 return 1;
564 }
565 #else
566 /* A default implementation: prefer a to b to c.
567 * This is unlikely to actually match any real implementation.
568 */
569 if (is_nan(a_cls)) {
570 return 0;
571 } else if (is_nan(b_cls)) {
572 return 1;
573 } else {
574 return 2;
575 }
576 #endif
577 }
578
579 /*----------------------------------------------------------------------------
580 | Takes two single-precision floating-point values `a' and `b', one of which
581 | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
582 | signaling NaN, the invalid exception is raised.
583 *----------------------------------------------------------------------------*/
584
585 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
586 {
587 flag aIsLargerSignificand;
588 uint32_t av, bv;
589 FloatClass a_cls, b_cls;
590
591 /* This is not complete, but is good enough for pickNaN. */
592 a_cls = (!float32_is_any_nan(a)
593 ? float_class_normal
594 : float32_is_signaling_nan(a, status)
595 ? float_class_snan
596 : float_class_qnan);
597 b_cls = (!float32_is_any_nan(b)
598 ? float_class_normal
599 : float32_is_signaling_nan(b, status)
600 ? float_class_snan
601 : float_class_qnan);
602
603 av = float32_val(a);
604 bv = float32_val(b);
605
606 if (is_snan(a_cls) || is_snan(b_cls)) {
607 float_raise(float_flag_invalid, status);
608 }
609
610 if (status->default_nan_mode) {
611 return float32_default_nan(status);
612 }
613
614 if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
615 aIsLargerSignificand = 0;
616 } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
617 aIsLargerSignificand = 1;
618 } else {
619 aIsLargerSignificand = (av < bv) ? 1 : 0;
620 }
621
622 if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
623 if (is_snan(b_cls)) {
624 return float32_silence_nan(b, status);
625 }
626 return b;
627 } else {
628 if (is_snan(a_cls)) {
629 return float32_silence_nan(a, status);
630 }
631 return a;
632 }
633 }
634
635 /*----------------------------------------------------------------------------
636 | Returns 1 if the double-precision floating-point value `a' is a quiet
637 | NaN; otherwise returns 0.
638 *----------------------------------------------------------------------------*/
639
640 int float64_is_quiet_nan(float64 a_, float_status *status)
641 {
642 #ifdef NO_SIGNALING_NANS
643 return float64_is_any_nan(a_);
644 #else
645 uint64_t a = float64_val(a_);
646 if (snan_bit_is_one(status)) {
647 return (((a >> 51) & 0xFFF) == 0xFFE)
648 && (a & 0x0007FFFFFFFFFFFFULL);
649 } else {
650 return ((a << 1) >= 0xFFF0000000000000ULL);
651 }
652 #endif
653 }
654
655 /*----------------------------------------------------------------------------
656 | Returns 1 if the double-precision floating-point value `a' is a signaling
657 | NaN; otherwise returns 0.
658 *----------------------------------------------------------------------------*/
659
660 int float64_is_signaling_nan(float64 a_, float_status *status)
661 {
662 #ifdef NO_SIGNALING_NANS
663 return 0;
664 #else
665 uint64_t a = float64_val(a_);
666 if (snan_bit_is_one(status)) {
667 return ((a << 1) >= 0xFFF0000000000000ULL);
668 } else {
669 return (((a >> 51) & 0xFFF) == 0xFFE)
670 && (a & LIT64(0x0007FFFFFFFFFFFF));
671 }
672 #endif
673 }
674
675 /*----------------------------------------------------------------------------
676 | Returns the result of converting the double-precision floating-point NaN
677 | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
678 | exception is raised.
679 *----------------------------------------------------------------------------*/
680
681 static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
682 {
683 commonNaNT z;
684
685 if (float64_is_signaling_nan(a, status)) {
686 float_raise(float_flag_invalid, status);
687 }
688 z.sign = float64_val(a) >> 63;
689 z.low = 0;
690 z.high = float64_val(a) << 12;
691 return z;
692 }
693
694 /*----------------------------------------------------------------------------
695 | Returns the result of converting the canonical NaN `a' to the double-
696 | precision floating-point format.
697 *----------------------------------------------------------------------------*/
698
699 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
700 {
701 uint64_t mantissa = a.high >> 12;
702
703 if (status->default_nan_mode) {
704 return float64_default_nan(status);
705 }
706
707 if (mantissa) {
708 return make_float64(
709 (((uint64_t) a.sign) << 63)
710 | LIT64(0x7FF0000000000000)
711 | (a.high >> 12));
712 } else {
713 return float64_default_nan(status);
714 }
715 }
716
717 /*----------------------------------------------------------------------------
718 | Takes two double-precision floating-point values `a' and `b', one of which
719 | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
720 | signaling NaN, the invalid exception is raised.
721 *----------------------------------------------------------------------------*/
722
723 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
724 {
725 flag aIsLargerSignificand;
726 uint64_t av, bv;
727 FloatClass a_cls, b_cls;
728
729 /* This is not complete, but is good enough for pickNaN. */
730 a_cls = (!float64_is_any_nan(a)
731 ? float_class_normal
732 : float64_is_signaling_nan(a, status)
733 ? float_class_snan
734 : float_class_qnan);
735 b_cls = (!float64_is_any_nan(b)
736 ? float_class_normal
737 : float64_is_signaling_nan(b, status)
738 ? float_class_snan
739 : float_class_qnan);
740
741 av = float64_val(a);
742 bv = float64_val(b);
743
744 if (is_snan(a_cls) || is_snan(b_cls)) {
745 float_raise(float_flag_invalid, status);
746 }
747
748 if (status->default_nan_mode) {
749 return float64_default_nan(status);
750 }
751
752 if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
753 aIsLargerSignificand = 0;
754 } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
755 aIsLargerSignificand = 1;
756 } else {
757 aIsLargerSignificand = (av < bv) ? 1 : 0;
758 }
759
760 if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
761 if (is_snan(b_cls)) {
762 return float64_silence_nan(b, status);
763 }
764 return b;
765 } else {
766 if (is_snan(a_cls)) {
767 return float64_silence_nan(a, status);
768 }
769 return a;
770 }
771 }
772
773 /*----------------------------------------------------------------------------
774 | Returns 1 if the extended double-precision floating-point value `a' is a
775 | quiet NaN; otherwise returns 0. This slightly differs from the same
776 | function for other types as floatx80 has an explicit bit.
777 *----------------------------------------------------------------------------*/
778
779 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
780 {
781 #ifdef NO_SIGNALING_NANS
782 return floatx80_is_any_nan(a);
783 #else
784 if (snan_bit_is_one(status)) {
785 uint64_t aLow;
786
787 aLow = a.low & ~0x4000000000000000ULL;
788 return ((a.high & 0x7FFF) == 0x7FFF)
789 && (aLow << 1)
790 && (a.low == aLow);
791 } else {
792 return ((a.high & 0x7FFF) == 0x7FFF)
793 && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
794 }
795 #endif
796 }
797
798 /*----------------------------------------------------------------------------
799 | Returns 1 if the extended double-precision floating-point value `a' is a
800 | signaling NaN; otherwise returns 0. This slightly differs from the same
801 | function for other types as floatx80 has an explicit bit.
802 *----------------------------------------------------------------------------*/
803
804 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
805 {
806 #ifdef NO_SIGNALING_NANS
807 return 0;
808 #else
809 if (snan_bit_is_one(status)) {
810 return ((a.high & 0x7FFF) == 0x7FFF)
811 && ((a.low << 1) >= 0x8000000000000000ULL);
812 } else {
813 uint64_t aLow;
814
815 aLow = a.low & ~LIT64(0x4000000000000000);
816 return ((a.high & 0x7FFF) == 0x7FFF)
817 && (uint64_t)(aLow << 1)
818 && (a.low == aLow);
819 }
820 #endif
821 }
822
823 /*----------------------------------------------------------------------------
824 | Returns a quiet NaN from a signalling NaN for the extended double-precision
825 | floating point value `a'.
826 *----------------------------------------------------------------------------*/
827
828 floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
829 {
830 /* None of the targets that have snan_bit_is_one use floatx80. */
831 assert(!snan_bit_is_one(status));
832 a.low |= LIT64(0xC000000000000000);
833 return a;
834 }
835
836 /*----------------------------------------------------------------------------
837 | Returns the result of converting the extended double-precision floating-
838 | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
839 | invalid exception is raised.
840 *----------------------------------------------------------------------------*/
841
842 static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
843 {
844 floatx80 dflt;
845 commonNaNT z;
846
847 if (floatx80_is_signaling_nan(a, status)) {
848 float_raise(float_flag_invalid, status);
849 }
850 if (a.low >> 63) {
851 z.sign = a.high >> 15;
852 z.low = 0;
853 z.high = a.low << 1;
854 } else {
855 dflt = floatx80_default_nan(status);
856 z.sign = dflt.high >> 15;
857 z.low = 0;
858 z.high = dflt.low << 1;
859 }
860 return z;
861 }
862
863 /*----------------------------------------------------------------------------
864 | Returns the result of converting the canonical NaN `a' to the extended
865 | double-precision floating-point format.
866 *----------------------------------------------------------------------------*/
867
868 static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
869 {
870 floatx80 z;
871
872 if (status->default_nan_mode) {
873 return floatx80_default_nan(status);
874 }
875
876 if (a.high >> 1) {
877 z.low = LIT64(0x8000000000000000) | a.high >> 1;
878 z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
879 } else {
880 z = floatx80_default_nan(status);
881 }
882 return z;
883 }
884
885 /*----------------------------------------------------------------------------
886 | Takes two extended double-precision floating-point values `a' and `b', one
887 | of which is a NaN, and returns the appropriate NaN result. If either `a' or
888 | `b' is a signaling NaN, the invalid exception is raised.
889 *----------------------------------------------------------------------------*/
890
891 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
892 {
893 flag aIsLargerSignificand;
894 FloatClass a_cls, b_cls;
895
896 /* This is not complete, but is good enough for pickNaN. */
897 a_cls = (!floatx80_is_any_nan(a)
898 ? float_class_normal
899 : floatx80_is_signaling_nan(a, status)
900 ? float_class_snan
901 : float_class_qnan);
902 b_cls = (!floatx80_is_any_nan(b)
903 ? float_class_normal
904 : floatx80_is_signaling_nan(b, status)
905 ? float_class_snan
906 : float_class_qnan);
907
908 if (is_snan(a_cls) || is_snan(b_cls)) {
909 float_raise(float_flag_invalid, status);
910 }
911
912 if (status->default_nan_mode) {
913 return floatx80_default_nan(status);
914 }
915
916 if (a.low < b.low) {
917 aIsLargerSignificand = 0;
918 } else if (b.low < a.low) {
919 aIsLargerSignificand = 1;
920 } else {
921 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
922 }
923
924 if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
925 if (is_snan(b_cls)) {
926 return floatx80_silence_nan(b, status);
927 }
928 return b;
929 } else {
930 if (is_snan(a_cls)) {
931 return floatx80_silence_nan(a, status);
932 }
933 return a;
934 }
935 }
936
937 /*----------------------------------------------------------------------------
938 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
939 | NaN; otherwise returns 0.
940 *----------------------------------------------------------------------------*/
941
942 int float128_is_quiet_nan(float128 a, float_status *status)
943 {
944 #ifdef NO_SIGNALING_NANS
945 return float128_is_any_nan(a);
946 #else
947 if (snan_bit_is_one(status)) {
948 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
949 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
950 } else {
951 return ((a.high << 1) >= 0xFFFF000000000000ULL)
952 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
953 }
954 #endif
955 }
956
957 /*----------------------------------------------------------------------------
958 | Returns 1 if the quadruple-precision floating-point value `a' is a
959 | signaling NaN; otherwise returns 0.
960 *----------------------------------------------------------------------------*/
961
962 int float128_is_signaling_nan(float128 a, float_status *status)
963 {
964 #ifdef NO_SIGNALING_NANS
965 return 0;
966 #else
967 if (snan_bit_is_one(status)) {
968 return ((a.high << 1) >= 0xFFFF000000000000ULL)
969 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
970 } else {
971 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
972 && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF)));
973 }
974 #endif
975 }
976
977 /*----------------------------------------------------------------------------
978 | Returns a quiet NaN from a signalling NaN for the quadruple-precision
979 | floating point value `a'.
980 *----------------------------------------------------------------------------*/
981
982 float128 float128_silence_nan(float128 a, float_status *status)
983 {
984 #ifdef NO_SIGNALING_NANS
985 g_assert_not_reached();
986 #else
987 if (snan_bit_is_one(status)) {
988 return float128_default_nan(status);
989 } else {
990 a.high |= LIT64(0x0000800000000000);
991 return a;
992 }
993 #endif
994 }
995
996 /*----------------------------------------------------------------------------
997 | Returns the result of converting the quadruple-precision floating-point NaN
998 | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
999 | exception is raised.
1000 *----------------------------------------------------------------------------*/
1001
1002 static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1003 {
1004 commonNaNT z;
1005
1006 if (float128_is_signaling_nan(a, status)) {
1007 float_raise(float_flag_invalid, status);
1008 }
1009 z.sign = a.high >> 63;
1010 shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1011 return z;
1012 }
1013
1014 /*----------------------------------------------------------------------------
1015 | Returns the result of converting the canonical NaN `a' to the quadruple-
1016 | precision floating-point format.
1017 *----------------------------------------------------------------------------*/
1018
1019 static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1020 {
1021 float128 z;
1022
1023 if (status->default_nan_mode) {
1024 return float128_default_nan(status);
1025 }
1026
1027 shift128Right(a.high, a.low, 16, &z.high, &z.low);
1028 z.high |= (((uint64_t)a.sign) << 63) | LIT64(0x7FFF000000000000);
1029 return z;
1030 }
1031
1032 /*----------------------------------------------------------------------------
1033 | Takes two quadruple-precision floating-point values `a' and `b', one of
1034 | which is a NaN, and returns the appropriate NaN result. If either `a' or
1035 | `b' is a signaling NaN, the invalid exception is raised.
1036 *----------------------------------------------------------------------------*/
1037
1038 static float128 propagateFloat128NaN(float128 a, float128 b,
1039 float_status *status)
1040 {
1041 flag aIsLargerSignificand;
1042 FloatClass a_cls, b_cls;
1043
1044 /* This is not complete, but is good enough for pickNaN. */
1045 a_cls = (!float128_is_any_nan(a)
1046 ? float_class_normal
1047 : float128_is_signaling_nan(a, status)
1048 ? float_class_snan
1049 : float_class_qnan);
1050 b_cls = (!float128_is_any_nan(b)
1051 ? float_class_normal
1052 : float128_is_signaling_nan(b, status)
1053 ? float_class_snan
1054 : float_class_qnan);
1055
1056 if (is_snan(a_cls) || is_snan(b_cls)) {
1057 float_raise(float_flag_invalid, status);
1058 }
1059
1060 if (status->default_nan_mode) {
1061 return float128_default_nan(status);
1062 }
1063
1064 if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1065 aIsLargerSignificand = 0;
1066 } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1067 aIsLargerSignificand = 1;
1068 } else {
1069 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1070 }
1071
1072 if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
1073 if (is_snan(b_cls)) {
1074 return float128_silence_nan(b, status);
1075 }
1076 return b;
1077 } else {
1078 if (is_snan(a_cls)) {
1079 return float128_silence_nan(a, status);
1080 }
1081 return a;
1082 }
1083 }