meson: convert qapi-specific to meson
[qemu.git] / hw / acpi / nvdimm.c
1 /*
2 * NVDIMM ACPI Implementation
3 *
4 * Copyright(C) 2015 Intel Corporation.
5 *
6 * Author:
7 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
8 *
9 * NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
10 * and the DSM specification can be found at:
11 * http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
12 *
13 * Currently, it only supports PMEM Virtualization.
14 *
15 * This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU Lesser General Public
17 * License as published by the Free Software Foundation; either
18 * version 2 of the License, or (at your option) any later version.
19 *
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * Lesser General Public License for more details.
24 *
25 * You should have received a copy of the GNU Lesser General Public
26 * License along with this library; if not, see <http://www.gnu.org/licenses/>
27 */
28
29 #include "qemu/osdep.h"
30 #include "qemu/uuid.h"
31 #include "qapi/error.h"
32 #include "hw/acpi/acpi.h"
33 #include "hw/acpi/aml-build.h"
34 #include "hw/acpi/bios-linker-loader.h"
35 #include "hw/nvram/fw_cfg.h"
36 #include "hw/mem/nvdimm.h"
37 #include "qemu/nvdimm-utils.h"
38
39 /*
40 * define Byte Addressable Persistent Memory (PM) Region according to
41 * ACPI 6.0: 5.2.25.1 System Physical Address Range Structure.
42 */
43 static const uint8_t nvdimm_nfit_spa_uuid[] =
44 UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
45 0x18, 0xb7, 0x8c, 0xdb);
46
47 /*
48 * NVDIMM Firmware Interface Table
49 * @signature: "NFIT"
50 *
51 * It provides information that allows OSPM to enumerate NVDIMM present in
52 * the platform and associate system physical address ranges created by the
53 * NVDIMMs.
54 *
55 * It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
56 */
57 struct NvdimmNfitHeader {
58 ACPI_TABLE_HEADER_DEF
59 uint32_t reserved;
60 } QEMU_PACKED;
61 typedef struct NvdimmNfitHeader NvdimmNfitHeader;
62
63 /*
64 * define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
65 * Interface Table (NFIT).
66 */
67
68 /*
69 * System Physical Address Range Structure
70 *
71 * It describes the system physical address ranges occupied by NVDIMMs and
72 * the types of the regions.
73 */
74 struct NvdimmNfitSpa {
75 uint16_t type;
76 uint16_t length;
77 uint16_t spa_index;
78 uint16_t flags;
79 uint32_t reserved;
80 uint32_t proximity_domain;
81 uint8_t type_guid[16];
82 uint64_t spa_base;
83 uint64_t spa_length;
84 uint64_t mem_attr;
85 } QEMU_PACKED;
86 typedef struct NvdimmNfitSpa NvdimmNfitSpa;
87
88 /*
89 * Memory Device to System Physical Address Range Mapping Structure
90 *
91 * It enables identifying each NVDIMM region and the corresponding SPA
92 * describing the memory interleave
93 */
94 struct NvdimmNfitMemDev {
95 uint16_t type;
96 uint16_t length;
97 uint32_t nfit_handle;
98 uint16_t phys_id;
99 uint16_t region_id;
100 uint16_t spa_index;
101 uint16_t dcr_index;
102 uint64_t region_len;
103 uint64_t region_offset;
104 uint64_t region_dpa;
105 uint16_t interleave_index;
106 uint16_t interleave_ways;
107 uint16_t flags;
108 uint16_t reserved;
109 } QEMU_PACKED;
110 typedef struct NvdimmNfitMemDev NvdimmNfitMemDev;
111
112 #define ACPI_NFIT_MEM_NOT_ARMED (1 << 3)
113
114 /*
115 * NVDIMM Control Region Structure
116 *
117 * It describes the NVDIMM and if applicable, Block Control Window.
118 */
119 struct NvdimmNfitControlRegion {
120 uint16_t type;
121 uint16_t length;
122 uint16_t dcr_index;
123 uint16_t vendor_id;
124 uint16_t device_id;
125 uint16_t revision_id;
126 uint16_t sub_vendor_id;
127 uint16_t sub_device_id;
128 uint16_t sub_revision_id;
129 uint8_t reserved[6];
130 uint32_t serial_number;
131 uint16_t fic;
132 uint16_t num_bcw;
133 uint64_t bcw_size;
134 uint64_t cmd_offset;
135 uint64_t cmd_size;
136 uint64_t status_offset;
137 uint64_t status_size;
138 uint16_t flags;
139 uint8_t reserved2[6];
140 } QEMU_PACKED;
141 typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion;
142
143 /*
144 * NVDIMM Platform Capabilities Structure
145 *
146 * Defined in section 5.2.25.9 of ACPI 6.2 Errata A, September 2017
147 */
148 struct NvdimmNfitPlatformCaps {
149 uint16_t type;
150 uint16_t length;
151 uint8_t highest_cap;
152 uint8_t reserved[3];
153 uint32_t capabilities;
154 uint8_t reserved2[4];
155 } QEMU_PACKED;
156 typedef struct NvdimmNfitPlatformCaps NvdimmNfitPlatformCaps;
157
158 /*
159 * Module serial number is a unique number for each device. We use the
160 * slot id of NVDIMM device to generate this number so that each device
161 * associates with a different number.
162 *
163 * 0x123456 is a magic number we arbitrarily chose.
164 */
165 static uint32_t nvdimm_slot_to_sn(int slot)
166 {
167 return 0x123456 + slot;
168 }
169
170 /*
171 * handle is used to uniquely associate nfit_memdev structure with NVDIMM
172 * ACPI device - nfit_memdev.nfit_handle matches with the value returned
173 * by ACPI device _ADR method.
174 *
175 * We generate the handle with the slot id of NVDIMM device and reserve
176 * 0 for NVDIMM root device.
177 */
178 static uint32_t nvdimm_slot_to_handle(int slot)
179 {
180 return slot + 1;
181 }
182
183 /*
184 * index uniquely identifies the structure, 0 is reserved which indicates
185 * that the structure is not valid or the associated structure is not
186 * present.
187 *
188 * Each NVDIMM device needs two indexes, one for nfit_spa and another for
189 * nfit_dc which are generated by the slot id of NVDIMM device.
190 */
191 static uint16_t nvdimm_slot_to_spa_index(int slot)
192 {
193 return (slot + 1) << 1;
194 }
195
196 /* See the comments of nvdimm_slot_to_spa_index(). */
197 static uint32_t nvdimm_slot_to_dcr_index(int slot)
198 {
199 return nvdimm_slot_to_spa_index(slot) + 1;
200 }
201
202 static NVDIMMDevice *nvdimm_get_device_by_handle(uint32_t handle)
203 {
204 NVDIMMDevice *nvdimm = NULL;
205 GSList *list, *device_list = nvdimm_get_device_list();
206
207 for (list = device_list; list; list = list->next) {
208 NVDIMMDevice *nvd = list->data;
209 int slot = object_property_get_int(OBJECT(nvd), PC_DIMM_SLOT_PROP,
210 NULL);
211
212 if (nvdimm_slot_to_handle(slot) == handle) {
213 nvdimm = nvd;
214 break;
215 }
216 }
217
218 g_slist_free(device_list);
219 return nvdimm;
220 }
221
222 /* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */
223 static void
224 nvdimm_build_structure_spa(GArray *structures, DeviceState *dev)
225 {
226 NvdimmNfitSpa *nfit_spa;
227 uint64_t addr = object_property_get_uint(OBJECT(dev), PC_DIMM_ADDR_PROP,
228 NULL);
229 uint64_t size = object_property_get_uint(OBJECT(dev), PC_DIMM_SIZE_PROP,
230 NULL);
231 uint32_t node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP,
232 NULL);
233 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
234 NULL);
235
236 nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa));
237
238 nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range
239 Structure */);
240 nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa));
241 nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
242
243 /*
244 * Control region is strict as all the device info, such as SN, index,
245 * is associated with slot id.
246 */
247 nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for
248 management during hot add/online
249 operation */ |
250 2 /* Data in Proximity Domain field is
251 valid*/);
252
253 /* NUMA node. */
254 nfit_spa->proximity_domain = cpu_to_le32(node);
255 /* the region reported as PMEM. */
256 memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid,
257 sizeof(nvdimm_nfit_spa_uuid));
258
259 nfit_spa->spa_base = cpu_to_le64(addr);
260 nfit_spa->spa_length = cpu_to_le64(size);
261
262 /* It is the PMEM and can be cached as writeback. */
263 nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ |
264 0x8000ULL /* EFI_MEMORY_NV */);
265 }
266
267 /*
268 * ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping
269 * Structure
270 */
271 static void
272 nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev)
273 {
274 NvdimmNfitMemDev *nfit_memdev;
275 NVDIMMDevice *nvdimm = NVDIMM(OBJECT(dev));
276 uint64_t size = object_property_get_uint(OBJECT(dev), PC_DIMM_SIZE_PROP,
277 NULL);
278 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
279 NULL);
280 uint32_t handle = nvdimm_slot_to_handle(slot);
281
282 nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev));
283
284 nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address
285 Range Map Structure*/);
286 nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev));
287 nfit_memdev->nfit_handle = cpu_to_le32(handle);
288
289 /*
290 * associate memory device with System Physical Address Range
291 * Structure.
292 */
293 nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
294 /* associate memory device with Control Region Structure. */
295 nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
296
297 /* The memory region on the device. */
298 nfit_memdev->region_len = cpu_to_le64(size);
299 /* The device address starts from 0. */
300 nfit_memdev->region_dpa = cpu_to_le64(0);
301
302 /* Only one interleave for PMEM. */
303 nfit_memdev->interleave_ways = cpu_to_le16(1);
304
305 if (nvdimm->unarmed) {
306 nfit_memdev->flags |= cpu_to_le16(ACPI_NFIT_MEM_NOT_ARMED);
307 }
308 }
309
310 /*
311 * ACPI 6.0: 5.2.25.5 NVDIMM Control Region Structure.
312 */
313 static void nvdimm_build_structure_dcr(GArray *structures, DeviceState *dev)
314 {
315 NvdimmNfitControlRegion *nfit_dcr;
316 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
317 NULL);
318 uint32_t sn = nvdimm_slot_to_sn(slot);
319
320 nfit_dcr = acpi_data_push(structures, sizeof(*nfit_dcr));
321
322 nfit_dcr->type = cpu_to_le16(4 /* NVDIMM Control Region Structure */);
323 nfit_dcr->length = cpu_to_le16(sizeof(*nfit_dcr));
324 nfit_dcr->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
325
326 /* vendor: Intel. */
327 nfit_dcr->vendor_id = cpu_to_le16(0x8086);
328 nfit_dcr->device_id = cpu_to_le16(1);
329
330 /* The _DSM method is following Intel's DSM specification. */
331 nfit_dcr->revision_id = cpu_to_le16(1 /* Current Revision supported
332 in ACPI 6.0 is 1. */);
333 nfit_dcr->serial_number = cpu_to_le32(sn);
334 nfit_dcr->fic = cpu_to_le16(0x301 /* Format Interface Code:
335 Byte addressable, no energy backed.
336 See ACPI 6.2, sect 5.2.25.6 and
337 JEDEC Annex L Release 3. */);
338 }
339
340 /*
341 * ACPI 6.2 Errata A: 5.2.25.9 NVDIMM Platform Capabilities Structure
342 */
343 static void
344 nvdimm_build_structure_caps(GArray *structures, uint32_t capabilities)
345 {
346 NvdimmNfitPlatformCaps *nfit_caps;
347
348 nfit_caps = acpi_data_push(structures, sizeof(*nfit_caps));
349
350 nfit_caps->type = cpu_to_le16(7 /* NVDIMM Platform Capabilities */);
351 nfit_caps->length = cpu_to_le16(sizeof(*nfit_caps));
352 nfit_caps->highest_cap = 31 - clz32(capabilities);
353 nfit_caps->capabilities = cpu_to_le32(capabilities);
354 }
355
356 static GArray *nvdimm_build_device_structure(NVDIMMState *state)
357 {
358 GSList *device_list = nvdimm_get_device_list();
359 GArray *structures = g_array_new(false, true /* clear */, 1);
360
361 for (; device_list; device_list = device_list->next) {
362 DeviceState *dev = device_list->data;
363
364 /* build System Physical Address Range Structure. */
365 nvdimm_build_structure_spa(structures, dev);
366
367 /*
368 * build Memory Device to System Physical Address Range Mapping
369 * Structure.
370 */
371 nvdimm_build_structure_memdev(structures, dev);
372
373 /* build NVDIMM Control Region Structure. */
374 nvdimm_build_structure_dcr(structures, dev);
375 }
376 g_slist_free(device_list);
377
378 if (state->persistence) {
379 nvdimm_build_structure_caps(structures, state->persistence);
380 }
381
382 return structures;
383 }
384
385 static void nvdimm_init_fit_buffer(NvdimmFitBuffer *fit_buf)
386 {
387 fit_buf->fit = g_array_new(false, true /* clear */, 1);
388 }
389
390 static void nvdimm_build_fit_buffer(NVDIMMState *state)
391 {
392 NvdimmFitBuffer *fit_buf = &state->fit_buf;
393
394 g_array_free(fit_buf->fit, true);
395 fit_buf->fit = nvdimm_build_device_structure(state);
396 fit_buf->dirty = true;
397 }
398
399 void nvdimm_plug(NVDIMMState *state)
400 {
401 nvdimm_build_fit_buffer(state);
402 }
403
404 static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets,
405 GArray *table_data, BIOSLinker *linker)
406 {
407 NvdimmFitBuffer *fit_buf = &state->fit_buf;
408 unsigned int header;
409
410 acpi_add_table(table_offsets, table_data);
411
412 /* NFIT header. */
413 header = table_data->len;
414 acpi_data_push(table_data, sizeof(NvdimmNfitHeader));
415 /* NVDIMM device structures. */
416 g_array_append_vals(table_data, fit_buf->fit->data, fit_buf->fit->len);
417
418 build_header(linker, table_data,
419 (void *)(table_data->data + header), "NFIT",
420 sizeof(NvdimmNfitHeader) + fit_buf->fit->len, 1, NULL, NULL);
421 }
422
423 #define NVDIMM_DSM_MEMORY_SIZE 4096
424
425 struct NvdimmDsmIn {
426 uint32_t handle;
427 uint32_t revision;
428 uint32_t function;
429 /* the remaining size in the page is used by arg3. */
430 union {
431 uint8_t arg3[4084];
432 };
433 } QEMU_PACKED;
434 typedef struct NvdimmDsmIn NvdimmDsmIn;
435 QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmIn) != NVDIMM_DSM_MEMORY_SIZE);
436
437 struct NvdimmDsmOut {
438 /* the size of buffer filled by QEMU. */
439 uint32_t len;
440 uint8_t data[4092];
441 } QEMU_PACKED;
442 typedef struct NvdimmDsmOut NvdimmDsmOut;
443 QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmOut) != NVDIMM_DSM_MEMORY_SIZE);
444
445 struct NvdimmDsmFunc0Out {
446 /* the size of buffer filled by QEMU. */
447 uint32_t len;
448 uint32_t supported_func;
449 } QEMU_PACKED;
450 typedef struct NvdimmDsmFunc0Out NvdimmDsmFunc0Out;
451
452 struct NvdimmDsmFuncNoPayloadOut {
453 /* the size of buffer filled by QEMU. */
454 uint32_t len;
455 uint32_t func_ret_status;
456 } QEMU_PACKED;
457 typedef struct NvdimmDsmFuncNoPayloadOut NvdimmDsmFuncNoPayloadOut;
458
459 struct NvdimmFuncGetLabelSizeOut {
460 /* the size of buffer filled by QEMU. */
461 uint32_t len;
462 uint32_t func_ret_status; /* return status code. */
463 uint32_t label_size; /* the size of label data area. */
464 /*
465 * Maximum size of the namespace label data length supported by
466 * the platform in Get/Set Namespace Label Data functions.
467 */
468 uint32_t max_xfer;
469 } QEMU_PACKED;
470 typedef struct NvdimmFuncGetLabelSizeOut NvdimmFuncGetLabelSizeOut;
471 QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelSizeOut) > NVDIMM_DSM_MEMORY_SIZE);
472
473 struct NvdimmFuncGetLabelDataIn {
474 uint32_t offset; /* the offset in the namespace label data area. */
475 uint32_t length; /* the size of data is to be read via the function. */
476 } QEMU_PACKED;
477 typedef struct NvdimmFuncGetLabelDataIn NvdimmFuncGetLabelDataIn;
478 QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataIn) +
479 offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
480
481 struct NvdimmFuncGetLabelDataOut {
482 /* the size of buffer filled by QEMU. */
483 uint32_t len;
484 uint32_t func_ret_status; /* return status code. */
485 uint8_t out_buf[]; /* the data got via Get Namesapce Label function. */
486 } QEMU_PACKED;
487 typedef struct NvdimmFuncGetLabelDataOut NvdimmFuncGetLabelDataOut;
488 QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataOut) > NVDIMM_DSM_MEMORY_SIZE);
489
490 struct NvdimmFuncSetLabelDataIn {
491 uint32_t offset; /* the offset in the namespace label data area. */
492 uint32_t length; /* the size of data is to be written via the function. */
493 uint8_t in_buf[]; /* the data written to label data area. */
494 } QEMU_PACKED;
495 typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn;
496 QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncSetLabelDataIn) +
497 offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
498
499 struct NvdimmFuncReadFITIn {
500 uint32_t offset; /* the offset into FIT buffer. */
501 } QEMU_PACKED;
502 typedef struct NvdimmFuncReadFITIn NvdimmFuncReadFITIn;
503 QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITIn) +
504 offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
505
506 struct NvdimmFuncReadFITOut {
507 /* the size of buffer filled by QEMU. */
508 uint32_t len;
509 uint32_t func_ret_status; /* return status code. */
510 uint8_t fit[]; /* the FIT data. */
511 } QEMU_PACKED;
512 typedef struct NvdimmFuncReadFITOut NvdimmFuncReadFITOut;
513 QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITOut) > NVDIMM_DSM_MEMORY_SIZE);
514
515 static void
516 nvdimm_dsm_function0(uint32_t supported_func, hwaddr dsm_mem_addr)
517 {
518 NvdimmDsmFunc0Out func0 = {
519 .len = cpu_to_le32(sizeof(func0)),
520 .supported_func = cpu_to_le32(supported_func),
521 };
522 cpu_physical_memory_write(dsm_mem_addr, &func0, sizeof(func0));
523 }
524
525 static void
526 nvdimm_dsm_no_payload(uint32_t func_ret_status, hwaddr dsm_mem_addr)
527 {
528 NvdimmDsmFuncNoPayloadOut out = {
529 .len = cpu_to_le32(sizeof(out)),
530 .func_ret_status = cpu_to_le32(func_ret_status),
531 };
532 cpu_physical_memory_write(dsm_mem_addr, &out, sizeof(out));
533 }
534
535 #define NVDIMM_DSM_RET_STATUS_SUCCESS 0 /* Success */
536 #define NVDIMM_DSM_RET_STATUS_UNSUPPORT 1 /* Not Supported */
537 #define NVDIMM_DSM_RET_STATUS_NOMEMDEV 2 /* Non-Existing Memory Device */
538 #define NVDIMM_DSM_RET_STATUS_INVALID 3 /* Invalid Input Parameters */
539 #define NVDIMM_DSM_RET_STATUS_FIT_CHANGED 0x100 /* FIT Changed */
540
541 #define NVDIMM_QEMU_RSVD_HANDLE_ROOT 0x10000
542
543 /* Read FIT data, defined in docs/specs/acpi_nvdimm.txt. */
544 static void nvdimm_dsm_func_read_fit(NVDIMMState *state, NvdimmDsmIn *in,
545 hwaddr dsm_mem_addr)
546 {
547 NvdimmFitBuffer *fit_buf = &state->fit_buf;
548 NvdimmFuncReadFITIn *read_fit;
549 NvdimmFuncReadFITOut *read_fit_out;
550 GArray *fit;
551 uint32_t read_len = 0, func_ret_status;
552 int size;
553
554 read_fit = (NvdimmFuncReadFITIn *)in->arg3;
555 read_fit->offset = le32_to_cpu(read_fit->offset);
556
557 fit = fit_buf->fit;
558
559 nvdimm_debug("Read FIT: offset %#x FIT size %#x Dirty %s.\n",
560 read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : "No");
561
562 if (read_fit->offset > fit->len) {
563 func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID;
564 goto exit;
565 }
566
567 /* It is the first time to read FIT. */
568 if (!read_fit->offset) {
569 fit_buf->dirty = false;
570 } else if (fit_buf->dirty) { /* FIT has been changed during RFIT. */
571 func_ret_status = NVDIMM_DSM_RET_STATUS_FIT_CHANGED;
572 goto exit;
573 }
574
575 func_ret_status = NVDIMM_DSM_RET_STATUS_SUCCESS;
576 read_len = MIN(fit->len - read_fit->offset,
577 NVDIMM_DSM_MEMORY_SIZE - sizeof(NvdimmFuncReadFITOut));
578
579 exit:
580 size = sizeof(NvdimmFuncReadFITOut) + read_len;
581 read_fit_out = g_malloc(size);
582
583 read_fit_out->len = cpu_to_le32(size);
584 read_fit_out->func_ret_status = cpu_to_le32(func_ret_status);
585 memcpy(read_fit_out->fit, fit->data + read_fit->offset, read_len);
586
587 cpu_physical_memory_write(dsm_mem_addr, read_fit_out, size);
588
589 g_free(read_fit_out);
590 }
591
592 static void
593 nvdimm_dsm_handle_reserved_root_method(NVDIMMState *state,
594 NvdimmDsmIn *in, hwaddr dsm_mem_addr)
595 {
596 switch (in->function) {
597 case 0x0:
598 nvdimm_dsm_function0(0x1 | 1 << 1 /* Read FIT */, dsm_mem_addr);
599 return;
600 case 0x1 /* Read FIT */:
601 nvdimm_dsm_func_read_fit(state, in, dsm_mem_addr);
602 return;
603 }
604
605 nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
606 }
607
608 static void nvdimm_dsm_root(NvdimmDsmIn *in, hwaddr dsm_mem_addr)
609 {
610 /*
611 * function 0 is called to inquire which functions are supported by
612 * OSPM
613 */
614 if (!in->function) {
615 nvdimm_dsm_function0(0 /* No function supported other than
616 function 0 */, dsm_mem_addr);
617 return;
618 }
619
620 /* No function except function 0 is supported yet. */
621 nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
622 }
623
624 /*
625 * the max transfer size is the max size transferred by both a
626 * 'Get Namespace Label Data' function and a 'Set Namespace Label Data'
627 * function.
628 */
629 static uint32_t nvdimm_get_max_xfer_label_size(void)
630 {
631 uint32_t max_get_size, max_set_size, dsm_memory_size;
632
633 dsm_memory_size = NVDIMM_DSM_MEMORY_SIZE;
634
635 /*
636 * the max data ACPI can read one time which is transferred by
637 * the response of 'Get Namespace Label Data' function.
638 */
639 max_get_size = dsm_memory_size - sizeof(NvdimmFuncGetLabelDataOut);
640
641 /*
642 * the max data ACPI can write one time which is transferred by
643 * 'Set Namespace Label Data' function.
644 */
645 max_set_size = dsm_memory_size - offsetof(NvdimmDsmIn, arg3) -
646 sizeof(NvdimmFuncSetLabelDataIn);
647
648 return MIN(max_get_size, max_set_size);
649 }
650
651 /*
652 * DSM Spec Rev1 4.4 Get Namespace Label Size (Function Index 4).
653 *
654 * It gets the size of Namespace Label data area and the max data size
655 * that Get/Set Namespace Label Data functions can transfer.
656 */
657 static void nvdimm_dsm_label_size(NVDIMMDevice *nvdimm, hwaddr dsm_mem_addr)
658 {
659 NvdimmFuncGetLabelSizeOut label_size_out = {
660 .len = cpu_to_le32(sizeof(label_size_out)),
661 };
662 uint32_t label_size, mxfer;
663
664 label_size = nvdimm->label_size;
665 mxfer = nvdimm_get_max_xfer_label_size();
666
667 nvdimm_debug("label_size %#x, max_xfer %#x.\n", label_size, mxfer);
668
669 label_size_out.func_ret_status = cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS);
670 label_size_out.label_size = cpu_to_le32(label_size);
671 label_size_out.max_xfer = cpu_to_le32(mxfer);
672
673 cpu_physical_memory_write(dsm_mem_addr, &label_size_out,
674 sizeof(label_size_out));
675 }
676
677 static uint32_t nvdimm_rw_label_data_check(NVDIMMDevice *nvdimm,
678 uint32_t offset, uint32_t length)
679 {
680 uint32_t ret = NVDIMM_DSM_RET_STATUS_INVALID;
681
682 if (offset + length < offset) {
683 nvdimm_debug("offset %#x + length %#x is overflow.\n", offset,
684 length);
685 return ret;
686 }
687
688 if (nvdimm->label_size < offset + length) {
689 nvdimm_debug("position %#x is beyond label data (len = %" PRIx64 ").\n",
690 offset + length, nvdimm->label_size);
691 return ret;
692 }
693
694 if (length > nvdimm_get_max_xfer_label_size()) {
695 nvdimm_debug("length (%#x) is larger than max_xfer (%#x).\n",
696 length, nvdimm_get_max_xfer_label_size());
697 return ret;
698 }
699
700 return NVDIMM_DSM_RET_STATUS_SUCCESS;
701 }
702
703 /*
704 * DSM Spec Rev1 4.5 Get Namespace Label Data (Function Index 5).
705 */
706 static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in,
707 hwaddr dsm_mem_addr)
708 {
709 NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm);
710 NvdimmFuncGetLabelDataIn *get_label_data;
711 NvdimmFuncGetLabelDataOut *get_label_data_out;
712 uint32_t status;
713 int size;
714
715 get_label_data = (NvdimmFuncGetLabelDataIn *)in->arg3;
716 get_label_data->offset = le32_to_cpu(get_label_data->offset);
717 get_label_data->length = le32_to_cpu(get_label_data->length);
718
719 nvdimm_debug("Read Label Data: offset %#x length %#x.\n",
720 get_label_data->offset, get_label_data->length);
721
722 status = nvdimm_rw_label_data_check(nvdimm, get_label_data->offset,
723 get_label_data->length);
724 if (status != NVDIMM_DSM_RET_STATUS_SUCCESS) {
725 nvdimm_dsm_no_payload(status, dsm_mem_addr);
726 return;
727 }
728
729 size = sizeof(*get_label_data_out) + get_label_data->length;
730 assert(size <= NVDIMM_DSM_MEMORY_SIZE);
731 get_label_data_out = g_malloc(size);
732
733 get_label_data_out->len = cpu_to_le32(size);
734 get_label_data_out->func_ret_status =
735 cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS);
736 nvc->read_label_data(nvdimm, get_label_data_out->out_buf,
737 get_label_data->length, get_label_data->offset);
738
739 cpu_physical_memory_write(dsm_mem_addr, get_label_data_out, size);
740 g_free(get_label_data_out);
741 }
742
743 /*
744 * DSM Spec Rev1 4.6 Set Namespace Label Data (Function Index 6).
745 */
746 static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in,
747 hwaddr dsm_mem_addr)
748 {
749 NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm);
750 NvdimmFuncSetLabelDataIn *set_label_data;
751 uint32_t status;
752
753 set_label_data = (NvdimmFuncSetLabelDataIn *)in->arg3;
754
755 set_label_data->offset = le32_to_cpu(set_label_data->offset);
756 set_label_data->length = le32_to_cpu(set_label_data->length);
757
758 nvdimm_debug("Write Label Data: offset %#x length %#x.\n",
759 set_label_data->offset, set_label_data->length);
760
761 status = nvdimm_rw_label_data_check(nvdimm, set_label_data->offset,
762 set_label_data->length);
763 if (status != NVDIMM_DSM_RET_STATUS_SUCCESS) {
764 nvdimm_dsm_no_payload(status, dsm_mem_addr);
765 return;
766 }
767
768 assert(offsetof(NvdimmDsmIn, arg3) + sizeof(*set_label_data) +
769 set_label_data->length <= NVDIMM_DSM_MEMORY_SIZE);
770
771 nvc->write_label_data(nvdimm, set_label_data->in_buf,
772 set_label_data->length, set_label_data->offset);
773 nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_SUCCESS, dsm_mem_addr);
774 }
775
776 static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr)
777 {
778 NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(in->handle);
779
780 /* See the comments in nvdimm_dsm_root(). */
781 if (!in->function) {
782 uint32_t supported_func = 0;
783
784 if (nvdimm && nvdimm->label_size) {
785 supported_func |= 0x1 /* Bit 0 indicates whether there is
786 support for any functions other
787 than function 0. */ |
788 1 << 4 /* Get Namespace Label Size */ |
789 1 << 5 /* Get Namespace Label Data */ |
790 1 << 6 /* Set Namespace Label Data */;
791 }
792 nvdimm_dsm_function0(supported_func, dsm_mem_addr);
793 return;
794 }
795
796 if (!nvdimm) {
797 nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_NOMEMDEV,
798 dsm_mem_addr);
799 return;
800 }
801
802 /* Encode DSM function according to DSM Spec Rev1. */
803 switch (in->function) {
804 case 4 /* Get Namespace Label Size */:
805 if (nvdimm->label_size) {
806 nvdimm_dsm_label_size(nvdimm, dsm_mem_addr);
807 return;
808 }
809 break;
810 case 5 /* Get Namespace Label Data */:
811 if (nvdimm->label_size) {
812 nvdimm_dsm_get_label_data(nvdimm, in, dsm_mem_addr);
813 return;
814 }
815 break;
816 case 0x6 /* Set Namespace Label Data */:
817 if (nvdimm->label_size) {
818 nvdimm_dsm_set_label_data(nvdimm, in, dsm_mem_addr);
819 return;
820 }
821 break;
822 }
823
824 nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
825 }
826
827 static uint64_t
828 nvdimm_dsm_read(void *opaque, hwaddr addr, unsigned size)
829 {
830 nvdimm_debug("BUG: we never read _DSM IO Port.\n");
831 return 0;
832 }
833
834 static void
835 nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
836 {
837 NVDIMMState *state = opaque;
838 NvdimmDsmIn *in;
839 hwaddr dsm_mem_addr = val;
840
841 nvdimm_debug("dsm memory address %#" HWADDR_PRIx ".\n", dsm_mem_addr);
842
843 /*
844 * The DSM memory is mapped to guest address space so an evil guest
845 * can change its content while we are doing DSM emulation. Avoid
846 * this by copying DSM memory to QEMU local memory.
847 */
848 in = g_new(NvdimmDsmIn, 1);
849 cpu_physical_memory_read(dsm_mem_addr, in, sizeof(*in));
850
851 in->revision = le32_to_cpu(in->revision);
852 in->function = le32_to_cpu(in->function);
853 in->handle = le32_to_cpu(in->handle);
854
855 nvdimm_debug("Revision %#x Handler %#x Function %#x.\n", in->revision,
856 in->handle, in->function);
857
858 if (in->revision != 0x1 /* Currently we only support DSM Spec Rev1. */) {
859 nvdimm_debug("Revision %#x is not supported, expect %#x.\n",
860 in->revision, 0x1);
861 nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
862 goto exit;
863 }
864
865 if (in->handle == NVDIMM_QEMU_RSVD_HANDLE_ROOT) {
866 nvdimm_dsm_handle_reserved_root_method(state, in, dsm_mem_addr);
867 goto exit;
868 }
869
870 /* Handle 0 is reserved for NVDIMM Root Device. */
871 if (!in->handle) {
872 nvdimm_dsm_root(in, dsm_mem_addr);
873 goto exit;
874 }
875
876 nvdimm_dsm_device(in, dsm_mem_addr);
877
878 exit:
879 g_free(in);
880 }
881
882 static const MemoryRegionOps nvdimm_dsm_ops = {
883 .read = nvdimm_dsm_read,
884 .write = nvdimm_dsm_write,
885 .endianness = DEVICE_LITTLE_ENDIAN,
886 .valid = {
887 .min_access_size = 4,
888 .max_access_size = 4,
889 },
890 };
891
892 void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev)
893 {
894 if (dev->hotplugged) {
895 acpi_send_event(DEVICE(hotplug_dev), ACPI_NVDIMM_HOTPLUG_STATUS);
896 }
897 }
898
899 void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io,
900 struct AcpiGenericAddress dsm_io,
901 FWCfgState *fw_cfg, Object *owner)
902 {
903 state->dsm_io = dsm_io;
904 memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state,
905 "nvdimm-acpi-io", dsm_io.bit_width >> 3);
906 memory_region_add_subregion(io, dsm_io.address, &state->io_mr);
907
908 state->dsm_mem = g_array_new(false, true /* clear */, 1);
909 acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn));
910 fw_cfg_add_file(fw_cfg, NVDIMM_DSM_MEM_FILE, state->dsm_mem->data,
911 state->dsm_mem->len);
912
913 nvdimm_init_fit_buffer(&state->fit_buf);
914 }
915
916 #define NVDIMM_COMMON_DSM "NCAL"
917 #define NVDIMM_ACPI_MEM_ADDR "MEMA"
918
919 #define NVDIMM_DSM_MEMORY "NRAM"
920 #define NVDIMM_DSM_IOPORT "NPIO"
921
922 #define NVDIMM_DSM_NOTIFY "NTFI"
923 #define NVDIMM_DSM_HANDLE "HDLE"
924 #define NVDIMM_DSM_REVISION "REVS"
925 #define NVDIMM_DSM_FUNCTION "FUNC"
926 #define NVDIMM_DSM_ARG3 "FARG"
927
928 #define NVDIMM_DSM_OUT_BUF_SIZE "RLEN"
929 #define NVDIMM_DSM_OUT_BUF "ODAT"
930
931 #define NVDIMM_DSM_RFIT_STATUS "RSTA"
932
933 #define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62"
934
935 static void nvdimm_build_common_dsm(Aml *dev,
936 NVDIMMState *nvdimm_state)
937 {
938 Aml *method, *ifctx, *function, *handle, *uuid, *dsm_mem, *elsectx2;
939 Aml *elsectx, *unsupport, *unpatched, *expected_uuid, *uuid_invalid;
940 Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_size;
941 Aml *whilectx, *offset;
942 uint8_t byte_list[1];
943 AmlRegionSpace rs;
944
945 method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED);
946 uuid = aml_arg(0);
947 function = aml_arg(2);
948 handle = aml_arg(4);
949 dsm_mem = aml_local(6);
950 dsm_out_buf = aml_local(7);
951
952 aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem));
953
954 if (nvdimm_state->dsm_io.space_id == AML_AS_SYSTEM_IO) {
955 rs = AML_SYSTEM_IO;
956 } else {
957 rs = AML_SYSTEM_MEMORY;
958 }
959
960 /* map DSM memory and IO into ACPI namespace. */
961 aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, rs,
962 aml_int(nvdimm_state->dsm_io.address),
963 nvdimm_state->dsm_io.bit_width >> 3));
964 aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY,
965 AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn)));
966
967 /*
968 * DSM notifier:
969 * NVDIMM_DSM_NOTIFY: write the address of DSM memory and notify QEMU to
970 * emulate the access.
971 *
972 * It is the IO port so that accessing them will cause VM-exit, the
973 * control will be transferred to QEMU.
974 */
975 field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK,
976 AML_PRESERVE);
977 aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY,
978 nvdimm_state->dsm_io.bit_width));
979 aml_append(method, field);
980
981 /*
982 * DSM input:
983 * NVDIMM_DSM_HANDLE: store device's handle, it's zero if the _DSM call
984 * happens on NVDIMM Root Device.
985 * NVDIMM_DSM_REVISION: store the Arg1 of _DSM call.
986 * NVDIMM_DSM_FUNCTION: store the Arg2 of _DSM call.
987 * NVDIMM_DSM_ARG3: store the Arg3 of _DSM call which is a Package
988 * containing function-specific arguments.
989 *
990 * They are RAM mapping on host so that these accesses never cause
991 * VM-EXIT.
992 */
993 field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK,
994 AML_PRESERVE);
995 aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE,
996 sizeof(typeof_field(NvdimmDsmIn, handle)) * BITS_PER_BYTE));
997 aml_append(field, aml_named_field(NVDIMM_DSM_REVISION,
998 sizeof(typeof_field(NvdimmDsmIn, revision)) * BITS_PER_BYTE));
999 aml_append(field, aml_named_field(NVDIMM_DSM_FUNCTION,
1000 sizeof(typeof_field(NvdimmDsmIn, function)) * BITS_PER_BYTE));
1001 aml_append(field, aml_named_field(NVDIMM_DSM_ARG3,
1002 (sizeof(NvdimmDsmIn) - offsetof(NvdimmDsmIn, arg3)) * BITS_PER_BYTE));
1003 aml_append(method, field);
1004
1005 /*
1006 * DSM output:
1007 * NVDIMM_DSM_OUT_BUF_SIZE: the size of the buffer filled by QEMU.
1008 * NVDIMM_DSM_OUT_BUF: the buffer QEMU uses to store the result.
1009 *
1010 * Since the page is reused by both input and out, the input data
1011 * will be lost after storing new result into ODAT so we should fetch
1012 * all the input data before writing the result.
1013 */
1014 field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK,
1015 AML_PRESERVE);
1016 aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE,
1017 sizeof(typeof_field(NvdimmDsmOut, len)) * BITS_PER_BYTE));
1018 aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF,
1019 (sizeof(NvdimmDsmOut) - offsetof(NvdimmDsmOut, data)) * BITS_PER_BYTE));
1020 aml_append(method, field);
1021
1022 /*
1023 * do not support any method if DSM memory address has not been
1024 * patched.
1025 */
1026 unpatched = aml_equal(dsm_mem, aml_int(0x0));
1027
1028 expected_uuid = aml_local(0);
1029
1030 ifctx = aml_if(aml_equal(handle, aml_int(0x0)));
1031 aml_append(ifctx, aml_store(
1032 aml_touuid("2F10E7A4-9E91-11E4-89D3-123B93F75CBA")
1033 /* UUID for NVDIMM Root Device */, expected_uuid));
1034 aml_append(method, ifctx);
1035 elsectx = aml_else();
1036 ifctx = aml_if(aml_equal(handle, aml_int(NVDIMM_QEMU_RSVD_HANDLE_ROOT)));
1037 aml_append(ifctx, aml_store(aml_touuid(NVDIMM_QEMU_RSVD_UUID
1038 /* UUID for QEMU internal use */), expected_uuid));
1039 aml_append(elsectx, ifctx);
1040 elsectx2 = aml_else();
1041 aml_append(elsectx2, aml_store(
1042 aml_touuid("4309AC30-0D11-11E4-9191-0800200C9A66")
1043 /* UUID for NVDIMM Devices */, expected_uuid));
1044 aml_append(elsectx, elsectx2);
1045 aml_append(method, elsectx);
1046
1047 uuid_invalid = aml_lnot(aml_equal(uuid, expected_uuid));
1048
1049 unsupport = aml_if(aml_or(unpatched, uuid_invalid, NULL));
1050
1051 /*
1052 * function 0 is called to inquire what functions are supported by
1053 * OSPM
1054 */
1055 ifctx = aml_if(aml_equal(function, aml_int(0)));
1056 byte_list[0] = 0 /* No function Supported */;
1057 aml_append(ifctx, aml_return(aml_buffer(1, byte_list)));
1058 aml_append(unsupport, ifctx);
1059
1060 /* No function is supported yet. */
1061 byte_list[0] = NVDIMM_DSM_RET_STATUS_UNSUPPORT;
1062 aml_append(unsupport, aml_return(aml_buffer(1, byte_list)));
1063 aml_append(method, unsupport);
1064
1065 /*
1066 * The HDLE indicates the DSM function is issued from which device,
1067 * it reserves 0 for root device and is the handle for NVDIMM devices.
1068 * See the comments in nvdimm_slot_to_handle().
1069 */
1070 aml_append(method, aml_store(handle, aml_name(NVDIMM_DSM_HANDLE)));
1071 aml_append(method, aml_store(aml_arg(1), aml_name(NVDIMM_DSM_REVISION)));
1072 aml_append(method, aml_store(function, aml_name(NVDIMM_DSM_FUNCTION)));
1073
1074 /*
1075 * The fourth parameter (Arg3) of _DSM is a package which contains
1076 * a buffer, the layout of the buffer is specified by UUID (Arg0),
1077 * Revision ID (Arg1) and Function Index (Arg2) which are documented
1078 * in the DSM Spec.
1079 */
1080 pckg = aml_arg(3);
1081 ifctx = aml_if(aml_and(aml_equal(aml_object_type(pckg),
1082 aml_int(4 /* Package */)) /* It is a Package? */,
1083 aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */,
1084 NULL));
1085
1086 pckg_index = aml_local(2);
1087 pckg_buf = aml_local(3);
1088 aml_append(ifctx, aml_store(aml_index(pckg, aml_int(0)), pckg_index));
1089 aml_append(ifctx, aml_store(aml_derefof(pckg_index), pckg_buf));
1090 aml_append(ifctx, aml_store(pckg_buf, aml_name(NVDIMM_DSM_ARG3)));
1091 aml_append(method, ifctx);
1092
1093 /*
1094 * tell QEMU about the real address of DSM memory, then QEMU
1095 * gets the control and fills the result in DSM memory.
1096 */
1097 aml_append(method, aml_store(dsm_mem, aml_name(NVDIMM_DSM_NOTIFY)));
1098
1099 dsm_out_buf_size = aml_local(1);
1100 /* RLEN is not included in the payload returned to guest. */
1101 aml_append(method, aml_subtract(aml_name(NVDIMM_DSM_OUT_BUF_SIZE),
1102 aml_int(4), dsm_out_buf_size));
1103
1104 /*
1105 * As per ACPI spec 6.3, Table 19-419 Object Conversion Rules, if
1106 * the Buffer Field <= to the size of an Integer (in bits), it will
1107 * be treated as an integer. Moreover, the integer size depends on
1108 * DSDT tables revision number. If revision number is < 2, integer
1109 * size is 32 bits, otherwise it is 64 bits.
1110 * Because of this CreateField() canot be used if RLEN < Integer Size.
1111 *
1112 * Also please note that APCI ASL operator SizeOf() doesn't support
1113 * Integer and there isn't any other way to figure out the Integer
1114 * size. Hence we assume 8 byte as Integer size and if RLEN < 8 bytes,
1115 * build dsm_out_buf byte by byte.
1116 */
1117 ifctx = aml_if(aml_lless(dsm_out_buf_size, aml_int(8)));
1118 offset = aml_local(2);
1119 aml_append(ifctx, aml_store(aml_int(0), offset));
1120 aml_append(ifctx, aml_name_decl("TBUF", aml_buffer(1, NULL)));
1121 aml_append(ifctx, aml_store(aml_buffer(0, NULL), dsm_out_buf));
1122
1123 whilectx = aml_while(aml_lless(offset, dsm_out_buf_size));
1124 /* Copy 1 byte at offset from ODAT to temporary buffer(TBUF). */
1125 aml_append(whilectx, aml_store(aml_derefof(aml_index(
1126 aml_name(NVDIMM_DSM_OUT_BUF), offset)),
1127 aml_index(aml_name("TBUF"), aml_int(0))));
1128 aml_append(whilectx, aml_concatenate(dsm_out_buf, aml_name("TBUF"),
1129 dsm_out_buf));
1130 aml_append(whilectx, aml_increment(offset));
1131 aml_append(ifctx, whilectx);
1132
1133 aml_append(ifctx, aml_return(dsm_out_buf));
1134 aml_append(method, ifctx);
1135
1136 /* If RLEN >= Integer size, just use CreateField() operator */
1137 aml_append(method, aml_store(aml_shiftleft(dsm_out_buf_size, aml_int(3)),
1138 dsm_out_buf_size));
1139 aml_append(method, aml_create_field(aml_name(NVDIMM_DSM_OUT_BUF),
1140 aml_int(0), dsm_out_buf_size, "OBUF"));
1141 aml_append(method, aml_return(aml_name("OBUF")));
1142
1143 aml_append(dev, method);
1144 }
1145
1146 static void nvdimm_build_device_dsm(Aml *dev, uint32_t handle)
1147 {
1148 Aml *method;
1149
1150 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
1151 aml_append(method, aml_return(aml_call5(NVDIMM_COMMON_DSM, aml_arg(0),
1152 aml_arg(1), aml_arg(2), aml_arg(3),
1153 aml_int(handle))));
1154 aml_append(dev, method);
1155 }
1156
1157 static void nvdimm_build_fit(Aml *dev)
1158 {
1159 Aml *method, *pkg, *buf, *buf_size, *offset, *call_result;
1160 Aml *whilectx, *ifcond, *ifctx, *elsectx, *fit;
1161
1162 buf = aml_local(0);
1163 buf_size = aml_local(1);
1164 fit = aml_local(2);
1165
1166 aml_append(dev, aml_name_decl(NVDIMM_DSM_RFIT_STATUS, aml_int(0)));
1167
1168 /* build helper function, RFIT. */
1169 method = aml_method("RFIT", 1, AML_SERIALIZED);
1170 aml_append(method, aml_name_decl("OFST", aml_int(0)));
1171
1172 /* prepare input package. */
1173 pkg = aml_package(1);
1174 aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
1175 aml_append(pkg, aml_name("OFST"));
1176
1177 /* call Read_FIT function. */
1178 call_result = aml_call5(NVDIMM_COMMON_DSM,
1179 aml_touuid(NVDIMM_QEMU_RSVD_UUID),
1180 aml_int(1) /* Revision 1 */,
1181 aml_int(0x1) /* Read FIT */,
1182 pkg, aml_int(NVDIMM_QEMU_RSVD_HANDLE_ROOT));
1183 aml_append(method, aml_store(call_result, buf));
1184
1185 /* handle _DSM result. */
1186 aml_append(method, aml_create_dword_field(buf,
1187 aml_int(0) /* offset at byte 0 */, "STAU"));
1188
1189 aml_append(method, aml_store(aml_name("STAU"),
1190 aml_name(NVDIMM_DSM_RFIT_STATUS)));
1191
1192 /* if something is wrong during _DSM. */
1193 ifcond = aml_equal(aml_int(NVDIMM_DSM_RET_STATUS_SUCCESS),
1194 aml_name("STAU"));
1195 ifctx = aml_if(aml_lnot(ifcond));
1196 aml_append(ifctx, aml_return(aml_buffer(0, NULL)));
1197 aml_append(method, ifctx);
1198
1199 aml_append(method, aml_store(aml_sizeof(buf), buf_size));
1200 aml_append(method, aml_subtract(buf_size,
1201 aml_int(4) /* the size of "STAU" */,
1202 buf_size));
1203
1204 /* if we read the end of fit. */
1205 ifctx = aml_if(aml_equal(buf_size, aml_int(0)));
1206 aml_append(ifctx, aml_return(aml_buffer(0, NULL)));
1207 aml_append(method, ifctx);
1208
1209 aml_append(method, aml_create_field(buf,
1210 aml_int(4 * BITS_PER_BYTE), /* offset at byte 4.*/
1211 aml_shiftleft(buf_size, aml_int(3)), "BUFF"));
1212 aml_append(method, aml_return(aml_name("BUFF")));
1213 aml_append(dev, method);
1214
1215 /* build _FIT. */
1216 method = aml_method("_FIT", 0, AML_SERIALIZED);
1217 offset = aml_local(3);
1218
1219 aml_append(method, aml_store(aml_buffer(0, NULL), fit));
1220 aml_append(method, aml_store(aml_int(0), offset));
1221
1222 whilectx = aml_while(aml_int(1));
1223 aml_append(whilectx, aml_store(aml_call1("RFIT", offset), buf));
1224 aml_append(whilectx, aml_store(aml_sizeof(buf), buf_size));
1225
1226 /*
1227 * if fit buffer was changed during RFIT, read from the beginning
1228 * again.
1229 */
1230 ifctx = aml_if(aml_equal(aml_name(NVDIMM_DSM_RFIT_STATUS),
1231 aml_int(NVDIMM_DSM_RET_STATUS_FIT_CHANGED)));
1232 aml_append(ifctx, aml_store(aml_buffer(0, NULL), fit));
1233 aml_append(ifctx, aml_store(aml_int(0), offset));
1234 aml_append(whilectx, ifctx);
1235
1236 elsectx = aml_else();
1237
1238 /* finish fit read if no data is read out. */
1239 ifctx = aml_if(aml_equal(buf_size, aml_int(0)));
1240 aml_append(ifctx, aml_return(fit));
1241 aml_append(elsectx, ifctx);
1242
1243 /* update the offset. */
1244 aml_append(elsectx, aml_add(offset, buf_size, offset));
1245 /* append the data we read out to the fit buffer. */
1246 aml_append(elsectx, aml_concatenate(fit, buf, fit));
1247 aml_append(whilectx, elsectx);
1248 aml_append(method, whilectx);
1249
1250 aml_append(dev, method);
1251 }
1252
1253 static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots)
1254 {
1255 uint32_t slot;
1256
1257 for (slot = 0; slot < ram_slots; slot++) {
1258 uint32_t handle = nvdimm_slot_to_handle(slot);
1259 Aml *nvdimm_dev;
1260
1261 nvdimm_dev = aml_device("NV%02X", slot);
1262
1263 /*
1264 * ACPI 6.0: 9.20 NVDIMM Devices:
1265 *
1266 * _ADR object that is used to supply OSPM with unique address
1267 * of the NVDIMM device. This is done by returning the NFIT Device
1268 * handle that is used to identify the associated entries in ACPI
1269 * table NFIT or _FIT.
1270 */
1271 aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
1272
1273 nvdimm_build_device_dsm(nvdimm_dev, handle);
1274 aml_append(root_dev, nvdimm_dev);
1275 }
1276 }
1277
1278 static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data,
1279 BIOSLinker *linker,
1280 NVDIMMState *nvdimm_state,
1281 uint32_t ram_slots)
1282 {
1283 Aml *ssdt, *sb_scope, *dev;
1284 int mem_addr_offset, nvdimm_ssdt;
1285
1286 acpi_add_table(table_offsets, table_data);
1287
1288 ssdt = init_aml_allocator();
1289 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
1290
1291 sb_scope = aml_scope("\\_SB");
1292
1293 dev = aml_device("NVDR");
1294
1295 /*
1296 * ACPI 6.0: 9.20 NVDIMM Devices:
1297 *
1298 * The ACPI Name Space device uses _HID of ACPI0012 to identify the root
1299 * NVDIMM interface device. Platform firmware is required to contain one
1300 * such device in _SB scope if NVDIMMs support is exposed by platform to
1301 * OSPM.
1302 * For each NVDIMM present or intended to be supported by platform,
1303 * platform firmware also exposes an ACPI Namespace Device under the
1304 * root device.
1305 */
1306 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
1307
1308 nvdimm_build_common_dsm(dev, nvdimm_state);
1309
1310 /* 0 is reserved for root device. */
1311 nvdimm_build_device_dsm(dev, 0);
1312 nvdimm_build_fit(dev);
1313
1314 nvdimm_build_nvdimm_devices(dev, ram_slots);
1315
1316 aml_append(sb_scope, dev);
1317 aml_append(ssdt, sb_scope);
1318
1319 nvdimm_ssdt = table_data->len;
1320
1321 /* copy AML table into ACPI tables blob and patch header there */
1322 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1323 mem_addr_offset = build_append_named_dword(table_data,
1324 NVDIMM_ACPI_MEM_ADDR);
1325
1326 bios_linker_loader_alloc(linker,
1327 NVDIMM_DSM_MEM_FILE, nvdimm_state->dsm_mem,
1328 sizeof(NvdimmDsmIn), false /* high memory */);
1329 bios_linker_loader_add_pointer(linker,
1330 ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t),
1331 NVDIMM_DSM_MEM_FILE, 0);
1332 build_header(linker, table_data,
1333 (void *)(table_data->data + nvdimm_ssdt),
1334 "SSDT", table_data->len - nvdimm_ssdt, 1, NULL, "NVDIMM");
1335 free_aml_allocator();
1336 }
1337
1338 void nvdimm_build_srat(GArray *table_data)
1339 {
1340 GSList *device_list = nvdimm_get_device_list();
1341
1342 for (; device_list; device_list = device_list->next) {
1343 AcpiSratMemoryAffinity *numamem = NULL;
1344 DeviceState *dev = device_list->data;
1345 Object *obj = OBJECT(dev);
1346 uint64_t addr, size;
1347 int node;
1348
1349 node = object_property_get_int(obj, PC_DIMM_NODE_PROP, &error_abort);
1350 addr = object_property_get_uint(obj, PC_DIMM_ADDR_PROP, &error_abort);
1351 size = object_property_get_uint(obj, PC_DIMM_SIZE_PROP, &error_abort);
1352
1353 numamem = acpi_data_push(table_data, sizeof *numamem);
1354 build_srat_memory(numamem, addr, size, node,
1355 MEM_AFFINITY_ENABLED | MEM_AFFINITY_NON_VOLATILE);
1356 }
1357 g_slist_free(device_list);
1358 }
1359
1360 void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
1361 BIOSLinker *linker, NVDIMMState *state,
1362 uint32_t ram_slots)
1363 {
1364 GSList *device_list;
1365
1366 /* no nvdimm device can be plugged. */
1367 if (!ram_slots) {
1368 return;
1369 }
1370
1371 nvdimm_build_ssdt(table_offsets, table_data, linker, state,
1372 ram_slots);
1373
1374 device_list = nvdimm_get_device_list();
1375 /* no NVDIMM device is plugged. */
1376 if (!device_list) {
1377 return;
1378 }
1379
1380 nvdimm_build_nfit(state, table_offsets, table_data, linker);
1381 g_slist_free(device_list);
1382 }