explicitly include qom/cpu.h
[qemu.git] / hw / acpi / piix4.c
1 /*
2 * ACPI implementation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
9 *
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
17 *
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
20 */
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "hw/i386/pc.h"
24 #include "hw/isa/apm.h"
25 #include "hw/i2c/pm_smbus.h"
26 #include "hw/pci/pci.h"
27 #include "hw/acpi/acpi.h"
28 #include "sysemu/sysemu.h"
29 #include "qapi/error.h"
30 #include "qemu/range.h"
31 #include "exec/ioport.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "exec/address-spaces.h"
34 #include "hw/acpi/piix4.h"
35 #include "hw/acpi/pcihp.h"
36 #include "hw/acpi/cpu_hotplug.h"
37 #include "hw/hotplug.h"
38 #include "hw/mem/pc-dimm.h"
39 #include "hw/acpi/memory_hotplug.h"
40 #include "hw/acpi/acpi_dev_interface.h"
41 #include "hw/xen/xen.h"
42 #include "qom/cpu.h"
43
44 //#define DEBUG
45
46 #ifdef DEBUG
47 # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48 #else
49 # define PIIX4_DPRINTF(format, ...) do { } while (0)
50 #endif
51
52 #define GPE_BASE 0xafe0
53 #define GPE_LEN 4
54
55 struct pci_status {
56 uint32_t up; /* deprecated, maintained for migration compatibility */
57 uint32_t down;
58 };
59
60 typedef struct PIIX4PMState {
61 /*< private >*/
62 PCIDevice parent_obj;
63 /*< public >*/
64
65 MemoryRegion io;
66 uint32_t io_base;
67
68 MemoryRegion io_gpe;
69 ACPIREGS ar;
70
71 APMState apm;
72
73 PMSMBus smb;
74 uint32_t smb_io_base;
75
76 qemu_irq irq;
77 qemu_irq smi_irq;
78 int smm_enabled;
79 Notifier machine_ready;
80 Notifier powerdown_notifier;
81
82 AcpiPciHpState acpi_pci_hotplug;
83 bool use_acpi_pci_hotplug;
84
85 uint8_t disable_s3;
86 uint8_t disable_s4;
87 uint8_t s4_val;
88
89 AcpiCpuHotplug gpe_cpu;
90
91 MemHotplugState acpi_memory_hotplug;
92 } PIIX4PMState;
93
94 #define TYPE_PIIX4_PM "PIIX4_PM"
95
96 #define PIIX4_PM(obj) \
97 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
98
99 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
100 PCIBus *bus, PIIX4PMState *s);
101
102 #define ACPI_ENABLE 0xf1
103 #define ACPI_DISABLE 0xf0
104
105 static void pm_tmr_timer(ACPIREGS *ar)
106 {
107 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
108 acpi_update_sci(&s->ar, s->irq);
109 }
110
111 static void apm_ctrl_changed(uint32_t val, void *arg)
112 {
113 PIIX4PMState *s = arg;
114 PCIDevice *d = PCI_DEVICE(s);
115
116 /* ACPI specs 3.0, 4.7.2.5 */
117 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
118 if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
119 return;
120 }
121
122 if (d->config[0x5b] & (1 << 1)) {
123 if (s->smi_irq) {
124 qemu_irq_raise(s->smi_irq);
125 }
126 }
127 }
128
129 static void pm_io_space_update(PIIX4PMState *s)
130 {
131 PCIDevice *d = PCI_DEVICE(s);
132
133 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
134 s->io_base &= 0xffc0;
135
136 memory_region_transaction_begin();
137 memory_region_set_enabled(&s->io, d->config[0x80] & 1);
138 memory_region_set_address(&s->io, s->io_base);
139 memory_region_transaction_commit();
140 }
141
142 static void smbus_io_space_update(PIIX4PMState *s)
143 {
144 PCIDevice *d = PCI_DEVICE(s);
145
146 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
147 s->smb_io_base &= 0xffc0;
148
149 memory_region_transaction_begin();
150 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
151 memory_region_set_address(&s->smb.io, s->smb_io_base);
152 memory_region_transaction_commit();
153 }
154
155 static void pm_write_config(PCIDevice *d,
156 uint32_t address, uint32_t val, int len)
157 {
158 pci_default_write_config(d, address, val, len);
159 if (range_covers_byte(address, len, 0x80) ||
160 ranges_overlap(address, len, 0x40, 4)) {
161 pm_io_space_update((PIIX4PMState *)d);
162 }
163 if (range_covers_byte(address, len, 0xd2) ||
164 ranges_overlap(address, len, 0x90, 4)) {
165 smbus_io_space_update((PIIX4PMState *)d);
166 }
167 }
168
169 static int vmstate_acpi_post_load(void *opaque, int version_id)
170 {
171 PIIX4PMState *s = opaque;
172
173 pm_io_space_update(s);
174 return 0;
175 }
176
177 #define VMSTATE_GPE_ARRAY(_field, _state) \
178 { \
179 .name = (stringify(_field)), \
180 .version_id = 0, \
181 .info = &vmstate_info_uint16, \
182 .size = sizeof(uint16_t), \
183 .flags = VMS_SINGLE | VMS_POINTER, \
184 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
185 }
186
187 static const VMStateDescription vmstate_gpe = {
188 .name = "gpe",
189 .version_id = 1,
190 .minimum_version_id = 1,
191 .fields = (VMStateField[]) {
192 VMSTATE_GPE_ARRAY(sts, ACPIGPE),
193 VMSTATE_GPE_ARRAY(en, ACPIGPE),
194 VMSTATE_END_OF_LIST()
195 }
196 };
197
198 static const VMStateDescription vmstate_pci_status = {
199 .name = "pci_status",
200 .version_id = 1,
201 .minimum_version_id = 1,
202 .fields = (VMStateField[]) {
203 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
204 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
205 VMSTATE_END_OF_LIST()
206 }
207 };
208
209 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
210 {
211 PIIX4PMState *s = opaque;
212 int ret, i;
213 uint16_t temp;
214
215 ret = pci_device_load(PCI_DEVICE(s), f);
216 if (ret < 0) {
217 return ret;
218 }
219 qemu_get_be16s(f, &s->ar.pm1.evt.sts);
220 qemu_get_be16s(f, &s->ar.pm1.evt.en);
221 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
222
223 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
224 if (ret) {
225 return ret;
226 }
227
228 timer_get(f, s->ar.tmr.timer);
229 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
230
231 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
232 for (i = 0; i < 3; i++) {
233 qemu_get_be16s(f, &temp);
234 }
235
236 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
237 for (i = 0; i < 3; i++) {
238 qemu_get_be16s(f, &temp);
239 }
240
241 ret = vmstate_load_state(f, &vmstate_pci_status,
242 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
243 return ret;
244 }
245
246 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
247 {
248 PIIX4PMState *s = opaque;
249 return s->use_acpi_pci_hotplug;
250 }
251
252 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
253 {
254 PIIX4PMState *s = opaque;
255 return !s->use_acpi_pci_hotplug;
256 }
257
258 static bool vmstate_test_use_memhp(void *opaque)
259 {
260 PIIX4PMState *s = opaque;
261 return s->acpi_memory_hotplug.is_enabled;
262 }
263
264 static const VMStateDescription vmstate_memhp_state = {
265 .name = "piix4_pm/memhp",
266 .version_id = 1,
267 .minimum_version_id = 1,
268 .minimum_version_id_old = 1,
269 .needed = vmstate_test_use_memhp,
270 .fields = (VMStateField[]) {
271 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
272 VMSTATE_END_OF_LIST()
273 }
274 };
275
276 /* qemu-kvm 1.2 uses version 3 but advertised as 2
277 * To support incoming qemu-kvm 1.2 migration, change version_id
278 * and minimum_version_id to 2 below (which breaks migration from
279 * qemu 1.2).
280 *
281 */
282 static const VMStateDescription vmstate_acpi = {
283 .name = "piix4_pm",
284 .version_id = 3,
285 .minimum_version_id = 3,
286 .minimum_version_id_old = 1,
287 .load_state_old = acpi_load_old,
288 .post_load = vmstate_acpi_post_load,
289 .fields = (VMStateField[]) {
290 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
291 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
292 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
293 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
294 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
295 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
296 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
297 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
298 VMSTATE_STRUCT_TEST(
299 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
300 PIIX4PMState,
301 vmstate_test_no_use_acpi_pci_hotplug,
302 2, vmstate_pci_status,
303 struct AcpiPciHpPciStatus),
304 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
305 vmstate_test_use_acpi_pci_hotplug),
306 VMSTATE_END_OF_LIST()
307 },
308 .subsections = (const VMStateDescription*[]) {
309 &vmstate_memhp_state,
310 NULL
311 }
312 };
313
314 static void piix4_reset(void *opaque)
315 {
316 PIIX4PMState *s = opaque;
317 PCIDevice *d = PCI_DEVICE(s);
318 uint8_t *pci_conf = d->config;
319
320 pci_conf[0x58] = 0;
321 pci_conf[0x59] = 0;
322 pci_conf[0x5a] = 0;
323 pci_conf[0x5b] = 0;
324
325 pci_conf[0x40] = 0x01; /* PM io base read only bit */
326 pci_conf[0x80] = 0;
327
328 if (!s->smm_enabled) {
329 /* Mark SMM as already inited (until KVM supports SMM). */
330 pci_conf[0x5B] = 0x02;
331 }
332 pm_io_space_update(s);
333 acpi_pcihp_reset(&s->acpi_pci_hotplug);
334 }
335
336 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
337 {
338 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
339
340 assert(s != NULL);
341 acpi_pm1_evt_power_down(&s->ar);
342 }
343
344 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
345 DeviceState *dev, Error **errp)
346 {
347 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
348
349 if (s->acpi_memory_hotplug.is_enabled &&
350 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
351 acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp);
352 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
353 acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
354 errp);
355 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
356 acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp);
357 } else {
358 error_setg(errp, "acpi: device plug request for not supported device"
359 " type: %s", object_get_typename(OBJECT(dev)));
360 }
361 }
362
363 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
364 DeviceState *dev, Error **errp)
365 {
366 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
367
368 if (s->acpi_memory_hotplug.is_enabled &&
369 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
370 acpi_memory_unplug_request_cb(&s->ar, s->irq, &s->acpi_memory_hotplug,
371 dev, errp);
372 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
373 acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
374 errp);
375 } else {
376 error_setg(errp, "acpi: device unplug request for not supported device"
377 " type: %s", object_get_typename(OBJECT(dev)));
378 }
379 }
380
381 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
382 DeviceState *dev, Error **errp)
383 {
384 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
385
386 if (s->acpi_memory_hotplug.is_enabled &&
387 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
388 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
389 } else {
390 error_setg(errp, "acpi: device unplug for not supported device"
391 " type: %s", object_get_typename(OBJECT(dev)));
392 }
393 }
394
395 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
396 {
397 PIIX4PMState *s = opaque;
398
399 qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
400 }
401
402 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
403 {
404 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
405 PCIDevice *d = PCI_DEVICE(s);
406 MemoryRegion *io_as = pci_address_space_io(d);
407 uint8_t *pci_conf;
408
409 pci_conf = d->config;
410 pci_conf[0x5f] = 0x10 |
411 (memory_region_present(io_as, 0x378) ? 0x80 : 0);
412 pci_conf[0x63] = 0x60;
413 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
414 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
415
416 if (s->use_acpi_pci_hotplug) {
417 pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
418 } else {
419 piix4_update_bus_hotplug(d->bus, s);
420 }
421 }
422
423 static void piix4_pm_add_propeties(PIIX4PMState *s)
424 {
425 static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
426 static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
427 static const uint32_t gpe0_blk = GPE_BASE;
428 static const uint32_t gpe0_blk_len = GPE_LEN;
429 static const uint16_t sci_int = 9;
430
431 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
432 &acpi_enable_cmd, NULL);
433 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
434 &acpi_disable_cmd, NULL);
435 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
436 &gpe0_blk, NULL);
437 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
438 &gpe0_blk_len, NULL);
439 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
440 &sci_int, NULL);
441 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
442 &s->io_base, NULL);
443 }
444
445 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
446 {
447 PIIX4PMState *s = PIIX4_PM(dev);
448 uint8_t *pci_conf;
449
450 pci_conf = dev->config;
451 pci_conf[0x06] = 0x80;
452 pci_conf[0x07] = 0x02;
453 pci_conf[0x09] = 0x00;
454 pci_conf[0x3d] = 0x01; // interrupt pin 1
455
456 /* APM */
457 apm_init(dev, &s->apm, apm_ctrl_changed, s);
458
459 if (!s->smm_enabled) {
460 /* Mark SMM as already inited to prevent SMM from running. KVM does not
461 * support SMM mode. */
462 pci_conf[0x5B] = 0x02;
463 }
464
465 /* XXX: which specification is used ? The i82731AB has different
466 mappings */
467 pci_conf[0x90] = s->smb_io_base | 1;
468 pci_conf[0x91] = s->smb_io_base >> 8;
469 pci_conf[0xd2] = 0x09;
470 pm_smbus_init(DEVICE(dev), &s->smb);
471 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
472 memory_region_add_subregion(pci_address_space_io(dev),
473 s->smb_io_base, &s->smb.io);
474
475 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
476 memory_region_set_enabled(&s->io, false);
477 memory_region_add_subregion(pci_address_space_io(dev),
478 0, &s->io);
479
480 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
481 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
482 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
483 acpi_gpe_init(&s->ar, GPE_LEN);
484
485 s->powerdown_notifier.notify = piix4_pm_powerdown_req;
486 qemu_register_powerdown_notifier(&s->powerdown_notifier);
487
488 s->machine_ready.notify = piix4_pm_machine_ready;
489 qemu_add_machine_init_done_notifier(&s->machine_ready);
490 qemu_register_reset(piix4_reset, s);
491
492 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
493
494 piix4_pm_add_propeties(s);
495 }
496
497 Object *piix4_pm_find(void)
498 {
499 bool ambig;
500 Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
501
502 if (ambig || !o) {
503 return NULL;
504 }
505 return o;
506 }
507
508 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
509 qemu_irq sci_irq, qemu_irq smi_irq,
510 int smm_enabled, DeviceState **piix4_pm)
511 {
512 DeviceState *dev;
513 PIIX4PMState *s;
514
515 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
516 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
517 if (piix4_pm) {
518 *piix4_pm = dev;
519 }
520
521 s = PIIX4_PM(dev);
522 s->irq = sci_irq;
523 s->smi_irq = smi_irq;
524 s->smm_enabled = smm_enabled;
525 if (xen_enabled()) {
526 s->use_acpi_pci_hotplug = false;
527 }
528
529 qdev_init_nofail(dev);
530
531 return s->smb.smbus;
532 }
533
534 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
535 {
536 PIIX4PMState *s = opaque;
537 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
538
539 PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
540 return val;
541 }
542
543 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
544 unsigned width)
545 {
546 PIIX4PMState *s = opaque;
547
548 acpi_gpe_ioport_writeb(&s->ar, addr, val);
549 acpi_update_sci(&s->ar, s->irq);
550
551 PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
552 }
553
554 static const MemoryRegionOps piix4_gpe_ops = {
555 .read = gpe_readb,
556 .write = gpe_writeb,
557 .valid.min_access_size = 1,
558 .valid.max_access_size = 4,
559 .impl.min_access_size = 1,
560 .impl.max_access_size = 1,
561 .endianness = DEVICE_LITTLE_ENDIAN,
562 };
563
564 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
565 PCIBus *bus, PIIX4PMState *s)
566 {
567 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
568 "acpi-gpe0", GPE_LEN);
569 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
570
571 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
572 s->use_acpi_pci_hotplug);
573
574 acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
575 PIIX4_CPU_HOTPLUG_IO_BASE);
576
577 if (s->acpi_memory_hotplug.is_enabled) {
578 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug);
579 }
580 }
581
582 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
583 {
584 PIIX4PMState *s = PIIX4_PM(adev);
585
586 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
587 }
588
589 static Property piix4_pm_properties[] = {
590 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
591 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
592 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
593 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
594 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
595 use_acpi_pci_hotplug, true),
596 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
597 acpi_memory_hotplug.is_enabled, true),
598 DEFINE_PROP_END_OF_LIST(),
599 };
600
601 static void piix4_pm_class_init(ObjectClass *klass, void *data)
602 {
603 DeviceClass *dc = DEVICE_CLASS(klass);
604 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
605 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
606 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
607
608 k->realize = piix4_pm_realize;
609 k->config_write = pm_write_config;
610 k->vendor_id = PCI_VENDOR_ID_INTEL;
611 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
612 k->revision = 0x03;
613 k->class_id = PCI_CLASS_BRIDGE_OTHER;
614 dc->desc = "PM";
615 dc->vmsd = &vmstate_acpi;
616 dc->props = piix4_pm_properties;
617 /*
618 * Reason: part of PIIX4 southbridge, needs to be wired up,
619 * e.g. by mips_malta_init()
620 */
621 dc->cannot_instantiate_with_device_add_yet = true;
622 dc->hotpluggable = false;
623 hc->plug = piix4_device_plug_cb;
624 hc->unplug_request = piix4_device_unplug_request_cb;
625 hc->unplug = piix4_device_unplug_cb;
626 adevc->ospm_status = piix4_ospm_status;
627 }
628
629 static const TypeInfo piix4_pm_info = {
630 .name = TYPE_PIIX4_PM,
631 .parent = TYPE_PCI_DEVICE,
632 .instance_size = sizeof(PIIX4PMState),
633 .class_init = piix4_pm_class_init,
634 .interfaces = (InterfaceInfo[]) {
635 { TYPE_HOTPLUG_HANDLER },
636 { TYPE_ACPI_DEVICE_IF },
637 { }
638 }
639 };
640
641 static void piix4_pm_register_types(void)
642 {
643 type_register_static(&piix4_pm_info);
644 }
645
646 type_init(piix4_pm_register_types)