Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / arm / bcm2836.c
1 /*
2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
4 *
5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
6 * Written by Andrew Baumann
7 *
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "qemu/module.h"
15 #include "cpu.h"
16 #include "hw/arm/bcm2836.h"
17 #include "hw/arm/raspi_platform.h"
18 #include "hw/sysbus.h"
19
20 struct BCM283XInfo {
21 const char *name;
22 const char *cpu_type;
23 hwaddr peri_base; /* Peripheral base address seen by the CPU */
24 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
25 int clusterid;
26 };
27
28 static const BCM283XInfo bcm283x_socs[] = {
29 {
30 .name = TYPE_BCM2836,
31 .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
32 .peri_base = 0x3f000000,
33 .ctrl_base = 0x40000000,
34 .clusterid = 0xf,
35 },
36 #ifdef TARGET_AARCH64
37 {
38 .name = TYPE_BCM2837,
39 .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
40 .peri_base = 0x3f000000,
41 .ctrl_base = 0x40000000,
42 .clusterid = 0x0,
43 },
44 #endif
45 };
46
47 static void bcm2836_init(Object *obj)
48 {
49 BCM283XState *s = BCM283X(obj);
50 BCM283XClass *bc = BCM283X_GET_CLASS(obj);
51 const BCM283XInfo *info = bc->info;
52 int n;
53
54 for (n = 0; n < BCM283X_NCPUS; n++) {
55 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
56 info->cpu_type);
57 }
58
59 object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
60
61 object_initialize_child(obj, "peripherals", &s->peripherals,
62 TYPE_BCM2835_PERIPHERALS);
63 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
64 "board-rev");
65 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
66 "vcram-size");
67 }
68
69 static void bcm2836_realize(DeviceState *dev, Error **errp)
70 {
71 BCM283XState *s = BCM283X(dev);
72 BCM283XClass *bc = BCM283X_GET_CLASS(dev);
73 const BCM283XInfo *info = bc->info;
74 Object *obj;
75 int n;
76
77 /* common peripherals from bcm2835 */
78
79 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
80
81 object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
82
83 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
84 return;
85 }
86
87 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
88 "sd-bus");
89
90 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
91 info->peri_base, 1);
92
93 /* bcm2836 interrupt controller (and mailboxes, etc.) */
94 if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
95 return;
96 }
97
98 sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
99
100 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
101 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
102 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
103 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0));
104
105 for (n = 0; n < BCM283X_NCPUS; n++) {
106 /* TODO: this should be converted to a property of ARM_CPU */
107 s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
108
109 /* set periphbase/CBAR value for CPU-local registers */
110 if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
111 info->peri_base, errp)) {
112 return;
113 }
114
115 /* start powered off if not enabled */
116 if (!object_property_set_bool(OBJECT(&s->cpu[n].core),
117 "start-powered-off",
118 n >= s->enabled_cpus,
119 errp)) {
120 return;
121 }
122
123 if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) {
124 return;
125 }
126
127 /* Connect irq/fiq outputs from the interrupt controller. */
128 qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,
129 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));
130 qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,
131 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));
132
133 /* Connect timers from the CPU to the interrupt controller */
134 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,
135 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
136 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,
137 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
138 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,
139 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
140 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,
141 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
142 }
143 }
144
145 static Property bcm2836_props[] = {
146 DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
147 BCM283X_NCPUS),
148 DEFINE_PROP_END_OF_LIST()
149 };
150
151 static void bcm283x_class_init(ObjectClass *oc, void *data)
152 {
153 DeviceClass *dc = DEVICE_CLASS(oc);
154 BCM283XClass *bc = BCM283X_CLASS(oc);
155
156 bc->info = data;
157 dc->realize = bcm2836_realize;
158 device_class_set_props(dc, bcm2836_props);
159 /* Reason: Must be wired up in code (see raspi_init() function) */
160 dc->user_creatable = false;
161 }
162
163 static const TypeInfo bcm283x_type_info = {
164 .name = TYPE_BCM283X,
165 .parent = TYPE_DEVICE,
166 .instance_size = sizeof(BCM283XState),
167 .instance_init = bcm2836_init,
168 .class_size = sizeof(BCM283XClass),
169 .abstract = true,
170 };
171
172 static void bcm2836_register_types(void)
173 {
174 int i;
175
176 type_register_static(&bcm283x_type_info);
177 for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
178 TypeInfo ti = {
179 .name = bcm283x_socs[i].name,
180 .parent = TYPE_BCM283X,
181 .class_init = bcm283x_class_init,
182 .class_data = (void *) &bcm283x_socs[i],
183 };
184 type_register(&ti);
185 }
186 }
187
188 type_init(bcm2836_register_types)