Merge tag 'seabios-20211203-pull-request' of git://git.kraxel.org/qemu into staging
[qemu.git] / hw / arm / boot.c
1 /*
2 * ARM kernel loader.
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu-common.h"
12 #include "qemu/datadir.h"
13 #include "qemu/error-report.h"
14 #include "qapi/error.h"
15 #include <libfdt.h>
16 #include "hw/arm/boot.h"
17 #include "hw/arm/linux-boot-if.h"
18 #include "sysemu/kvm.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/numa.h"
21 #include "hw/boards.h"
22 #include "sysemu/reset.h"
23 #include "hw/loader.h"
24 #include "elf.h"
25 #include "sysemu/device_tree.h"
26 #include "qemu/config-file.h"
27 #include "qemu/option.h"
28 #include "qemu/units.h"
29
30 /* Kernel boot protocol is specified in the kernel docs
31 * Documentation/arm/Booting and Documentation/arm64/booting.txt
32 * They have different preferred image load offsets from system RAM base.
33 */
34 #define KERNEL_ARGS_ADDR 0x100
35 #define KERNEL_NOLOAD_ADDR 0x02000000
36 #define KERNEL_LOAD_ADDR 0x00010000
37 #define KERNEL64_LOAD_ADDR 0x00080000
38
39 #define ARM64_TEXT_OFFSET_OFFSET 8
40 #define ARM64_MAGIC_OFFSET 56
41
42 #define BOOTLOADER_MAX_SIZE (4 * KiB)
43
44 AddressSpace *arm_boot_address_space(ARMCPU *cpu,
45 const struct arm_boot_info *info)
46 {
47 /* Return the address space to use for bootloader reads and writes.
48 * We prefer the secure address space if the CPU has it and we're
49 * going to boot the guest into it.
50 */
51 int asidx;
52 CPUState *cs = CPU(cpu);
53
54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {
55 asidx = ARMASIdx_S;
56 } else {
57 asidx = ARMASIdx_NS;
58 }
59
60 return cpu_get_address_space(cs, asidx);
61 }
62
63 typedef enum {
64 FIXUP_NONE = 0, /* do nothing */
65 FIXUP_TERMINATOR, /* end of insns */
66 FIXUP_BOARDID, /* overwrite with board ID number */
67 FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
68 FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
69 FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
70 FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
71 FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
72 FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
73 FIXUP_BOOTREG, /* overwrite with boot register address */
74 FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
75 FIXUP_MAX,
76 } FixupType;
77
78 typedef struct ARMInsnFixup {
79 uint32_t insn;
80 FixupType fixup;
81 } ARMInsnFixup;
82
83 static const ARMInsnFixup bootloader_aarch64[] = {
84 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
85 { 0xaa1f03e1 }, /* mov x1, xzr */
86 { 0xaa1f03e2 }, /* mov x2, xzr */
87 { 0xaa1f03e3 }, /* mov x3, xzr */
88 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
89 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
90 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
91 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
92 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */
93 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */
94 { 0, FIXUP_TERMINATOR }
95 };
96
97 /* A very small bootloader: call the board-setup code (if needed),
98 * set r0-r2, then jump to the kernel.
99 * If we're not calling boot setup code then we don't copy across
100 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array.
101 */
102
103 static const ARMInsnFixup bootloader[] = {
104 { 0xe28fe004 }, /* add lr, pc, #4 */
105 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */
106 { 0, FIXUP_BOARD_SETUP },
107 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
108 { 0xe3a00000 }, /* mov r0, #0 */
109 { 0xe59f1004 }, /* ldr r1, [pc, #4] */
110 { 0xe59f2004 }, /* ldr r2, [pc, #4] */
111 { 0xe59ff004 }, /* ldr pc, [pc, #4] */
112 { 0, FIXUP_BOARDID },
113 { 0, FIXUP_ARGPTR_LO },
114 { 0, FIXUP_ENTRYPOINT_LO },
115 { 0, FIXUP_TERMINATOR }
116 };
117
118 /* Handling for secondary CPU boot in a multicore system.
119 * Unlike the uniprocessor/primary CPU boot, this is platform
120 * dependent. The default code here is based on the secondary
121 * CPU boot protocol used on realview/vexpress boards, with
122 * some parameterisation to increase its flexibility.
123 * QEMU platform models for which this code is not appropriate
124 * should override write_secondary_boot and secondary_cpu_reset_hook
125 * instead.
126 *
127 * This code enables the interrupt controllers for the secondary
128 * CPUs and then puts all the secondary CPUs into a loop waiting
129 * for an interprocessor interrupt and polling a configurable
130 * location for the kernel secondary CPU entry point.
131 */
132 #define DSB_INSN 0xf57ff04f
133 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
134
135 static const ARMInsnFixup smpboot[] = {
136 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
137 { 0xe59f0028 }, /* ldr r0, bootreg_addr */
138 { 0xe3a01001 }, /* mov r1, #1 */
139 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
140 { 0xe3a010ff }, /* mov r1, #0xff */
141 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
142 { 0, FIXUP_DSB }, /* dsb */
143 { 0xe320f003 }, /* wfi */
144 { 0xe5901000 }, /* ldr r1, [r0] */
145 { 0xe1110001 }, /* tst r1, r1 */
146 { 0x0afffffb }, /* beq <wfi> */
147 { 0xe12fff11 }, /* bx r1 */
148 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */
149 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */
150 { 0, FIXUP_TERMINATOR }
151 };
152
153 static void write_bootloader(const char *name, hwaddr addr,
154 const ARMInsnFixup *insns, uint32_t *fixupcontext,
155 AddressSpace *as)
156 {
157 /* Fix up the specified bootloader fragment and write it into
158 * guest memory using rom_add_blob_fixed(). fixupcontext is
159 * an array giving the values to write in for the fixup types
160 * which write a value into the code array.
161 */
162 int i, len;
163 uint32_t *code;
164
165 len = 0;
166 while (insns[len].fixup != FIXUP_TERMINATOR) {
167 len++;
168 }
169
170 code = g_new0(uint32_t, len);
171
172 for (i = 0; i < len; i++) {
173 uint32_t insn = insns[i].insn;
174 FixupType fixup = insns[i].fixup;
175
176 switch (fixup) {
177 case FIXUP_NONE:
178 break;
179 case FIXUP_BOARDID:
180 case FIXUP_BOARD_SETUP:
181 case FIXUP_ARGPTR_LO:
182 case FIXUP_ARGPTR_HI:
183 case FIXUP_ENTRYPOINT_LO:
184 case FIXUP_ENTRYPOINT_HI:
185 case FIXUP_GIC_CPU_IF:
186 case FIXUP_BOOTREG:
187 case FIXUP_DSB:
188 insn = fixupcontext[fixup];
189 break;
190 default:
191 abort();
192 }
193 code[i] = tswap32(insn);
194 }
195
196 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
197
198 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
199
200 g_free(code);
201 }
202
203 static void default_write_secondary(ARMCPU *cpu,
204 const struct arm_boot_info *info)
205 {
206 uint32_t fixupcontext[FIXUP_MAX];
207 AddressSpace *as = arm_boot_address_space(cpu, info);
208
209 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
210 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
211 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
212 fixupcontext[FIXUP_DSB] = DSB_INSN;
213 } else {
214 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
215 }
216
217 write_bootloader("smpboot", info->smp_loader_start,
218 smpboot, fixupcontext, as);
219 }
220
221 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
222 const struct arm_boot_info *info,
223 hwaddr mvbar_addr)
224 {
225 AddressSpace *as = arm_boot_address_space(cpu, info);
226 int n;
227 uint32_t mvbar_blob[] = {
228 /* mvbar_addr: secure monitor vectors
229 * Default unimplemented and unused vectors to spin. Makes it
230 * easier to debug (as opposed to the CPU running away).
231 */
232 0xeafffffe, /* (spin) */
233 0xeafffffe, /* (spin) */
234 0xe1b0f00e, /* movs pc, lr ;SMC exception return */
235 0xeafffffe, /* (spin) */
236 0xeafffffe, /* (spin) */
237 0xeafffffe, /* (spin) */
238 0xeafffffe, /* (spin) */
239 0xeafffffe, /* (spin) */
240 };
241 uint32_t board_setup_blob[] = {
242 /* board setup addr */
243 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */
244 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */
245 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */
246 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */
247 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
248 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
249 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */
250 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */
251 0xe1a0100e, /* mov r1, lr ;save LR across SMC */
252 0xe1600070, /* smc #0 ;call monitor to flush SCR */
253 0xe1a0f001, /* mov pc, r1 ;return */
254 };
255
256 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */
257 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
258
259 /* check that these blobs don't overlap */
260 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
261 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
262
263 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
264 mvbar_blob[n] = tswap32(mvbar_blob[n]);
265 }
266 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
267 mvbar_addr, as);
268
269 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
270 board_setup_blob[n] = tswap32(board_setup_blob[n]);
271 }
272 rom_add_blob_fixed_as("board-setup", board_setup_blob,
273 sizeof(board_setup_blob), info->board_setup_addr, as);
274 }
275
276 static void default_reset_secondary(ARMCPU *cpu,
277 const struct arm_boot_info *info)
278 {
279 AddressSpace *as = arm_boot_address_space(cpu, info);
280 CPUState *cs = CPU(cpu);
281
282 address_space_stl_notdirty(as, info->smp_bootreg_addr,
283 0, MEMTXATTRS_UNSPECIFIED, NULL);
284 cpu_set_pc(cs, info->smp_loader_start);
285 }
286
287 static inline bool have_dtb(const struct arm_boot_info *info)
288 {
289 return info->dtb_filename || info->get_dtb;
290 }
291
292 #define WRITE_WORD(p, value) do { \
293 address_space_stl_notdirty(as, p, value, \
294 MEMTXATTRS_UNSPECIFIED, NULL); \
295 p += 4; \
296 } while (0)
297
298 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
299 {
300 int initrd_size = info->initrd_size;
301 hwaddr base = info->loader_start;
302 hwaddr p;
303
304 p = base + KERNEL_ARGS_ADDR;
305 /* ATAG_CORE */
306 WRITE_WORD(p, 5);
307 WRITE_WORD(p, 0x54410001);
308 WRITE_WORD(p, 1);
309 WRITE_WORD(p, 0x1000);
310 WRITE_WORD(p, 0);
311 /* ATAG_MEM */
312 /* TODO: handle multiple chips on one ATAG list */
313 WRITE_WORD(p, 4);
314 WRITE_WORD(p, 0x54410002);
315 WRITE_WORD(p, info->ram_size);
316 WRITE_WORD(p, info->loader_start);
317 if (initrd_size) {
318 /* ATAG_INITRD2 */
319 WRITE_WORD(p, 4);
320 WRITE_WORD(p, 0x54420005);
321 WRITE_WORD(p, info->initrd_start);
322 WRITE_WORD(p, initrd_size);
323 }
324 if (info->kernel_cmdline && *info->kernel_cmdline) {
325 /* ATAG_CMDLINE */
326 int cmdline_size;
327
328 cmdline_size = strlen(info->kernel_cmdline);
329 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
330 info->kernel_cmdline, cmdline_size + 1);
331 cmdline_size = (cmdline_size >> 2) + 1;
332 WRITE_WORD(p, cmdline_size + 2);
333 WRITE_WORD(p, 0x54410009);
334 p += cmdline_size * 4;
335 }
336 if (info->atag_board) {
337 /* ATAG_BOARD */
338 int atag_board_len;
339 uint8_t atag_board_buf[0x1000];
340
341 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
342 WRITE_WORD(p, (atag_board_len + 8) >> 2);
343 WRITE_WORD(p, 0x414f4d50);
344 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
345 atag_board_buf, atag_board_len);
346 p += atag_board_len;
347 }
348 /* ATAG_END */
349 WRITE_WORD(p, 0);
350 WRITE_WORD(p, 0);
351 }
352
353 static void set_kernel_args_old(const struct arm_boot_info *info,
354 AddressSpace *as)
355 {
356 hwaddr p;
357 const char *s;
358 int initrd_size = info->initrd_size;
359 hwaddr base = info->loader_start;
360
361 /* see linux/include/asm-arm/setup.h */
362 p = base + KERNEL_ARGS_ADDR;
363 /* page_size */
364 WRITE_WORD(p, 4096);
365 /* nr_pages */
366 WRITE_WORD(p, info->ram_size / 4096);
367 /* ramdisk_size */
368 WRITE_WORD(p, 0);
369 #define FLAG_READONLY 1
370 #define FLAG_RDLOAD 4
371 #define FLAG_RDPROMPT 8
372 /* flags */
373 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
374 /* rootdev */
375 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
376 /* video_num_cols */
377 WRITE_WORD(p, 0);
378 /* video_num_rows */
379 WRITE_WORD(p, 0);
380 /* video_x */
381 WRITE_WORD(p, 0);
382 /* video_y */
383 WRITE_WORD(p, 0);
384 /* memc_control_reg */
385 WRITE_WORD(p, 0);
386 /* unsigned char sounddefault */
387 /* unsigned char adfsdrives */
388 /* unsigned char bytes_per_char_h */
389 /* unsigned char bytes_per_char_v */
390 WRITE_WORD(p, 0);
391 /* pages_in_bank[4] */
392 WRITE_WORD(p, 0);
393 WRITE_WORD(p, 0);
394 WRITE_WORD(p, 0);
395 WRITE_WORD(p, 0);
396 /* pages_in_vram */
397 WRITE_WORD(p, 0);
398 /* initrd_start */
399 if (initrd_size) {
400 WRITE_WORD(p, info->initrd_start);
401 } else {
402 WRITE_WORD(p, 0);
403 }
404 /* initrd_size */
405 WRITE_WORD(p, initrd_size);
406 /* rd_start */
407 WRITE_WORD(p, 0);
408 /* system_rev */
409 WRITE_WORD(p, 0);
410 /* system_serial_low */
411 WRITE_WORD(p, 0);
412 /* system_serial_high */
413 WRITE_WORD(p, 0);
414 /* mem_fclk_21285 */
415 WRITE_WORD(p, 0);
416 /* zero unused fields */
417 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
418 WRITE_WORD(p, 0);
419 }
420 s = info->kernel_cmdline;
421 if (s) {
422 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
423 } else {
424 WRITE_WORD(p, 0);
425 }
426 }
427
428 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base,
429 uint32_t scells, hwaddr mem_len,
430 int numa_node_id)
431 {
432 char *nodename;
433 int ret;
434
435 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
436 qemu_fdt_add_subnode(fdt, nodename);
437 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
438 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base,
439 scells, mem_len);
440 if (ret < 0) {
441 goto out;
442 }
443
444 /* only set the NUMA ID if it is specified */
445 if (numa_node_id >= 0) {
446 ret = qemu_fdt_setprop_cell(fdt, nodename,
447 "numa-node-id", numa_node_id);
448 }
449 out:
450 g_free(nodename);
451 return ret;
452 }
453
454 static void fdt_add_psci_node(void *fdt)
455 {
456 uint32_t cpu_suspend_fn;
457 uint32_t cpu_off_fn;
458 uint32_t cpu_on_fn;
459 uint32_t migrate_fn;
460 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
461 const char *psci_method;
462 int64_t psci_conduit;
463 int rc;
464
465 psci_conduit = object_property_get_int(OBJECT(armcpu),
466 "psci-conduit",
467 &error_abort);
468 switch (psci_conduit) {
469 case QEMU_PSCI_CONDUIT_DISABLED:
470 return;
471 case QEMU_PSCI_CONDUIT_HVC:
472 psci_method = "hvc";
473 break;
474 case QEMU_PSCI_CONDUIT_SMC:
475 psci_method = "smc";
476 break;
477 default:
478 g_assert_not_reached();
479 }
480
481 /*
482 * If /psci node is present in provided DTB, assume that no fixup
483 * is necessary and all PSCI configuration should be taken as-is
484 */
485 rc = fdt_path_offset(fdt, "/psci");
486 if (rc >= 0) {
487 return;
488 }
489
490 qemu_fdt_add_subnode(fdt, "/psci");
491 if (armcpu->psci_version == 2) {
492 const char comp[] = "arm,psci-0.2\0arm,psci";
493 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
494
495 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
496 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
497 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
498 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
499 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
500 } else {
501 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
502 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
503 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
504 }
505 } else {
506 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
507
508 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
509 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
510 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
511 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
512 }
513
514 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
515 * to the instruction that should be used to invoke PSCI functions.
516 * However, the device tree binding uses 'method' instead, so that is
517 * what we should use here.
518 */
519 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
520
521 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
522 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
523 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
524 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
525 }
526
527 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
528 hwaddr addr_limit, AddressSpace *as, MachineState *ms)
529 {
530 void *fdt = NULL;
531 int size, rc, n = 0;
532 uint32_t acells, scells;
533 unsigned int i;
534 hwaddr mem_base, mem_len;
535 char **node_path;
536 Error *err = NULL;
537
538 if (binfo->dtb_filename) {
539 char *filename;
540 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
541 if (!filename) {
542 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
543 goto fail;
544 }
545
546 fdt = load_device_tree(filename, &size);
547 if (!fdt) {
548 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
549 g_free(filename);
550 goto fail;
551 }
552 g_free(filename);
553 } else {
554 fdt = binfo->get_dtb(binfo, &size);
555 if (!fdt) {
556 fprintf(stderr, "Board was unable to create a dtb blob\n");
557 goto fail;
558 }
559 }
560
561 if (addr_limit > addr && size > (addr_limit - addr)) {
562 /* Installing the device tree blob at addr would exceed addr_limit.
563 * Whether this constitutes failure is up to the caller to decide,
564 * so just return 0 as size, i.e., no error.
565 */
566 g_free(fdt);
567 return 0;
568 }
569
570 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
571 NULL, &error_fatal);
572 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
573 NULL, &error_fatal);
574 if (acells == 0 || scells == 0) {
575 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
576 goto fail;
577 }
578
579 if (scells < 2 && binfo->ram_size >= 4 * GiB) {
580 /* This is user error so deserves a friendlier error message
581 * than the failure of setprop_sized_cells would provide
582 */
583 fprintf(stderr, "qemu: dtb file not compatible with "
584 "RAM size > 4GB\n");
585 goto fail;
586 }
587
588 /* nop all root nodes matching /memory or /memory@unit-address */
589 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
590 if (err) {
591 error_report_err(err);
592 goto fail;
593 }
594 while (node_path[n]) {
595 if (g_str_has_prefix(node_path[n], "/memory")) {
596 qemu_fdt_nop_node(fdt, node_path[n]);
597 }
598 n++;
599 }
600 g_strfreev(node_path);
601
602 /*
603 * We drop all the memory nodes which correspond to empty NUMA nodes
604 * from the device tree, because the Linux NUMA binding document
605 * states they should not be generated. Linux will get the NUMA node
606 * IDs of the empty NUMA nodes from the distance map if they are needed.
607 * This means QEMU users may be obliged to provide command lines which
608 * configure distance maps when the empty NUMA node IDs are needed and
609 * Linux's default distance map isn't sufficient.
610 */
611 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
612 mem_base = binfo->loader_start;
613 for (i = 0; i < ms->numa_state->num_nodes; i++) {
614 mem_len = ms->numa_state->nodes[i].node_mem;
615 if (!mem_len) {
616 continue;
617 }
618
619 rc = fdt_add_memory_node(fdt, acells, mem_base,
620 scells, mem_len, i);
621 if (rc < 0) {
622 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
623 mem_base);
624 goto fail;
625 }
626
627 mem_base += mem_len;
628 }
629 } else {
630 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start,
631 scells, binfo->ram_size, -1);
632 if (rc < 0) {
633 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
634 binfo->loader_start);
635 goto fail;
636 }
637 }
638
639 rc = fdt_path_offset(fdt, "/chosen");
640 if (rc < 0) {
641 qemu_fdt_add_subnode(fdt, "/chosen");
642 }
643
644 if (ms->kernel_cmdline && *ms->kernel_cmdline) {
645 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
646 ms->kernel_cmdline);
647 if (rc < 0) {
648 fprintf(stderr, "couldn't set /chosen/bootargs\n");
649 goto fail;
650 }
651 }
652
653 if (binfo->initrd_size) {
654 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
655 binfo->initrd_start);
656 if (rc < 0) {
657 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
658 goto fail;
659 }
660
661 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
662 binfo->initrd_start + binfo->initrd_size);
663 if (rc < 0) {
664 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
665 goto fail;
666 }
667 }
668
669 fdt_add_psci_node(fdt);
670
671 if (binfo->modify_dtb) {
672 binfo->modify_dtb(binfo, fdt);
673 }
674
675 qemu_fdt_dumpdtb(fdt, size);
676
677 /* Put the DTB into the memory map as a ROM image: this will ensure
678 * the DTB is copied again upon reset, even if addr points into RAM.
679 */
680 rom_add_blob_fixed_as("dtb", fdt, size, addr, as);
681
682 g_free(fdt);
683
684 return size;
685
686 fail:
687 g_free(fdt);
688 return -1;
689 }
690
691 static void do_cpu_reset(void *opaque)
692 {
693 ARMCPU *cpu = opaque;
694 CPUState *cs = CPU(cpu);
695 CPUARMState *env = &cpu->env;
696 const struct arm_boot_info *info = env->boot_info;
697
698 cpu_reset(cs);
699 if (info) {
700 if (!info->is_linux) {
701 int i;
702 /* Jump to the entry point. */
703 uint64_t entry = info->entry;
704
705 switch (info->endianness) {
706 case ARM_ENDIANNESS_LE:
707 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
708 for (i = 1; i < 4; ++i) {
709 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
710 }
711 env->uncached_cpsr &= ~CPSR_E;
712 break;
713 case ARM_ENDIANNESS_BE8:
714 env->cp15.sctlr_el[1] |= SCTLR_E0E;
715 for (i = 1; i < 4; ++i) {
716 env->cp15.sctlr_el[i] |= SCTLR_EE;
717 }
718 env->uncached_cpsr |= CPSR_E;
719 break;
720 case ARM_ENDIANNESS_BE32:
721 env->cp15.sctlr_el[1] |= SCTLR_B;
722 break;
723 case ARM_ENDIANNESS_UNKNOWN:
724 break; /* Board's decision */
725 default:
726 g_assert_not_reached();
727 }
728
729 cpu_set_pc(cs, entry);
730 } else {
731 /* If we are booting Linux then we need to check whether we are
732 * booting into secure or non-secure state and adjust the state
733 * accordingly. Out of reset, ARM is defined to be in secure state
734 * (SCR.NS = 0), we change that here if non-secure boot has been
735 * requested.
736 */
737 if (arm_feature(env, ARM_FEATURE_EL3)) {
738 /* AArch64 is defined to come out of reset into EL3 if enabled.
739 * If we are booting Linux then we need to adjust our EL as
740 * Linux expects us to be in EL2 or EL1. AArch32 resets into
741 * SVC, which Linux expects, so no privilege/exception level to
742 * adjust.
743 */
744 if (env->aarch64) {
745 env->cp15.scr_el3 |= SCR_RW;
746 if (arm_feature(env, ARM_FEATURE_EL2)) {
747 env->cp15.hcr_el2 |= HCR_RW;
748 env->pstate = PSTATE_MODE_EL2h;
749 } else {
750 env->pstate = PSTATE_MODE_EL1h;
751 }
752 if (cpu_isar_feature(aa64_pauth, cpu)) {
753 env->cp15.scr_el3 |= SCR_API | SCR_APK;
754 }
755 if (cpu_isar_feature(aa64_mte, cpu)) {
756 env->cp15.scr_el3 |= SCR_ATA;
757 }
758 if (cpu_isar_feature(aa64_sve, cpu)) {
759 env->cp15.cptr_el[3] |= CPTR_EZ;
760 }
761 /* AArch64 kernels never boot in secure mode */
762 assert(!info->secure_boot);
763 /* This hook is only supported for AArch32 currently:
764 * bootloader_aarch64[] will not call the hook, and
765 * the code above has already dropped us into EL2 or EL1.
766 */
767 assert(!info->secure_board_setup);
768 }
769
770 if (arm_feature(env, ARM_FEATURE_EL2)) {
771 /* If we have EL2 then Linux expects the HVC insn to work */
772 env->cp15.scr_el3 |= SCR_HCE;
773 }
774
775 /* Set to non-secure if not a secure boot */
776 if (!info->secure_boot &&
777 (cs != first_cpu || !info->secure_board_setup)) {
778 /* Linux expects non-secure state */
779 env->cp15.scr_el3 |= SCR_NS;
780 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
781 env->cp15.nsacr |= 3 << 10;
782 }
783 }
784
785 if (!env->aarch64 && !info->secure_boot &&
786 arm_feature(env, ARM_FEATURE_EL2)) {
787 /*
788 * This is an AArch32 boot not to Secure state, and
789 * we have Hyp mode available, so boot the kernel into
790 * Hyp mode. This is not how the CPU comes out of reset,
791 * so we need to manually put it there.
792 */
793 cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
794 }
795
796 if (cs == first_cpu) {
797 AddressSpace *as = arm_boot_address_space(cpu, info);
798
799 cpu_set_pc(cs, info->loader_start);
800
801 if (!have_dtb(info)) {
802 if (old_param) {
803 set_kernel_args_old(info, as);
804 } else {
805 set_kernel_args(info, as);
806 }
807 }
808 } else {
809 info->secondary_cpu_reset_hook(cpu, info);
810 }
811 }
812 arm_rebuild_hflags(env);
813 }
814 }
815
816 /**
817 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
818 * by key.
819 * @fw_cfg: The firmware config instance to store the data in.
820 * @size_key: The firmware config key to store the size of the loaded
821 * data under, with fw_cfg_add_i32().
822 * @data_key: The firmware config key to store the loaded data under,
823 * with fw_cfg_add_bytes().
824 * @image_name: The name of the image file to load. If it is NULL, the
825 * function returns without doing anything.
826 * @try_decompress: Whether the image should be decompressed (gunzipped) before
827 * adding it to fw_cfg. If decompression fails, the image is
828 * loaded as-is.
829 *
830 * In case of failure, the function prints an error message to stderr and the
831 * process exits with status 1.
832 */
833 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
834 uint16_t data_key, const char *image_name,
835 bool try_decompress)
836 {
837 size_t size = -1;
838 uint8_t *data;
839
840 if (image_name == NULL) {
841 return;
842 }
843
844 if (try_decompress) {
845 size = load_image_gzipped_buffer(image_name,
846 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
847 }
848
849 if (size == (size_t)-1) {
850 gchar *contents;
851 gsize length;
852
853 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
854 error_report("failed to load \"%s\"", image_name);
855 exit(1);
856 }
857 size = length;
858 data = (uint8_t *)contents;
859 }
860
861 fw_cfg_add_i32(fw_cfg, size_key, size);
862 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
863 }
864
865 static int do_arm_linux_init(Object *obj, void *opaque)
866 {
867 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
868 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
869 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
870 struct arm_boot_info *info = opaque;
871
872 if (albifc->arm_linux_init) {
873 albifc->arm_linux_init(albif, info->secure_boot);
874 }
875 }
876 return 0;
877 }
878
879 static int64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
880 uint64_t *lowaddr, uint64_t *highaddr,
881 int elf_machine, AddressSpace *as)
882 {
883 bool elf_is64;
884 union {
885 Elf32_Ehdr h32;
886 Elf64_Ehdr h64;
887 } elf_header;
888 int data_swab = 0;
889 bool big_endian;
890 int64_t ret = -1;
891 Error *err = NULL;
892
893
894 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
895 if (err) {
896 error_free(err);
897 return ret;
898 }
899
900 if (elf_is64) {
901 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
902 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
903 : ARM_ENDIANNESS_LE;
904 } else {
905 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
906 if (big_endian) {
907 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
908 info->endianness = ARM_ENDIANNESS_BE8;
909 } else {
910 info->endianness = ARM_ENDIANNESS_BE32;
911 /* In BE32, the CPU has a different view of the per-byte
912 * address map than the rest of the system. BE32 ELF files
913 * are organised such that they can be programmed through
914 * the CPU's per-word byte-reversed view of the world. QEMU
915 * however loads ELF files independently of the CPU. So
916 * tell the ELF loader to byte reverse the data for us.
917 */
918 data_swab = 2;
919 }
920 } else {
921 info->endianness = ARM_ENDIANNESS_LE;
922 }
923 }
924
925 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL,
926 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine,
927 1, data_swab, as);
928 if (ret <= 0) {
929 /* The header loaded but the image didn't */
930 exit(1);
931 }
932
933 return ret;
934 }
935
936 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
937 hwaddr *entry, AddressSpace *as)
938 {
939 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
940 uint64_t kernel_size = 0;
941 uint8_t *buffer;
942 int size;
943
944 /* On aarch64, it's the bootloader's job to uncompress the kernel. */
945 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
946 &buffer);
947
948 if (size < 0) {
949 gsize len;
950
951 /* Load as raw file otherwise */
952 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
953 return -1;
954 }
955 size = len;
956 }
957
958 /* check the arm64 magic header value -- very old kernels may not have it */
959 if (size > ARM64_MAGIC_OFFSET + 4 &&
960 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
961 uint64_t hdrvals[2];
962
963 /* The arm64 Image header has text_offset and image_size fields at 8 and
964 * 16 bytes into the Image header, respectively. The text_offset field
965 * is only valid if the image_size is non-zero.
966 */
967 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
968
969 kernel_size = le64_to_cpu(hdrvals[1]);
970
971 if (kernel_size != 0) {
972 kernel_load_offset = le64_to_cpu(hdrvals[0]);
973
974 /*
975 * We write our startup "bootloader" at the very bottom of RAM,
976 * so that bit can't be used for the image. Luckily the Image
977 * format specification is that the image requests only an offset
978 * from a 2MB boundary, not an absolute load address. So if the
979 * image requests an offset that might mean it overlaps with the
980 * bootloader, we can just load it starting at 2MB+offset rather
981 * than 0MB + offset.
982 */
983 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
984 kernel_load_offset += 2 * MiB;
985 }
986 }
987 }
988
989 /*
990 * Kernels before v3.17 don't populate the image_size field, and
991 * raw images have no header. For those our best guess at the size
992 * is the size of the Image file itself.
993 */
994 if (kernel_size == 0) {
995 kernel_size = size;
996 }
997
998 *entry = mem_base + kernel_load_offset;
999 rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
1000
1001 g_free(buffer);
1002
1003 return kernel_size;
1004 }
1005
1006 static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
1007 struct arm_boot_info *info)
1008 {
1009 /* Set up for a direct boot of a kernel image file. */
1010 CPUState *cs;
1011 AddressSpace *as = arm_boot_address_space(cpu, info);
1012 int kernel_size;
1013 int initrd_size;
1014 int is_linux = 0;
1015 uint64_t elf_entry;
1016 /* Addresses of first byte used and first byte not used by the image */
1017 uint64_t image_low_addr = 0, image_high_addr = 0;
1018 int elf_machine;
1019 hwaddr entry;
1020 static const ARMInsnFixup *primary_loader;
1021 uint64_t ram_end = info->loader_start + info->ram_size;
1022
1023 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1024 primary_loader = bootloader_aarch64;
1025 elf_machine = EM_AARCH64;
1026 } else {
1027 primary_loader = bootloader;
1028 if (!info->write_board_setup) {
1029 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
1030 }
1031 elf_machine = EM_ARM;
1032 }
1033
1034 if (!info->secondary_cpu_reset_hook) {
1035 info->secondary_cpu_reset_hook = default_reset_secondary;
1036 }
1037 if (!info->write_secondary_boot) {
1038 info->write_secondary_boot = default_write_secondary;
1039 }
1040
1041 if (info->nb_cpus == 0)
1042 info->nb_cpus = 1;
1043
1044 /* Assume that raw images are linux kernels, and ELF images are not. */
1045 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr,
1046 &image_high_addr, elf_machine, as);
1047 if (kernel_size > 0 && have_dtb(info)) {
1048 /*
1049 * If there is still some room left at the base of RAM, try and put
1050 * the DTB there like we do for images loaded with -bios or -pflash.
1051 */
1052 if (image_low_addr > info->loader_start
1053 || image_high_addr < info->loader_start) {
1054 /*
1055 * Set image_low_addr as address limit for arm_load_dtb if it may be
1056 * pointing into RAM, otherwise pass '0' (no limit)
1057 */
1058 if (image_low_addr < info->loader_start) {
1059 image_low_addr = 0;
1060 }
1061 info->dtb_start = info->loader_start;
1062 info->dtb_limit = image_low_addr;
1063 }
1064 }
1065 entry = elf_entry;
1066 if (kernel_size < 0) {
1067 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR;
1068 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr,
1069 &is_linux, NULL, NULL, as);
1070 if (kernel_size >= 0) {
1071 image_low_addr = loadaddr;
1072 image_high_addr = image_low_addr + kernel_size;
1073 }
1074 }
1075 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
1076 kernel_size = load_aarch64_image(info->kernel_filename,
1077 info->loader_start, &entry, as);
1078 is_linux = 1;
1079 if (kernel_size >= 0) {
1080 image_low_addr = entry;
1081 image_high_addr = image_low_addr + kernel_size;
1082 }
1083 } else if (kernel_size < 0) {
1084 /* 32-bit ARM */
1085 entry = info->loader_start + KERNEL_LOAD_ADDR;
1086 kernel_size = load_image_targphys_as(info->kernel_filename, entry,
1087 ram_end - KERNEL_LOAD_ADDR, as);
1088 is_linux = 1;
1089 if (kernel_size >= 0) {
1090 image_low_addr = entry;
1091 image_high_addr = image_low_addr + kernel_size;
1092 }
1093 }
1094 if (kernel_size < 0) {
1095 error_report("could not load kernel '%s'", info->kernel_filename);
1096 exit(1);
1097 }
1098
1099 if (kernel_size > info->ram_size) {
1100 error_report("kernel '%s' is too large to fit in RAM "
1101 "(kernel size %d, RAM size %" PRId64 ")",
1102 info->kernel_filename, kernel_size, info->ram_size);
1103 exit(1);
1104 }
1105
1106 info->entry = entry;
1107
1108 /*
1109 * We want to put the initrd far enough into RAM that when the
1110 * kernel is uncompressed it will not clobber the initrd. However
1111 * on boards without much RAM we must ensure that we still leave
1112 * enough room for a decent sized initrd, and on boards with large
1113 * amounts of RAM we must avoid the initrd being so far up in RAM
1114 * that it is outside lowmem and inaccessible to the kernel.
1115 * So for boards with less than 256MB of RAM we put the initrd
1116 * halfway into RAM, and for boards with 256MB of RAM or more we put
1117 * the initrd at 128MB.
1118 * We also refuse to put the initrd somewhere that will definitely
1119 * overlay the kernel we just loaded, though for kernel formats which
1120 * don't tell us their exact size (eg self-decompressing 32-bit kernels)
1121 * we might still make a bad choice here.
1122 */
1123 info->initrd_start = info->loader_start +
1124 MIN(info->ram_size / 2, 128 * MiB);
1125 if (image_high_addr) {
1126 info->initrd_start = MAX(info->initrd_start, image_high_addr);
1127 }
1128 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
1129
1130 if (is_linux) {
1131 uint32_t fixupcontext[FIXUP_MAX];
1132
1133 if (info->initrd_filename) {
1134
1135 if (info->initrd_start >= ram_end) {
1136 error_report("not enough space after kernel to load initrd");
1137 exit(1);
1138 }
1139
1140 initrd_size = load_ramdisk_as(info->initrd_filename,
1141 info->initrd_start,
1142 ram_end - info->initrd_start, as);
1143 if (initrd_size < 0) {
1144 initrd_size = load_image_targphys_as(info->initrd_filename,
1145 info->initrd_start,
1146 ram_end -
1147 info->initrd_start,
1148 as);
1149 }
1150 if (initrd_size < 0) {
1151 error_report("could not load initrd '%s'",
1152 info->initrd_filename);
1153 exit(1);
1154 }
1155 if (info->initrd_start + initrd_size > ram_end) {
1156 error_report("could not load initrd '%s': "
1157 "too big to fit into RAM after the kernel",
1158 info->initrd_filename);
1159 exit(1);
1160 }
1161 } else {
1162 initrd_size = 0;
1163 }
1164 info->initrd_size = initrd_size;
1165
1166 fixupcontext[FIXUP_BOARDID] = info->board_id;
1167 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
1168
1169 /*
1170 * for device tree boot, we pass the DTB directly in r2. Otherwise
1171 * we point to the kernel args.
1172 */
1173 if (have_dtb(info)) {
1174 hwaddr align;
1175
1176 if (elf_machine == EM_AARCH64) {
1177 /*
1178 * Some AArch64 kernels on early bootup map the fdt region as
1179 *
1180 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]
1181 *
1182 * Let's play safe and prealign it to 2MB to give us some space.
1183 */
1184 align = 2 * MiB;
1185 } else {
1186 /*
1187 * Some 32bit kernels will trash anything in the 4K page the
1188 * initrd ends in, so make sure the DTB isn't caught up in that.
1189 */
1190 align = 4 * KiB;
1191 }
1192
1193 /* Place the DTB after the initrd in memory with alignment. */
1194 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
1195 align);
1196 if (info->dtb_start >= ram_end) {
1197 error_report("Not enough space for DTB after kernel/initrd");
1198 exit(1);
1199 }
1200 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
1201 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
1202 } else {
1203 fixupcontext[FIXUP_ARGPTR_LO] =
1204 info->loader_start + KERNEL_ARGS_ADDR;
1205 fixupcontext[FIXUP_ARGPTR_HI] =
1206 (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
1207 if (info->ram_size >= 4 * GiB) {
1208 error_report("RAM size must be less than 4GB to boot"
1209 " Linux kernel using ATAGS (try passing a device tree"
1210 " using -dtb)");
1211 exit(1);
1212 }
1213 }
1214 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
1215 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
1216
1217 write_bootloader("bootloader", info->loader_start,
1218 primary_loader, fixupcontext, as);
1219
1220 if (info->nb_cpus > 1) {
1221 info->write_secondary_boot(cpu, info);
1222 }
1223 if (info->write_board_setup) {
1224 info->write_board_setup(cpu, info);
1225 }
1226
1227 /*
1228 * Notify devices which need to fake up firmware initialization
1229 * that we're doing a direct kernel boot.
1230 */
1231 object_child_foreach_recursive(object_get_root(),
1232 do_arm_linux_init, info);
1233 }
1234 info->is_linux = is_linux;
1235
1236 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1237 ARM_CPU(cs)->env.boot_info = info;
1238 }
1239 }
1240
1241 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info)
1242 {
1243 /* Set up for booting firmware (which might load a kernel via fw_cfg) */
1244
1245 if (have_dtb(info)) {
1246 /*
1247 * If we have a device tree blob, but no kernel to supply it to (or
1248 * the kernel is supposed to be loaded by the bootloader), copy the
1249 * DTB to the base of RAM for the bootloader to pick up.
1250 */
1251 info->dtb_start = info->loader_start;
1252 }
1253
1254 if (info->kernel_filename) {
1255 FWCfgState *fw_cfg;
1256 bool try_decompressing_kernel;
1257
1258 fw_cfg = fw_cfg_find();
1259
1260 if (!fw_cfg) {
1261 error_report("This machine type does not support loading both "
1262 "a guest firmware/BIOS image and a guest kernel at "
1263 "the same time. You should change your QEMU command "
1264 "line to specify one or the other, but not both.");
1265 exit(1);
1266 }
1267
1268 try_decompressing_kernel = arm_feature(&cpu->env,
1269 ARM_FEATURE_AARCH64);
1270
1271 /*
1272 * Expose the kernel, the command line, and the initrd in fw_cfg.
1273 * We don't process them here at all, it's all left to the
1274 * firmware.
1275 */
1276 load_image_to_fw_cfg(fw_cfg,
1277 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
1278 info->kernel_filename,
1279 try_decompressing_kernel);
1280 load_image_to_fw_cfg(fw_cfg,
1281 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
1282 info->initrd_filename, false);
1283
1284 if (info->kernel_cmdline) {
1285 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1286 strlen(info->kernel_cmdline) + 1);
1287 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
1288 info->kernel_cmdline);
1289 }
1290 }
1291
1292 /*
1293 * We will start from address 0 (typically a boot ROM image) in the
1294 * same way as hardware. Leave env->boot_info NULL, so that
1295 * do_cpu_reset() knows it does not need to alter the PC on reset.
1296 */
1297 }
1298
1299 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
1300 {
1301 CPUState *cs;
1302 AddressSpace *as = arm_boot_address_space(cpu, info);
1303
1304 /*
1305 * CPU objects (unlike devices) are not automatically reset on system
1306 * reset, so we must always register a handler to do so. If we're
1307 * actually loading a kernel, the handler is also responsible for
1308 * arranging that we start it correctly.
1309 */
1310 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1311 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1312 }
1313
1314 /*
1315 * The board code is not supposed to set secure_board_setup unless
1316 * running its code in secure mode is actually possible, and KVM
1317 * doesn't support secure.
1318 */
1319 assert(!(info->secure_board_setup && kvm_enabled()));
1320 info->kernel_filename = ms->kernel_filename;
1321 info->kernel_cmdline = ms->kernel_cmdline;
1322 info->initrd_filename = ms->initrd_filename;
1323 info->dtb_filename = ms->dtb;
1324 info->dtb_limit = 0;
1325
1326 /* Load the kernel. */
1327 if (!info->kernel_filename || info->firmware_loaded) {
1328 arm_setup_firmware_boot(cpu, info);
1329 } else {
1330 arm_setup_direct_kernel_boot(cpu, info);
1331 }
1332
1333 if (!info->skip_dtb_autoload && have_dtb(info)) {
1334 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1335 exit(1);
1336 }
1337 }
1338 }
1339
1340 static const TypeInfo arm_linux_boot_if_info = {
1341 .name = TYPE_ARM_LINUX_BOOT_IF,
1342 .parent = TYPE_INTERFACE,
1343 .class_size = sizeof(ARMLinuxBootIfClass),
1344 };
1345
1346 static void arm_linux_boot_register_types(void)
1347 {
1348 type_register_static(&arm_linux_boot_if_info);
1349 }
1350
1351 type_init(arm_linux_boot_register_types)