arm/{bcm2835,fsl-imx25,fsl-imx6}: Fix realize error API violations
[qemu.git] / hw / arm / fsl-imx6.c
1 /*
2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/usb/imx-usb-phy.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29 #include "chardev/char.h"
30 #include "qemu/error-report.h"
31 #include "qemu/module.h"
32
33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
34
35 #define NAME_SIZE 20
36
37 static void fsl_imx6_init(Object *obj)
38 {
39 MachineState *ms = MACHINE(qdev_get_machine());
40 FslIMX6State *s = FSL_IMX6(obj);
41 char name[NAME_SIZE];
42 int i;
43
44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
45 snprintf(name, NAME_SIZE, "cpu%d", i);
46 object_initialize_child(obj, name, &s->cpu[i],
47 ARM_CPU_TYPE_NAME("cortex-a9"));
48 }
49
50 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
51
52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
53
54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
55
56 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
57 snprintf(name, NAME_SIZE, "uart%d", i + 1);
58 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
59 }
60
61 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
62
63 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
64 snprintf(name, NAME_SIZE, "epit%d", i + 1);
65 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
66 }
67
68 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
69 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
70 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
71 }
72
73 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
74 snprintf(name, NAME_SIZE, "gpio%d", i + 1);
75 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
76 }
77
78 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
79 snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
80 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
81 }
82
83 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
84 snprintf(name, NAME_SIZE, "usbphy%d", i);
85 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
86 }
87 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
88 snprintf(name, NAME_SIZE, "usb%d", i);
89 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
90 }
91
92 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
93 snprintf(name, NAME_SIZE, "spi%d", i + 1);
94 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
95 }
96 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
97 snprintf(name, NAME_SIZE, "wdt%d", i);
98 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
99 }
100
101
102 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
103 }
104
105 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
106 {
107 MachineState *ms = MACHINE(qdev_get_machine());
108 FslIMX6State *s = FSL_IMX6(dev);
109 uint16_t i;
110 Error *err = NULL;
111 unsigned int smp_cpus = ms->smp.cpus;
112
113 if (smp_cpus > FSL_IMX6_NUM_CPUS) {
114 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
115 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
116 return;
117 }
118
119 for (i = 0; i < smp_cpus; i++) {
120
121 /* On uniprocessor, the CBAR is set to 0 */
122 if (smp_cpus > 1) {
123 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
124 "reset-cbar", &error_abort);
125 }
126
127 /* All CPU but CPU 0 start in power off mode */
128 if (i) {
129 object_property_set_bool(OBJECT(&s->cpu[i]), true,
130 "start-powered-off", &error_abort);
131 }
132
133 qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
134 if (err) {
135 error_propagate(errp, err);
136 return;
137 }
138 }
139
140 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
141 &error_abort);
142
143 object_property_set_int(OBJECT(&s->a9mpcore),
144 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
145 &error_abort);
146
147 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err);
148 if (err) {
149 error_propagate(errp, err);
150 return;
151 }
152 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
153
154 for (i = 0; i < smp_cpus; i++) {
155 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
156 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
157 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
158 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
159 }
160
161 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
162 if (err) {
163 error_propagate(errp, err);
164 return;
165 }
166 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
167
168 sysbus_realize(SYS_BUS_DEVICE(&s->src), &err);
169 if (err) {
170 error_propagate(errp, err);
171 return;
172 }
173 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
174
175 /* Initialize all UARTs */
176 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
177 static const struct {
178 hwaddr addr;
179 unsigned int irq;
180 } serial_table[FSL_IMX6_NUM_UARTS] = {
181 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
182 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
183 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
184 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
185 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
186 };
187
188 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
189
190 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
191 if (err) {
192 error_propagate(errp, err);
193 return;
194 }
195
196 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
197 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
198 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
199 serial_table[i].irq));
200 }
201
202 s->gpt.ccm = IMX_CCM(&s->ccm);
203
204 sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err);
205 if (err) {
206 error_propagate(errp, err);
207 return;
208 }
209
210 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
211 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
212 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
213 FSL_IMX6_GPT_IRQ));
214
215 /* Initialize all EPIT timers */
216 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
217 static const struct {
218 hwaddr addr;
219 unsigned int irq;
220 } epit_table[FSL_IMX6_NUM_EPITS] = {
221 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
222 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
223 };
224
225 s->epit[i].ccm = IMX_CCM(&s->ccm);
226
227 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
228 if (err) {
229 error_propagate(errp, err);
230 return;
231 }
232
233 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
234 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
235 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
236 epit_table[i].irq));
237 }
238
239 /* Initialize all I2C */
240 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
241 static const struct {
242 hwaddr addr;
243 unsigned int irq;
244 } i2c_table[FSL_IMX6_NUM_I2CS] = {
245 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
246 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
247 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
248 };
249
250 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
251 if (err) {
252 error_propagate(errp, err);
253 return;
254 }
255
256 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
257 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
258 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
259 i2c_table[i].irq));
260 }
261
262 /* Initialize all GPIOs */
263 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
264 static const struct {
265 hwaddr addr;
266 unsigned int irq_low;
267 unsigned int irq_high;
268 } gpio_table[FSL_IMX6_NUM_GPIOS] = {
269 {
270 FSL_IMX6_GPIO1_ADDR,
271 FSL_IMX6_GPIO1_LOW_IRQ,
272 FSL_IMX6_GPIO1_HIGH_IRQ
273 },
274 {
275 FSL_IMX6_GPIO2_ADDR,
276 FSL_IMX6_GPIO2_LOW_IRQ,
277 FSL_IMX6_GPIO2_HIGH_IRQ
278 },
279 {
280 FSL_IMX6_GPIO3_ADDR,
281 FSL_IMX6_GPIO3_LOW_IRQ,
282 FSL_IMX6_GPIO3_HIGH_IRQ
283 },
284 {
285 FSL_IMX6_GPIO4_ADDR,
286 FSL_IMX6_GPIO4_LOW_IRQ,
287 FSL_IMX6_GPIO4_HIGH_IRQ
288 },
289 {
290 FSL_IMX6_GPIO5_ADDR,
291 FSL_IMX6_GPIO5_LOW_IRQ,
292 FSL_IMX6_GPIO5_HIGH_IRQ
293 },
294 {
295 FSL_IMX6_GPIO6_ADDR,
296 FSL_IMX6_GPIO6_LOW_IRQ,
297 FSL_IMX6_GPIO6_HIGH_IRQ
298 },
299 {
300 FSL_IMX6_GPIO7_ADDR,
301 FSL_IMX6_GPIO7_LOW_IRQ,
302 FSL_IMX6_GPIO7_HIGH_IRQ
303 },
304 };
305
306 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
307 &error_abort);
308 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
309 &error_abort);
310 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
311 if (err) {
312 error_propagate(errp, err);
313 return;
314 }
315
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
317 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
318 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
319 gpio_table[i].irq_low));
320 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
321 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
322 gpio_table[i].irq_high));
323 }
324
325 /* Initialize all SDHC */
326 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
327 static const struct {
328 hwaddr addr;
329 unsigned int irq;
330 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
331 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
332 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
333 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
334 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
335 };
336
337 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
338 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
339 &error_abort);
340 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
341 "capareg",
342 &error_abort);
343 object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX,
344 "vendor",
345 &error_abort);
346 sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
347 if (err) {
348 error_propagate(errp, err);
349 return;
350 }
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
352 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
353 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
354 esdhc_table[i].irq));
355 }
356
357 /* USB */
358 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
359 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
361 FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
362 }
363 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
364 static const int FSL_IMX6_USBn_IRQ[] = {
365 FSL_IMX6_USB_OTG_IRQ,
366 FSL_IMX6_USB_HOST1_IRQ,
367 FSL_IMX6_USB_HOST2_IRQ,
368 FSL_IMX6_USB_HOST3_IRQ,
369 };
370
371 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
372 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
373 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
374 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
375 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
376 FSL_IMX6_USBn_IRQ[i]));
377 }
378
379 /* Initialize all ECSPI */
380 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
381 static const struct {
382 hwaddr addr;
383 unsigned int irq;
384 } spi_table[FSL_IMX6_NUM_ECSPIS] = {
385 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
386 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
387 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
388 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
389 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
390 };
391
392 /* Initialize the SPI */
393 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
394 if (err) {
395 error_propagate(errp, err);
396 return;
397 }
398
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
401 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
402 spi_table[i].irq));
403 }
404
405 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
406 sysbus_realize(SYS_BUS_DEVICE(&s->eth), &err);
407 if (err) {
408 error_propagate(errp, err);
409 return;
410 }
411 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
413 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
414 FSL_IMX6_ENET_MAC_IRQ));
415 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
416 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
417 FSL_IMX6_ENET_MAC_1588_IRQ));
418
419 /*
420 * Watchdog
421 */
422 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
423 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
424 FSL_IMX6_WDOG1_ADDR,
425 FSL_IMX6_WDOG2_ADDR,
426 };
427 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
428 FSL_IMX6_WDOG1_IRQ,
429 FSL_IMX6_WDOG2_IRQ,
430 };
431
432 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support",
433 &error_abort);
434 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
435
436 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
437 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
438 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
439 FSL_IMX6_WDOGn_IRQ[i]));
440 }
441
442 /* ROM memory */
443 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
444 FSL_IMX6_ROM_SIZE, &err);
445 if (err) {
446 error_propagate(errp, err);
447 return;
448 }
449 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
450 &s->rom);
451
452 /* CAAM memory */
453 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
454 FSL_IMX6_CAAM_MEM_SIZE, &err);
455 if (err) {
456 error_propagate(errp, err);
457 return;
458 }
459 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
460 &s->caam);
461
462 /* OCRAM memory */
463 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
464 &err);
465 if (err) {
466 error_propagate(errp, err);
467 return;
468 }
469 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
470 &s->ocram);
471
472 /* internal OCRAM (256 KB) is aliased over 1 MB */
473 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
474 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
475 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
476 &s->ocram_alias);
477 }
478
479 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
480 {
481 DeviceClass *dc = DEVICE_CLASS(oc);
482
483 dc->realize = fsl_imx6_realize;
484 dc->desc = "i.MX6 SOC";
485 /* Reason: Uses serial_hd() in the realize() function */
486 dc->user_creatable = false;
487 }
488
489 static const TypeInfo fsl_imx6_type_info = {
490 .name = TYPE_FSL_IMX6,
491 .parent = TYPE_DEVICE,
492 .instance_size = sizeof(FslIMX6State),
493 .instance_init = fsl_imx6_init,
494 .class_init = fsl_imx6_class_init,
495 };
496
497 static void fsl_imx6_register_types(void)
498 {
499 type_register_static(&fsl_imx6_type_info);
500 }
501
502 type_init(fsl_imx6_register_types)