Update version for v6.2.0-rc3 release
[qemu.git] / hw / arm / highbank.c
1 /*
2 * Calxeda Highbank SoC emulation
3 *
4 * Copyright (c) 2010-2012 Calxeda
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qapi/error.h"
24 #include "hw/sysbus.h"
25 #include "migration/vmstate.h"
26 #include "hw/arm/boot.h"
27 #include "hw/loader.h"
28 #include "net/net.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/boards.h"
32 #include "qemu/error-report.h"
33 #include "hw/char/pl011.h"
34 #include "hw/ide/ahci.h"
35 #include "hw/cpu/a9mpcore.h"
36 #include "hw/cpu/a15mpcore.h"
37 #include "qemu/log.h"
38 #include "qom/object.h"
39 #include "cpu.h"
40
41 #define SMP_BOOT_ADDR 0x100
42 #define SMP_BOOT_REG 0x40
43 #define MPCORE_PERIPHBASE 0xfff10000
44
45 #define MVBAR_ADDR 0x200
46 #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
47
48 #define NIRQ_GIC 160
49
50 /* Board init. */
51
52 static void hb_write_board_setup(ARMCPU *cpu,
53 const struct arm_boot_info *info)
54 {
55 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
56 }
57
58 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
59 {
60 int n;
61 uint32_t smpboot[] = {
62 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
63 0xe210000f, /* ands r0, r0, #0x0f */
64 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
65 0xe0830200, /* add r0, r3, r0, lsl #4 */
66 0xe59f2024, /* ldr r2, privbase */
67 0xe3a01001, /* mov r1, #1 */
68 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
69 0xe3a010ff, /* mov r1, #0xff */
70 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
71 0xf57ff04f, /* dsb */
72 0xe320f003, /* wfi */
73 0xe5901000, /* ldr r1, [r0] */
74 0xe1110001, /* tst r1, r1 */
75 0x0afffffb, /* beq <wfi> */
76 0xe12fff11, /* bx r1 */
77 MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
78 };
79 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
80 smpboot[n] = tswap32(smpboot[n]);
81 }
82 rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,
83 arm_boot_address_space(cpu, info));
84 }
85
86 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
87 {
88 CPUARMState *env = &cpu->env;
89
90 switch (info->nb_cpus) {
91 case 4:
92 address_space_stl_notdirty(&address_space_memory,
93 SMP_BOOT_REG + 0x30, 0,
94 MEMTXATTRS_UNSPECIFIED, NULL);
95 /* fallthrough */
96 case 3:
97 address_space_stl_notdirty(&address_space_memory,
98 SMP_BOOT_REG + 0x20, 0,
99 MEMTXATTRS_UNSPECIFIED, NULL);
100 /* fallthrough */
101 case 2:
102 address_space_stl_notdirty(&address_space_memory,
103 SMP_BOOT_REG + 0x10, 0,
104 MEMTXATTRS_UNSPECIFIED, NULL);
105 env->regs[15] = SMP_BOOT_ADDR;
106 break;
107 default:
108 break;
109 }
110 }
111
112 #define NUM_REGS 0x200
113 static void hb_regs_write(void *opaque, hwaddr offset,
114 uint64_t value, unsigned size)
115 {
116 uint32_t *regs = opaque;
117
118 if (offset == 0xf00) {
119 if (value == 1 || value == 2) {
120 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
121 } else if (value == 3) {
122 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
123 }
124 }
125
126 if (offset / 4 >= NUM_REGS) {
127 qemu_log_mask(LOG_GUEST_ERROR,
128 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
129 return;
130 }
131 regs[offset / 4] = value;
132 }
133
134 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
135 unsigned size)
136 {
137 uint32_t value;
138 uint32_t *regs = opaque;
139
140 if (offset / 4 >= NUM_REGS) {
141 qemu_log_mask(LOG_GUEST_ERROR,
142 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
143 return 0;
144 }
145 value = regs[offset / 4];
146
147 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
148 value |= 0x30000000;
149 }
150
151 return value;
152 }
153
154 static const MemoryRegionOps hb_mem_ops = {
155 .read = hb_regs_read,
156 .write = hb_regs_write,
157 .endianness = DEVICE_NATIVE_ENDIAN,
158 };
159
160 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
161 OBJECT_DECLARE_SIMPLE_TYPE(HighbankRegsState, HIGHBANK_REGISTERS)
162
163 struct HighbankRegsState {
164 /*< private >*/
165 SysBusDevice parent_obj;
166 /*< public >*/
167
168 MemoryRegion iomem;
169 uint32_t regs[NUM_REGS];
170 };
171
172 static const VMStateDescription vmstate_highbank_regs = {
173 .name = "highbank-regs",
174 .version_id = 0,
175 .minimum_version_id = 0,
176 .fields = (VMStateField[]) {
177 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
178 VMSTATE_END_OF_LIST(),
179 },
180 };
181
182 static void highbank_regs_reset(DeviceState *dev)
183 {
184 HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
185
186 s->regs[0x40] = 0x05F20121;
187 s->regs[0x41] = 0x2;
188 s->regs[0x42] = 0x05F30121;
189 s->regs[0x43] = 0x05F40121;
190 }
191
192 static void highbank_regs_init(Object *obj)
193 {
194 HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
195 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
196
197 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
198 "highbank_regs", 0x1000);
199 sysbus_init_mmio(dev, &s->iomem);
200 }
201
202 static void highbank_regs_class_init(ObjectClass *klass, void *data)
203 {
204 DeviceClass *dc = DEVICE_CLASS(klass);
205
206 dc->desc = "Calxeda Highbank registers";
207 dc->vmsd = &vmstate_highbank_regs;
208 dc->reset = highbank_regs_reset;
209 }
210
211 static const TypeInfo highbank_regs_info = {
212 .name = TYPE_HIGHBANK_REGISTERS,
213 .parent = TYPE_SYS_BUS_DEVICE,
214 .instance_size = sizeof(HighbankRegsState),
215 .instance_init = highbank_regs_init,
216 .class_init = highbank_regs_class_init,
217 };
218
219 static void highbank_regs_register_types(void)
220 {
221 type_register_static(&highbank_regs_info);
222 }
223
224 type_init(highbank_regs_register_types)
225
226 static struct arm_boot_info highbank_binfo;
227
228 enum cxmachines {
229 CALXEDA_HIGHBANK,
230 CALXEDA_MIDWAY,
231 };
232
233 /* ram_size must be set to match the upper bound of memory in the
234 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
235 * normally 0xff900000 or -m 4089. When running this board on a
236 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
237 * device tree and pass -m 2047 to QEMU.
238 */
239 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
240 {
241 DeviceState *dev = NULL;
242 SysBusDevice *busdev;
243 qemu_irq pic[128];
244 int n;
245 unsigned int smp_cpus = machine->smp.cpus;
246 qemu_irq cpu_irq[4];
247 qemu_irq cpu_fiq[4];
248 qemu_irq cpu_virq[4];
249 qemu_irq cpu_vfiq[4];
250 MemoryRegion *sysram;
251 MemoryRegion *sysmem;
252 char *sysboot_filename;
253
254 switch (machine_id) {
255 case CALXEDA_HIGHBANK:
256 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
257 break;
258 case CALXEDA_MIDWAY:
259 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
260 break;
261 default:
262 assert(0);
263 }
264
265 for (n = 0; n < smp_cpus; n++) {
266 Object *cpuobj;
267 ARMCPU *cpu;
268
269 cpuobj = object_new(machine->cpu_type);
270 cpu = ARM_CPU(cpuobj);
271
272 object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC,
273 &error_abort);
274
275 if (n) {
276 /* Secondary CPUs start in PSCI powered-down state */
277 object_property_set_bool(cpuobj, "start-powered-off", true,
278 &error_abort);
279 }
280
281 if (object_property_find(cpuobj, "reset-cbar")) {
282 object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
283 &error_abort);
284 }
285 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
286 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
287 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
288 cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
289 cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
290 }
291
292 sysmem = get_system_memory();
293 /* SDRAM at address zero. */
294 memory_region_add_subregion(sysmem, 0, machine->ram);
295
296 sysram = g_new(MemoryRegion, 1);
297 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
298 &error_fatal);
299 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
300 if (machine->firmware != NULL) {
301 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
302 if (sysboot_filename != NULL) {
303 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
304 error_report("Unable to load %s", machine->firmware);
305 exit(1);
306 }
307 g_free(sysboot_filename);
308 } else {
309 error_report("Unable to find %s", machine->firmware);
310 exit(1);
311 }
312 }
313
314 switch (machine_id) {
315 case CALXEDA_HIGHBANK:
316 dev = qdev_new("l2x0");
317 busdev = SYS_BUS_DEVICE(dev);
318 sysbus_realize_and_unref(busdev, &error_fatal);
319 sysbus_mmio_map(busdev, 0, 0xfff12000);
320
321 dev = qdev_new(TYPE_A9MPCORE_PRIV);
322 break;
323 case CALXEDA_MIDWAY:
324 dev = qdev_new(TYPE_A15MPCORE_PRIV);
325 break;
326 }
327 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
328 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
329 busdev = SYS_BUS_DEVICE(dev);
330 sysbus_realize_and_unref(busdev, &error_fatal);
331 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
332 for (n = 0; n < smp_cpus; n++) {
333 sysbus_connect_irq(busdev, n, cpu_irq[n]);
334 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
335 sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
336 sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
337 }
338
339 for (n = 0; n < 128; n++) {
340 pic[n] = qdev_get_gpio_in(dev, n);
341 }
342
343 dev = qdev_new("sp804");
344 qdev_prop_set_uint32(dev, "freq0", 150000000);
345 qdev_prop_set_uint32(dev, "freq1", 150000000);
346 busdev = SYS_BUS_DEVICE(dev);
347 sysbus_realize_and_unref(busdev, &error_fatal);
348 sysbus_mmio_map(busdev, 0, 0xfff34000);
349 sysbus_connect_irq(busdev, 0, pic[18]);
350 pl011_create(0xfff36000, pic[20], serial_hd(0));
351
352 dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
353 busdev = SYS_BUS_DEVICE(dev);
354 sysbus_realize_and_unref(busdev, &error_fatal);
355 sysbus_mmio_map(busdev, 0, 0xfff3c000);
356
357 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
358 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
359 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
360 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
361 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
362 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
363
364 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
365
366 if (nd_table[0].used) {
367 qemu_check_nic_model(&nd_table[0], "xgmac");
368 dev = qdev_new("xgmac");
369 qdev_set_nic_properties(dev, &nd_table[0]);
370 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
371 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
372 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
373 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
374 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
375
376 qemu_check_nic_model(&nd_table[1], "xgmac");
377 dev = qdev_new("xgmac");
378 qdev_set_nic_properties(dev, &nd_table[1]);
379 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
380 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
381 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
382 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
383 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
384 }
385
386 /* TODO create and connect IDE devices for ide_drive_get() */
387
388 highbank_binfo.ram_size = machine->ram_size;
389 /* highbank requires a dtb in order to boot, and the dtb will override
390 * the board ID. The following value is ignored, so set it to -1 to be
391 * clear that the value is meaningless.
392 */
393 highbank_binfo.board_id = -1;
394 highbank_binfo.nb_cpus = smp_cpus;
395 highbank_binfo.loader_start = 0;
396 highbank_binfo.write_secondary_boot = hb_write_secondary;
397 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
398 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
399 highbank_binfo.write_board_setup = hb_write_board_setup;
400 highbank_binfo.secure_board_setup = true;
401
402 arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
403 }
404
405 static void highbank_init(MachineState *machine)
406 {
407 calxeda_init(machine, CALXEDA_HIGHBANK);
408 }
409
410 static void midway_init(MachineState *machine)
411 {
412 calxeda_init(machine, CALXEDA_MIDWAY);
413 }
414
415 static void highbank_class_init(ObjectClass *oc, void *data)
416 {
417 MachineClass *mc = MACHINE_CLASS(oc);
418
419 mc->desc = "Calxeda Highbank (ECX-1000)";
420 mc->init = highbank_init;
421 mc->block_default_type = IF_IDE;
422 mc->units_per_default_bus = 1;
423 mc->max_cpus = 4;
424 mc->ignore_memory_transaction_failures = true;
425 mc->default_ram_id = "highbank.dram";
426 }
427
428 static const TypeInfo highbank_type = {
429 .name = MACHINE_TYPE_NAME("highbank"),
430 .parent = TYPE_MACHINE,
431 .class_init = highbank_class_init,
432 };
433
434 static void midway_class_init(ObjectClass *oc, void *data)
435 {
436 MachineClass *mc = MACHINE_CLASS(oc);
437
438 mc->desc = "Calxeda Midway (ECX-2000)";
439 mc->init = midway_init;
440 mc->block_default_type = IF_IDE;
441 mc->units_per_default_bus = 1;
442 mc->max_cpus = 4;
443 mc->ignore_memory_transaction_failures = true;
444 mc->default_ram_id = "highbank.dram";
445 }
446
447 static const TypeInfo midway_type = {
448 .name = MACHINE_TYPE_NAME("midway"),
449 .parent = TYPE_MACHINE,
450 .class_init = midway_class_init,
451 };
452
453 static void calxeda_machines_init(void)
454 {
455 type_register_static(&highbank_type);
456 type_register_static(&midway_type);
457 }
458
459 type_init(calxeda_machines_init)