Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / arm / musca.c
1 /*
2 * Arm Musca-B1 test chip board emulation
3 *
4 * Copyright (c) 2019 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /*
13 * The Musca boards are a reference implementation of a system using
14 * the SSE-200 subsystem for embedded:
15 * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board
16 * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
17 * We model the A and B1 variants of this board, as described in the TRMs:
18 * http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/index.html
19 * http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/index.html
20 */
21
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/arm/boot.h"
28 #include "hw/arm/armsse.h"
29 #include "hw/boards.h"
30 #include "hw/char/pl011.h"
31 #include "hw/core/split-irq.h"
32 #include "hw/misc/tz-mpc.h"
33 #include "hw/misc/tz-ppc.h"
34 #include "hw/misc/unimp.h"
35 #include "hw/rtc/pl031.h"
36 #include "qom/object.h"
37
38 #define MUSCA_NUMIRQ_MAX 96
39 #define MUSCA_PPC_MAX 3
40 #define MUSCA_MPC_MAX 5
41
42 typedef struct MPCInfo MPCInfo;
43
44 typedef enum MuscaType {
45 MUSCA_A,
46 MUSCA_B1,
47 } MuscaType;
48
49 struct MuscaMachineClass {
50 MachineClass parent;
51 MuscaType type;
52 uint32_t init_svtor;
53 int sram_addr_width;
54 int num_irqs;
55 const MPCInfo *mpc_info;
56 int num_mpcs;
57 };
58
59 struct MuscaMachineState {
60 MachineState parent;
61
62 ARMSSE sse;
63 /* RAM and flash */
64 MemoryRegion ram[MUSCA_MPC_MAX];
65 SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX];
66 SplitIRQ sec_resp_splitter;
67 TZPPC ppc[MUSCA_PPC_MAX];
68 MemoryRegion container;
69 UnimplementedDeviceState eflash[2];
70 UnimplementedDeviceState qspi;
71 TZMPC mpc[MUSCA_MPC_MAX];
72 UnimplementedDeviceState mhu[2];
73 UnimplementedDeviceState pwm[3];
74 UnimplementedDeviceState i2s;
75 PL011State uart[2];
76 UnimplementedDeviceState i2c[2];
77 UnimplementedDeviceState spi;
78 UnimplementedDeviceState scc;
79 UnimplementedDeviceState timer;
80 PL031State rtc;
81 UnimplementedDeviceState pvt;
82 UnimplementedDeviceState sdio;
83 UnimplementedDeviceState gpio;
84 UnimplementedDeviceState cryptoisland;
85 };
86
87 #define TYPE_MUSCA_MACHINE "musca"
88 #define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a")
89 #define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1")
90
91 OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
92
93 /*
94 * Main SYSCLK frequency in Hz
95 * TODO this should really be different for the two cores, but we
96 * don't model that in our SSE-200 model yet.
97 */
98 #define SYSCLK_FRQ 40000000
99
100 static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
101 {
102 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
103 assert(irqno < MUSCA_NUMIRQ_MAX);
104
105 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
106 }
107
108 /*
109 * Most of the devices in the Musca board sit behind Peripheral Protection
110 * Controllers. These data structures define the layout of which devices
111 * sit behind which PPCs.
112 * The devfn for each port is a function which creates, configures
113 * and initializes the device, returning the MemoryRegion which
114 * needs to be plugged into the downstream end of the PPC port.
115 */
116 typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque,
117 const char *name, hwaddr size);
118
119 typedef struct PPCPortInfo {
120 const char *name;
121 MakeDevFn *devfn;
122 void *opaque;
123 hwaddr addr;
124 hwaddr size;
125 } PPCPortInfo;
126
127 typedef struct PPCInfo {
128 const char *name;
129 PPCPortInfo ports[TZ_NUM_PORTS];
130 } PPCInfo;
131
132 static MemoryRegion *make_unimp_dev(MuscaMachineState *mms,
133 void *opaque, const char *name, hwaddr size)
134 {
135 /*
136 * Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
137 * and return a pointer to its MemoryRegion.
138 */
139 UnimplementedDeviceState *uds = opaque;
140
141 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
142 qdev_prop_set_string(DEVICE(uds), "name", name);
143 qdev_prop_set_uint64(DEVICE(uds), "size", size);
144 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
145 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
146 }
147
148 typedef enum MPCInfoType {
149 MPC_RAM,
150 MPC_ROM,
151 MPC_CRYPTOISLAND,
152 } MPCInfoType;
153
154 struct MPCInfo {
155 const char *name;
156 hwaddr addr;
157 hwaddr size;
158 MPCInfoType type;
159 };
160
161 /* Order of the MPCs here must match the order of the bits in SECMPCINTSTATUS */
162 static const MPCInfo a_mpc_info[] = { {
163 .name = "qspi",
164 .type = MPC_ROM,
165 .addr = 0x00200000,
166 .size = 0x00800000,
167 }, {
168 .name = "sram",
169 .type = MPC_RAM,
170 .addr = 0x00000000,
171 .size = 0x00200000,
172 }
173 };
174
175 static const MPCInfo b1_mpc_info[] = { {
176 .name = "qspi",
177 .type = MPC_ROM,
178 .addr = 0x00000000,
179 .size = 0x02000000,
180 }, {
181 .name = "sram",
182 .type = MPC_RAM,
183 .addr = 0x0a400000,
184 .size = 0x00080000,
185 }, {
186 .name = "eflash0",
187 .type = MPC_ROM,
188 .addr = 0x0a000000,
189 .size = 0x00200000,
190 }, {
191 .name = "eflash1",
192 .type = MPC_ROM,
193 .addr = 0x0a200000,
194 .size = 0x00200000,
195 }, {
196 .name = "cryptoisland",
197 .type = MPC_CRYPTOISLAND,
198 .addr = 0x0a000000,
199 .size = 0x00200000,
200 }
201 };
202
203 static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque,
204 const char *name, hwaddr size)
205 {
206 /*
207 * Create an MPC and the RAM or flash behind it.
208 * MPC 0: eFlash 0
209 * MPC 1: eFlash 1
210 * MPC 2: SRAM
211 * MPC 3: QSPI flash
212 * MPC 4: CryptoIsland
213 * For now we implement the flash regions as ROM (ie not programmable)
214 * (with their control interface memory regions being unimplemented
215 * stubs behind the PPCs).
216 * The whole CryptoIsland region behind its MPC is an unimplemented stub.
217 */
218 MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
219 TZMPC *mpc = opaque;
220 int i = mpc - &mms->mpc[0];
221 MemoryRegion *downstream;
222 MemoryRegion *upstream;
223 UnimplementedDeviceState *uds;
224 char *mpcname;
225 const MPCInfo *mpcinfo = mmc->mpc_info;
226
227 mpcname = g_strdup_printf("%s-mpc", mpcinfo[i].name);
228
229 switch (mpcinfo[i].type) {
230 case MPC_ROM:
231 downstream = &mms->ram[i];
232 memory_region_init_rom(downstream, NULL, mpcinfo[i].name,
233 mpcinfo[i].size, &error_fatal);
234 break;
235 case MPC_RAM:
236 downstream = &mms->ram[i];
237 memory_region_init_ram(downstream, NULL, mpcinfo[i].name,
238 mpcinfo[i].size, &error_fatal);
239 break;
240 case MPC_CRYPTOISLAND:
241 /* We don't implement the CryptoIsland yet */
242 uds = &mms->cryptoisland;
243 object_initialize_child(OBJECT(mms), name, uds,
244 TYPE_UNIMPLEMENTED_DEVICE);
245 qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name);
246 qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size);
247 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
248 downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
249 break;
250 default:
251 g_assert_not_reached();
252 }
253
254 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
255 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(downstream),
256 &error_fatal);
257 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
258 /* Map the upstream end of the MPC into system memory */
259 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
260 memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream);
261 /* and connect its interrupt to the SSE-200 */
262 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
263 qdev_get_gpio_in_named(DEVICE(&mms->sse),
264 "mpcexp_status", i));
265
266 g_free(mpcname);
267 /* Return the register interface MR for our caller to map behind the PPC */
268 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
269 }
270
271 static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque,
272 const char *name, hwaddr size)
273 {
274 PL031State *rtc = opaque;
275
276 object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031);
277 sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal);
278 sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39));
279 return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0);
280 }
281
282 static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque,
283 const char *name, hwaddr size)
284 {
285 PL011State *uart = opaque;
286 int i = uart - &mms->uart[0];
287 int irqbase = 7 + i * 6;
288 SysBusDevice *s;
289
290 object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011);
291 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
292 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
293 s = SYS_BUS_DEVICE(uart);
294 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */
295 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */
296 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */
297 sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */
298 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */
299 sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */
300 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
301 }
302
303 static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque,
304 const char *name, hwaddr size)
305 {
306 /*
307 * Create the container MemoryRegion for all the devices that live
308 * behind the Musca-A PPC's single port. These devices don't have a PPC
309 * port each, but we use the PPCPortInfo struct as a convenient way
310 * to describe them. Note that addresses here are relative to the base
311 * address of the PPC port region: 0x40100000, and devices appear both
312 * at the 0x4... NS region and the 0x5... S region.
313 */
314 int i;
315 MemoryRegion *container = &mms->container;
316
317 const PPCPortInfo devices[] = {
318 { "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 },
319 { "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 },
320 { "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 },
321 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 },
322 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 },
323 { "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 },
324 { "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 },
325 { "rtc", make_rtc, &mms->rtc, 0x8000, 0x1000 },
326 { "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 },
327 { "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 },
328 { "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 },
329 { "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 },
330 { "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 },
331 { "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 },
332 { "mpc0", make_mpc, &mms->mpc[0], 0x12000, 0x1000 },
333 { "mpc1", make_mpc, &mms->mpc[1], 0x13000, 0x1000 },
334 };
335
336 memory_region_init(container, OBJECT(mms), "musca-device-container", size);
337
338 for (i = 0; i < ARRAY_SIZE(devices); i++) {
339 const PPCPortInfo *pinfo = &devices[i];
340 MemoryRegion *mr;
341
342 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
343 memory_region_add_subregion(container, pinfo->addr, mr);
344 }
345
346 return &mms->container;
347 }
348
349 static void musca_init(MachineState *machine)
350 {
351 MuscaMachineState *mms = MUSCA_MACHINE(machine);
352 MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
353 MachineClass *mc = MACHINE_GET_CLASS(machine);
354 MemoryRegion *system_memory = get_system_memory();
355 DeviceState *ssedev;
356 DeviceState *dev_splitter;
357 const PPCInfo *ppcs;
358 int num_ppcs;
359 int i;
360
361 assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX);
362 assert(mmc->num_mpcs <= MUSCA_MPC_MAX);
363
364 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
365 error_report("This board can only be used with CPU %s",
366 mc->default_cpu_type);
367 exit(1);
368 }
369
370 object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
371 TYPE_SSE200);
372 ssedev = DEVICE(&mms->sse);
373 object_property_set_link(OBJECT(&mms->sse), "memory",
374 OBJECT(system_memory), &error_fatal);
375 qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
376 qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
377 qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
378 qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ);
379 /*
380 * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
381 * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
382 */
383 if (mmc->type == MUSCA_B1) {
384 qdev_prop_set_bit(ssedev, "CPU0_FPU", true);
385 qdev_prop_set_bit(ssedev, "CPU0_DSP", true);
386 }
387 sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal);
388
389 /*
390 * We need to create splitters to feed the IRQ inputs
391 * for each CPU in the SSE-200 from each device in the board.
392 */
393 for (i = 0; i < mmc->num_irqs; i++) {
394 char *name = g_strdup_printf("musca-irq-splitter%d", i);
395 SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
396
397 object_initialize_child_with_props(OBJECT(machine), name, splitter,
398 sizeof(*splitter), TYPE_SPLIT_IRQ,
399 &error_fatal, NULL);
400 g_free(name);
401
402 object_property_set_int(OBJECT(splitter), "num-lines", 2,
403 &error_fatal);
404 qdev_realize(DEVICE(splitter), NULL, &error_fatal);
405 qdev_connect_gpio_out(DEVICE(splitter), 0,
406 qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i));
407 qdev_connect_gpio_out(DEVICE(splitter), 1,
408 qdev_get_gpio_in_named(ssedev,
409 "EXP_CPU1_IRQ", i));
410 }
411
412 /*
413 * The sec_resp_cfg output from the SSE-200 must be split into multiple
414 * lines, one for each of the PPCs we create here.
415 */
416 object_initialize_child_with_props(OBJECT(machine), "sec-resp-splitter",
417 &mms->sec_resp_splitter,
418 sizeof(mms->sec_resp_splitter),
419 TYPE_SPLIT_IRQ, &error_fatal, NULL);
420
421 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines",
422 ARRAY_SIZE(mms->ppc), &error_fatal);
423 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
424 dev_splitter = DEVICE(&mms->sec_resp_splitter);
425 qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0,
426 qdev_get_gpio_in(dev_splitter, 0));
427
428 /*
429 * Most of the devices in the board are behind Peripheral Protection
430 * Controllers. The required order for initializing things is:
431 * + initialize the PPC
432 * + initialize, configure and realize downstream devices
433 * + connect downstream device MemoryRegions to the PPC
434 * + realize the PPC
435 * + map the PPC's MemoryRegions to the places in the address map
436 * where the downstream devices should appear
437 * + wire up the PPC's control lines to the SSE object
438 *
439 * The PPC mapping differs for the -A and -B1 variants; the -A version
440 * is much simpler, using only a single port of a single PPC and putting
441 * all the devices behind that.
442 */
443 const PPCInfo a_ppcs[] = { {
444 .name = "ahb_ppcexp0",
445 .ports = {
446 { "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100000 },
447 },
448 },
449 };
450
451 /*
452 * Devices listed with an 0x4.. address appear in both the NS 0x4.. region
453 * and the 0x5.. S region. Devices listed with an 0x5.. address appear
454 * only in the S region.
455 */
456 const PPCInfo b1_ppcs[] = { {
457 .name = "apb_ppcexp0",
458 .ports = {
459 { "eflash0", make_unimp_dev, &mms->eflash[0],
460 0x52400000, 0x1000 },
461 { "eflash1", make_unimp_dev, &mms->eflash[1],
462 0x52500000, 0x1000 },
463 { "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000 },
464 { "mpc0", make_mpc, &mms->mpc[0], 0x52000000, 0x1000 },
465 { "mpc1", make_mpc, &mms->mpc[1], 0x52100000, 0x1000 },
466 { "mpc2", make_mpc, &mms->mpc[2], 0x52200000, 0x1000 },
467 { "mpc3", make_mpc, &mms->mpc[3], 0x52300000, 0x1000 },
468 { "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 },
469 { "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 },
470 { }, /* port 9: unused */
471 { }, /* port 10: unused */
472 { }, /* port 11: unused */
473 { }, /* port 12: unused */
474 { }, /* port 13: unused */
475 { "mpc4", make_mpc, &mms->mpc[4], 0x52e00000, 0x1000 },
476 },
477 }, {
478 .name = "apb_ppcexp1",
479 .ports = {
480 { "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 },
481 { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 },
482 { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 },
483 { "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 },
484 { "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 },
485 { "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 },
486 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 },
487 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 },
488 { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 },
489 { "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 },
490 { "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000 },
491 { "rtc", make_rtc, &mms->rtc, 0x4010d000, 0x1000 },
492 { "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 },
493 { "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 },
494 },
495 }, {
496 .name = "ahb_ppcexp0",
497 .ports = {
498 { }, /* port 0: unused */
499 { "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 },
500 },
501 },
502 };
503
504 switch (mmc->type) {
505 case MUSCA_A:
506 ppcs = a_ppcs;
507 num_ppcs = ARRAY_SIZE(a_ppcs);
508 break;
509 case MUSCA_B1:
510 ppcs = b1_ppcs;
511 num_ppcs = ARRAY_SIZE(b1_ppcs);
512 break;
513 default:
514 g_assert_not_reached();
515 }
516 assert(num_ppcs <= MUSCA_PPC_MAX);
517
518 for (i = 0; i < num_ppcs; i++) {
519 const PPCInfo *ppcinfo = &ppcs[i];
520 TZPPC *ppc = &mms->ppc[i];
521 DeviceState *ppcdev;
522 int port;
523 char *gpioname;
524
525 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
526 TYPE_TZ_PPC);
527 ppcdev = DEVICE(ppc);
528
529 for (port = 0; port < TZ_NUM_PORTS; port++) {
530 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
531 MemoryRegion *mr;
532 char *portname;
533
534 if (!pinfo->devfn) {
535 continue;
536 }
537
538 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
539 portname = g_strdup_printf("port[%d]", port);
540 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
541 &error_fatal);
542 g_free(portname);
543 }
544
545 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
546
547 for (port = 0; port < TZ_NUM_PORTS; port++) {
548 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
549
550 if (!pinfo->devfn) {
551 continue;
552 }
553 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
554
555 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
556 qdev_connect_gpio_out_named(ssedev, gpioname, port,
557 qdev_get_gpio_in_named(ppcdev,
558 "cfg_nonsec",
559 port));
560 g_free(gpioname);
561 gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
562 qdev_connect_gpio_out_named(ssedev, gpioname, port,
563 qdev_get_gpio_in_named(ppcdev,
564 "cfg_ap", port));
565 g_free(gpioname);
566 }
567
568 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
569 qdev_connect_gpio_out_named(ssedev, gpioname, 0,
570 qdev_get_gpio_in_named(ppcdev,
571 "irq_enable", 0));
572 g_free(gpioname);
573 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
574 qdev_connect_gpio_out_named(ssedev, gpioname, 0,
575 qdev_get_gpio_in_named(ppcdev,
576 "irq_clear", 0));
577 g_free(gpioname);
578 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
579 qdev_connect_gpio_out_named(ppcdev, "irq", 0,
580 qdev_get_gpio_in_named(ssedev,
581 gpioname, 0));
582 g_free(gpioname);
583
584 qdev_connect_gpio_out(dev_splitter, i,
585 qdev_get_gpio_in_named(ppcdev,
586 "cfg_sec_resp", 0));
587 }
588
589 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x2000000);
590 }
591
592 static void musca_class_init(ObjectClass *oc, void *data)
593 {
594 MachineClass *mc = MACHINE_CLASS(oc);
595
596 mc->default_cpus = 2;
597 mc->min_cpus = mc->default_cpus;
598 mc->max_cpus = mc->default_cpus;
599 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
600 mc->init = musca_init;
601 }
602
603 static void musca_a_class_init(ObjectClass *oc, void *data)
604 {
605 MachineClass *mc = MACHINE_CLASS(oc);
606 MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
607
608 mc->desc = "ARM Musca-A board (dual Cortex-M33)";
609 mmc->type = MUSCA_A;
610 mmc->init_svtor = 0x10200000;
611 mmc->sram_addr_width = 15;
612 mmc->num_irqs = 64;
613 mmc->mpc_info = a_mpc_info;
614 mmc->num_mpcs = ARRAY_SIZE(a_mpc_info);
615 }
616
617 static void musca_b1_class_init(ObjectClass *oc, void *data)
618 {
619 MachineClass *mc = MACHINE_CLASS(oc);
620 MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
621
622 mc->desc = "ARM Musca-B1 board (dual Cortex-M33)";
623 mmc->type = MUSCA_B1;
624 /*
625 * This matches the DAPlink firmware which boots from QSPI. There
626 * is also a firmware blob which boots from the eFlash, which
627 * uses init_svtor = 0x1A000000. QEMU doesn't currently support that,
628 * though we could in theory expose a machine property on the command
629 * line to allow the user to request eFlash boot.
630 */
631 mmc->init_svtor = 0x10000000;
632 mmc->sram_addr_width = 17;
633 mmc->num_irqs = 96;
634 mmc->mpc_info = b1_mpc_info;
635 mmc->num_mpcs = ARRAY_SIZE(b1_mpc_info);
636 }
637
638 static const TypeInfo musca_info = {
639 .name = TYPE_MUSCA_MACHINE,
640 .parent = TYPE_MACHINE,
641 .abstract = true,
642 .instance_size = sizeof(MuscaMachineState),
643 .class_size = sizeof(MuscaMachineClass),
644 .class_init = musca_class_init,
645 };
646
647 static const TypeInfo musca_a_info = {
648 .name = TYPE_MUSCA_A_MACHINE,
649 .parent = TYPE_MUSCA_MACHINE,
650 .class_init = musca_a_class_init,
651 };
652
653 static const TypeInfo musca_b1_info = {
654 .name = TYPE_MUSCA_B1_MACHINE,
655 .parent = TYPE_MUSCA_MACHINE,
656 .class_init = musca_b1_class_init,
657 };
658
659 static void musca_machine_init(void)
660 {
661 type_register_static(&musca_info);
662 type_register_static(&musca_a_info);
663 type_register_static(&musca_b1_info);
664 }
665
666 type_init(musca_machine_init);